Chuan Liu e6f1d9db24 clk: s7: optimize clock performance [2/2] ...

PD#SWPL-135780

Problem:
optimize clock performance.

Solution:
1 Optimize cpu_clk switching frequency timing;
2 Move all cpu_clk set frequency operations to bl31.

Verify:
pxp

Change-Id: I6147683b713a9b4854cd8f92e13b396f8705ea30
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2024-01-22 12:48:44 +08:00

..

drm

drm: add vrr range getting ioctl [1/1]

2023-12-13 20:59:09 -07:00

dt-bindings

clk: s7: optimize clock performance [2/2]

2024-01-22 12:48:44 +08:00

linux/amlogic

pwm: add pwm tee driver for s7 [1/2]

2024-01-22 12:48:43 +08:00

trace/events

debug: add meson_atrace inline function. [1/1]

2023-03-07 23:10:47 -08:00

uapi/amlogic

hdmirx: add 480/567 format [1/1]

2024-01-15 06:39:38 -07:00