Xingxing Wang 46199b50cc thermal: ddr thermal param update of t5d&t5w [1/1] ...

PD#SWPL-169759

Problem:
align 20nm ddr thermal params to kernel5.4

Solution:
1. align 20nm ddr thermal params to kernel5.4
2. update ddr status when coolingdevice registerd

Verify:
t5d&t5w

Change-Id: Ib33b715e790a72f2969dc69c3dec159589ae0d3f
Signed-off-by: Xingxing Wang <xingxing.wang@amlogic.com>

2024-05-22 03:59:31 -07:00

..

arm

thermal: ddr thermal param update of t5d&t5w [1/1]

2024-05-22 03:59:31 -07:00

arm64

thermal: ddr thermal param update of t5d&t5w [1/1]

2024-05-22 03:59:31 -07:00

riscv

dump_stack: optimize dts property [1/1]

2023-04-16 21:24:26 -07:00