can.zhang ffcfa1561a amdv: resync cl optimize dma time cost [1/1] ...

PD#SWPL-231112

Problem:
wr reg interface error

Solution:
resync cl

Verify:
s7d

Change-Id: I32370171a88297f8dba2ca08bc4de8c01133fa73
Signed-off-by: can.zhang <can.zhang@amlogic.com>

2025-09-12 21:06:58 -07:00

..

amlogic

amdv: resync cl optimize dma time cost [1/1]

2025-09-12 21:06:58 -07:00

upstream_version.h

upgrade: common16-6.12 upgrade by July 23 [1/4]

2025-08-06 20:30:04 -07:00