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stm32: Enable ADC support on stm32g0

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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
2021-12-19 21:30:33 -05:00
parent 88325b6c93
commit 1c24317380
4 changed files with 57 additions and 12 deletions
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59
src/stm32/stm32f0_adc.c
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@@ -21,11 +21,49 @@ DECL_ENUMERATION("pin", "ADC_TEMPERATURE", ADC_TEMPERATURE_PIN);
static const uint8_t adc_pins[] = {
GPIO('A', 0), GPIO('A', 1), GPIO('A', 2), GPIO('A', 3),
GPIO('A', 4), GPIO('A', 5), GPIO('A', 6), GPIO('A', 7),
GPIO('B', 0), GPIO('B', 1), GPIO('C', 0), GPIO('C', 1),
GPIO('B', 0), GPIO('B', 1),
#if CONFIG_MACH_STM32F0
GPIO('C', 0), GPIO('C', 1),
GPIO('C', 2), GPIO('C', 3), GPIO('C', 4), GPIO('C', 5),
ADC_TEMPERATURE_PIN
#elif CONFIG_MACH_STM32G0
GPIO('B', 2), GPIO('B', 10),
ADC_TEMPERATURE_PIN, 0x00, 0x00,
GPIO('B', 11), GPIO('B', 12), GPIO('C', 4), GPIO('C', 5),
#endif
};
// Setup and calibrate ADC on stm32f0 chips
static void
stm32f0_adc_setup(void)
{
#if CONFIG_MACH_STM32F0
#define CR_FLAGS 0
ADC_TypeDef *adc = ADC1;
// 100: 41.5 ADC clock cycles
adc->SMPR = 4 << ADC_SMPR_SMP_Pos;
#endif
}
// Setup and calibrate ADC on stm32g0 chips
static void
stm32g0_adc_setup(void)
{
#if CONFIG_MACH_STM32G0
#define CR_FLAGS ADC_CR_ADVREGEN
ADC_TypeDef *adc = ADC1;
// 101: 39.5 ADC clock cycles
adc->SMPR = 5 << ADC_SMPR_SMP1_Pos;
adc->CFGR2 = 2 << ADC_CFGR2_CKMODE_Pos; // 16Mhz
// Enable voltage regulator
adc->CR = CR_FLAGS;
uint32_t end = timer_read_time() + timer_from_us(20);
while (timer_is_before(timer_read_time(), end))
;
#endif
}
struct gpio_adc
gpio_adc_setup(uint32_t pin)
{
@@ -41,18 +79,19 @@ gpio_adc_setup(uint32_t pin)
// Enable the ADC
if (!is_enabled_pclock(ADC1_BASE)) {
enable_pclock(ADC1_BASE);
if (CONFIG_MACH_STM32F0)
stm32f0_adc_setup();
else if (CONFIG_MACH_STM32G0)
stm32g0_adc_setup();
// Start calibration and wait for completion
ADC_TypeDef *adc = ADC1;
// 100: 41.5 ADC clock cycles
adc->SMPR = 4 << ADC_SMPR_SMP_Pos;
// start calibration and wait for completion
adc->CR = ADC_CR_ADCAL;
adc->CR = CR_FLAGS | ADC_CR_ADCAL;
while (adc->CR & ADC_CR_ADCAL)
;
// Enable ADC
adc->ISR = ADC_ISR_ADRDY;
adc->CR = ADC_CR_ADEN;
adc->CR = CR_FLAGS | ADC_CR_ADEN;
while (!(adc->ISR & ADC_ISR_ADRDY))
;
}
@@ -80,7 +119,7 @@ gpio_adc_sample(struct gpio_adc g)
goto need_delay;
}
adc->CHSELR = g.chan;
adc->CR = ADC_CR_ADSTART;
adc->CR = CR_FLAGS | ADC_CR_ADSTART;
need_delay:
return timer_from_us(10);
@@ -102,7 +141,7 @@ gpio_adc_cancel_sample(struct gpio_adc g)
irqstatus_t flag = irq_save();
if (adc->CHSELR == g.chan) {
if (adc->CR & ADC_CR_ADSTART)
adc->CR = ADC_CR_ADSTP;
adc->CR = CR_FLAGS | ADC_CR_ADSTP;
if (adc->ISR & ADC_ISR_EOC)
gpio_adc_read(g);
}