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stm32: Add USBOTG support to stm32h7

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Signed-off-by: Aaron DeLyser <bluwolf@gmail.com>
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
adelyser
2021-10-27 21:43:47 -06:00
committed by Kevin O'Connor
parent 4d738c8379
commit 4eeb4620cd
3 changed files with 81 additions and 23 deletions
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53
src/stm32/usbotg.c
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@@ -14,16 +14,34 @@
#include "internal.h" // GPIO
#include "sched.h" // DECL_INIT
#if CONFIG_STM32_USB_PB14_PB15
#define USB_PERIPH_BASE USB_OTG_HS_PERIPH_BASE
#define OTG_IRQn OTG_HS_IRQn
#define USBOTGEN RCC_AHB1ENR_USB1OTGHSEN
#define GPIO_D_NEG GPIO('B', 14)
#define GPIO_D_POS GPIO('B', 15)
#define GPIO_FUNC GPIO_FUNCTION(12)
DECL_CONSTANT_STR("RESERVE_PINS_USB1", "PB14,PB15");
#else
#define USB_PERIPH_BASE USB_OTG_FS_PERIPH_BASE
#define OTG_IRQn OTG_FS_IRQn
#define USBOTGEN RCC_AHB1ENR_USB2OTGHSEN
#define GPIO_D_NEG GPIO('A', 11)
#define GPIO_D_POS GPIO('A', 12)
#define GPIO_FUNC GPIO_FUNCTION(10)
DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12");
#endif
static void
usb_irq_disable(void)
{
NVIC_DisableIRQ(OTG_FS_IRQn);
NVIC_DisableIRQ(OTG_IRQn);
}
static void
usb_irq_enable(void)
{
NVIC_EnableIRQ(OTG_FS_IRQn);
NVIC_EnableIRQ(OTG_IRQn);
}
@@ -31,17 +49,13 @@ usb_irq_enable(void)
* USB transfer memory
****************************************************************/
#define OTG ((USB_OTG_GlobalTypeDef*)USB_OTG_FS_PERIPH_BASE)
#define OTGD ((USB_OTG_DeviceTypeDef*) \
(USB_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE))
#define EPFIFO(EP) ((void*)(USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE \
+ ((EP) << 12)))
#define OTG ((USB_OTG_GlobalTypeDef*)USB_PERIPH_BASE)
#define OTGD ((USB_OTG_DeviceTypeDef*)(USB_PERIPH_BASE + USB_OTG_DEVICE_BASE))
#define EPFIFO(EP) ((void*)(USB_PERIPH_BASE + USB_OTG_FIFO_BASE + ((EP) << 12)))
#define EPIN(EP) ((USB_OTG_INEndpointTypeDef*) \
(USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE \
+ ((EP) << 5)))
(USB_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE + ((EP) << 5)))
#define EPOUT(EP) ((USB_OTG_OUTEndpointTypeDef*) \
(USB_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE \
+ ((EP) << 5)))
(USB_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((EP) << 5)))
// Setup the USB fifos
static void
@@ -382,14 +396,19 @@ OTG_FS_IRQHandler(void)
}
}
DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12");
// Initialize the usb controller
void
usb_init(void)
{
// Enable USB clock
#if CONFIG_MACH_STM32H7
if (READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) != (PWR_CR3_USB33RDY)) {
SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
}
SET_BIT(RCC->AHB1ENR, USBOTGEN);
#else
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
#endif
while (!(OTG->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL))
;
@@ -397,15 +416,15 @@ usb_init(void)
OTG->GUSBCFG = (USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL
| (6 << USB_OTG_GUSBCFG_TRDT_Pos));
OTGD->DCFG |= (3 << USB_OTG_DCFG_DSPD_Pos);
#if CONFIG_MACH_STM32F446
#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7
OTG->GOTGCTL = USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
#else
OTG->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
#endif
// Route pins
gpio_peripheral(GPIO('A', 11), GPIO_FUNCTION(10), 0);
gpio_peripheral(GPIO('A', 12), GPIO_FUNCTION(10), 0);
gpio_peripheral(GPIO_D_NEG, GPIO_FUNC, 0);
gpio_peripheral(GPIO_D_POS, GPIO_FUNC, 0);
// Setup USB packet memory
fifo_configure();
@@ -423,7 +442,7 @@ usb_init(void)
OTGD->DIEPMSK = USB_OTG_DIEPMSK_XFRCM;
OTG->GINTMSK = USB_OTG_GINTMSK_RXFLVLM | USB_OTG_GINTMSK_IEPINT;
OTG->GAHBCFG = USB_OTG_GAHBCFG_GINT;
armcm_enable_irq(OTG_FS_IRQHandler, OTG_FS_IRQn, 1);
armcm_enable_irq(OTG_FS_IRQHandler, OTG_IRQn, 1);
// Enable USB
OTG->GCCFG |= USB_OTG_GCCFG_PWRDWN;