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lib: Add rp2350 files to pico-sdk

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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
2024-10-25 14:08:46 -04:00
parent 2ad0b1afc2
commit f00919070e
107 changed files with 128556 additions and 0 deletions
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4953
lib/pico-sdk/rp2350/hardware/regs/accessctrl.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/adc.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : ADC
// Version : 2
// Bus type : apb
// Description : Control and data interface to SAR ADC
// =============================================================================
#ifndef _HARDWARE_REGS_ADC_H
#define _HARDWARE_REGS_ADC_H
// =============================================================================
// Register : ADC_CS
// Description : ADC Control and Status
#define ADC_CS_OFFSET _u(0x00000000)
#define ADC_CS_BITS _u(0x01fff70f)
#define ADC_CS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_CS_RROBIN
// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
// disable.
// Otherwise, the ADC will cycle through each enabled channel in a
// round-robin fashion.
// The first channel to be sampled will be the one currently
// indicated by AINSEL.
// AINSEL will be updated after each conversion with the newly-
// selected channel.
#define ADC_CS_RROBIN_RESET _u(0x000)
#define ADC_CS_RROBIN_BITS _u(0x01ff0000)
#define ADC_CS_RROBIN_MSB _u(24)
#define ADC_CS_RROBIN_LSB _u(16)
#define ADC_CS_RROBIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_AINSEL
// Description : Select analog mux input. Updated automatically in round-robin
// mode.
// This is corrected for the package option so only ADC channels
// which are bonded are available, and in the correct order
#define ADC_CS_AINSEL_RESET _u(0x0)
#define ADC_CS_AINSEL_BITS _u(0x0000f000)
#define ADC_CS_AINSEL_MSB _u(15)
#define ADC_CS_AINSEL_LSB _u(12)
#define ADC_CS_AINSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR_STICKY
// Description : Some past ADC conversion encountered an error. Write 1 to
// clear.
#define ADC_CS_ERR_STICKY_RESET _u(0x0)
#define ADC_CS_ERR_STICKY_BITS _u(0x00000400)
#define ADC_CS_ERR_STICKY_MSB _u(10)
#define ADC_CS_ERR_STICKY_LSB _u(10)
#define ADC_CS_ERR_STICKY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR
// Description : The most recent ADC conversion encountered an error; result is
// undefined or noisy.
#define ADC_CS_ERR_RESET _u(0x0)
#define ADC_CS_ERR_BITS _u(0x00000200)
#define ADC_CS_ERR_MSB _u(9)
#define ADC_CS_ERR_LSB _u(9)
#define ADC_CS_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_READY
// Description : 1 if the ADC is ready to start a new conversion. Implies any
// previous conversion has completed.
// 0 whilst conversion in progress.
#define ADC_CS_READY_RESET _u(0x0)
#define ADC_CS_READY_BITS _u(0x00000100)
#define ADC_CS_READY_MSB _u(8)
#define ADC_CS_READY_LSB _u(8)
#define ADC_CS_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_MANY
// Description : Continuously perform conversions whilst this bit is 1. A new
// conversion will start immediately after the previous finishes.
#define ADC_CS_START_MANY_RESET _u(0x0)
#define ADC_CS_START_MANY_BITS _u(0x00000008)
#define ADC_CS_START_MANY_MSB _u(3)
#define ADC_CS_START_MANY_LSB _u(3)
#define ADC_CS_START_MANY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_ONCE
// Description : Start a single conversion. Self-clearing. Ignored if start_many
// is asserted.
#define ADC_CS_START_ONCE_RESET _u(0x0)
#define ADC_CS_START_ONCE_BITS _u(0x00000004)
#define ADC_CS_START_ONCE_MSB _u(2)
#define ADC_CS_START_ONCE_LSB _u(2)
#define ADC_CS_START_ONCE_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_TS_EN
// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
#define ADC_CS_TS_EN_RESET _u(0x0)
#define ADC_CS_TS_EN_BITS _u(0x00000002)
#define ADC_CS_TS_EN_MSB _u(1)
#define ADC_CS_TS_EN_LSB _u(1)
#define ADC_CS_TS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_EN
// Description : Power on ADC and enable its clock.
// 1 - enabled. 0 - disabled.
#define ADC_CS_EN_RESET _u(0x0)
#define ADC_CS_EN_BITS _u(0x00000001)
#define ADC_CS_EN_MSB _u(0)
#define ADC_CS_EN_LSB _u(0)
#define ADC_CS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_RESULT
// Description : Result of most recent ADC conversion
#define ADC_RESULT_OFFSET _u(0x00000004)
#define ADC_RESULT_BITS _u(0x00000fff)
#define ADC_RESULT_RESET _u(0x00000000)
#define ADC_RESULT_MSB _u(11)
#define ADC_RESULT_LSB _u(0)
#define ADC_RESULT_ACCESS "RO"
// =============================================================================
// Register : ADC_FCS
// Description : FIFO control and status
#define ADC_FCS_OFFSET _u(0x00000008)
#define ADC_FCS_BITS _u(0x0f0f0f0f)
#define ADC_FCS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FCS_THRESH
// Description : DREQ/IRQ asserted when level >= threshold
#define ADC_FCS_THRESH_RESET _u(0x0)
#define ADC_FCS_THRESH_BITS _u(0x0f000000)
#define ADC_FCS_THRESH_MSB _u(27)
#define ADC_FCS_THRESH_LSB _u(24)
#define ADC_FCS_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_LEVEL
// Description : The number of conversion results currently waiting in the FIFO
#define ADC_FCS_LEVEL_RESET _u(0x0)
#define ADC_FCS_LEVEL_BITS _u(0x000f0000)
#define ADC_FCS_LEVEL_MSB _u(19)
#define ADC_FCS_LEVEL_LSB _u(16)
#define ADC_FCS_LEVEL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_OVER
// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
#define ADC_FCS_OVER_RESET _u(0x0)
#define ADC_FCS_OVER_BITS _u(0x00000800)
#define ADC_FCS_OVER_MSB _u(11)
#define ADC_FCS_OVER_LSB _u(11)
#define ADC_FCS_OVER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_UNDER
// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
#define ADC_FCS_UNDER_RESET _u(0x0)
#define ADC_FCS_UNDER_BITS _u(0x00000400)
#define ADC_FCS_UNDER_MSB _u(10)
#define ADC_FCS_UNDER_LSB _u(10)
#define ADC_FCS_UNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_FULL
#define ADC_FCS_FULL_RESET _u(0x0)
#define ADC_FCS_FULL_BITS _u(0x00000200)
#define ADC_FCS_FULL_MSB _u(9)
#define ADC_FCS_FULL_LSB _u(9)
#define ADC_FCS_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EMPTY
#define ADC_FCS_EMPTY_RESET _u(0x0)
#define ADC_FCS_EMPTY_BITS _u(0x00000100)
#define ADC_FCS_EMPTY_MSB _u(8)
#define ADC_FCS_EMPTY_LSB _u(8)
#define ADC_FCS_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_DREQ_EN
// Description : If 1: assert DMA requests when FIFO contains data
#define ADC_FCS_DREQ_EN_RESET _u(0x0)
#define ADC_FCS_DREQ_EN_BITS _u(0x00000008)
#define ADC_FCS_DREQ_EN_MSB _u(3)
#define ADC_FCS_DREQ_EN_LSB _u(3)
#define ADC_FCS_DREQ_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_ERR
// Description : If 1: conversion error bit appears in the FIFO alongside the
// result
#define ADC_FCS_ERR_RESET _u(0x0)
#define ADC_FCS_ERR_BITS _u(0x00000004)
#define ADC_FCS_ERR_MSB _u(2)
#define ADC_FCS_ERR_LSB _u(2)
#define ADC_FCS_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_SHIFT
// Description : If 1: FIFO results are right-shifted to be one byte in size.
// Enables DMA to byte buffers.
#define ADC_FCS_SHIFT_RESET _u(0x0)
#define ADC_FCS_SHIFT_BITS _u(0x00000002)
#define ADC_FCS_SHIFT_MSB _u(1)
#define ADC_FCS_SHIFT_LSB _u(1)
#define ADC_FCS_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EN
// Description : If 1: write result to the FIFO after each conversion.
#define ADC_FCS_EN_RESET _u(0x0)
#define ADC_FCS_EN_BITS _u(0x00000001)
#define ADC_FCS_EN_MSB _u(0)
#define ADC_FCS_EN_LSB _u(0)
#define ADC_FCS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_FIFO
// Description : Conversion result FIFO
#define ADC_FIFO_OFFSET _u(0x0000000c)
#define ADC_FIFO_BITS _u(0x00008fff)
#define ADC_FIFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_ERR
// Description : 1 if this particular sample experienced a conversion error.
// Remains in the same location if the sample is shifted.
#define ADC_FIFO_ERR_RESET "-"
#define ADC_FIFO_ERR_BITS _u(0x00008000)
#define ADC_FIFO_ERR_MSB _u(15)
#define ADC_FIFO_ERR_LSB _u(15)
#define ADC_FIFO_ERR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_VAL
#define ADC_FIFO_VAL_RESET "-"
#define ADC_FIFO_VAL_BITS _u(0x00000fff)
#define ADC_FIFO_VAL_MSB _u(11)
#define ADC_FIFO_VAL_LSB _u(0)
#define ADC_FIFO_VAL_ACCESS "RF"
// =============================================================================
// Register : ADC_DIV
// Description : Clock divider. If non-zero, CS_START_MANY will start
// conversions
// at regular intervals rather than back-to-back.
// The divider is reset when either of these fields are written.
// Total period is 1 + INT + FRAC / 256
#define ADC_DIV_OFFSET _u(0x00000010)
#define ADC_DIV_BITS _u(0x00ffffff)
#define ADC_DIV_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_DIV_INT
// Description : Integer part of clock divisor.
#define ADC_DIV_INT_RESET _u(0x0000)
#define ADC_DIV_INT_BITS _u(0x00ffff00)
#define ADC_DIV_INT_MSB _u(23)
#define ADC_DIV_INT_LSB _u(8)
#define ADC_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_DIV_FRAC
// Description : Fractional part of clock divisor. First-order delta-sigma.
#define ADC_DIV_FRAC_RESET _u(0x00)
#define ADC_DIV_FRAC_BITS _u(0x000000ff)
#define ADC_DIV_FRAC_MSB _u(7)
#define ADC_DIV_FRAC_LSB _u(0)
#define ADC_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : ADC_INTR
// Description : Raw Interrupts
#define ADC_INTR_OFFSET _u(0x00000014)
#define ADC_INTR_BITS _u(0x00000001)
#define ADC_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTR_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTR_FIFO_RESET _u(0x0)
#define ADC_INTR_FIFO_BITS _u(0x00000001)
#define ADC_INTR_FIFO_MSB _u(0)
#define ADC_INTR_FIFO_LSB _u(0)
#define ADC_INTR_FIFO_ACCESS "RO"
// =============================================================================
// Register : ADC_INTE
// Description : Interrupt Enable
#define ADC_INTE_OFFSET _u(0x00000018)
#define ADC_INTE_BITS _u(0x00000001)
#define ADC_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTE_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTE_FIFO_RESET _u(0x0)
#define ADC_INTE_FIFO_BITS _u(0x00000001)
#define ADC_INTE_FIFO_MSB _u(0)
#define ADC_INTE_FIFO_LSB _u(0)
#define ADC_INTE_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTF
// Description : Interrupt Force
#define ADC_INTF_OFFSET _u(0x0000001c)
#define ADC_INTF_BITS _u(0x00000001)
#define ADC_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTF_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTF_FIFO_RESET _u(0x0)
#define ADC_INTF_FIFO_BITS _u(0x00000001)
#define ADC_INTF_FIFO_MSB _u(0)
#define ADC_INTF_FIFO_LSB _u(0)
#define ADC_INTF_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTS
// Description : Interrupt status after masking & forcing
#define ADC_INTS_OFFSET _u(0x00000020)
#define ADC_INTS_BITS _u(0x00000001)
#define ADC_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTS_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTS_FIFO_RESET _u(0x0)
#define ADC_INTS_FIFO_BITS _u(0x00000001)
#define ADC_INTS_FIFO_MSB _u(0)
#define ADC_INTS_FIFO_LSB _u(0)
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_ADC_H

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lib/pico-sdk/rp2350/hardware/regs/addressmap.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _ADDRESSMAP_H
#define _ADDRESSMAP_H
/**
* \file rp2350/addressmap.h
*/
#include "hardware/platform_defs.h"
// Register address offsets for atomic RMW aliases
#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12))
#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12))
#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12))
#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12))
#define ROM_BASE _u(0x00000000)
#define XIP_BASE _u(0x10000000)
#define XIP_SRAM_BASE _u(0x13ffc000)
#define XIP_END _u(0x14000000)
#define XIP_NOCACHE_NOALLOC_BASE _u(0x14000000)
#define XIP_SRAM_END _u(0x14000000)
#define XIP_NOCACHE_NOALLOC_END _u(0x18000000)
#define XIP_MAINTENANCE_BASE _u(0x18000000)
#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_BASE _u(0x1c000000)
#define SRAM0_BASE _u(0x20000000)
#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_END _u(0x20000000)
#define SRAM_BASE _u(0x20000000)
#define SRAM_STRIPED_BASE _u(0x20000000)
#define SRAM4_BASE _u(0x20040000)
#define SRAM8_BASE _u(0x20080000)
#define SRAM_STRIPED_END _u(0x20080000)
#define SRAM_SCRATCH_X_BASE _u(0x20080000)
#define SRAM9_BASE _u(0x20081000)
#define SRAM_SCRATCH_Y_BASE _u(0x20081000)
#define SRAM_END _u(0x20082000)
#define SYSINFO_BASE _u(0x40000000)
#define SYSCFG_BASE _u(0x40008000)
#define CLOCKS_BASE _u(0x40010000)
#define PSM_BASE _u(0x40018000)
#define RESETS_BASE _u(0x40020000)
#define IO_BANK0_BASE _u(0x40028000)
#define IO_QSPI_BASE _u(0x40030000)
#define PADS_BANK0_BASE _u(0x40038000)
#define PADS_QSPI_BASE _u(0x40040000)
#define XOSC_BASE _u(0x40048000)
#define PLL_SYS_BASE _u(0x40050000)
#define PLL_USB_BASE _u(0x40058000)
#define ACCESSCTRL_BASE _u(0x40060000)
#define BUSCTRL_BASE _u(0x40068000)
#define UART0_BASE _u(0x40070000)
#define UART1_BASE _u(0x40078000)
#define SPI0_BASE _u(0x40080000)
#define SPI1_BASE _u(0x40088000)
#define I2C0_BASE _u(0x40090000)
#define I2C1_BASE _u(0x40098000)
#define ADC_BASE _u(0x400a0000)
#define PWM_BASE _u(0x400a8000)
#define TIMER0_BASE _u(0x400b0000)
#define TIMER1_BASE _u(0x400b8000)
#define HSTX_CTRL_BASE _u(0x400c0000)
#define XIP_CTRL_BASE _u(0x400c8000)
#define XIP_QMI_BASE _u(0x400d0000)
#define WATCHDOG_BASE _u(0x400d8000)
#define BOOTRAM_BASE _u(0x400e0000)
#define BOOTRAM_END _u(0x400e0400)
#define ROSC_BASE _u(0x400e8000)
#define TRNG_BASE _u(0x400f0000)
#define SHA256_BASE _u(0x400f8000)
#define POWMAN_BASE _u(0x40100000)
#define TICKS_BASE _u(0x40108000)
#define OTP_BASE _u(0x40120000)
#define OTP_DATA_BASE _u(0x40130000)
#define OTP_DATA_RAW_BASE _u(0x40134000)
#define OTP_DATA_GUARDED_BASE _u(0x40138000)
#define OTP_DATA_RAW_GUARDED_BASE _u(0x4013c000)
#define CORESIGHT_PERIPH_BASE _u(0x40140000)
#define CORESIGHT_ROMTABLE_BASE _u(0x40140000)
#define CORESIGHT_AHB_AP_CORE0_BASE _u(0x40142000)
#define CORESIGHT_AHB_AP_CORE1_BASE _u(0x40144000)
#define CORESIGHT_TIMESTAMP_GEN_BASE _u(0x40146000)
#define CORESIGHT_ATB_FUNNEL_BASE _u(0x40147000)
#define CORESIGHT_TPIU_BASE _u(0x40148000)
#define CORESIGHT_CTI_BASE _u(0x40149000)
#define CORESIGHT_APB_AP_RISCV_BASE _u(0x4014a000)
#define DFT_BASE _u(0x40150000)
#define GLITCH_DETECTOR_BASE _u(0x40158000)
#define TBMAN_BASE _u(0x40160000)
#define DMA_BASE _u(0x50000000)
#define USBCTRL_BASE _u(0x50100000)
#define USBCTRL_DPRAM_BASE _u(0x50100000)
#define USBCTRL_REGS_BASE _u(0x50110000)
#define PIO0_BASE _u(0x50200000)
#define PIO1_BASE _u(0x50300000)
#define PIO2_BASE _u(0x50400000)
#define XIP_AUX_BASE _u(0x50500000)
#define HSTX_FIFO_BASE _u(0x50600000)
#define CORESIGHT_TRACE_BASE _u(0x50700000)
#define SIO_BASE _u(0xd0000000)
#define SIO_NONSEC_BASE _u(0xd0020000)
#define PPB_BASE _u(0xe0000000)
#define PPB_NONSEC_BASE _u(0xe0020000)
#define EPPB_BASE _u(0xe0080000)
#endif // _ADDRESSMAP_H

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lib/pico-sdk/rp2350/hardware/regs/bootram.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : BOOTRAM
// Version : 1
// Bus type : apb
// Description : Additional registers mapped adjacent to the bootram, for use
// by the bootrom.
// =============================================================================
#ifndef _HARDWARE_REGS_BOOTRAM_H
#define _HARDWARE_REGS_BOOTRAM_H
// =============================================================================
// Register : BOOTRAM_WRITE_ONCE0
// Description : This registers always ORs writes into its current contents.
// Once a bit is set, it can only be cleared by a reset.
#define BOOTRAM_WRITE_ONCE0_OFFSET _u(0x00000800)
#define BOOTRAM_WRITE_ONCE0_BITS _u(0xffffffff)
#define BOOTRAM_WRITE_ONCE0_RESET _u(0x00000000)
#define BOOTRAM_WRITE_ONCE0_MSB _u(31)
#define BOOTRAM_WRITE_ONCE0_LSB _u(0)
#define BOOTRAM_WRITE_ONCE0_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_WRITE_ONCE1
// Description : This registers always ORs writes into its current contents.
// Once a bit is set, it can only be cleared by a reset.
#define BOOTRAM_WRITE_ONCE1_OFFSET _u(0x00000804)
#define BOOTRAM_WRITE_ONCE1_BITS _u(0xffffffff)
#define BOOTRAM_WRITE_ONCE1_RESET _u(0x00000000)
#define BOOTRAM_WRITE_ONCE1_MSB _u(31)
#define BOOTRAM_WRITE_ONCE1_LSB _u(0)
#define BOOTRAM_WRITE_ONCE1_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK_STAT
// Description : Bootlock status register. 1=unclaimed, 0=claimed. These locks
// function identically to the SIO spinlocks, but are reserved for
// bootrom use.
#define BOOTRAM_BOOTLOCK_STAT_OFFSET _u(0x00000808)
#define BOOTRAM_BOOTLOCK_STAT_BITS _u(0x000000ff)
#define BOOTRAM_BOOTLOCK_STAT_RESET _u(0x000000ff)
#define BOOTRAM_BOOTLOCK_STAT_MSB _u(7)
#define BOOTRAM_BOOTLOCK_STAT_LSB _u(0)
#define BOOTRAM_BOOTLOCK_STAT_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK0
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK0_OFFSET _u(0x0000080c)
#define BOOTRAM_BOOTLOCK0_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK0_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK0_MSB _u(31)
#define BOOTRAM_BOOTLOCK0_LSB _u(0)
#define BOOTRAM_BOOTLOCK0_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK1
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK1_OFFSET _u(0x00000810)
#define BOOTRAM_BOOTLOCK1_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK1_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK1_MSB _u(31)
#define BOOTRAM_BOOTLOCK1_LSB _u(0)
#define BOOTRAM_BOOTLOCK1_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK2
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK2_OFFSET _u(0x00000814)
#define BOOTRAM_BOOTLOCK2_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK2_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK2_MSB _u(31)
#define BOOTRAM_BOOTLOCK2_LSB _u(0)
#define BOOTRAM_BOOTLOCK2_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK3
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK3_OFFSET _u(0x00000818)
#define BOOTRAM_BOOTLOCK3_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK3_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK3_MSB _u(31)
#define BOOTRAM_BOOTLOCK3_LSB _u(0)
#define BOOTRAM_BOOTLOCK3_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK4
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK4_OFFSET _u(0x0000081c)
#define BOOTRAM_BOOTLOCK4_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK4_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK4_MSB _u(31)
#define BOOTRAM_BOOTLOCK4_LSB _u(0)
#define BOOTRAM_BOOTLOCK4_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK5
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK5_OFFSET _u(0x00000820)
#define BOOTRAM_BOOTLOCK5_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK5_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK5_MSB _u(31)
#define BOOTRAM_BOOTLOCK5_LSB _u(0)
#define BOOTRAM_BOOTLOCK5_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK6
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK6_OFFSET _u(0x00000824)
#define BOOTRAM_BOOTLOCK6_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK6_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK6_MSB _u(31)
#define BOOTRAM_BOOTLOCK6_LSB _u(0)
#define BOOTRAM_BOOTLOCK6_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK7
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK7_OFFSET _u(0x00000828)
#define BOOTRAM_BOOTLOCK7_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK7_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK7_MSB _u(31)
#define BOOTRAM_BOOTLOCK7_LSB _u(0)
#define BOOTRAM_BOOTLOCK7_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_BOOTRAM_H

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lib/pico-sdk/rp2350/hardware/regs/busctrl.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : BUSCTRL
// Version : 1
// Bus type : apb
// Description : Register block for busfabric control signals and performance
// counters
// =============================================================================
#ifndef _HARDWARE_REGS_BUSCTRL_H
#define _HARDWARE_REGS_BUSCTRL_H
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY
// Description : Set the priority of each master for bus arbitration.
#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111)
#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_W
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000)
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_R
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100)
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC1
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010)
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC0
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001)
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY_ACK
// Description : Bus priority acknowledge
// Goes to 1 once all arbiters have registered the new global
// priority levels.
// Arbiters update their local priority when servicing a new
// nonsequential access.
// In normal circumstances this will happen almost immediately.
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001)
#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000)
#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
// =============================================================================
// Register : BUSCTRL_PERFCTR_EN
// Description : Enable the performance counters. If 0, the performance counters
// do not increment. This can be used to precisely start/stop
// event sampling around the profiled section of code.
//
// The performance counters are initially disabled, to save
// energy.
#define BUSCTRL_PERFCTR_EN_OFFSET _u(0x00000008)
#define BUSCTRL_PERFCTR_EN_BITS _u(0x00000001)
#define BUSCTRL_PERFCTR_EN_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR_EN_MSB _u(0)
#define BUSCTRL_PERFCTR_EN_LSB _u(0)
#define BUSCTRL_PERFCTR_EN_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_PERFCTR0
// Description : Bus fabric performance counter 0
// Busfabric saturating performance counter 0
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL0
#define BUSCTRL_PERFCTR0_OFFSET _u(0x0000000c)
#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR0_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR0_MSB _u(23)
#define BUSCTRL_PERFCTR0_LSB _u(0)
#define BUSCTRL_PERFCTR0_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL0
// Description : Bus fabric performance event select for PERFCTR0
// Select an event for PERFCTR0. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL0_OFFSET _u(0x00000010)
#define BUSCTRL_PERFSEL0_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL0_MSB _u(6)
#define BUSCTRL_PERFSEL0_LSB _u(0)
#define BUSCTRL_PERFSEL0_ACCESS "RW"
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR1
// Description : Bus fabric performance counter 1
// Busfabric saturating performance counter 1
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL1
#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000014)
#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR1_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR1_MSB _u(23)
#define BUSCTRL_PERFCTR1_LSB _u(0)
#define BUSCTRL_PERFCTR1_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL1
// Description : Bus fabric performance event select for PERFCTR1
// Select an event for PERFCTR1. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000018)
#define BUSCTRL_PERFSEL1_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL1_MSB _u(6)
#define BUSCTRL_PERFSEL1_LSB _u(0)
#define BUSCTRL_PERFSEL1_ACCESS "RW"
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR2
// Description : Bus fabric performance counter 2
// Busfabric saturating performance counter 2
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL2
#define BUSCTRL_PERFCTR2_OFFSET _u(0x0000001c)
#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR2_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR2_MSB _u(23)
#define BUSCTRL_PERFCTR2_LSB _u(0)
#define BUSCTRL_PERFCTR2_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL2
// Description : Bus fabric performance event select for PERFCTR2
// Select an event for PERFCTR2. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL2_OFFSET _u(0x00000020)
#define BUSCTRL_PERFSEL2_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL2_MSB _u(6)
#define BUSCTRL_PERFSEL2_LSB _u(0)
#define BUSCTRL_PERFSEL2_ACCESS "RW"
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR3
// Description : Bus fabric performance counter 3
// Busfabric saturating performance counter 3
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL3
#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000024)
#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR3_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR3_MSB _u(23)
#define BUSCTRL_PERFCTR3_LSB _u(0)
#define BUSCTRL_PERFCTR3_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL3
// Description : Bus fabric performance event select for PERFCTR3
// Select an event for PERFCTR3. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000028)
#define BUSCTRL_PERFSEL3_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL3_MSB _u(6)
#define BUSCTRL_PERFSEL3_LSB _u(0)
#define BUSCTRL_PERFSEL3_ACCESS "RW"
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
#endif // _HARDWARE_REGS_BUSCTRL_H

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lib/pico-sdk/rp2350/hardware/regs/clocks.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/coresight_trace.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : CORESIGHT_TRACE
// Version : 1
// Bus type : ahbl
// Description : Coresight block - RP specific registers
// =============================================================================
#ifndef _HARDWARE_REGS_CORESIGHT_TRACE_H
#define _HARDWARE_REGS_CORESIGHT_TRACE_H
// =============================================================================
// Register : CORESIGHT_TRACE_CTRL_STATUS
// Description : Control and status register
#define CORESIGHT_TRACE_CTRL_STATUS_OFFSET _u(0x00000000)
#define CORESIGHT_TRACE_CTRL_STATUS_BITS _u(0x00000003)
#define CORESIGHT_TRACE_CTRL_STATUS_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW
// Description : This status flag is set high when trace data has been dropped
// due to the FIFO being full at the point trace data was sampled.
// Write 1 to acknowledge and clear the bit.
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_RESET _u(0x0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_BITS _u(0x00000002)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_MSB _u(1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_LSB _u(1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH
// Description : Set to 1 to continuously hold the trace FIFO in a flushed state
// and prevent overflow.
//
// Before clearing this flag, configure and start a DMA channel
// with the correct DREQ for the TRACE_CAPTURE_FIFO register.
//
// Clear this flag to begin sampling trace data, and set once
// again once the trace capture buffer is full. You must configure
// the TPIU in order to generate trace packets to be captured, as
// well as components like the ETM further upstream to generate
// the event stream propagated to the TPIU.
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_RESET _u(0x1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_BITS _u(0x00000001)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_MSB _u(0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_LSB _u(0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_ACCESS "RW"
// =============================================================================
// Register : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO
// Description : FIFO for trace data captured from the TPIU
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET _u(0x00000004)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_BITS _u(0xffffffff)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA
// Description : Read from an 8 x 32-bit FIFO containing trace data captured
// from the TPIU.
//
// Hardware pushes to the FIFO on rising edges of clk_sys, when
// either of the following is true:
//
// * TPIU TRACECTL output is low (normal trace data)
//
// * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and
// TRACEDATA1 are both low (trigger packet)
//
// These conditions are in accordance with Arm Coresight
// Architecture Spec v3.0 section D3.3.3: Decoding requirements
// for Trace Capture Devices
//
// The data captured into the FIFO is the full 32-bit TRACEDATA
// bus output by the TPIU. Note that the TPIU is a DDR output at
// half of clk_sys, therefore this interface can capture the full
// 32-bit TPIU DDR output bandwidth as it samples once per active
// edge of the TPIU output clock.
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_RESET _u(0x00000000)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_BITS _u(0xffffffff)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MSB _u(31)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_LSB _u(0)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_CORESIGHT_TRACE_H

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lib/pico-sdk/rp2350/hardware/regs/dma.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/dreq.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _DREQ_H
#define _DREQ_H
/**
* \file rp2350/dreq.h
*/
#ifdef __ASSEMBLER__
#define DREQ_PIO0_TX0 0
#define DREQ_PIO0_TX1 1
#define DREQ_PIO0_TX2 2
#define DREQ_PIO0_TX3 3
#define DREQ_PIO0_RX0 4
#define DREQ_PIO0_RX1 5
#define DREQ_PIO0_RX2 6
#define DREQ_PIO0_RX3 7
#define DREQ_PIO1_TX0 8
#define DREQ_PIO1_TX1 9
#define DREQ_PIO1_TX2 10
#define DREQ_PIO1_TX3 11
#define DREQ_PIO1_RX0 12
#define DREQ_PIO1_RX1 13
#define DREQ_PIO1_RX2 14
#define DREQ_PIO1_RX3 15
#define DREQ_PIO2_TX0 16
#define DREQ_PIO2_TX1 17
#define DREQ_PIO2_TX2 18
#define DREQ_PIO2_TX3 19
#define DREQ_PIO2_RX0 20
#define DREQ_PIO2_RX1 21
#define DREQ_PIO2_RX2 22
#define DREQ_PIO2_RX3 23
#define DREQ_SPI0_TX 24
#define DREQ_SPI0_RX 25
#define DREQ_SPI1_TX 26
#define DREQ_SPI1_RX 27
#define DREQ_UART0_TX 28
#define DREQ_UART0_RX 29
#define DREQ_UART1_TX 30
#define DREQ_UART1_RX 31
#define DREQ_PWM_WRAP0 32
#define DREQ_PWM_WRAP1 33
#define DREQ_PWM_WRAP2 34
#define DREQ_PWM_WRAP3 35
#define DREQ_PWM_WRAP4 36
#define DREQ_PWM_WRAP5 37
#define DREQ_PWM_WRAP6 38
#define DREQ_PWM_WRAP7 39
#define DREQ_PWM_WRAP8 40
#define DREQ_PWM_WRAP9 41
#define DREQ_PWM_WRAP10 42
#define DREQ_PWM_WRAP11 43
#define DREQ_I2C0_TX 44
#define DREQ_I2C0_RX 45
#define DREQ_I2C1_TX 46
#define DREQ_I2C1_RX 47
#define DREQ_ADC 48
#define DREQ_XIP_STREAM 49
#define DREQ_XIP_QMITX 50
#define DREQ_XIP_QMIRX 51
#define DREQ_HSTX 52
#define DREQ_CORESIGHT 53
#define DREQ_SHA256 54
#define DREQ_DMA_TIMER0 59
#define DREQ_DMA_TIMER1 60
#define DREQ_DMA_TIMER2 61
#define DREQ_DMA_TIMER3 62
#define DREQ_FORCE 63
#else
/**
* \brief DREQ numbers for DMA pacing on RP2350 (used as typedef \ref dreq_num_t)
* \ingroup hardware_dma
*/
typedef enum dreq_num_rp2350 {
DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ
DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ
DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ
DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ
DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ
DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ
DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ
DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ
DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ
DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ
DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ
DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ
DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ
DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ
DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ
DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ
DREQ_PIO2_TX0 = 16, ///< Select PIO2's TX FIFO 0 as DREQ
DREQ_PIO2_TX1 = 17, ///< Select PIO2's TX FIFO 1 as DREQ
DREQ_PIO2_TX2 = 18, ///< Select PIO2's TX FIFO 2 as DREQ
DREQ_PIO2_TX3 = 19, ///< Select PIO2's TX FIFO 3 as DREQ
DREQ_PIO2_RX0 = 20, ///< Select PIO2's RX FIFO 0 as DREQ
DREQ_PIO2_RX1 = 21, ///< Select PIO2's RX FIFO 1 as DREQ
DREQ_PIO2_RX2 = 22, ///< Select PIO2's RX FIFO 2 as DREQ
DREQ_PIO2_RX3 = 23, ///< Select PIO2's RX FIFO 3 as DREQ
DREQ_SPI0_TX = 24, ///< Select SPI0's TX FIFO as DREQ
DREQ_SPI0_RX = 25, ///< Select SPI0's RX FIFO as DREQ
DREQ_SPI1_TX = 26, ///< Select SPI1's TX FIFO as DREQ
DREQ_SPI1_RX = 27, ///< Select SPI1's RX FIFO as DREQ
DREQ_UART0_TX = 28, ///< Select UART0's TX FIFO as DREQ
DREQ_UART0_RX = 29, ///< Select UART0's RX FIFO as DREQ
DREQ_UART1_TX = 30, ///< Select UART1's TX FIFO as DREQ
DREQ_UART1_RX = 31, ///< Select UART1's RX FIFO as DREQ
DREQ_PWM_WRAP0 = 32, ///< Select PWM Counter 0's Wrap Value as DREQ
DREQ_PWM_WRAP1 = 33, ///< Select PWM Counter 1's Wrap Value as DREQ
DREQ_PWM_WRAP2 = 34, ///< Select PWM Counter 2's Wrap Value as DREQ
DREQ_PWM_WRAP3 = 35, ///< Select PWM Counter 3's Wrap Value as DREQ
DREQ_PWM_WRAP4 = 36, ///< Select PWM Counter 4's Wrap Value as DREQ
DREQ_PWM_WRAP5 = 37, ///< Select PWM Counter 5's Wrap Value as DREQ
DREQ_PWM_WRAP6 = 38, ///< Select PWM Counter 6's Wrap Value as DREQ
DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ
DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ
DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ
DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ
DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ
DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ
DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ
DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ
DREQ_I2C1_RX = 47, ///< Select I2C1's RX FIFO as DREQ
DREQ_ADC = 48, ///< Select the ADC as DREQ
DREQ_XIP_STREAM = 49, ///< Select the XIP Streaming FIFO as DREQ
DREQ_XIP_QMITX = 50, ///< Select XIP_QMITX as DREQ
DREQ_XIP_QMIRX = 51, ///< Select XIP_QMIRX as DREQ
DREQ_HSTX = 52, ///< Select HSTX as DREQ
DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ
DREQ_SHA256 = 54, ///< Select SHA256 as DREQ
DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
DREQ_FORCE = 63, ///< Select FORCE as DREQ
DREQ_COUNT
} dreq_num_t;
#endif
#endif // _DREQ_H

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lib/pico-sdk/rp2350/hardware/regs/glitch_detector.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : GLITCH_DETECTOR
// Version : 1
// Bus type : apb
// Description : Glitch detector controls
// =============================================================================
#ifndef _HARDWARE_REGS_GLITCH_DETECTOR_H
#define _HARDWARE_REGS_GLITCH_DETECTOR_H
// =============================================================================
// Register : GLITCH_DETECTOR_ARM
// Description : Forcibly arm the glitch detectors, if they are not already
// armed by OTP. When armed, any individual detector trigger will
// cause a restart of the switched core power domain's power-on
// reset state machine.
//
// Glitch detector triggers are recorded accumulatively in
// TRIG_STATUS. If the system is reset by a glitch detector
// trigger, this is recorded in POWMAN_CHIP_RESET.
//
// This register is Secure read/write only.
// 0x5bad -> Do not force the glitch detectors to be armed
// 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)
#define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000)
#define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff)
#define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad)
#define GLITCH_DETECTOR_ARM_MSB _u(15)
#define GLITCH_DETECTOR_ARM_LSB _u(0)
#define GLITCH_DETECTOR_ARM_ACCESS "RW"
#define GLITCH_DETECTOR_ARM_VALUE_NO _u(0x5bad)
#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000)
// =============================================================================
// Register : GLITCH_DETECTOR_DISARM
// Description : None
// Forcibly disarm the glitch detectors, if they are armed by OTP.
// Ignored if ARM is YES.
//
// This register is Secure read/write only.
// 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)
// 0xdcaf -> Disarm the glitch detectors
#define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004)
#define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff)
#define GLITCH_DETECTOR_DISARM_RESET _u(0x00000000)
#define GLITCH_DETECTOR_DISARM_MSB _u(15)
#define GLITCH_DETECTOR_DISARM_LSB _u(0)
#define GLITCH_DETECTOR_DISARM_ACCESS "RW"
#define GLITCH_DETECTOR_DISARM_VALUE_NO _u(0x0000)
#define GLITCH_DETECTOR_DISARM_VALUE_YES _u(0xdcaf)
// =============================================================================
// Register : GLITCH_DETECTOR_SENSITIVITY
// Description : Adjust the sensitivity of glitch detectors to values other than
// their OTP-provided defaults.
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_SENSITIVITY_OFFSET _u(0x00000008)
#define GLITCH_DETECTOR_SENSITIVITY_BITS _u(0xff00ffff)
#define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT
// 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)
// 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register.
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_LSB _u(24)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_ACCESS "RW"
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_YES _u(0x00)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_NO _u(0xde)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET3_INV
// Description : Must be the inverse of DET3, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_BITS _u(0x0000c000)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MSB _u(15)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_LSB _u(14)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET2_INV
// Description : Must be the inverse of DET2, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_BITS _u(0x00003000)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MSB _u(13)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_LSB _u(12)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET1_INV
// Description : Must be the inverse of DET1, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_BITS _u(0x00000c00)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MSB _u(11)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_LSB _u(10)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET0_INV
// Description : Must be the inverse of DET0, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_BITS _u(0x00000300)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MSB _u(9)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_LSB _u(8)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET3
// Description : Set sensitivity for detector 3. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET3_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_BITS _u(0x000000c0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_MSB _u(7)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_LSB _u(6)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET2
// Description : Set sensitivity for detector 2. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET2_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_BITS _u(0x00000030)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_MSB _u(5)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_LSB _u(4)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET1
// Description : Set sensitivity for detector 1. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET1_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_BITS _u(0x0000000c)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_MSB _u(3)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_LSB _u(2)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET0
// Description : Set sensitivity for detector 0. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET0_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_BITS _u(0x00000003)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_MSB _u(1)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_LSB _u(0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW"
// =============================================================================
// Register : GLITCH_DETECTOR_LOCK
// Description : None
// Write any nonzero value to disable writes to ARM, DISARM,
// SENSITIVITY and LOCK. This register is Secure read/write only.
#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c)
#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff)
#define GLITCH_DETECTOR_LOCK_RESET _u(0x00000000)
#define GLITCH_DETECTOR_LOCK_MSB _u(7)
#define GLITCH_DETECTOR_LOCK_LSB _u(0)
#define GLITCH_DETECTOR_LOCK_ACCESS "RW"
// =============================================================================
// Register : GLITCH_DETECTOR_TRIG_STATUS
// Description : Set when a detector output triggers. Write-1-clear.
//
// (May immediately return high if the detector remains in a
// failed state. Detectors can only be cleared by a full reset of
// the switched core power domain.)
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_TRIG_STATUS_OFFSET _u(0x00000010)
#define GLITCH_DETECTOR_TRIG_STATUS_BITS _u(0x0000000f)
#define GLITCH_DETECTOR_TRIG_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET3
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_BITS _u(0x00000008)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_MSB _u(3)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_LSB _u(3)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET2
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_BITS _u(0x00000004)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_MSB _u(2)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_LSB _u(2)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET1
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_BITS _u(0x00000002)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_MSB _u(1)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_LSB _u(1)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET0
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_BITS _u(0x00000001)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_MSB _u(0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_LSB _u(0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_ACCESS "WC"
// =============================================================================
// Register : GLITCH_DETECTOR_TRIG_FORCE
// Description : Simulate the firing of one or more detectors. Writing ones to
// this register will set the matching bits in STATUS_TRIG.
//
// If the glitch detectors are currently armed, writing ones will
// also immediately reset the switched core power domain, and set
// the reset reason latches in POWMAN_CHIP_RESET to indicate a
// glitch detector resets.
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_TRIG_FORCE_OFFSET _u(0x00000014)
#define GLITCH_DETECTOR_TRIG_FORCE_BITS _u(0x0000000f)
#define GLITCH_DETECTOR_TRIG_FORCE_RESET _u(0x00000000)
#define GLITCH_DETECTOR_TRIG_FORCE_MSB _u(3)
#define GLITCH_DETECTOR_TRIG_FORCE_LSB _u(0)
#define GLITCH_DETECTOR_TRIG_FORCE_ACCESS "SC"
// =============================================================================
#endif // _HARDWARE_REGS_GLITCH_DETECTOR_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : HSTX_CTRL
// Version : 0
// Bus type : apb
// Description : Control interface to HSTX. For FIFO write access and status,
// see the HSTX_FIFO register block.
// =============================================================================
#ifndef _HARDWARE_REGS_HSTX_CTRL_H
#define _HARDWARE_REGS_HSTX_CTRL_H
// =============================================================================
// Register : HSTX_CTRL_CSR
#define HSTX_CTRL_CSR_OFFSET _u(0x00000000)
#define HSTX_CTRL_CSR_BITS _u(0xff1f1f73)
#define HSTX_CTRL_CSR_RESET _u(0x10050600)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_CLKDIV
// Description : Clock period of the generated clock, measured in HSTX clock
// cycles. Can be odd or even. The generated clock advances only
// on cycles where the shift register shifts.
//
// For example, a clkdiv of 5 would generate a complete output
// clock period for every 5 HSTX clocks (or every 10 half-clocks).
//
// A CLKDIV value of 0 is mapped to a period of 16 HSTX clock
// cycles.
#define HSTX_CTRL_CSR_CLKDIV_RESET _u(0x1)
#define HSTX_CTRL_CSR_CLKDIV_BITS _u(0xf0000000)
#define HSTX_CTRL_CSR_CLKDIV_MSB _u(31)
#define HSTX_CTRL_CSR_CLKDIV_LSB _u(28)
#define HSTX_CTRL_CSR_CLKDIV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_CLKPHASE
// Description : Set the initial phase of the generated clock.
//
// A CLKPHASE of 0 means the clock is initially low, and the first
// rising edge occurs after one half period of the generated clock
// (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1
// will advance the initial clock phase by one half clk_hstx
// period. For example, if CLKDIV=2 and CLKPHASE=1:
//
// * The clock will be initially low
//
// * The first rising edge will be 0.5 clk_hstx cycles after
// asserting first data
//
// * The first falling edge will be 1.5 clk_hstx cycles after
// asserting first data
//
// This configuration would be suitable for serialising at a bit
// rate of clk_hstx with a centre-aligned DDR clock.
//
// When the HSTX is halted by clearing CSR_EN, the clock generator
// will return to its initial phase as configured by the CLKPHASE
// field.
//
// Note CLKPHASE must be strictly less than double the value of
// CLKDIV (one full period), else its operation is undefined.
#define HSTX_CTRL_CSR_CLKPHASE_RESET _u(0x0)
#define HSTX_CTRL_CSR_CLKPHASE_BITS _u(0x0f000000)
#define HSTX_CTRL_CSR_CLKPHASE_MSB _u(27)
#define HSTX_CTRL_CSR_CLKPHASE_LSB _u(24)
#define HSTX_CTRL_CSR_CLKPHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_N_SHIFTS
// Description : Number of times to shift the shift register before refilling it
// from the FIFO. (A count of how many times it has been shifted,
// *not* the total shift distance.)
//
// A register value of 0 means shift 32 times.
#define HSTX_CTRL_CSR_N_SHIFTS_RESET _u(0x05)
#define HSTX_CTRL_CSR_N_SHIFTS_BITS _u(0x001f0000)
#define HSTX_CTRL_CSR_N_SHIFTS_MSB _u(20)
#define HSTX_CTRL_CSR_N_SHIFTS_LSB _u(16)
#define HSTX_CTRL_CSR_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_SHIFT
// Description : How many bits to right-rotate the shift register by each cycle.
//
// The use of a rotate rather than a shift allows left shifts to
// be emulated, by subtracting the left-shift amount from 32. It
// also allows data to be repeated, when the product of SHIFT and
// N_SHIFTS is greater than 32.
#define HSTX_CTRL_CSR_SHIFT_RESET _u(0x06)
#define HSTX_CTRL_CSR_SHIFT_BITS _u(0x00001f00)
#define HSTX_CTRL_CSR_SHIFT_MSB _u(12)
#define HSTX_CTRL_CSR_SHIFT_LSB _u(8)
#define HSTX_CTRL_CSR_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_COUPLED_SEL
// Description : Select which PIO to use for coupled mode operation.
#define HSTX_CTRL_CSR_COUPLED_SEL_RESET _u(0x0)
#define HSTX_CTRL_CSR_COUPLED_SEL_BITS _u(0x00000060)
#define HSTX_CTRL_CSR_COUPLED_SEL_MSB _u(6)
#define HSTX_CTRL_CSR_COUPLED_SEL_LSB _u(5)
#define HSTX_CTRL_CSR_COUPLED_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_COUPLED_MODE
// Description : Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked
// *directly* from the system clock (not just from some other
// clock source of the same frequency) for this synchronous
// interface to function correctly.
//
// When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24
// through 31 will select bits from the 8-bit PIO-to-HSTX path,
// rather than shifter bits. Indices of 0 through 23 will still
// index the shift register as normal.
//
// The PIO outputs connected to the PIO-to-HSTX bus are those same
// outputs that would appear on the HSTX-capable pins if those
// pins' FUNCSELs were set to PIO instead of HSTX.
//
// For example, if HSTX is on GPIOs 12 through 19, then PIO
// outputs 12 through 19 are connected to the HSTX when coupled
// mode is engaged.
#define HSTX_CTRL_CSR_COUPLED_MODE_RESET _u(0x0)
#define HSTX_CTRL_CSR_COUPLED_MODE_BITS _u(0x00000010)
#define HSTX_CTRL_CSR_COUPLED_MODE_MSB _u(4)
#define HSTX_CTRL_CSR_COUPLED_MODE_LSB _u(4)
#define HSTX_CTRL_CSR_COUPLED_MODE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_EXPAND_EN
// Description : Enable the command expander. When 0, raw FIFO data is passed
// directly to the output shift register. When 1, the command
// expander can perform simple operations such as run length
// decoding on data between the FIFO and the shift register.
//
// Do not change CXPD_EN whilst EN is set. It's safe to set
// CXPD_EN simultaneously with setting EN.
#define HSTX_CTRL_CSR_EXPAND_EN_RESET _u(0x0)
#define HSTX_CTRL_CSR_EXPAND_EN_BITS _u(0x00000002)
#define HSTX_CTRL_CSR_EXPAND_EN_MSB _u(1)
#define HSTX_CTRL_CSR_EXPAND_EN_LSB _u(1)
#define HSTX_CTRL_CSR_EXPAND_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_EN
// Description : When EN is 1, the HSTX will shift out data as it appears in the
// FIFO. As long as there is data, the HSTX shift register will
// shift once per clock cycle, and the frequency of popping from
// the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH.
//
// When EN is 0, the FIFO is not popped. The shift counter and
// clock generator are also reset to their initial state for as
// long as EN is low. Note the initial phase of the clock
// generator can be configured by the CLKPHASE field.
//
// Once the HSTX is enabled again, and data is pushed to the FIFO,
// the generated clock's first rising edge will be one half-period
// after the first data is launched.
#define HSTX_CTRL_CSR_EN_RESET _u(0x0)
#define HSTX_CTRL_CSR_EN_BITS _u(0x00000001)
#define HSTX_CTRL_CSR_EN_MSB _u(0)
#define HSTX_CTRL_CSR_EN_LSB _u(0)
#define HSTX_CTRL_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT0
// Description : Data control register for output bit 0
#define HSTX_CTRL_BIT0_OFFSET _u(0x00000004)
#define HSTX_CTRL_BIT0_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT0_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT0_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT0_CLK_MSB _u(17)
#define HSTX_CTRL_BIT0_CLK_LSB _u(17)
#define HSTX_CTRL_BIT0_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT0_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT0_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT0_INV_MSB _u(16)
#define HSTX_CTRL_BIT0_INV_LSB _u(16)
#define HSTX_CTRL_BIT0_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT0_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT0_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT0_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT0_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT0_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT0_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT0_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT0_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT0_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT0_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT1
// Description : Data control register for output bit 1
#define HSTX_CTRL_BIT1_OFFSET _u(0x00000008)
#define HSTX_CTRL_BIT1_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT1_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT1_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT1_CLK_MSB _u(17)
#define HSTX_CTRL_BIT1_CLK_LSB _u(17)
#define HSTX_CTRL_BIT1_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT1_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT1_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT1_INV_MSB _u(16)
#define HSTX_CTRL_BIT1_INV_LSB _u(16)
#define HSTX_CTRL_BIT1_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT1_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT1_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT1_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT1_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT1_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT1_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT1_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT1_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT1_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT1_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT2
// Description : Data control register for output bit 2
#define HSTX_CTRL_BIT2_OFFSET _u(0x0000000c)
#define HSTX_CTRL_BIT2_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT2_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT2_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT2_CLK_MSB _u(17)
#define HSTX_CTRL_BIT2_CLK_LSB _u(17)
#define HSTX_CTRL_BIT2_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT2_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT2_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT2_INV_MSB _u(16)
#define HSTX_CTRL_BIT2_INV_LSB _u(16)
#define HSTX_CTRL_BIT2_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT2_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT2_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT2_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT2_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT2_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT2_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT2_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT2_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT2_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT2_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT3
// Description : Data control register for output bit 3
#define HSTX_CTRL_BIT3_OFFSET _u(0x00000010)
#define HSTX_CTRL_BIT3_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT3_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT3_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT3_CLK_MSB _u(17)
#define HSTX_CTRL_BIT3_CLK_LSB _u(17)
#define HSTX_CTRL_BIT3_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT3_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT3_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT3_INV_MSB _u(16)
#define HSTX_CTRL_BIT3_INV_LSB _u(16)
#define HSTX_CTRL_BIT3_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT3_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT3_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT3_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT3_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT3_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT3_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT3_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT3_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT3_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT3_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT4
// Description : Data control register for output bit 4
#define HSTX_CTRL_BIT4_OFFSET _u(0x00000014)
#define HSTX_CTRL_BIT4_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT4_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT4_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT4_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT4_CLK_MSB _u(17)
#define HSTX_CTRL_BIT4_CLK_LSB _u(17)
#define HSTX_CTRL_BIT4_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT4_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT4_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT4_INV_MSB _u(16)
#define HSTX_CTRL_BIT4_INV_LSB _u(16)
#define HSTX_CTRL_BIT4_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT4_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT4_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT4_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT4_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT4_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT4_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT4_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT4_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT4_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT4_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT5
// Description : Data control register for output bit 5
#define HSTX_CTRL_BIT5_OFFSET _u(0x00000018)
#define HSTX_CTRL_BIT5_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT5_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT5_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT5_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT5_CLK_MSB _u(17)
#define HSTX_CTRL_BIT5_CLK_LSB _u(17)
#define HSTX_CTRL_BIT5_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT5_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT5_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT5_INV_MSB _u(16)
#define HSTX_CTRL_BIT5_INV_LSB _u(16)
#define HSTX_CTRL_BIT5_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT5_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT5_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT5_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT5_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT5_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT5_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT5_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT5_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT5_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT5_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT6
// Description : Data control register for output bit 6
#define HSTX_CTRL_BIT6_OFFSET _u(0x0000001c)
#define HSTX_CTRL_BIT6_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT6_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT6_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT6_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT6_CLK_MSB _u(17)
#define HSTX_CTRL_BIT6_CLK_LSB _u(17)
#define HSTX_CTRL_BIT6_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT6_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT6_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT6_INV_MSB _u(16)
#define HSTX_CTRL_BIT6_INV_LSB _u(16)
#define HSTX_CTRL_BIT6_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT6_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT6_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT6_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT6_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT6_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT6_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT6_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT6_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT6_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT6_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT7
// Description : Data control register for output bit 7
#define HSTX_CTRL_BIT7_OFFSET _u(0x00000020)
#define HSTX_CTRL_BIT7_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT7_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT7_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT7_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT7_CLK_MSB _u(17)
#define HSTX_CTRL_BIT7_CLK_LSB _u(17)
#define HSTX_CTRL_BIT7_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT7_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT7_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT7_INV_MSB _u(16)
#define HSTX_CTRL_BIT7_INV_LSB _u(16)
#define HSTX_CTRL_BIT7_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT7_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT7_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT7_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT7_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT7_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT7_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT7_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT7_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT7_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT7_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_EXPAND_SHIFT
// Description : Configure the optional shifter inside the command expander
#define HSTX_CTRL_EXPAND_SHIFT_OFFSET _u(0x00000024)
#define HSTX_CTRL_EXPAND_SHIFT_BITS _u(0x1f1f1f1f)
#define HSTX_CTRL_EXPAND_SHIFT_RESET _u(0x01000100)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS
// Description : Number of times to consume from the shift register before
// refilling it from the FIFO, when the current command is an
// encoded data command (e.g. TMDS). A register value of 0 means
// shift 32 times.
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_RESET _u(0x01)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_BITS _u(0x1f000000)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MSB _u(28)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_LSB _u(24)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT
// Description : How many bits to right-rotate the shift register by each time
// data is pushed to the output shifter, when the current command
// is an encoded data command (e.g. TMDS).
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_BITS _u(0x001f0000)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MSB _u(20)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_LSB _u(16)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS
// Description : Number of times to consume from the shift register before
// refilling it from the FIFO, when the current command is a raw
// data command. A register value of 0 means shift 32 times.
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_RESET _u(0x01)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_BITS _u(0x00001f00)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MSB _u(12)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_LSB _u(8)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT
// Description : How many bits to right-rotate the shift register by each time
// data is pushed to the output shifter, when the current command
// is a raw data command.
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_BITS _u(0x0000001f)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MSB _u(4)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_LSB _u(0)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_EXPAND_TMDS
// Description : Configure the optional TMDS encoder inside the command expander
#define HSTX_CTRL_EXPAND_TMDS_OFFSET _u(0x00000028)
#define HSTX_CTRL_EXPAND_TMDS_BITS _u(0x00ffffff)
#define HSTX_CTRL_EXPAND_TMDS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L2_NBITS
// Description : Number of valid data bits for the lane 2 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_BITS _u(0x00e00000)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MSB _u(23)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB _u(21)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L2_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 2 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_BITS _u(0x001f0000)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_MSB _u(20)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB _u(16)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L1_NBITS
// Description : Number of valid data bits for the lane 1 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_BITS _u(0x0000e000)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MSB _u(15)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB _u(13)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L1_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 1 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_BITS _u(0x00001f00)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_MSB _u(12)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB _u(8)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L0_NBITS
// Description : Number of valid data bits for the lane 0 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_BITS _u(0x000000e0)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MSB _u(7)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB _u(5)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L0_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 0 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_BITS _u(0x0000001f)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_MSB _u(4)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB _u(0)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_HSTX_CTRL_H

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lib/pico-sdk/rp2350/hardware/regs/hstx_fifo.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : HSTX_FIFO
// Version : 1
// Bus type : ahbl
// Description : FIFO status and write access for HSTX
// =============================================================================
#ifndef _HARDWARE_REGS_HSTX_FIFO_H
#define _HARDWARE_REGS_HSTX_FIFO_H
// =============================================================================
// Register : HSTX_FIFO_STAT
// Description : FIFO status
#define HSTX_FIFO_STAT_OFFSET _u(0x00000000)
#define HSTX_FIFO_STAT_BITS _u(0x000007ff)
#define HSTX_FIFO_STAT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_WOF
// Description : FIFO was written when full. Write 1 to clear.
#define HSTX_FIFO_STAT_WOF_RESET _u(0x0)
#define HSTX_FIFO_STAT_WOF_BITS _u(0x00000400)
#define HSTX_FIFO_STAT_WOF_MSB _u(10)
#define HSTX_FIFO_STAT_WOF_LSB _u(10)
#define HSTX_FIFO_STAT_WOF_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_EMPTY
#define HSTX_FIFO_STAT_EMPTY_RESET "-"
#define HSTX_FIFO_STAT_EMPTY_BITS _u(0x00000200)
#define HSTX_FIFO_STAT_EMPTY_MSB _u(9)
#define HSTX_FIFO_STAT_EMPTY_LSB _u(9)
#define HSTX_FIFO_STAT_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_FULL
#define HSTX_FIFO_STAT_FULL_RESET "-"
#define HSTX_FIFO_STAT_FULL_BITS _u(0x00000100)
#define HSTX_FIFO_STAT_FULL_MSB _u(8)
#define HSTX_FIFO_STAT_FULL_LSB _u(8)
#define HSTX_FIFO_STAT_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_LEVEL
#define HSTX_FIFO_STAT_LEVEL_RESET _u(0x00)
#define HSTX_FIFO_STAT_LEVEL_BITS _u(0x000000ff)
#define HSTX_FIFO_STAT_LEVEL_MSB _u(7)
#define HSTX_FIFO_STAT_LEVEL_LSB _u(0)
#define HSTX_FIFO_STAT_LEVEL_ACCESS "RO"
// =============================================================================
// Register : HSTX_FIFO_FIFO
// Description : Write access to FIFO
#define HSTX_FIFO_FIFO_OFFSET _u(0x00000004)
#define HSTX_FIFO_FIFO_BITS _u(0xffffffff)
#define HSTX_FIFO_FIFO_RESET _u(0x00000000)
#define HSTX_FIFO_FIFO_MSB _u(31)
#define HSTX_FIFO_FIFO_LSB _u(0)
#define HSTX_FIFO_FIFO_ACCESS "WF"
// =============================================================================
#endif // _HARDWARE_REGS_HSTX_FIFO_H

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lib/pico-sdk/rp2350/hardware/regs/i2c.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/intctrl.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _INTCTRL_H
#define _INTCTRL_H
/**
* \file rp2350/intctrl.h
*/
#ifdef __ASSEMBLER__
#define TIMER0_IRQ_0 0
#define TIMER0_IRQ_1 1
#define TIMER0_IRQ_2 2
#define TIMER0_IRQ_3 3
#define TIMER1_IRQ_0 4
#define TIMER1_IRQ_1 5
#define TIMER1_IRQ_2 6
#define TIMER1_IRQ_3 7
#define PWM_IRQ_WRAP_0 8
#define PWM_IRQ_WRAP_1 9
#define DMA_IRQ_0 10
#define DMA_IRQ_1 11
#define DMA_IRQ_2 12
#define DMA_IRQ_3 13
#define USBCTRL_IRQ 14
#define PIO0_IRQ_0 15
#define PIO0_IRQ_1 16
#define PIO1_IRQ_0 17
#define PIO1_IRQ_1 18
#define PIO2_IRQ_0 19
#define PIO2_IRQ_1 20
#define IO_IRQ_BANK0 21
#define IO_IRQ_BANK0_NS 22
#define IO_IRQ_QSPI 23
#define IO_IRQ_QSPI_NS 24
#define SIO_IRQ_FIFO 25
#define SIO_IRQ_BELL 26
#define SIO_IRQ_FIFO_NS 27
#define SIO_IRQ_BELL_NS 28
#define SIO_IRQ_MTIMECMP 29
#define CLOCKS_IRQ 30
#define SPI0_IRQ 31
#define SPI1_IRQ 32
#define UART0_IRQ 33
#define UART1_IRQ 34
#define ADC_IRQ_FIFO 35
#define I2C0_IRQ 36
#define I2C1_IRQ 37
#define OTP_IRQ 38
#define TRNG_IRQ 39
#define PROC0_IRQ_CTI 40
#define PROC1_IRQ_CTI 41
#define PLL_SYS_IRQ 42
#define PLL_USB_IRQ 43
#define POWMAN_IRQ_POW 44
#define POWMAN_IRQ_TIMER 45
#define SPAREIRQ_IRQ_0 46
#define SPAREIRQ_IRQ_1 47
#define SPAREIRQ_IRQ_2 48
#define SPAREIRQ_IRQ_3 49
#define SPAREIRQ_IRQ_4 50
#define SPAREIRQ_IRQ_5 51
#else
/**
* \brief Interrupt numbers on RP2350 (used as typedef \ref irq_num_t)
* \ingroup hardware_irq
*/
typedef enum irq_num_rp2350 {
TIMER0_IRQ_0 = 0, ///< Select TIMER0's IRQ 0 output
TIMER0_IRQ_1 = 1, ///< Select TIMER0's IRQ 1 output
TIMER0_IRQ_2 = 2, ///< Select TIMER0's IRQ 2 output
TIMER0_IRQ_3 = 3, ///< Select TIMER0's IRQ 3 output
TIMER1_IRQ_0 = 4, ///< Select TIMER1's IRQ 0 output
TIMER1_IRQ_1 = 5, ///< Select TIMER1's IRQ 1 output
TIMER1_IRQ_2 = 6, ///< Select TIMER1's IRQ 2 output
TIMER1_IRQ_3 = 7, ///< Select TIMER1's IRQ 3 output
PWM_IRQ_WRAP_0 = 8, ///< Select PWM's IRQ_WRAP 0 output
PWM_IRQ_WRAP_1 = 9, ///< Select PWM's IRQ_WRAP 1 output
DMA_IRQ_0 = 10, ///< Select DMA's IRQ 0 output
DMA_IRQ_1 = 11, ///< Select DMA's IRQ 1 output
DMA_IRQ_2 = 12, ///< Select DMA's IRQ 2 output
DMA_IRQ_3 = 13, ///< Select DMA's IRQ 3 output
USBCTRL_IRQ = 14, ///< Select USBCTRL's IRQ output
PIO0_IRQ_0 = 15, ///< Select PIO0's IRQ 0 output
PIO0_IRQ_1 = 16, ///< Select PIO0's IRQ 1 output
PIO1_IRQ_0 = 17, ///< Select PIO1's IRQ 0 output
PIO1_IRQ_1 = 18, ///< Select PIO1's IRQ 1 output
PIO2_IRQ_0 = 19, ///< Select PIO2's IRQ 0 output
PIO2_IRQ_1 = 20, ///< Select PIO2's IRQ 1 output
IO_IRQ_BANK0 = 21, ///< Select IO_BANK0's IRQ output
IO_IRQ_BANK0_NS = 22, ///< Select IO_BANK0_NS's IRQ output
IO_IRQ_QSPI = 23, ///< Select IO_QSPI's IRQ output
IO_IRQ_QSPI_NS = 24, ///< Select IO_QSPI_NS's IRQ output
SIO_IRQ_FIFO = 25, ///< Select SIO's IRQ_FIFO output
SIO_IRQ_BELL = 26, ///< Select SIO's IRQ_BELL output
SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's IRQ_FIFO output
SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's IRQ_BELL output
SIO_IRQ_MTIMECMP = 29, ///< Select SIO_IRQ_MTIMECMP's IRQ output
CLOCKS_IRQ = 30, ///< Select CLOCKS's IRQ output
SPI0_IRQ = 31, ///< Select SPI0's IRQ output
SPI1_IRQ = 32, ///< Select SPI1's IRQ output
UART0_IRQ = 33, ///< Select UART0's IRQ output
UART1_IRQ = 34, ///< Select UART1's IRQ output
ADC_IRQ_FIFO = 35, ///< Select ADC's IRQ_FIFO output
I2C0_IRQ = 36, ///< Select I2C0's IRQ output
I2C1_IRQ = 37, ///< Select I2C1's IRQ output
OTP_IRQ = 38, ///< Select OTP's IRQ output
TRNG_IRQ = 39, ///< Select TRNG's IRQ output
PROC0_IRQ_CTI = 40, ///< Select PROC0's IRQ_CTI output
PROC1_IRQ_CTI = 41, ///< Select PROC1's IRQ_CTI output
PLL_SYS_IRQ = 42, ///< Select PLL_SYS's IRQ output
PLL_USB_IRQ = 43, ///< Select PLL_USB's IRQ output
POWMAN_IRQ_POW = 44, ///< Select POWMAN's IRQ_POW output
POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's IRQ_TIMER output
SPARE_IRQ_0 = 46, ///< Select SPARE IRQ 0
SPARE_IRQ_1 = 47, ///< Select SPARE IRQ 1
SPARE_IRQ_2 = 48, ///< Select SPARE IRQ 2
SPARE_IRQ_3 = 49, ///< Select SPARE IRQ 3
SPARE_IRQ_4 = 50, ///< Select SPARE IRQ 4
SPARE_IRQ_5 = 51, ///< Select SPARE IRQ 5
IRQ_COUNT
} irq_num_t;
#endif
#define isr_timer0_0 isr_irq0
#define isr_timer0_1 isr_irq1
#define isr_timer0_2 isr_irq2
#define isr_timer0_3 isr_irq3
#define isr_timer1_0 isr_irq4
#define isr_timer1_1 isr_irq5
#define isr_timer1_2 isr_irq6
#define isr_timer1_3 isr_irq7
#define isr_pwm_wrap_0 isr_irq8
#define isr_pwm_wrap_1 isr_irq9
#define isr_dma_0 isr_irq10
#define isr_dma_1 isr_irq11
#define isr_dma_2 isr_irq12
#define isr_dma_3 isr_irq13
#define isr_usbctrl isr_irq14
#define isr_pio0_0 isr_irq15
#define isr_pio0_1 isr_irq16
#define isr_pio1_0 isr_irq17
#define isr_pio1_1 isr_irq18
#define isr_pio2_0 isr_irq19
#define isr_pio2_1 isr_irq20
#define isr_io_bank0 isr_irq21
#define isr_io_bank0_ns isr_irq22
#define isr_io_qspi isr_irq23
#define isr_io_qspi_ns isr_irq24
#define isr_sio_fifo isr_irq25
#define isr_sio_bell isr_irq26
#define isr_sio_fifo_ns isr_irq27
#define isr_sio_bell_ns isr_irq28
#define isr_sio_mtimecmp isr_irq29
#define isr_clocks isr_irq30
#define isr_spi0 isr_irq31
#define isr_spi1 isr_irq32
#define isr_uart0 isr_irq33
#define isr_uart1 isr_irq34
#define isr_adc_fifo isr_irq35
#define isr_i2c0 isr_irq36
#define isr_i2c1 isr_irq37
#define isr_otp isr_irq38
#define isr_trng isr_irq39
#define isr_proc0_cti isr_irq40
#define isr_proc1_cti isr_irq41
#define isr_pll_sys isr_irq42
#define isr_pll_usb isr_irq43
#define isr_powman_pow isr_irq44
#define isr_powman_timer isr_irq45
#define isr_spare_0 isr_irq46
#define isr_spare_1 isr_irq47
#define isr_spare_2 isr_irq48
#define isr_spare_3 isr_irq49
#define isr_spare_4 isr_irq50
#define isr_spare_5 isr_irq51
#endif // _INTCTRL_H

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lib/pico-sdk/rp2350/hardware/regs/io_bank0.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/io_qspi.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/m33.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : M33_EPPB
// Version : 1
// Bus type : apb
// Description : Cortex-M33 EPPB vendor register block for RP2350
// =============================================================================
#ifndef _HARDWARE_REGS_M33_EPPB_H
#define _HARDWARE_REGS_M33_EPPB_H
// =============================================================================
// Register : M33_EPPB_NMI_MASK0
// Description : NMI mask for IRQs 0 through 31. This register is core-local,
// and is reset by a processor warm reset.
#define M33_EPPB_NMI_MASK0_OFFSET _u(0x00000000)
#define M33_EPPB_NMI_MASK0_BITS _u(0xffffffff)
#define M33_EPPB_NMI_MASK0_RESET _u(0x00000000)
#define M33_EPPB_NMI_MASK0_MSB _u(31)
#define M33_EPPB_NMI_MASK0_LSB _u(0)
#define M33_EPPB_NMI_MASK0_ACCESS "RW"
// =============================================================================
// Register : M33_EPPB_NMI_MASK1
// Description : NMI mask for IRQs 0 though 51. This register is core-local, and
// is reset by a processor warm reset.
#define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004)
#define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff)
#define M33_EPPB_NMI_MASK1_RESET _u(0x00000000)
#define M33_EPPB_NMI_MASK1_MSB _u(19)
#define M33_EPPB_NMI_MASK1_LSB _u(0)
#define M33_EPPB_NMI_MASK1_ACCESS "RW"
// =============================================================================
// Register : M33_EPPB_SLEEPCTRL
// Description : Nonstandard sleep control register
#define M33_EPPB_SLEEPCTRL_OFFSET _u(0x00000008)
#define M33_EPPB_SLEEPCTRL_BITS _u(0x00000007)
#define M33_EPPB_SLEEPCTRL_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_WICENACK
// Description : Status signal from the processor's interrupt controller.
// Changes to WICENREQ are eventually reflected in WICENACK.
#define M33_EPPB_SLEEPCTRL_WICENACK_RESET _u(0x0)
#define M33_EPPB_SLEEPCTRL_WICENACK_BITS _u(0x00000004)
#define M33_EPPB_SLEEPCTRL_WICENACK_MSB _u(2)
#define M33_EPPB_SLEEPCTRL_WICENACK_LSB _u(2)
#define M33_EPPB_SLEEPCTRL_WICENACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_WICENREQ
// Description : Request that the next processor deep sleep is a WIC sleep.
// After setting this bit, before sleeping, poll WICENACK to
// ensure the processor interrupt controller has acknowledged the
// change.
#define M33_EPPB_SLEEPCTRL_WICENREQ_RESET _u(0x1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_BITS _u(0x00000002)
#define M33_EPPB_SLEEPCTRL_WICENREQ_MSB _u(1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_LSB _u(1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_LIGHT_SLEEP
// Description : By default, any processor sleep will deassert the system-level
// clock request. Reenabling the clocks incurs 5 cycles of
// additional latency on wakeup.
//
// Setting LIGHT_SLEEP to 1 keeps the clock request asserted
// during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster
// wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not
// affected, and will always deassert the system-level clock
// request.
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_RESET _u(0x0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_BITS _u(0x00000001)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_MSB _u(0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_LSB _u(0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_M33_EPPB_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PADS_QSPI
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PADS_QSPI_H
#define _HARDWARE_REGS_PADS_QSPI_H
// =============================================================================
// Register : PADS_QSPI_VOLTAGE_SELECT
// Description : Voltage select. Per bank control
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001)
#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SCLK
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD0
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD1
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD2
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD3
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SS
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SS_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_PADS_QSPI_H

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lib/pico-sdk/rp2350/hardware/regs/pio.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/pll.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PLL
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PLL_H
#define _HARDWARE_REGS_PLL_H
// =============================================================================
// Register : PLL_CS
// Description : Control and Status
// GENERAL CONSTRAINTS:
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=750MHz, max=1600MHz
#define PLL_CS_OFFSET _u(0x00000000)
#define PLL_CS_BITS _u(0xc000013f)
#define PLL_CS_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK
// Description : PLL is locked
#define PLL_CS_LOCK_RESET _u(0x0)
#define PLL_CS_LOCK_BITS _u(0x80000000)
#define PLL_CS_LOCK_MSB _u(31)
#define PLL_CS_LOCK_LSB _u(31)
#define PLL_CS_LOCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK_N
// Description : PLL is not locked
// Ideally this is cleared when PLL lock is seen and this should
// never normally be set
#define PLL_CS_LOCK_N_RESET _u(0x0)
#define PLL_CS_LOCK_N_BITS _u(0x40000000)
#define PLL_CS_LOCK_N_MSB _u(30)
#define PLL_CS_LOCK_N_LSB _u(30)
#define PLL_CS_LOCK_N_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PLL_CS_BYPASS
// Description : Passes the reference clock to the output instead of the divided
// VCO. The VCO continues to run so the user can switch between
// the reference clock and the divided VCO but the output will
// glitch when doing so.
#define PLL_CS_BYPASS_RESET _u(0x0)
#define PLL_CS_BYPASS_BITS _u(0x00000100)
#define PLL_CS_BYPASS_MSB _u(8)
#define PLL_CS_BYPASS_LSB _u(8)
#define PLL_CS_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_CS_REFDIV
// Description : Divides the PLL input reference clock.
// Behaviour is undefined for div=0.
// PLL output will be unpredictable during refdiv changes, wait
// for lock=1 before using it.
#define PLL_CS_REFDIV_RESET _u(0x01)
#define PLL_CS_REFDIV_BITS _u(0x0000003f)
#define PLL_CS_REFDIV_MSB _u(5)
#define PLL_CS_REFDIV_LSB _u(0)
#define PLL_CS_REFDIV_ACCESS "RW"
// =============================================================================
// Register : PLL_PWR
// Description : Controls the PLL power modes.
#define PLL_PWR_OFFSET _u(0x00000004)
#define PLL_PWR_BITS _u(0x0000002d)
#define PLL_PWR_RESET _u(0x0000002d)
// -----------------------------------------------------------------------------
// Field : PLL_PWR_VCOPD
// Description : PLL VCO powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_VCOPD_RESET _u(0x1)
#define PLL_PWR_VCOPD_BITS _u(0x00000020)
#define PLL_PWR_VCOPD_MSB _u(5)
#define PLL_PWR_VCOPD_LSB _u(5)
#define PLL_PWR_VCOPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_POSTDIVPD
// Description : PLL post divider powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_POSTDIVPD_RESET _u(0x1)
#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008)
#define PLL_PWR_POSTDIVPD_MSB _u(3)
#define PLL_PWR_POSTDIVPD_LSB _u(3)
#define PLL_PWR_POSTDIVPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_DSMPD
// Description : PLL DSM powerdown
// Nothing is achieved by setting this low.
#define PLL_PWR_DSMPD_RESET _u(0x1)
#define PLL_PWR_DSMPD_BITS _u(0x00000004)
#define PLL_PWR_DSMPD_MSB _u(2)
#define PLL_PWR_DSMPD_LSB _u(2)
#define PLL_PWR_DSMPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_PD
// Description : PLL powerdown
// To save power set high when PLL output not required.
#define PLL_PWR_PD_RESET _u(0x1)
#define PLL_PWR_PD_BITS _u(0x00000001)
#define PLL_PWR_PD_MSB _u(0)
#define PLL_PWR_PD_LSB _u(0)
#define PLL_PWR_PD_ACCESS "RW"
// =============================================================================
// Register : PLL_FBDIV_INT
// Description : Feedback divisor
// (note: this PLL does not support fractional division)
// see ctrl reg description for constraints
#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
#define PLL_FBDIV_INT_BITS _u(0x00000fff)
#define PLL_FBDIV_INT_RESET _u(0x00000000)
#define PLL_FBDIV_INT_MSB _u(11)
#define PLL_FBDIV_INT_LSB _u(0)
#define PLL_FBDIV_INT_ACCESS "RW"
// =============================================================================
// Register : PLL_PRIM
// Description : Controls the PLL post dividers for the primary output
// (note: this PLL does not have a secondary output)
// the primary output is driven from VCO divided by
// postdiv1*postdiv2
#define PLL_PRIM_OFFSET _u(0x0000000c)
#define PLL_PRIM_BITS _u(0x00077000)
#define PLL_PRIM_RESET _u(0x00077000)
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV1
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV1_RESET _u(0x7)
#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000)
#define PLL_PRIM_POSTDIV1_MSB _u(18)
#define PLL_PRIM_POSTDIV1_LSB _u(16)
#define PLL_PRIM_POSTDIV1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV2
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV2_RESET _u(0x7)
#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000)
#define PLL_PRIM_POSTDIV2_MSB _u(14)
#define PLL_PRIM_POSTDIV2_LSB _u(12)
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
// =============================================================================
// Register : PLL_INTR
// Description : Raw Interrupts
#define PLL_INTR_OFFSET _u(0x00000010)
#define PLL_INTR_BITS _u(0x00000001)
#define PLL_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTR_LOCK_N_STICKY
#define PLL_INTR_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTR_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTR_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTR_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTR_LOCK_N_STICKY_ACCESS "WC"
// =============================================================================
// Register : PLL_INTE
// Description : Interrupt Enable
#define PLL_INTE_OFFSET _u(0x00000014)
#define PLL_INTE_BITS _u(0x00000001)
#define PLL_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTE_LOCK_N_STICKY
#define PLL_INTE_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTE_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTE_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTE_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTE_LOCK_N_STICKY_ACCESS "RW"
// =============================================================================
// Register : PLL_INTF
// Description : Interrupt Force
#define PLL_INTF_OFFSET _u(0x00000018)
#define PLL_INTF_BITS _u(0x00000001)
#define PLL_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTF_LOCK_N_STICKY
#define PLL_INTF_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTF_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTF_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTF_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTF_LOCK_N_STICKY_ACCESS "RW"
// =============================================================================
// Register : PLL_INTS
// Description : Interrupt status after masking & forcing
#define PLL_INTS_OFFSET _u(0x0000001c)
#define PLL_INTS_BITS _u(0x00000001)
#define PLL_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTS_LOCK_N_STICKY
#define PLL_INTS_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTS_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTS_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTS_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTS_LOCK_N_STICKY_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_PLL_H

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lib/pico-sdk/rp2350/hardware/regs/powman.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/psm.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PSM
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PSM_H
#define _HARDWARE_REGS_PSM_H
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
#define PSM_FRCE_ON_OFFSET _u(0x00000000)
#define PSM_FRCE_ON_BITS _u(0x01ffffff)
#define PSM_FRCE_ON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
#define PSM_FRCE_ON_PROC1_BITS _u(0x01000000)
#define PSM_FRCE_ON_PROC1_MSB _u(24)
#define PSM_FRCE_ON_PROC1_LSB _u(24)
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
#define PSM_FRCE_ON_PROC0_BITS _u(0x00800000)
#define PSM_FRCE_ON_PROC0_MSB _u(23)
#define PSM_FRCE_ON_PROC0_LSB _u(23)
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ACCESSCTRL
#define PSM_FRCE_ON_ACCESSCTRL_RESET _u(0x0)
#define PSM_FRCE_ON_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_FRCE_ON_ACCESSCTRL_MSB _u(22)
#define PSM_FRCE_ON_ACCESSCTRL_LSB _u(22)
#define PSM_FRCE_ON_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
#define PSM_FRCE_ON_SIO_RESET _u(0x0)
#define PSM_FRCE_ON_SIO_BITS _u(0x00200000)
#define PSM_FRCE_ON_SIO_MSB _u(21)
#define PSM_FRCE_ON_SIO_LSB _u(21)
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
#define PSM_FRCE_ON_XIP_RESET _u(0x0)
#define PSM_FRCE_ON_XIP_BITS _u(0x00100000)
#define PSM_FRCE_ON_XIP_MSB _u(20)
#define PSM_FRCE_ON_XIP_LSB _u(20)
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM9
#define PSM_FRCE_ON_SRAM9_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM9_BITS _u(0x00080000)
#define PSM_FRCE_ON_SRAM9_MSB _u(19)
#define PSM_FRCE_ON_SRAM9_LSB _u(19)
#define PSM_FRCE_ON_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM8
#define PSM_FRCE_ON_SRAM8_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM8_BITS _u(0x00040000)
#define PSM_FRCE_ON_SRAM8_MSB _u(18)
#define PSM_FRCE_ON_SRAM8_LSB _u(18)
#define PSM_FRCE_ON_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM7
#define PSM_FRCE_ON_SRAM7_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM7_BITS _u(0x00020000)
#define PSM_FRCE_ON_SRAM7_MSB _u(17)
#define PSM_FRCE_ON_SRAM7_LSB _u(17)
#define PSM_FRCE_ON_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM6
#define PSM_FRCE_ON_SRAM6_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM6_BITS _u(0x00010000)
#define PSM_FRCE_ON_SRAM6_MSB _u(16)
#define PSM_FRCE_ON_SRAM6_LSB _u(16)
#define PSM_FRCE_ON_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM5_BITS _u(0x00008000)
#define PSM_FRCE_ON_SRAM5_MSB _u(15)
#define PSM_FRCE_ON_SRAM5_LSB _u(15)
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM4_BITS _u(0x00004000)
#define PSM_FRCE_ON_SRAM4_MSB _u(14)
#define PSM_FRCE_ON_SRAM4_LSB _u(14)
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM3_BITS _u(0x00002000)
#define PSM_FRCE_ON_SRAM3_MSB _u(13)
#define PSM_FRCE_ON_SRAM3_LSB _u(13)
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM2_BITS _u(0x00001000)
#define PSM_FRCE_ON_SRAM2_MSB _u(12)
#define PSM_FRCE_ON_SRAM2_LSB _u(12)
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000800)
#define PSM_FRCE_ON_SRAM1_MSB _u(11)
#define PSM_FRCE_ON_SRAM1_LSB _u(11)
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000400)
#define PSM_FRCE_ON_SRAM0_MSB _u(10)
#define PSM_FRCE_ON_SRAM0_LSB _u(10)
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BOOTRAM
#define PSM_FRCE_ON_BOOTRAM_RESET _u(0x0)
#define PSM_FRCE_ON_BOOTRAM_BITS _u(0x00000200)
#define PSM_FRCE_ON_BOOTRAM_MSB _u(9)
#define PSM_FRCE_ON_BOOTRAM_LSB _u(9)
#define PSM_FRCE_ON_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
#define PSM_FRCE_ON_ROM_RESET _u(0x0)
#define PSM_FRCE_ON_ROM_BITS _u(0x00000100)
#define PSM_FRCE_ON_ROM_MSB _u(8)
#define PSM_FRCE_ON_ROM_LSB _u(8)
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000080)
#define PSM_FRCE_ON_BUSFABRIC_MSB _u(7)
#define PSM_FRCE_ON_BUSFABRIC_LSB _u(7)
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PSM_READY
#define PSM_FRCE_ON_PSM_READY_RESET _u(0x0)
#define PSM_FRCE_ON_PSM_READY_BITS _u(0x00000040)
#define PSM_FRCE_ON_PSM_READY_MSB _u(6)
#define PSM_FRCE_ON_PSM_READY_LSB _u(6)
#define PSM_FRCE_ON_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000020)
#define PSM_FRCE_ON_CLOCKS_MSB _u(5)
#define PSM_FRCE_ON_CLOCKS_LSB _u(5)
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
#define PSM_FRCE_ON_RESETS_BITS _u(0x00000010)
#define PSM_FRCE_ON_RESETS_MSB _u(4)
#define PSM_FRCE_ON_RESETS_LSB _u(4)
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
#define PSM_FRCE_ON_XOSC_BITS _u(0x00000008)
#define PSM_FRCE_ON_XOSC_MSB _u(3)
#define PSM_FRCE_ON_XOSC_LSB _u(3)
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
#define PSM_FRCE_ON_ROSC_BITS _u(0x00000004)
#define PSM_FRCE_ON_ROSC_MSB _u(2)
#define PSM_FRCE_ON_ROSC_LSB _u(2)
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_OTP
#define PSM_FRCE_ON_OTP_RESET _u(0x0)
#define PSM_FRCE_ON_OTP_BITS _u(0x00000002)
#define PSM_FRCE_ON_OTP_MSB _u(1)
#define PSM_FRCE_ON_OTP_LSB _u(1)
#define PSM_FRCE_ON_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC_COLD
#define PSM_FRCE_ON_PROC_COLD_RESET _u(0x0)
#define PSM_FRCE_ON_PROC_COLD_BITS _u(0x00000001)
#define PSM_FRCE_ON_PROC_COLD_MSB _u(0)
#define PSM_FRCE_ON_PROC_COLD_LSB _u(0)
#define PSM_FRCE_ON_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_FRCE_OFF
// Description : Force into reset (i.e. power it off)
#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
#define PSM_FRCE_OFF_BITS _u(0x01ffffff)
#define PSM_FRCE_OFF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC1_BITS _u(0x01000000)
#define PSM_FRCE_OFF_PROC1_MSB _u(24)
#define PSM_FRCE_OFF_PROC1_LSB _u(24)
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC0_BITS _u(0x00800000)
#define PSM_FRCE_OFF_PROC0_MSB _u(23)
#define PSM_FRCE_OFF_PROC0_LSB _u(23)
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ACCESSCTRL
#define PSM_FRCE_OFF_ACCESSCTRL_RESET _u(0x0)
#define PSM_FRCE_OFF_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_FRCE_OFF_ACCESSCTRL_MSB _u(22)
#define PSM_FRCE_OFF_ACCESSCTRL_LSB _u(22)
#define PSM_FRCE_OFF_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
#define PSM_FRCE_OFF_SIO_BITS _u(0x00200000)
#define PSM_FRCE_OFF_SIO_MSB _u(21)
#define PSM_FRCE_OFF_SIO_LSB _u(21)
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
#define PSM_FRCE_OFF_XIP_BITS _u(0x00100000)
#define PSM_FRCE_OFF_XIP_MSB _u(20)
#define PSM_FRCE_OFF_XIP_LSB _u(20)
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM9
#define PSM_FRCE_OFF_SRAM9_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM9_BITS _u(0x00080000)
#define PSM_FRCE_OFF_SRAM9_MSB _u(19)
#define PSM_FRCE_OFF_SRAM9_LSB _u(19)
#define PSM_FRCE_OFF_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM8
#define PSM_FRCE_OFF_SRAM8_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM8_BITS _u(0x00040000)
#define PSM_FRCE_OFF_SRAM8_MSB _u(18)
#define PSM_FRCE_OFF_SRAM8_LSB _u(18)
#define PSM_FRCE_OFF_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM7
#define PSM_FRCE_OFF_SRAM7_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM7_BITS _u(0x00020000)
#define PSM_FRCE_OFF_SRAM7_MSB _u(17)
#define PSM_FRCE_OFF_SRAM7_LSB _u(17)
#define PSM_FRCE_OFF_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM6
#define PSM_FRCE_OFF_SRAM6_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM6_BITS _u(0x00010000)
#define PSM_FRCE_OFF_SRAM6_MSB _u(16)
#define PSM_FRCE_OFF_SRAM6_LSB _u(16)
#define PSM_FRCE_OFF_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00008000)
#define PSM_FRCE_OFF_SRAM5_MSB _u(15)
#define PSM_FRCE_OFF_SRAM5_LSB _u(15)
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00004000)
#define PSM_FRCE_OFF_SRAM4_MSB _u(14)
#define PSM_FRCE_OFF_SRAM4_LSB _u(14)
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00002000)
#define PSM_FRCE_OFF_SRAM3_MSB _u(13)
#define PSM_FRCE_OFF_SRAM3_LSB _u(13)
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00001000)
#define PSM_FRCE_OFF_SRAM2_MSB _u(12)
#define PSM_FRCE_OFF_SRAM2_LSB _u(12)
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000800)
#define PSM_FRCE_OFF_SRAM1_MSB _u(11)
#define PSM_FRCE_OFF_SRAM1_LSB _u(11)
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000400)
#define PSM_FRCE_OFF_SRAM0_MSB _u(10)
#define PSM_FRCE_OFF_SRAM0_LSB _u(10)
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BOOTRAM
#define PSM_FRCE_OFF_BOOTRAM_RESET _u(0x0)
#define PSM_FRCE_OFF_BOOTRAM_BITS _u(0x00000200)
#define PSM_FRCE_OFF_BOOTRAM_MSB _u(9)
#define PSM_FRCE_OFF_BOOTRAM_LSB _u(9)
#define PSM_FRCE_OFF_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
#define PSM_FRCE_OFF_ROM_BITS _u(0x00000100)
#define PSM_FRCE_OFF_ROM_MSB _u(8)
#define PSM_FRCE_OFF_ROM_LSB _u(8)
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000080)
#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(7)
#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(7)
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PSM_READY
#define PSM_FRCE_OFF_PSM_READY_RESET _u(0x0)
#define PSM_FRCE_OFF_PSM_READY_BITS _u(0x00000040)
#define PSM_FRCE_OFF_PSM_READY_MSB _u(6)
#define PSM_FRCE_OFF_PSM_READY_LSB _u(6)
#define PSM_FRCE_OFF_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000020)
#define PSM_FRCE_OFF_CLOCKS_MSB _u(5)
#define PSM_FRCE_OFF_CLOCKS_LSB _u(5)
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000010)
#define PSM_FRCE_OFF_RESETS_MSB _u(4)
#define PSM_FRCE_OFF_RESETS_LSB _u(4)
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000008)
#define PSM_FRCE_OFF_XOSC_MSB _u(3)
#define PSM_FRCE_OFF_XOSC_LSB _u(3)
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000004)
#define PSM_FRCE_OFF_ROSC_MSB _u(2)
#define PSM_FRCE_OFF_ROSC_LSB _u(2)
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_OTP
#define PSM_FRCE_OFF_OTP_RESET _u(0x0)
#define PSM_FRCE_OFF_OTP_BITS _u(0x00000002)
#define PSM_FRCE_OFF_OTP_MSB _u(1)
#define PSM_FRCE_OFF_OTP_LSB _u(1)
#define PSM_FRCE_OFF_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC_COLD
#define PSM_FRCE_OFF_PROC_COLD_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC_COLD_BITS _u(0x00000001)
#define PSM_FRCE_OFF_PROC_COLD_MSB _u(0)
#define PSM_FRCE_OFF_PROC_COLD_LSB _u(0)
#define PSM_FRCE_OFF_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_WDSEL
// Description : Set to 1 if the watchdog should reset this
#define PSM_WDSEL_OFFSET _u(0x00000008)
#define PSM_WDSEL_BITS _u(0x01ffffff)
#define PSM_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
#define PSM_WDSEL_PROC1_RESET _u(0x0)
#define PSM_WDSEL_PROC1_BITS _u(0x01000000)
#define PSM_WDSEL_PROC1_MSB _u(24)
#define PSM_WDSEL_PROC1_LSB _u(24)
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
#define PSM_WDSEL_PROC0_RESET _u(0x0)
#define PSM_WDSEL_PROC0_BITS _u(0x00800000)
#define PSM_WDSEL_PROC0_MSB _u(23)
#define PSM_WDSEL_PROC0_LSB _u(23)
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ACCESSCTRL
#define PSM_WDSEL_ACCESSCTRL_RESET _u(0x0)
#define PSM_WDSEL_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_WDSEL_ACCESSCTRL_MSB _u(22)
#define PSM_WDSEL_ACCESSCTRL_LSB _u(22)
#define PSM_WDSEL_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
#define PSM_WDSEL_SIO_RESET _u(0x0)
#define PSM_WDSEL_SIO_BITS _u(0x00200000)
#define PSM_WDSEL_SIO_MSB _u(21)
#define PSM_WDSEL_SIO_LSB _u(21)
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
#define PSM_WDSEL_XIP_RESET _u(0x0)
#define PSM_WDSEL_XIP_BITS _u(0x00100000)
#define PSM_WDSEL_XIP_MSB _u(20)
#define PSM_WDSEL_XIP_LSB _u(20)
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM9
#define PSM_WDSEL_SRAM9_RESET _u(0x0)
#define PSM_WDSEL_SRAM9_BITS _u(0x00080000)
#define PSM_WDSEL_SRAM9_MSB _u(19)
#define PSM_WDSEL_SRAM9_LSB _u(19)
#define PSM_WDSEL_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM8
#define PSM_WDSEL_SRAM8_RESET _u(0x0)
#define PSM_WDSEL_SRAM8_BITS _u(0x00040000)
#define PSM_WDSEL_SRAM8_MSB _u(18)
#define PSM_WDSEL_SRAM8_LSB _u(18)
#define PSM_WDSEL_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM7
#define PSM_WDSEL_SRAM7_RESET _u(0x0)
#define PSM_WDSEL_SRAM7_BITS _u(0x00020000)
#define PSM_WDSEL_SRAM7_MSB _u(17)
#define PSM_WDSEL_SRAM7_LSB _u(17)
#define PSM_WDSEL_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM6
#define PSM_WDSEL_SRAM6_RESET _u(0x0)
#define PSM_WDSEL_SRAM6_BITS _u(0x00010000)
#define PSM_WDSEL_SRAM6_MSB _u(16)
#define PSM_WDSEL_SRAM6_LSB _u(16)
#define PSM_WDSEL_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
#define PSM_WDSEL_SRAM5_RESET _u(0x0)
#define PSM_WDSEL_SRAM5_BITS _u(0x00008000)
#define PSM_WDSEL_SRAM5_MSB _u(15)
#define PSM_WDSEL_SRAM5_LSB _u(15)
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
#define PSM_WDSEL_SRAM4_RESET _u(0x0)
#define PSM_WDSEL_SRAM4_BITS _u(0x00004000)
#define PSM_WDSEL_SRAM4_MSB _u(14)
#define PSM_WDSEL_SRAM4_LSB _u(14)
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
#define PSM_WDSEL_SRAM3_RESET _u(0x0)
#define PSM_WDSEL_SRAM3_BITS _u(0x00002000)
#define PSM_WDSEL_SRAM3_MSB _u(13)
#define PSM_WDSEL_SRAM3_LSB _u(13)
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
#define PSM_WDSEL_SRAM2_RESET _u(0x0)
#define PSM_WDSEL_SRAM2_BITS _u(0x00001000)
#define PSM_WDSEL_SRAM2_MSB _u(12)
#define PSM_WDSEL_SRAM2_LSB _u(12)
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
#define PSM_WDSEL_SRAM1_RESET _u(0x0)
#define PSM_WDSEL_SRAM1_BITS _u(0x00000800)
#define PSM_WDSEL_SRAM1_MSB _u(11)
#define PSM_WDSEL_SRAM1_LSB _u(11)
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
#define PSM_WDSEL_SRAM0_RESET _u(0x0)
#define PSM_WDSEL_SRAM0_BITS _u(0x00000400)
#define PSM_WDSEL_SRAM0_MSB _u(10)
#define PSM_WDSEL_SRAM0_LSB _u(10)
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BOOTRAM
#define PSM_WDSEL_BOOTRAM_RESET _u(0x0)
#define PSM_WDSEL_BOOTRAM_BITS _u(0x00000200)
#define PSM_WDSEL_BOOTRAM_MSB _u(9)
#define PSM_WDSEL_BOOTRAM_LSB _u(9)
#define PSM_WDSEL_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
#define PSM_WDSEL_ROM_RESET _u(0x0)
#define PSM_WDSEL_ROM_BITS _u(0x00000100)
#define PSM_WDSEL_ROM_MSB _u(8)
#define PSM_WDSEL_ROM_LSB _u(8)
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000080)
#define PSM_WDSEL_BUSFABRIC_MSB _u(7)
#define PSM_WDSEL_BUSFABRIC_LSB _u(7)
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PSM_READY
#define PSM_WDSEL_PSM_READY_RESET _u(0x0)
#define PSM_WDSEL_PSM_READY_BITS _u(0x00000040)
#define PSM_WDSEL_PSM_READY_MSB _u(6)
#define PSM_WDSEL_PSM_READY_LSB _u(6)
#define PSM_WDSEL_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
#define PSM_WDSEL_CLOCKS_BITS _u(0x00000020)
#define PSM_WDSEL_CLOCKS_MSB _u(5)
#define PSM_WDSEL_CLOCKS_LSB _u(5)
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
#define PSM_WDSEL_RESETS_RESET _u(0x0)
#define PSM_WDSEL_RESETS_BITS _u(0x00000010)
#define PSM_WDSEL_RESETS_MSB _u(4)
#define PSM_WDSEL_RESETS_LSB _u(4)
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
#define PSM_WDSEL_XOSC_RESET _u(0x0)
#define PSM_WDSEL_XOSC_BITS _u(0x00000008)
#define PSM_WDSEL_XOSC_MSB _u(3)
#define PSM_WDSEL_XOSC_LSB _u(3)
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
#define PSM_WDSEL_ROSC_RESET _u(0x0)
#define PSM_WDSEL_ROSC_BITS _u(0x00000004)
#define PSM_WDSEL_ROSC_MSB _u(2)
#define PSM_WDSEL_ROSC_LSB _u(2)
#define PSM_WDSEL_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_OTP
#define PSM_WDSEL_OTP_RESET _u(0x0)
#define PSM_WDSEL_OTP_BITS _u(0x00000002)
#define PSM_WDSEL_OTP_MSB _u(1)
#define PSM_WDSEL_OTP_LSB _u(1)
#define PSM_WDSEL_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC_COLD
#define PSM_WDSEL_PROC_COLD_RESET _u(0x0)
#define PSM_WDSEL_PROC_COLD_BITS _u(0x00000001)
#define PSM_WDSEL_PROC_COLD_MSB _u(0)
#define PSM_WDSEL_PROC_COLD_LSB _u(0)
#define PSM_WDSEL_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_DONE
// Description : Is the subsystem ready?
#define PSM_DONE_OFFSET _u(0x0000000c)
#define PSM_DONE_BITS _u(0x01ffffff)
#define PSM_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
#define PSM_DONE_PROC1_RESET _u(0x0)
#define PSM_DONE_PROC1_BITS _u(0x01000000)
#define PSM_DONE_PROC1_MSB _u(24)
#define PSM_DONE_PROC1_LSB _u(24)
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
#define PSM_DONE_PROC0_RESET _u(0x0)
#define PSM_DONE_PROC0_BITS _u(0x00800000)
#define PSM_DONE_PROC0_MSB _u(23)
#define PSM_DONE_PROC0_LSB _u(23)
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ACCESSCTRL
#define PSM_DONE_ACCESSCTRL_RESET _u(0x0)
#define PSM_DONE_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_DONE_ACCESSCTRL_MSB _u(22)
#define PSM_DONE_ACCESSCTRL_LSB _u(22)
#define PSM_DONE_ACCESSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
#define PSM_DONE_SIO_RESET _u(0x0)
#define PSM_DONE_SIO_BITS _u(0x00200000)
#define PSM_DONE_SIO_MSB _u(21)
#define PSM_DONE_SIO_LSB _u(21)
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
#define PSM_DONE_XIP_RESET _u(0x0)
#define PSM_DONE_XIP_BITS _u(0x00100000)
#define PSM_DONE_XIP_MSB _u(20)
#define PSM_DONE_XIP_LSB _u(20)
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM9
#define PSM_DONE_SRAM9_RESET _u(0x0)
#define PSM_DONE_SRAM9_BITS _u(0x00080000)
#define PSM_DONE_SRAM9_MSB _u(19)
#define PSM_DONE_SRAM9_LSB _u(19)
#define PSM_DONE_SRAM9_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM8
#define PSM_DONE_SRAM8_RESET _u(0x0)
#define PSM_DONE_SRAM8_BITS _u(0x00040000)
#define PSM_DONE_SRAM8_MSB _u(18)
#define PSM_DONE_SRAM8_LSB _u(18)
#define PSM_DONE_SRAM8_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM7
#define PSM_DONE_SRAM7_RESET _u(0x0)
#define PSM_DONE_SRAM7_BITS _u(0x00020000)
#define PSM_DONE_SRAM7_MSB _u(17)
#define PSM_DONE_SRAM7_LSB _u(17)
#define PSM_DONE_SRAM7_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM6
#define PSM_DONE_SRAM6_RESET _u(0x0)
#define PSM_DONE_SRAM6_BITS _u(0x00010000)
#define PSM_DONE_SRAM6_MSB _u(16)
#define PSM_DONE_SRAM6_LSB _u(16)
#define PSM_DONE_SRAM6_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
#define PSM_DONE_SRAM5_RESET _u(0x0)
#define PSM_DONE_SRAM5_BITS _u(0x00008000)
#define PSM_DONE_SRAM5_MSB _u(15)
#define PSM_DONE_SRAM5_LSB _u(15)
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
#define PSM_DONE_SRAM4_RESET _u(0x0)
#define PSM_DONE_SRAM4_BITS _u(0x00004000)
#define PSM_DONE_SRAM4_MSB _u(14)
#define PSM_DONE_SRAM4_LSB _u(14)
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
#define PSM_DONE_SRAM3_RESET _u(0x0)
#define PSM_DONE_SRAM3_BITS _u(0x00002000)
#define PSM_DONE_SRAM3_MSB _u(13)
#define PSM_DONE_SRAM3_LSB _u(13)
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
#define PSM_DONE_SRAM2_RESET _u(0x0)
#define PSM_DONE_SRAM2_BITS _u(0x00001000)
#define PSM_DONE_SRAM2_MSB _u(12)
#define PSM_DONE_SRAM2_LSB _u(12)
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
#define PSM_DONE_SRAM1_RESET _u(0x0)
#define PSM_DONE_SRAM1_BITS _u(0x00000800)
#define PSM_DONE_SRAM1_MSB _u(11)
#define PSM_DONE_SRAM1_LSB _u(11)
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
#define PSM_DONE_SRAM0_RESET _u(0x0)
#define PSM_DONE_SRAM0_BITS _u(0x00000400)
#define PSM_DONE_SRAM0_MSB _u(10)
#define PSM_DONE_SRAM0_LSB _u(10)
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BOOTRAM
#define PSM_DONE_BOOTRAM_RESET _u(0x0)
#define PSM_DONE_BOOTRAM_BITS _u(0x00000200)
#define PSM_DONE_BOOTRAM_MSB _u(9)
#define PSM_DONE_BOOTRAM_LSB _u(9)
#define PSM_DONE_BOOTRAM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
#define PSM_DONE_ROM_RESET _u(0x0)
#define PSM_DONE_ROM_BITS _u(0x00000100)
#define PSM_DONE_ROM_MSB _u(8)
#define PSM_DONE_ROM_LSB _u(8)
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
#define PSM_DONE_BUSFABRIC_BITS _u(0x00000080)
#define PSM_DONE_BUSFABRIC_MSB _u(7)
#define PSM_DONE_BUSFABRIC_LSB _u(7)
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PSM_READY
#define PSM_DONE_PSM_READY_RESET _u(0x0)
#define PSM_DONE_PSM_READY_BITS _u(0x00000040)
#define PSM_DONE_PSM_READY_MSB _u(6)
#define PSM_DONE_PSM_READY_LSB _u(6)
#define PSM_DONE_PSM_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
#define PSM_DONE_CLOCKS_RESET _u(0x0)
#define PSM_DONE_CLOCKS_BITS _u(0x00000020)
#define PSM_DONE_CLOCKS_MSB _u(5)
#define PSM_DONE_CLOCKS_LSB _u(5)
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
#define PSM_DONE_RESETS_RESET _u(0x0)
#define PSM_DONE_RESETS_BITS _u(0x00000010)
#define PSM_DONE_RESETS_MSB _u(4)
#define PSM_DONE_RESETS_LSB _u(4)
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
#define PSM_DONE_XOSC_RESET _u(0x0)
#define PSM_DONE_XOSC_BITS _u(0x00000008)
#define PSM_DONE_XOSC_MSB _u(3)
#define PSM_DONE_XOSC_LSB _u(3)
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
#define PSM_DONE_ROSC_RESET _u(0x0)
#define PSM_DONE_ROSC_BITS _u(0x00000004)
#define PSM_DONE_ROSC_MSB _u(2)
#define PSM_DONE_ROSC_LSB _u(2)
#define PSM_DONE_ROSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_OTP
#define PSM_DONE_OTP_RESET _u(0x0)
#define PSM_DONE_OTP_BITS _u(0x00000002)
#define PSM_DONE_OTP_MSB _u(1)
#define PSM_DONE_OTP_LSB _u(1)
#define PSM_DONE_OTP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC_COLD
#define PSM_DONE_PROC_COLD_RESET _u(0x0)
#define PSM_DONE_PROC_COLD_BITS _u(0x00000001)
#define PSM_DONE_PROC_COLD_MSB _u(0)
#define PSM_DONE_PROC_COLD_LSB _u(0)
#define PSM_DONE_PROC_COLD_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_PSM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : RESETS
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_RESETS_H
#define _HARDWARE_REGS_RESETS_H
// =============================================================================
// Register : RESETS_RESET
#define RESETS_RESET_OFFSET _u(0x00000000)
#define RESETS_RESET_BITS _u(0x1fffffff)
#define RESETS_RESET_RESET _u(0x1fffffff)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_USBCTRL
#define RESETS_RESET_USBCTRL_RESET _u(0x1)
#define RESETS_RESET_USBCTRL_BITS _u(0x10000000)
#define RESETS_RESET_USBCTRL_MSB _u(28)
#define RESETS_RESET_USBCTRL_LSB _u(28)
#define RESETS_RESET_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART1
#define RESETS_RESET_UART1_RESET _u(0x1)
#define RESETS_RESET_UART1_BITS _u(0x08000000)
#define RESETS_RESET_UART1_MSB _u(27)
#define RESETS_RESET_UART1_LSB _u(27)
#define RESETS_RESET_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART0
#define RESETS_RESET_UART0_RESET _u(0x1)
#define RESETS_RESET_UART0_BITS _u(0x04000000)
#define RESETS_RESET_UART0_MSB _u(26)
#define RESETS_RESET_UART0_LSB _u(26)
#define RESETS_RESET_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TRNG
#define RESETS_RESET_TRNG_RESET _u(0x1)
#define RESETS_RESET_TRNG_BITS _u(0x02000000)
#define RESETS_RESET_TRNG_MSB _u(25)
#define RESETS_RESET_TRNG_LSB _u(25)
#define RESETS_RESET_TRNG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER1
#define RESETS_RESET_TIMER1_RESET _u(0x1)
#define RESETS_RESET_TIMER1_BITS _u(0x01000000)
#define RESETS_RESET_TIMER1_MSB _u(24)
#define RESETS_RESET_TIMER1_LSB _u(24)
#define RESETS_RESET_TIMER1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER0
#define RESETS_RESET_TIMER0_RESET _u(0x1)
#define RESETS_RESET_TIMER0_BITS _u(0x00800000)
#define RESETS_RESET_TIMER0_MSB _u(23)
#define RESETS_RESET_TIMER0_LSB _u(23)
#define RESETS_RESET_TIMER0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TBMAN
#define RESETS_RESET_TBMAN_RESET _u(0x1)
#define RESETS_RESET_TBMAN_BITS _u(0x00400000)
#define RESETS_RESET_TBMAN_MSB _u(22)
#define RESETS_RESET_TBMAN_LSB _u(22)
#define RESETS_RESET_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSINFO
#define RESETS_RESET_SYSINFO_RESET _u(0x1)
#define RESETS_RESET_SYSINFO_BITS _u(0x00200000)
#define RESETS_RESET_SYSINFO_MSB _u(21)
#define RESETS_RESET_SYSINFO_LSB _u(21)
#define RESETS_RESET_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSCFG
#define RESETS_RESET_SYSCFG_RESET _u(0x1)
#define RESETS_RESET_SYSCFG_BITS _u(0x00100000)
#define RESETS_RESET_SYSCFG_MSB _u(20)
#define RESETS_RESET_SYSCFG_LSB _u(20)
#define RESETS_RESET_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI1
#define RESETS_RESET_SPI1_RESET _u(0x1)
#define RESETS_RESET_SPI1_BITS _u(0x00080000)
#define RESETS_RESET_SPI1_MSB _u(19)
#define RESETS_RESET_SPI1_LSB _u(19)
#define RESETS_RESET_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI0
#define RESETS_RESET_SPI0_RESET _u(0x1)
#define RESETS_RESET_SPI0_BITS _u(0x00040000)
#define RESETS_RESET_SPI0_MSB _u(18)
#define RESETS_RESET_SPI0_LSB _u(18)
#define RESETS_RESET_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SHA256
#define RESETS_RESET_SHA256_RESET _u(0x1)
#define RESETS_RESET_SHA256_BITS _u(0x00020000)
#define RESETS_RESET_SHA256_MSB _u(17)
#define RESETS_RESET_SHA256_LSB _u(17)
#define RESETS_RESET_SHA256_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PWM
#define RESETS_RESET_PWM_RESET _u(0x1)
#define RESETS_RESET_PWM_BITS _u(0x00010000)
#define RESETS_RESET_PWM_MSB _u(16)
#define RESETS_RESET_PWM_LSB _u(16)
#define RESETS_RESET_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_USB
#define RESETS_RESET_PLL_USB_RESET _u(0x1)
#define RESETS_RESET_PLL_USB_BITS _u(0x00008000)
#define RESETS_RESET_PLL_USB_MSB _u(15)
#define RESETS_RESET_PLL_USB_LSB _u(15)
#define RESETS_RESET_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_SYS
#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
#define RESETS_RESET_PLL_SYS_BITS _u(0x00004000)
#define RESETS_RESET_PLL_SYS_MSB _u(14)
#define RESETS_RESET_PLL_SYS_LSB _u(14)
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO2
#define RESETS_RESET_PIO2_RESET _u(0x1)
#define RESETS_RESET_PIO2_BITS _u(0x00002000)
#define RESETS_RESET_PIO2_MSB _u(13)
#define RESETS_RESET_PIO2_LSB _u(13)
#define RESETS_RESET_PIO2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO1
#define RESETS_RESET_PIO1_RESET _u(0x1)
#define RESETS_RESET_PIO1_BITS _u(0x00001000)
#define RESETS_RESET_PIO1_MSB _u(12)
#define RESETS_RESET_PIO1_LSB _u(12)
#define RESETS_RESET_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO0
#define RESETS_RESET_PIO0_RESET _u(0x1)
#define RESETS_RESET_PIO0_BITS _u(0x00000800)
#define RESETS_RESET_PIO0_MSB _u(11)
#define RESETS_RESET_PIO0_LSB _u(11)
#define RESETS_RESET_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_QSPI
#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_RESET_PADS_QSPI_MSB _u(10)
#define RESETS_RESET_PADS_QSPI_LSB _u(10)
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_BANK0
#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_RESET_PADS_BANK0_MSB _u(9)
#define RESETS_RESET_PADS_BANK0_LSB _u(9)
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_JTAG
#define RESETS_RESET_JTAG_RESET _u(0x1)
#define RESETS_RESET_JTAG_BITS _u(0x00000100)
#define RESETS_RESET_JTAG_MSB _u(8)
#define RESETS_RESET_JTAG_LSB _u(8)
#define RESETS_RESET_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_QSPI
#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
#define RESETS_RESET_IO_QSPI_BITS _u(0x00000080)
#define RESETS_RESET_IO_QSPI_MSB _u(7)
#define RESETS_RESET_IO_QSPI_LSB _u(7)
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_BANK0
#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
#define RESETS_RESET_IO_BANK0_BITS _u(0x00000040)
#define RESETS_RESET_IO_BANK0_MSB _u(6)
#define RESETS_RESET_IO_BANK0_LSB _u(6)
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C1
#define RESETS_RESET_I2C1_RESET _u(0x1)
#define RESETS_RESET_I2C1_BITS _u(0x00000020)
#define RESETS_RESET_I2C1_MSB _u(5)
#define RESETS_RESET_I2C1_LSB _u(5)
#define RESETS_RESET_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C0
#define RESETS_RESET_I2C0_RESET _u(0x1)
#define RESETS_RESET_I2C0_BITS _u(0x00000010)
#define RESETS_RESET_I2C0_MSB _u(4)
#define RESETS_RESET_I2C0_LSB _u(4)
#define RESETS_RESET_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_HSTX
#define RESETS_RESET_HSTX_RESET _u(0x1)
#define RESETS_RESET_HSTX_BITS _u(0x00000008)
#define RESETS_RESET_HSTX_MSB _u(3)
#define RESETS_RESET_HSTX_LSB _u(3)
#define RESETS_RESET_HSTX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DMA
#define RESETS_RESET_DMA_RESET _u(0x1)
#define RESETS_RESET_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DMA_MSB _u(2)
#define RESETS_RESET_DMA_LSB _u(2)
#define RESETS_RESET_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_BUSCTRL
#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_BUSCTRL_MSB _u(1)
#define RESETS_RESET_BUSCTRL_LSB _u(1)
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_ADC
#define RESETS_RESET_ADC_RESET _u(0x1)
#define RESETS_RESET_ADC_BITS _u(0x00000001)
#define RESETS_RESET_ADC_MSB _u(0)
#define RESETS_RESET_ADC_LSB _u(0)
#define RESETS_RESET_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_WDSEL
#define RESETS_WDSEL_OFFSET _u(0x00000004)
#define RESETS_WDSEL_BITS _u(0x1fffffff)
#define RESETS_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_USBCTRL
#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
#define RESETS_WDSEL_USBCTRL_BITS _u(0x10000000)
#define RESETS_WDSEL_USBCTRL_MSB _u(28)
#define RESETS_WDSEL_USBCTRL_LSB _u(28)
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART1
#define RESETS_WDSEL_UART1_RESET _u(0x0)
#define RESETS_WDSEL_UART1_BITS _u(0x08000000)
#define RESETS_WDSEL_UART1_MSB _u(27)
#define RESETS_WDSEL_UART1_LSB _u(27)
#define RESETS_WDSEL_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART0
#define RESETS_WDSEL_UART0_RESET _u(0x0)
#define RESETS_WDSEL_UART0_BITS _u(0x04000000)
#define RESETS_WDSEL_UART0_MSB _u(26)
#define RESETS_WDSEL_UART0_LSB _u(26)
#define RESETS_WDSEL_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TRNG
#define RESETS_WDSEL_TRNG_RESET _u(0x0)
#define RESETS_WDSEL_TRNG_BITS _u(0x02000000)
#define RESETS_WDSEL_TRNG_MSB _u(25)
#define RESETS_WDSEL_TRNG_LSB _u(25)
#define RESETS_WDSEL_TRNG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER1
#define RESETS_WDSEL_TIMER1_RESET _u(0x0)
#define RESETS_WDSEL_TIMER1_BITS _u(0x01000000)
#define RESETS_WDSEL_TIMER1_MSB _u(24)
#define RESETS_WDSEL_TIMER1_LSB _u(24)
#define RESETS_WDSEL_TIMER1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER0
#define RESETS_WDSEL_TIMER0_RESET _u(0x0)
#define RESETS_WDSEL_TIMER0_BITS _u(0x00800000)
#define RESETS_WDSEL_TIMER0_MSB _u(23)
#define RESETS_WDSEL_TIMER0_LSB _u(23)
#define RESETS_WDSEL_TIMER0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TBMAN
#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
#define RESETS_WDSEL_TBMAN_BITS _u(0x00400000)
#define RESETS_WDSEL_TBMAN_MSB _u(22)
#define RESETS_WDSEL_TBMAN_LSB _u(22)
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSINFO
#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
#define RESETS_WDSEL_SYSINFO_BITS _u(0x00200000)
#define RESETS_WDSEL_SYSINFO_MSB _u(21)
#define RESETS_WDSEL_SYSINFO_LSB _u(21)
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSCFG
#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
#define RESETS_WDSEL_SYSCFG_BITS _u(0x00100000)
#define RESETS_WDSEL_SYSCFG_MSB _u(20)
#define RESETS_WDSEL_SYSCFG_LSB _u(20)
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI1
#define RESETS_WDSEL_SPI1_RESET _u(0x0)
#define RESETS_WDSEL_SPI1_BITS _u(0x00080000)
#define RESETS_WDSEL_SPI1_MSB _u(19)
#define RESETS_WDSEL_SPI1_LSB _u(19)
#define RESETS_WDSEL_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI0
#define RESETS_WDSEL_SPI0_RESET _u(0x0)
#define RESETS_WDSEL_SPI0_BITS _u(0x00040000)
#define RESETS_WDSEL_SPI0_MSB _u(18)
#define RESETS_WDSEL_SPI0_LSB _u(18)
#define RESETS_WDSEL_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SHA256
#define RESETS_WDSEL_SHA256_RESET _u(0x0)
#define RESETS_WDSEL_SHA256_BITS _u(0x00020000)
#define RESETS_WDSEL_SHA256_MSB _u(17)
#define RESETS_WDSEL_SHA256_LSB _u(17)
#define RESETS_WDSEL_SHA256_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PWM
#define RESETS_WDSEL_PWM_RESET _u(0x0)
#define RESETS_WDSEL_PWM_BITS _u(0x00010000)
#define RESETS_WDSEL_PWM_MSB _u(16)
#define RESETS_WDSEL_PWM_LSB _u(16)
#define RESETS_WDSEL_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_USB
#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
#define RESETS_WDSEL_PLL_USB_BITS _u(0x00008000)
#define RESETS_WDSEL_PLL_USB_MSB _u(15)
#define RESETS_WDSEL_PLL_USB_LSB _u(15)
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_SYS
#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00004000)
#define RESETS_WDSEL_PLL_SYS_MSB _u(14)
#define RESETS_WDSEL_PLL_SYS_LSB _u(14)
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO2
#define RESETS_WDSEL_PIO2_RESET _u(0x0)
#define RESETS_WDSEL_PIO2_BITS _u(0x00002000)
#define RESETS_WDSEL_PIO2_MSB _u(13)
#define RESETS_WDSEL_PIO2_LSB _u(13)
#define RESETS_WDSEL_PIO2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO1
#define RESETS_WDSEL_PIO1_RESET _u(0x0)
#define RESETS_WDSEL_PIO1_BITS _u(0x00001000)
#define RESETS_WDSEL_PIO1_MSB _u(12)
#define RESETS_WDSEL_PIO1_LSB _u(12)
#define RESETS_WDSEL_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO0
#define RESETS_WDSEL_PIO0_RESET _u(0x0)
#define RESETS_WDSEL_PIO0_BITS _u(0x00000800)
#define RESETS_WDSEL_PIO0_MSB _u(11)
#define RESETS_WDSEL_PIO0_LSB _u(11)
#define RESETS_WDSEL_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_QSPI
#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_WDSEL_PADS_QSPI_MSB _u(10)
#define RESETS_WDSEL_PADS_QSPI_LSB _u(10)
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_BANK0
#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_WDSEL_PADS_BANK0_MSB _u(9)
#define RESETS_WDSEL_PADS_BANK0_LSB _u(9)
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_JTAG
#define RESETS_WDSEL_JTAG_RESET _u(0x0)
#define RESETS_WDSEL_JTAG_BITS _u(0x00000100)
#define RESETS_WDSEL_JTAG_MSB _u(8)
#define RESETS_WDSEL_JTAG_LSB _u(8)
#define RESETS_WDSEL_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_QSPI
#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000080)
#define RESETS_WDSEL_IO_QSPI_MSB _u(7)
#define RESETS_WDSEL_IO_QSPI_LSB _u(7)
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_BANK0
#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000040)
#define RESETS_WDSEL_IO_BANK0_MSB _u(6)
#define RESETS_WDSEL_IO_BANK0_LSB _u(6)
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C1
#define RESETS_WDSEL_I2C1_RESET _u(0x0)
#define RESETS_WDSEL_I2C1_BITS _u(0x00000020)
#define RESETS_WDSEL_I2C1_MSB _u(5)
#define RESETS_WDSEL_I2C1_LSB _u(5)
#define RESETS_WDSEL_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C0
#define RESETS_WDSEL_I2C0_RESET _u(0x0)
#define RESETS_WDSEL_I2C0_BITS _u(0x00000010)
#define RESETS_WDSEL_I2C0_MSB _u(4)
#define RESETS_WDSEL_I2C0_LSB _u(4)
#define RESETS_WDSEL_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_HSTX
#define RESETS_WDSEL_HSTX_RESET _u(0x0)
#define RESETS_WDSEL_HSTX_BITS _u(0x00000008)
#define RESETS_WDSEL_HSTX_MSB _u(3)
#define RESETS_WDSEL_HSTX_LSB _u(3)
#define RESETS_WDSEL_HSTX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_DMA
#define RESETS_WDSEL_DMA_RESET _u(0x0)
#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
#define RESETS_WDSEL_DMA_MSB _u(2)
#define RESETS_WDSEL_DMA_LSB _u(2)
#define RESETS_WDSEL_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_BUSCTRL
#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
#define RESETS_WDSEL_BUSCTRL_LSB _u(1)
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_ADC
#define RESETS_WDSEL_ADC_RESET _u(0x0)
#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
#define RESETS_WDSEL_ADC_MSB _u(0)
#define RESETS_WDSEL_ADC_LSB _u(0)
#define RESETS_WDSEL_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_RESET_DONE
#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
#define RESETS_RESET_DONE_BITS _u(0x1fffffff)
#define RESETS_RESET_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_USBCTRL
#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x10000000)
#define RESETS_RESET_DONE_USBCTRL_MSB _u(28)
#define RESETS_RESET_DONE_USBCTRL_LSB _u(28)
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART1
#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
#define RESETS_RESET_DONE_UART1_BITS _u(0x08000000)
#define RESETS_RESET_DONE_UART1_MSB _u(27)
#define RESETS_RESET_DONE_UART1_LSB _u(27)
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART0
#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
#define RESETS_RESET_DONE_UART0_BITS _u(0x04000000)
#define RESETS_RESET_DONE_UART0_MSB _u(26)
#define RESETS_RESET_DONE_UART0_LSB _u(26)
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TRNG
#define RESETS_RESET_DONE_TRNG_RESET _u(0x0)
#define RESETS_RESET_DONE_TRNG_BITS _u(0x02000000)
#define RESETS_RESET_DONE_TRNG_MSB _u(25)
#define RESETS_RESET_DONE_TRNG_LSB _u(25)
#define RESETS_RESET_DONE_TRNG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER1
#define RESETS_RESET_DONE_TIMER1_RESET _u(0x0)
#define RESETS_RESET_DONE_TIMER1_BITS _u(0x01000000)
#define RESETS_RESET_DONE_TIMER1_MSB _u(24)
#define RESETS_RESET_DONE_TIMER1_LSB _u(24)
#define RESETS_RESET_DONE_TIMER1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER0
#define RESETS_RESET_DONE_TIMER0_RESET _u(0x0)
#define RESETS_RESET_DONE_TIMER0_BITS _u(0x00800000)
#define RESETS_RESET_DONE_TIMER0_MSB _u(23)
#define RESETS_RESET_DONE_TIMER0_LSB _u(23)
#define RESETS_RESET_DONE_TIMER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TBMAN
#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00400000)
#define RESETS_RESET_DONE_TBMAN_MSB _u(22)
#define RESETS_RESET_DONE_TBMAN_LSB _u(22)
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSINFO
#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00200000)
#define RESETS_RESET_DONE_SYSINFO_MSB _u(21)
#define RESETS_RESET_DONE_SYSINFO_LSB _u(21)
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSCFG
#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00100000)
#define RESETS_RESET_DONE_SYSCFG_MSB _u(20)
#define RESETS_RESET_DONE_SYSCFG_LSB _u(20)
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI1
#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI1_BITS _u(0x00080000)
#define RESETS_RESET_DONE_SPI1_MSB _u(19)
#define RESETS_RESET_DONE_SPI1_LSB _u(19)
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI0
#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI0_BITS _u(0x00040000)
#define RESETS_RESET_DONE_SPI0_MSB _u(18)
#define RESETS_RESET_DONE_SPI0_LSB _u(18)
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SHA256
#define RESETS_RESET_DONE_SHA256_RESET _u(0x0)
#define RESETS_RESET_DONE_SHA256_BITS _u(0x00020000)
#define RESETS_RESET_DONE_SHA256_MSB _u(17)
#define RESETS_RESET_DONE_SHA256_LSB _u(17)
#define RESETS_RESET_DONE_SHA256_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PWM
#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
#define RESETS_RESET_DONE_PWM_BITS _u(0x00010000)
#define RESETS_RESET_DONE_PWM_MSB _u(16)
#define RESETS_RESET_DONE_PWM_LSB _u(16)
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_USB
#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00008000)
#define RESETS_RESET_DONE_PLL_USB_MSB _u(15)
#define RESETS_RESET_DONE_PLL_USB_LSB _u(15)
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_SYS
#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00004000)
#define RESETS_RESET_DONE_PLL_SYS_MSB _u(14)
#define RESETS_RESET_DONE_PLL_SYS_LSB _u(14)
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO2
#define RESETS_RESET_DONE_PIO2_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO2_BITS _u(0x00002000)
#define RESETS_RESET_DONE_PIO2_MSB _u(13)
#define RESETS_RESET_DONE_PIO2_LSB _u(13)
#define RESETS_RESET_DONE_PIO2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO1
#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO1_BITS _u(0x00001000)
#define RESETS_RESET_DONE_PIO1_MSB _u(12)
#define RESETS_RESET_DONE_PIO1_LSB _u(12)
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO0
#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000800)
#define RESETS_RESET_DONE_PIO0_MSB _u(11)
#define RESETS_RESET_DONE_PIO0_LSB _u(11)
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_QSPI
#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(10)
#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(10)
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_BANK0
#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(9)
#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(9)
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_JTAG
#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000100)
#define RESETS_RESET_DONE_JTAG_MSB _u(8)
#define RESETS_RESET_DONE_JTAG_LSB _u(8)
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_QSPI
#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000080)
#define RESETS_RESET_DONE_IO_QSPI_MSB _u(7)
#define RESETS_RESET_DONE_IO_QSPI_LSB _u(7)
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_BANK0
#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000040)
#define RESETS_RESET_DONE_IO_BANK0_MSB _u(6)
#define RESETS_RESET_DONE_IO_BANK0_LSB _u(6)
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C1
#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000020)
#define RESETS_RESET_DONE_I2C1_MSB _u(5)
#define RESETS_RESET_DONE_I2C1_LSB _u(5)
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C0
#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000010)
#define RESETS_RESET_DONE_I2C0_MSB _u(4)
#define RESETS_RESET_DONE_I2C0_LSB _u(4)
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_HSTX
#define RESETS_RESET_DONE_HSTX_RESET _u(0x0)
#define RESETS_RESET_DONE_HSTX_BITS _u(0x00000008)
#define RESETS_RESET_DONE_HSTX_MSB _u(3)
#define RESETS_RESET_DONE_HSTX_LSB _u(3)
#define RESETS_RESET_DONE_HSTX_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_DMA
#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DONE_DMA_MSB _u(2)
#define RESETS_RESET_DONE_DMA_LSB _u(2)
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_BUSCTRL
#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_ADC
#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
#define RESETS_RESET_DONE_ADC_MSB _u(0)
#define RESETS_RESET_DONE_ADC_LSB _u(0)
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_RESETS_H

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lib/pico-sdk/rp2350/hardware/regs/riscv_dm.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/rosc.h Normal file
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@@ -0,0 +1,345 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : ROSC
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_ROSC_H
#define _HARDWARE_REGS_ROSC_H
// =============================================================================
// Register : ROSC_CTRL
// Description : Ring Oscillator control
#define ROSC_CTRL_OFFSET _u(0x00000000)
#define ROSC_CTRL_BITS _u(0x00ffffff)
#define ROSC_CTRL_RESET _u(0x00000aa0)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_ENABLE
// Description : On power-up this field is initialised to ENABLE
// The system clock must be switched to another source before
// setting this field to DISABLE otherwise the chip will lock up
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will enable the
// oscillator.
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define ROSC_CTRL_ENABLE_RESET "-"
#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000)
#define ROSC_CTRL_ENABLE_MSB _u(23)
#define ROSC_CTRL_ENABLE_LSB _u(12)
#define ROSC_CTRL_ENABLE_ACCESS "RW"
#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_FREQ_RANGE
// Description : Controls the number of delay stages in the ROSC ring
// LOW uses stages 0 to 7
// MEDIUM uses stages 2 to 7
// HIGH uses stages 4 to 7
// TOOHIGH uses stages 6 to 7 and should not be used because its
// frequency exceeds design specifications
// The clock output will not glitch when changing the range up one
// step at a time
// The clock output will glitch when changing the range down
// Note: the values here are gray coded which is why HIGH comes
// before TOOHIGH
// 0xfa4 -> LOW
// 0xfa5 -> MEDIUM
// 0xfa7 -> HIGH
// 0xfa6 -> TOOHIGH
#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0)
#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
#define ROSC_CTRL_FREQ_RANGE_MSB _u(11)
#define ROSC_CTRL_FREQ_RANGE_LSB _u(0)
#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4)
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5)
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7)
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
// =============================================================================
// Register : ROSC_FREQA
// Description : The FREQA & FREQB registers control the frequency by
// controlling the drive strength of each stage
// The drive strength has 4 levels determined by the number of
// bits set
// Increasing the number of bits set increases the drive strength
// and increases the oscillation frequency
// 0 bits set is the default drive strength
// 1 bit set doubles the drive strength
// 2 bits set triples drive strength
// 3 bits set quadruples drive strength
// For frequency randomisation set both DS0_RANDOM=1 &
// DS1_RANDOM=1
#define ROSC_FREQA_OFFSET _u(0x00000004)
#define ROSC_FREQA_BITS _u(0xffff77ff)
#define ROSC_FREQA_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQA_PASSWD_RESET _u(0x0000)
#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000)
#define ROSC_FREQA_PASSWD_MSB _u(31)
#define ROSC_FREQA_PASSWD_LSB _u(16)
#define ROSC_FREQA_PASSWD_ACCESS "RW"
#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS3
// Description : Stage 3 drive strength
#define ROSC_FREQA_DS3_RESET _u(0x0)
#define ROSC_FREQA_DS3_BITS _u(0x00007000)
#define ROSC_FREQA_DS3_MSB _u(14)
#define ROSC_FREQA_DS3_LSB _u(12)
#define ROSC_FREQA_DS3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS2
// Description : Stage 2 drive strength
#define ROSC_FREQA_DS2_RESET _u(0x0)
#define ROSC_FREQA_DS2_BITS _u(0x00000700)
#define ROSC_FREQA_DS2_MSB _u(10)
#define ROSC_FREQA_DS2_LSB _u(8)
#define ROSC_FREQA_DS2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1_RANDOM
// Description : Randomises the stage 1 drive strength
#define ROSC_FREQA_DS1_RANDOM_RESET _u(0x0)
#define ROSC_FREQA_DS1_RANDOM_BITS _u(0x00000080)
#define ROSC_FREQA_DS1_RANDOM_MSB _u(7)
#define ROSC_FREQA_DS1_RANDOM_LSB _u(7)
#define ROSC_FREQA_DS1_RANDOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1
// Description : Stage 1 drive strength
#define ROSC_FREQA_DS1_RESET _u(0x0)
#define ROSC_FREQA_DS1_BITS _u(0x00000070)
#define ROSC_FREQA_DS1_MSB _u(6)
#define ROSC_FREQA_DS1_LSB _u(4)
#define ROSC_FREQA_DS1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0_RANDOM
// Description : Randomises the stage 0 drive strength
#define ROSC_FREQA_DS0_RANDOM_RESET _u(0x0)
#define ROSC_FREQA_DS0_RANDOM_BITS _u(0x00000008)
#define ROSC_FREQA_DS0_RANDOM_MSB _u(3)
#define ROSC_FREQA_DS0_RANDOM_LSB _u(3)
#define ROSC_FREQA_DS0_RANDOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0
// Description : Stage 0 drive strength
#define ROSC_FREQA_DS0_RESET _u(0x0)
#define ROSC_FREQA_DS0_BITS _u(0x00000007)
#define ROSC_FREQA_DS0_MSB _u(2)
#define ROSC_FREQA_DS0_LSB _u(0)
#define ROSC_FREQA_DS0_ACCESS "RW"
// =============================================================================
// Register : ROSC_FREQB
// Description : For a detailed description see freqa register
#define ROSC_FREQB_OFFSET _u(0x00000008)
#define ROSC_FREQB_BITS _u(0xffff7777)
#define ROSC_FREQB_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQB_PASSWD_RESET _u(0x0000)
#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000)
#define ROSC_FREQB_PASSWD_MSB _u(31)
#define ROSC_FREQB_PASSWD_LSB _u(16)
#define ROSC_FREQB_PASSWD_ACCESS "RW"
#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS7
// Description : Stage 7 drive strength
#define ROSC_FREQB_DS7_RESET _u(0x0)
#define ROSC_FREQB_DS7_BITS _u(0x00007000)
#define ROSC_FREQB_DS7_MSB _u(14)
#define ROSC_FREQB_DS7_LSB _u(12)
#define ROSC_FREQB_DS7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS6
// Description : Stage 6 drive strength
#define ROSC_FREQB_DS6_RESET _u(0x0)
#define ROSC_FREQB_DS6_BITS _u(0x00000700)
#define ROSC_FREQB_DS6_MSB _u(10)
#define ROSC_FREQB_DS6_LSB _u(8)
#define ROSC_FREQB_DS6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS5
// Description : Stage 5 drive strength
#define ROSC_FREQB_DS5_RESET _u(0x0)
#define ROSC_FREQB_DS5_BITS _u(0x00000070)
#define ROSC_FREQB_DS5_MSB _u(6)
#define ROSC_FREQB_DS5_LSB _u(4)
#define ROSC_FREQB_DS5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS4
// Description : Stage 4 drive strength
#define ROSC_FREQB_DS4_RESET _u(0x0)
#define ROSC_FREQB_DS4_BITS _u(0x00000007)
#define ROSC_FREQB_DS4_MSB _u(2)
#define ROSC_FREQB_DS4_LSB _u(0)
#define ROSC_FREQB_DS4_ACCESS "RW"
// =============================================================================
// Register : ROSC_RANDOM
// Description : Loads a value to the LFSR randomiser
#define ROSC_RANDOM_OFFSET _u(0x0000000c)
#define ROSC_RANDOM_BITS _u(0xffffffff)
#define ROSC_RANDOM_RESET _u(0x3f04b16d)
// -----------------------------------------------------------------------------
// Field : ROSC_RANDOM_SEED
#define ROSC_RANDOM_SEED_RESET _u(0x3f04b16d)
#define ROSC_RANDOM_SEED_BITS _u(0xffffffff)
#define ROSC_RANDOM_SEED_MSB _u(31)
#define ROSC_RANDOM_SEED_LSB _u(0)
#define ROSC_RANDOM_SEED_ACCESS "RW"
// =============================================================================
// Register : ROSC_DORMANT
// Description : Ring Oscillator pause control
// This is used to save power by pausing the ROSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> dormant
// 0x77616b65 -> WAKE
#define ROSC_DORMANT_OFFSET _u(0x00000010)
#define ROSC_DORMANT_BITS _u(0xffffffff)
#define ROSC_DORMANT_RESET "-"
#define ROSC_DORMANT_MSB _u(31)
#define ROSC_DORMANT_LSB _u(0)
#define ROSC_DORMANT_ACCESS "RW"
#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : ROSC_DIV
// Description : Controls the output divider
// set to 0xaa00 + div where
// div = 0 divides by 128
// div = 1-127 divides by div
// any other value sets div=128
// this register resets to div=32
// 0xaa00 -> PASS
#define ROSC_DIV_OFFSET _u(0x00000014)
#define ROSC_DIV_BITS _u(0x0000ffff)
#define ROSC_DIV_RESET "-"
#define ROSC_DIV_MSB _u(15)
#define ROSC_DIV_LSB _u(0)
#define ROSC_DIV_ACCESS "RW"
#define ROSC_DIV_VALUE_PASS _u(0xaa00)
// =============================================================================
// Register : ROSC_PHASE
// Description : Controls the phase shifted output
#define ROSC_PHASE_OFFSET _u(0x00000018)
#define ROSC_PHASE_BITS _u(0x00000fff)
#define ROSC_PHASE_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD
// Description : set to 0xaa
// any other value enables the output with shift=0
#define ROSC_PHASE_PASSWD_RESET _u(0x00)
#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
#define ROSC_PHASE_PASSWD_MSB _u(11)
#define ROSC_PHASE_PASSWD_LSB _u(4)
#define ROSC_PHASE_PASSWD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_ENABLE
// Description : enable the phase-shifted output
// this can be changed on-the-fly
#define ROSC_PHASE_ENABLE_RESET _u(0x1)
#define ROSC_PHASE_ENABLE_BITS _u(0x00000008)
#define ROSC_PHASE_ENABLE_MSB _u(3)
#define ROSC_PHASE_ENABLE_LSB _u(3)
#define ROSC_PHASE_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_FLIP
// Description : invert the phase-shifted output
// this is ignored when div=1
#define ROSC_PHASE_FLIP_RESET _u(0x0)
#define ROSC_PHASE_FLIP_BITS _u(0x00000004)
#define ROSC_PHASE_FLIP_MSB _u(2)
#define ROSC_PHASE_FLIP_LSB _u(2)
#define ROSC_PHASE_FLIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_SHIFT
// Description : phase shift the phase-shifted output by SHIFT input clocks
// this can be changed on-the-fly
// must be set to 0 before setting div=1
#define ROSC_PHASE_SHIFT_RESET _u(0x0)
#define ROSC_PHASE_SHIFT_BITS _u(0x00000003)
#define ROSC_PHASE_SHIFT_MSB _u(1)
#define ROSC_PHASE_SHIFT_LSB _u(0)
#define ROSC_PHASE_SHIFT_ACCESS "RW"
// =============================================================================
// Register : ROSC_STATUS
// Description : Ring Oscillator Status
#define ROSC_STATUS_OFFSET _u(0x0000001c)
#define ROSC_STATUS_BITS _u(0x81011000)
#define ROSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define ROSC_STATUS_STABLE_RESET _u(0x0)
#define ROSC_STATUS_STABLE_BITS _u(0x80000000)
#define ROSC_STATUS_STABLE_MSB _u(31)
#define ROSC_STATUS_STABLE_LSB _u(31)
#define ROSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define ROSC_STATUS_BADWRITE_MSB _u(24)
#define ROSC_STATUS_BADWRITE_LSB _u(24)
#define ROSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_DIV_RUNNING
// Description : post-divider is running
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_DIV_RUNNING_RESET "-"
#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000)
#define ROSC_STATUS_DIV_RUNNING_MSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_LSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_ENABLED_RESET "-"
#define ROSC_STATUS_ENABLED_BITS _u(0x00001000)
#define ROSC_STATUS_ENABLED_MSB _u(12)
#define ROSC_STATUS_ENABLED_LSB _u(12)
#define ROSC_STATUS_ENABLED_ACCESS "RO"
// =============================================================================
// Register : ROSC_RANDOMBIT
// Description : This just reads the state of the oscillator output so
// randomness is compromised if the ring oscillator is stopped or
// run at a harmonic of the bus frequency
#define ROSC_RANDOMBIT_OFFSET _u(0x00000020)
#define ROSC_RANDOMBIT_BITS _u(0x00000001)
#define ROSC_RANDOMBIT_RESET _u(0x00000001)
#define ROSC_RANDOMBIT_MSB _u(0)
#define ROSC_RANDOMBIT_LSB _u(0)
#define ROSC_RANDOMBIT_ACCESS "RO"
// =============================================================================
// Register : ROSC_COUNT
// Description : A down counter running at the ROSC frequency which counts to
// zero and stops.
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define ROSC_COUNT_OFFSET _u(0x00000024)
#define ROSC_COUNT_BITS _u(0x0000ffff)
#define ROSC_COUNT_RESET _u(0x00000000)
#define ROSC_COUNT_MSB _u(15)
#define ROSC_COUNT_LSB _u(0)
#define ROSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_ROSC_H

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lib/pico-sdk/rp2350/hardware/regs/rp_ap.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : RP_AP
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_RP_AP_H
#define _HARDWARE_REGS_RP_AP_H
// =============================================================================
// Register : RP_AP_CTRL
// Description : This register is primarily used for DFT but can also be used to
// overcome some power up problems. However, it should not be used
// to force power up of domains. Use DBG_POW_OVRD for that.
#define RP_AP_CTRL_OFFSET _u(0x00000000)
#define RP_AP_CTRL_BITS _u(0xc000007f)
#define RP_AP_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_RESCUE_RESTART
// Description : Allows debug of boot problems by restarting the chip with
// minimal boot code execution. Write to 1 to put the chip in
// reset then write to 0 to restart the chip with the rescue flag
// set. The rescue flag is in the POWMAN_CHIP_RESET register and
// is read by boot code. The rescue flag is cleared by writing 0
// to POWMAN_CHIP_RESET_RESCUE_FLAG or by resetting the chip by
// any means other than RESCUE_RESTART.
#define RP_AP_CTRL_RESCUE_RESTART_RESET _u(0x0)
#define RP_AP_CTRL_RESCUE_RESTART_BITS _u(0x80000000)
#define RP_AP_CTRL_RESCUE_RESTART_MSB _u(31)
#define RP_AP_CTRL_RESCUE_RESTART_LSB _u(31)
#define RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_SPARE
// Description : Unused
#define RP_AP_CTRL_SPARE_RESET _u(0x0)
#define RP_AP_CTRL_SPARE_BITS _u(0x40000000)
#define RP_AP_CTRL_SPARE_MSB _u(30)
#define RP_AP_CTRL_SPARE_LSB _u(30)
#define RP_AP_CTRL_SPARE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_DBG_FRCE_GPIO_LPCK
// Description : Allows chip start-up when the Low Power Oscillator (LPOSC) is
// inoperative or malfunctioning and also allows the initial power
// sequencing rate to be adjusted. Write to 1 to force the LPOSC
// output to be driven from a GPIO (gpio20 on 80-pin package,
// gpio34 on the 60-pin package). If the LPOSC is inoperative or
// malfunctioning it may also be necessary to set the
// LPOSC_STABLE_FRCE bit in this register. The user must provide a
// clock on the GPIO. For normal operation use a clock running at
// around 32kHz. Adjusting the frequency will speed up or slow
// down the initial power-up sequence.
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET _u(0x0)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS _u(0x00000040)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB _u(6)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB _u(6)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_LPOSC_STABLE_FRCE
// Description : Allows the chip to start-up even though the Low Power
// Oscillator (LPOSC) is failing to set its stable flag. Initial
// power sequencing is clocked by LPOSC at around 32kHz but does
// not start until the LPOSC declares itself to be stable. If the
// LPOSC is otherwise working correctly the chip will boot when
// this bit is set. If the LPOSC is not working then
// DBG_FRCE_GPIO_LPCK must be set and an external clock provided.
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET _u(0x0)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS _u(0x00000020)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB _u(5)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB _u(5)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DFT_ISO_OFF
// Description : Holds the isolation gates between power domains in the open
// state. This is intended to hold the gates open for DFT and
// power manager debug. It is not intended to force the isolation
// gates open. Use the overrides in DBG_POW_OVRD to force the
// isolation gates open or closed.
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS _u(0x00000010)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB _u(4)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB _u(4)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DFT_PWRON
// Description : Holds the power switches on for all domains. This is intended
// to keep the power on for DFT and debug, rather than for
// switching the power on. The power switches are not sequenced
// and the sudden demand for current could cause the always-on
// power domain to brown out. This register is in the always-on
// domain therefore chaos could ensue. It is recommended to use
// the DBG_POW_OVRD controls instead.
#define RP_AP_CTRL_POWMAN_DFT_PWRON_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_BITS _u(0x00000008)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_MSB _u(3)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_LSB _u(3)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DBGMODE
// Description : This prevents the power manager from powering down and
// resetting the switched-core power domain. It is intended for
// DFT and for debugging the power manager after the chip has
// booted. It cannot be used to force initial power on because it
// simultaneously deasserts the reset.
#define RP_AP_CTRL_POWMAN_DBGMODE_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DBGMODE_BITS _u(0x00000004)
#define RP_AP_CTRL_POWMAN_DBGMODE_MSB _u(2)
#define RP_AP_CTRL_POWMAN_DBGMODE_LSB _u(2)
#define RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_JTAG_FUNCSEL
// Description : Multiplexes the JTAG ports onto GPIO0-3
#define RP_AP_CTRL_JTAG_FUNCSEL_RESET _u(0x0)
#define RP_AP_CTRL_JTAG_FUNCSEL_BITS _u(0x00000002)
#define RP_AP_CTRL_JTAG_FUNCSEL_MSB _u(1)
#define RP_AP_CTRL_JTAG_FUNCSEL_LSB _u(1)
#define RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_JTAG_TRSTN
// Description : Resets the JTAG module. Active low.
#define RP_AP_CTRL_JTAG_TRSTN_RESET _u(0x0)
#define RP_AP_CTRL_JTAG_TRSTN_BITS _u(0x00000001)
#define RP_AP_CTRL_JTAG_TRSTN_MSB _u(0)
#define RP_AP_CTRL_JTAG_TRSTN_LSB _u(0)
#define RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBGKEY
// Description : Serial key load interface (write-only)
#define RP_AP_DBGKEY_OFFSET _u(0x00000004)
#define RP_AP_DBGKEY_BITS _u(0x00000007)
#define RP_AP_DBGKEY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_RESET
// Description : Reset (before sending a new key)
#define RP_AP_DBGKEY_RESET_RESET _u(0x0)
#define RP_AP_DBGKEY_RESET_BITS _u(0x00000004)
#define RP_AP_DBGKEY_RESET_MSB _u(2)
#define RP_AP_DBGKEY_RESET_LSB _u(2)
#define RP_AP_DBGKEY_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_PUSH
#define RP_AP_DBGKEY_PUSH_RESET _u(0x0)
#define RP_AP_DBGKEY_PUSH_BITS _u(0x00000002)
#define RP_AP_DBGKEY_PUSH_MSB _u(1)
#define RP_AP_DBGKEY_PUSH_LSB _u(1)
#define RP_AP_DBGKEY_PUSH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_DATA
#define RP_AP_DBGKEY_DATA_RESET _u(0x0)
#define RP_AP_DBGKEY_DATA_BITS _u(0x00000001)
#define RP_AP_DBGKEY_DATA_MSB _u(0)
#define RP_AP_DBGKEY_DATA_LSB _u(0)
#define RP_AP_DBGKEY_DATA_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SWCORE
// Description : This register indicates the state of the power sequencer for
// the switched-core domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
// Bits 9-11 describe the states of the power manager clocks which
// change as clock generators in the switched-core become
// available following switched-core power up.
// This bus can be sent to GPIO for debug. See
// DBG_POW_OUTPUT_TO_GPIO in the DBG_POW_OVRD register.
#define RP_AP_DBG_POW_STATE_SWCORE_OFFSET _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SWCORE_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK
// Description : Indicates the source of the power manager clock. On switched-
// core power up the clock switches from the LPOSC to clk_ref and
// this flag will be set. clk_ref will be running from the ROSC
// initially but will switch to XOSC when it comes available. On
// switched-core power down the clock switches to LPOSC and this
// flag will be cleared.
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS _u(0x00000800)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB _u(11)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB _u(11)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK
// Description : Indicates the switched-core power sequencer is waiting for the
// power manager clock to update. On switched-core power up the
// clock switches from the LPOSC to clk_ref. clk_ref will be
// running from the ROSC initially but will switch to XOSC when it
// comes available. On switched-core power down the clock switches
// to LPOSC.
// If the switched-core power up sequence stalls with this flag
// active then it means clk_ref is not running which indicates a
// problem with the ROSC. If that happens then set
// DBG_POW_RESTART_FROM_XOSC in the DBG_POW_OVRD register to avoid
// using the ROSC.
// If the switched-core power down sequence stalls with this flag
// active then it means LPOSC is not running. The solution is to
// not stop LPOSC when the switched-core power domain is powered.
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS _u(0x00000400)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB _u(10)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB _u(10)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK
// Description : Indicates that the switched-core power sequencer is waiting for
// the AON-Timer to update. On switched-core power-up there is
// nothing to be done. The AON-Timer continues to run from the
// LPOSC so this flag will not be set. Software decides whether to
// switch the AON-Timer clock to XOSC (via clk_ref). On switched-
// core power-down the sequencer will switch the AON-Timer back to
// LPOSC if software switched it to XOSC. During the switchover
// the WAITING_TIMCK flag will be set. If the switched-core power
// down sequence stalls with this flag active then the only
// recourse is to reset the chip and change software to not select
// XOSC as the AON-Timer source.
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS _u(0x00000200)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB _u(9)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB _u(9)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_XIP
// Description : This register indicates the state of the power sequencer for
// the XIP domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_XIP_OFFSET _u(0x0000000c)
#define RP_AP_DBG_POW_STATE_XIP_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_XIP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SRAM0
// Description : This register indicates the state of the power sequencer for
// the SRAM0 domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_SRAM0_OFFSET _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM0_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SRAM1
// Description : This register indicates the state of the power sequencer for
// the SRAM1 domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_SRAM1_OFFSET _u(0x00000014)
#define RP_AP_DBG_POW_STATE_SRAM1_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_OVRD
// Description : This register allows external control of the power sequencer
// outputs for all the switched power domains. If any of the power
// sequencers stall at any stage then force power up operation of
// all domains by running this sequence:
// - set DBG_POW_OVRD = 0x3b to force small power switches on,
// large power switches off, resets on and isolation on
// - allow time for the domain power supplies to reach full rail
// - set DBG_POW_OVRD = 0x3b to force large power switches on
// - set DBG_POW_OVRD = 0x37 to remove isolation
// - set DBG_POW_OVRD = 0x17 to remove resets
#define RP_AP_DBG_POW_OVRD_OFFSET _u(0x00000018)
#define RP_AP_DBG_POW_OVRD_BITS _u(0x0000007f)
#define RP_AP_DBG_POW_OVRD_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC
// Description : By default the system begins boot as soon as a clock is
// available from the ROSC, then it switches to the XOSC when it
// is available. This is done because the XOSC takes several ms to
// start up. If there is a problem with the ROSC then the default
// behaviour can be changed to not use the ROSC and wait for XOSC.
// However, this requires a mask change to modify the reset value
// of the Power Manager START_FROM_XOSC register. To allow
// experimentation the default can be temporarily changed by
// setting this register bit to 1. After setting this bit the core
// must be reset by a Coresight dprst or a rescue reset (see
// RESCUE_RESTART in the RP_AP_CTRL register above). A power-on
// reset, brown-out reset or RUN pin reset will reset this control
// and revert to the default behaviour.
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS _u(0x00000040)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB _u(6)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB _u(6)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESET
// Description : When DBG_POW_OVRD_RESET=1 this register bit controls the resets
// for all domains. 1 = reset. 0 = not reset.
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS _u(0x00000020)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB _u(5)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB _u(5)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET
// Description : Enables DBG_POW_RESET to control the resets for the power
// manager and the switched-core. Essentially that is everythjing
// except the Coresight 2-wire interface and the RP_AP registers.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS _u(0x00000010)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB _u(4)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB _u(4)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_ISO
// Description : When DBG_POW_OVRD_ISO=1 this register bit controls the
// isolation gates for all domains. 1 = isolated. 0 = not
// isolated.
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS _u(0x00000008)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB _u(3)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB _u(3)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO
// Description : Enables DBG_POW_ISO to control the isolation gates between
// domains.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS _u(0x00000004)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB _u(2)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB _u(2)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ
// Description : Turn on the large power switches for all domains. This should
// not be done until sufficient time has been allowed for the
// small switches to bring the supplies up. Switching the large
// switches on too soon risks browning out the always-on domain
// and corrupting these very registers.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS _u(0x00000002)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB _u(1)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB _u(1)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ
// Description : Turn on the small power switches for all domains. This switches
// on chain 0 for each domain and switches off chains 2 & 3 and
// the large power switch chain. This will bring the power up for
// all domains without browning out the always-on power domain.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS _u(0x00000001)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB _u(0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB _u(0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBG_POW_OUTPUT_TO_GPIO
// Description : Send some, or all, bits of DBG_POW_STATE_SWCORE to gpios.
// Bit 0 sends bit 0 of DBG_POW_STATE_SWCORE to GPIO 34
// Bit 1 sends bit 1 of DBG_POW_STATE_SWCORE to GPIO 35
// Bit 2 sends bit 2 of DBG_POW_STATE_SWCORE to GPIO 36
// .
// .
// Bit 11 sends bit 11 of DBG_POW_STATE_SWCORE to GPIO 45
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET _u(0x0000001c)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET _u(0x000)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB _u(11)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB _u(0)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW"
// =============================================================================
// Register : RP_AP_IDR
// Description : Standard Coresight ID Register
#define RP_AP_IDR_OFFSET _u(0x00000dfc)
#define RP_AP_IDR_BITS _u(0xffffffff)
#define RP_AP_IDR_RESET "-"
#define RP_AP_IDR_MSB _u(31)
#define RP_AP_IDR_LSB _u(0)
#define RP_AP_IDR_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_RP_AP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SHA256
// Version : 1
// Bus type : apb
// Description : SHA-256 hash function implementation
// =============================================================================
#ifndef _HARDWARE_REGS_SHA256_H
#define _HARDWARE_REGS_SHA256_H
// =============================================================================
// Register : SHA256_CSR
// Description : Control and status register
#define SHA256_CSR_OFFSET _u(0x00000000)
#define SHA256_CSR_BITS _u(0x00001317)
#define SHA256_CSR_RESET _u(0x00001206)
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_BSWAP
// Description : Enable byte swapping of 32-bit values at the point they are
// committed to the SHA message scheduler.
//
// This block's bus interface assembles byte/halfword data into
// message words in little-endian order, so that DMAing the same
// buffer with different transfer sizes always gives the same
// result on a little-endian system like RP2350.
//
// However, when marshalling bytes into blocks, SHA expects that
// the first byte is the *most significant* in each message word.
// To resolve this, once the bus interface has accumulated 32 bits
// of data (either a word write, two halfword writes in little-
// endian order, or four byte writes in little-endian order) the
// final value can be byte-swapped before passing to the actual
// SHA core.
//
// This feature is enabled by default because using the SHA core
// to checksum byte buffers is expected to be more common than
// having preformatted SHA message words lying around.
#define SHA256_CSR_BSWAP_RESET _u(0x1)
#define SHA256_CSR_BSWAP_BITS _u(0x00001000)
#define SHA256_CSR_BSWAP_MSB _u(12)
#define SHA256_CSR_BSWAP_LSB _u(12)
#define SHA256_CSR_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_DMA_SIZE
// Description : Configure DREQ logic for the correct DMA data size. Must be
// configured before the DMA channel is triggered.
//
// The SHA-256 core's DREQ logic requests one entire block of data
// at once, since there is no FIFO, and data goes straight into
// the core's message schedule and digest hardware. Therefore,
// when transferring data with DMA, CSR_DMA_SIZE must be
// configured in advance so that the correct number of transfers
// can be requested per block.
// 0x0 -> 8bit
// 0x1 -> 16bit
// 0x2 -> 32bit
#define SHA256_CSR_DMA_SIZE_RESET _u(0x2)
#define SHA256_CSR_DMA_SIZE_BITS _u(0x00000300)
#define SHA256_CSR_DMA_SIZE_MSB _u(9)
#define SHA256_CSR_DMA_SIZE_LSB _u(8)
#define SHA256_CSR_DMA_SIZE_ACCESS "RW"
#define SHA256_CSR_DMA_SIZE_VALUE_8BIT _u(0x0)
#define SHA256_CSR_DMA_SIZE_VALUE_16BIT _u(0x1)
#define SHA256_CSR_DMA_SIZE_VALUE_32BIT _u(0x2)
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_ERR_WDATA_NOT_RDY
// Description : Set when a write occurs whilst the SHA-256 core is not ready
// for data (WDATA_RDY is low). Write one to clear.
#define SHA256_CSR_ERR_WDATA_NOT_RDY_RESET _u(0x0)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_BITS _u(0x00000010)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_MSB _u(4)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_LSB _u(4)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_SUM_VLD
// Description : If 1, the SHA-256 checksum presented in registers SUM0 through
// SUM7 is currently valid.
//
// Goes low when WDATA is first written, then returns high once 16
// words have been written and the digest of the current 512-bit
// block has subsequently completed.
#define SHA256_CSR_SUM_VLD_RESET _u(0x1)
#define SHA256_CSR_SUM_VLD_BITS _u(0x00000004)
#define SHA256_CSR_SUM_VLD_MSB _u(2)
#define SHA256_CSR_SUM_VLD_LSB _u(2)
#define SHA256_CSR_SUM_VLD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_WDATA_RDY
// Description : If 1, the SHA-256 core is ready to accept more data through the
// WDATA register.
//
// After writing 16 words, this flag will go low for 57 cycles
// whilst the core completes its digest.
#define SHA256_CSR_WDATA_RDY_RESET _u(0x1)
#define SHA256_CSR_WDATA_RDY_BITS _u(0x00000002)
#define SHA256_CSR_WDATA_RDY_MSB _u(1)
#define SHA256_CSR_WDATA_RDY_LSB _u(1)
#define SHA256_CSR_WDATA_RDY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_START
// Description : Write 1 to prepare the SHA-256 core for a new checksum.
//
// The SUMx registers are initialised to the proper values
// (fractional bits of square roots of first 8 primes) and
// internal counters are cleared. This immediately forces
// WDATA_RDY and SUM_VLD high.
//
// START must be written before initiating a DMA transfer to the
// SHA-256 core, because the core will always request 16 transfers
// at a time (1 512-bit block). Additionally, the DMA channel
// should be configured for a multiple of 16 32-bit transfers.
#define SHA256_CSR_START_RESET _u(0x0)
#define SHA256_CSR_START_BITS _u(0x00000001)
#define SHA256_CSR_START_MSB _u(0)
#define SHA256_CSR_START_LSB _u(0)
#define SHA256_CSR_START_ACCESS "SC"
// =============================================================================
// Register : SHA256_WDATA
// Description : Write data register
// After pulsing START and writing 16 words of data to this
// register, WDATA_RDY will go low and the SHA-256 core will
// complete the digest of the current 512-bit block.
//
// Software is responsible for ensuring the data is correctly
// padded and terminated to a whole number of 512-bit blocks.
//
// After this, WDATA_RDY will return high, and more data can be
// written (if any).
//
// This register supports word, halfword and byte writes, so that
// DMA from non-word-aligned buffers can be supported. The total
// amount of data per block remains the same (16 words, 32
// halfwords or 64 bytes) and byte/halfword transfers must not be
// mixed within a block.
#define SHA256_WDATA_OFFSET _u(0x00000004)
#define SHA256_WDATA_BITS _u(0xffffffff)
#define SHA256_WDATA_RESET _u(0x00000000)
#define SHA256_WDATA_MSB _u(31)
#define SHA256_WDATA_LSB _u(0)
#define SHA256_WDATA_ACCESS "WF"
// =============================================================================
// Register : SHA256_SUM0
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM0_OFFSET _u(0x00000008)
#define SHA256_SUM0_BITS _u(0xffffffff)
#define SHA256_SUM0_RESET _u(0x00000000)
#define SHA256_SUM0_MSB _u(31)
#define SHA256_SUM0_LSB _u(0)
#define SHA256_SUM0_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM1
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM1_OFFSET _u(0x0000000c)
#define SHA256_SUM1_BITS _u(0xffffffff)
#define SHA256_SUM1_RESET _u(0x00000000)
#define SHA256_SUM1_MSB _u(31)
#define SHA256_SUM1_LSB _u(0)
#define SHA256_SUM1_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM2
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM2_OFFSET _u(0x00000010)
#define SHA256_SUM2_BITS _u(0xffffffff)
#define SHA256_SUM2_RESET _u(0x00000000)
#define SHA256_SUM2_MSB _u(31)
#define SHA256_SUM2_LSB _u(0)
#define SHA256_SUM2_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM3
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM3_OFFSET _u(0x00000014)
#define SHA256_SUM3_BITS _u(0xffffffff)
#define SHA256_SUM3_RESET _u(0x00000000)
#define SHA256_SUM3_MSB _u(31)
#define SHA256_SUM3_LSB _u(0)
#define SHA256_SUM3_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM4
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM4_OFFSET _u(0x00000018)
#define SHA256_SUM4_BITS _u(0xffffffff)
#define SHA256_SUM4_RESET _u(0x00000000)
#define SHA256_SUM4_MSB _u(31)
#define SHA256_SUM4_LSB _u(0)
#define SHA256_SUM4_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM5
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM5_OFFSET _u(0x0000001c)
#define SHA256_SUM5_BITS _u(0xffffffff)
#define SHA256_SUM5_RESET _u(0x00000000)
#define SHA256_SUM5_MSB _u(31)
#define SHA256_SUM5_LSB _u(0)
#define SHA256_SUM5_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM6
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM6_OFFSET _u(0x00000020)
#define SHA256_SUM6_BITS _u(0xffffffff)
#define SHA256_SUM6_RESET _u(0x00000000)
#define SHA256_SUM6_MSB _u(31)
#define SHA256_SUM6_LSB _u(0)
#define SHA256_SUM6_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM7
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM7_OFFSET _u(0x00000024)
#define SHA256_SUM7_BITS _u(0xffffffff)
#define SHA256_SUM7_RESET _u(0x00000000)
#define SHA256_SUM7_MSB _u(31)
#define SHA256_SUM7_LSB _u(0)
#define SHA256_SUM7_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SHA256_H

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lib/pico-sdk/rp2350/hardware/regs/spi.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SPI
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_SPI_H
#define _HARDWARE_REGS_SPI_H
// =============================================================================
// Register : SPI_SSPCR0
// Description : Control register 0, SSPCR0 on page 3-4
#define SPI_SSPCR0_OFFSET _u(0x00000000)
#define SPI_SSPCR0_BITS _u(0x0000ffff)
#define SPI_SSPCR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SCR
// Description : Serial clock rate. The value SCR is used to generate the
// transmit and receive bit rate of the PrimeCell SSP. The bit
// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
// value from 2-254, programmed through the SSPCPSR register and
// SCR is a value from 0-255.
#define SPI_SSPCR0_SCR_RESET _u(0x00)
#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00)
#define SPI_SSPCR0_SCR_MSB _u(15)
#define SPI_SSPCR0_SCR_LSB _u(8)
#define SPI_SSPCR0_SCR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPH
// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
// See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPH_RESET _u(0x0)
#define SPI_SSPCR0_SPH_BITS _u(0x00000080)
#define SPI_SSPCR0_SPH_MSB _u(7)
#define SPI_SSPCR0_SPH_LSB _u(7)
#define SPI_SSPCR0_SPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPO
// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
// only. See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPO_RESET _u(0x0)
#define SPI_SSPCR0_SPO_BITS _u(0x00000040)
#define SPI_SSPCR0_SPO_MSB _u(6)
#define SPI_SSPCR0_SPO_LSB _u(6)
#define SPI_SSPCR0_SPO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_FRF
// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
// serial frame format. 10 National Microwire frame format. 11
// Reserved, undefined operation.
#define SPI_SSPCR0_FRF_RESET _u(0x0)
#define SPI_SSPCR0_FRF_BITS _u(0x00000030)
#define SPI_SSPCR0_FRF_MSB _u(5)
#define SPI_SSPCR0_FRF_LSB _u(4)
#define SPI_SSPCR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_DSS
// Description : Data Size Select: 0000 Reserved, undefined operation. 0001
// Reserved, undefined operation. 0010 Reserved, undefined
// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data.
// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
#define SPI_SSPCR0_DSS_RESET _u(0x0)
#define SPI_SSPCR0_DSS_BITS _u(0x0000000f)
#define SPI_SSPCR0_DSS_MSB _u(3)
#define SPI_SSPCR0_DSS_LSB _u(0)
#define SPI_SSPCR0_DSS_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPCR1
// Description : Control register 1, SSPCR1 on page 3-5
#define SPI_SSPCR1_OFFSET _u(0x00000004)
#define SPI_SSPCR1_BITS _u(0x0000000f)
#define SPI_SSPCR1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SOD
// Description : Slave-mode output disable. This bit is relevant only in the
// slave mode, MS=1. In multiple-slave systems, it is possible for
// an PrimeCell SSP master to broadcast a message to all slaves in
// the system while ensuring that only one slave drives data onto
// its serial output line. In such systems the RXD lines from
// multiple slaves could be tied together. To operate in such
// systems, the SOD bit can be set if the PrimeCell SSP slave is
// not supposed to drive the SSPTXD line: 0 SSP can drive the
// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
// output in slave mode.
#define SPI_SSPCR1_SOD_RESET _u(0x0)
#define SPI_SSPCR1_SOD_BITS _u(0x00000008)
#define SPI_SSPCR1_SOD_MSB _u(3)
#define SPI_SSPCR1_SOD_LSB _u(3)
#define SPI_SSPCR1_SOD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_MS
// Description : Master or slave mode select. This bit can be modified only when
// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
// master, default. 1 Device configured as slave.
#define SPI_SSPCR1_MS_RESET _u(0x0)
#define SPI_SSPCR1_MS_BITS _u(0x00000004)
#define SPI_SSPCR1_MS_MSB _u(2)
#define SPI_SSPCR1_MS_LSB _u(2)
#define SPI_SSPCR1_MS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SSE
// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
// operation enabled.
#define SPI_SSPCR1_SSE_RESET _u(0x0)
#define SPI_SSPCR1_SSE_BITS _u(0x00000002)
#define SPI_SSPCR1_SSE_MSB _u(1)
#define SPI_SSPCR1_SSE_LSB _u(1)
#define SPI_SSPCR1_SSE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_LBM
// Description : Loop back mode: 0 Normal serial port operation enabled. 1
// Output of transmit serial shifter is connected to input of
// receive serial shifter internally.
#define SPI_SSPCR1_LBM_RESET _u(0x0)
#define SPI_SSPCR1_LBM_BITS _u(0x00000001)
#define SPI_SSPCR1_LBM_MSB _u(0)
#define SPI_SSPCR1_LBM_LSB _u(0)
#define SPI_SSPCR1_LBM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPDR
// Description : Data register, SSPDR on page 3-6
#define SPI_SSPDR_OFFSET _u(0x00000008)
#define SPI_SSPDR_BITS _u(0x0000ffff)
#define SPI_SSPDR_RESET "-"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDR_DATA
// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO.
// You must right-justify data when the PrimeCell SSP is
// programmed for a data size that is less than 16 bits. Unused
// bits at the top are ignored by transmit logic. The receive
// logic automatically right-justifies.
#define SPI_SSPDR_DATA_RESET "-"
#define SPI_SSPDR_DATA_BITS _u(0x0000ffff)
#define SPI_SSPDR_DATA_MSB _u(15)
#define SPI_SSPDR_DATA_LSB _u(0)
#define SPI_SSPDR_DATA_ACCESS "RWF"
// =============================================================================
// Register : SPI_SSPSR
// Description : Status register, SSPSR on page 3-7
#define SPI_SSPSR_OFFSET _u(0x0000000c)
#define SPI_SSPSR_BITS _u(0x0000001f)
#define SPI_SSPSR_RESET _u(0x00000003)
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_BSY
// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
// transmitting and/or receiving a frame or the transmit FIFO is
// not empty.
#define SPI_SSPSR_BSY_RESET _u(0x0)
#define SPI_SSPSR_BSY_BITS _u(0x00000010)
#define SPI_SSPSR_BSY_MSB _u(4)
#define SPI_SSPSR_BSY_LSB _u(4)
#define SPI_SSPSR_BSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RFF
// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
// FIFO is full.
#define SPI_SSPSR_RFF_RESET _u(0x0)
#define SPI_SSPSR_RFF_BITS _u(0x00000008)
#define SPI_SSPSR_RFF_MSB _u(3)
#define SPI_SSPSR_RFF_LSB _u(3)
#define SPI_SSPSR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RNE
// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
// FIFO is not empty.
#define SPI_SSPSR_RNE_RESET _u(0x0)
#define SPI_SSPSR_RNE_BITS _u(0x00000004)
#define SPI_SSPSR_RNE_MSB _u(2)
#define SPI_SSPSR_RNE_LSB _u(2)
#define SPI_SSPSR_RNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TNF
// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
// FIFO is not full.
#define SPI_SSPSR_TNF_RESET _u(0x1)
#define SPI_SSPSR_TNF_BITS _u(0x00000002)
#define SPI_SSPSR_TNF_MSB _u(1)
#define SPI_SSPSR_TNF_LSB _u(1)
#define SPI_SSPSR_TNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TFE
// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
// Transmit FIFO is empty.
#define SPI_SSPSR_TFE_RESET _u(0x1)
#define SPI_SSPSR_TFE_BITS _u(0x00000001)
#define SPI_SSPSR_TFE_MSB _u(0)
#define SPI_SSPSR_TFE_LSB _u(0)
#define SPI_SSPSR_TFE_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPCPSR
// Description : Clock prescale register, SSPCPSR on page 3-8
#define SPI_SSPCPSR_OFFSET _u(0x00000010)
#define SPI_SSPCPSR_BITS _u(0x000000ff)
#define SPI_SSPCPSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCPSR_CPSDVSR
// Description : Clock prescale divisor. Must be an even number from 2-254,
// depending on the frequency of SSPCLK. The least significant bit
// always returns zero on reads.
#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00)
#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff)
#define SPI_SSPCPSR_CPSDVSR_MSB _u(7)
#define SPI_SSPCPSR_CPSDVSR_LSB _u(0)
#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPIMSC
// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
#define SPI_SSPIMSC_OFFSET _u(0x00000014)
#define SPI_SSPIMSC_BITS _u(0x0000000f)
#define SPI_SSPIMSC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_TXIM
// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
// less condition interrupt is masked. 1 Transmit FIFO half empty
// or less condition interrupt is not masked.
#define SPI_SSPIMSC_TXIM_RESET _u(0x0)
#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008)
#define SPI_SSPIMSC_TXIM_MSB _u(3)
#define SPI_SSPIMSC_TXIM_LSB _u(3)
#define SPI_SSPIMSC_TXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RXIM
// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
// condition interrupt is masked. 1 Receive FIFO half full or less
// condition interrupt is not masked.
#define SPI_SSPIMSC_RXIM_RESET _u(0x0)
#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004)
#define SPI_SSPIMSC_RXIM_MSB _u(2)
#define SPI_SSPIMSC_RXIM_LSB _u(2)
#define SPI_SSPIMSC_RXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RTIM
// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no
// read prior to timeout period interrupt is masked. 1 Receive
// FIFO not empty and no read prior to timeout period interrupt is
// not masked.
#define SPI_SSPIMSC_RTIM_RESET _u(0x0)
#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002)
#define SPI_SSPIMSC_RTIM_MSB _u(1)
#define SPI_SSPIMSC_RTIM_LSB _u(1)
#define SPI_SSPIMSC_RTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RORIM
// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
// full condition interrupt is masked. 1 Receive FIFO written to
// while full condition interrupt is not masked.
#define SPI_SSPIMSC_RORIM_RESET _u(0x0)
#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001)
#define SPI_SSPIMSC_RORIM_MSB _u(0)
#define SPI_SSPIMSC_RORIM_LSB _u(0)
#define SPI_SSPIMSC_RORIM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPRIS
// Description : Raw interrupt status register, SSPRIS on page 3-10
#define SPI_SSPRIS_OFFSET _u(0x00000018)
#define SPI_SSPRIS_BITS _u(0x0000000f)
#define SPI_SSPRIS_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_TXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPTXINTR interrupt
#define SPI_SSPRIS_TXRIS_RESET _u(0x1)
#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008)
#define SPI_SSPRIS_TXRIS_MSB _u(3)
#define SPI_SSPRIS_TXRIS_LSB _u(3)
#define SPI_SSPRIS_TXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRXINTR interrupt
#define SPI_SSPRIS_RXRIS_RESET _u(0x0)
#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004)
#define SPI_SSPRIS_RXRIS_MSB _u(2)
#define SPI_SSPRIS_RXRIS_LSB _u(2)
#define SPI_SSPRIS_RXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RTRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRTINTR interrupt
#define SPI_SSPRIS_RTRIS_RESET _u(0x0)
#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002)
#define SPI_SSPRIS_RTRIS_MSB _u(1)
#define SPI_SSPRIS_RTRIS_LSB _u(1)
#define SPI_SSPRIS_RTRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RORRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRORINTR interrupt
#define SPI_SSPRIS_RORRIS_RESET _u(0x0)
#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001)
#define SPI_SSPRIS_RORRIS_MSB _u(0)
#define SPI_SSPRIS_RORRIS_LSB _u(0)
#define SPI_SSPRIS_RORRIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPMIS
// Description : Masked interrupt status register, SSPMIS on page 3-11
#define SPI_SSPMIS_OFFSET _u(0x0000001c)
#define SPI_SSPMIS_BITS _u(0x0000000f)
#define SPI_SSPMIS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_TXMIS
// Description : Gives the transmit FIFO masked interrupt state, after masking,
// of the SSPTXINTR interrupt
#define SPI_SSPMIS_TXMIS_RESET _u(0x0)
#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008)
#define SPI_SSPMIS_TXMIS_MSB _u(3)
#define SPI_SSPMIS_TXMIS_LSB _u(3)
#define SPI_SSPMIS_TXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RXMIS
// Description : Gives the receive FIFO masked interrupt state, after masking,
// of the SSPRXINTR interrupt
#define SPI_SSPMIS_RXMIS_RESET _u(0x0)
#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004)
#define SPI_SSPMIS_RXMIS_MSB _u(2)
#define SPI_SSPMIS_RXMIS_LSB _u(2)
#define SPI_SSPMIS_RXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RTMIS
// Description : Gives the receive timeout masked interrupt state, after
// masking, of the SSPRTINTR interrupt
#define SPI_SSPMIS_RTMIS_RESET _u(0x0)
#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002)
#define SPI_SSPMIS_RTMIS_MSB _u(1)
#define SPI_SSPMIS_RTMIS_LSB _u(1)
#define SPI_SSPMIS_RTMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RORMIS
// Description : Gives the receive over run masked interrupt status, after
// masking, of the SSPRORINTR interrupt
#define SPI_SSPMIS_RORMIS_RESET _u(0x0)
#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001)
#define SPI_SSPMIS_RORMIS_MSB _u(0)
#define SPI_SSPMIS_RORMIS_LSB _u(0)
#define SPI_SSPMIS_RORMIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPICR
// Description : Interrupt clear register, SSPICR on page 3-11
#define SPI_SSPICR_OFFSET _u(0x00000020)
#define SPI_SSPICR_BITS _u(0x00000003)
#define SPI_SSPICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RTIC
// Description : Clears the SSPRTINTR interrupt
#define SPI_SSPICR_RTIC_RESET _u(0x0)
#define SPI_SSPICR_RTIC_BITS _u(0x00000002)
#define SPI_SSPICR_RTIC_MSB _u(1)
#define SPI_SSPICR_RTIC_LSB _u(1)
#define SPI_SSPICR_RTIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RORIC
// Description : Clears the SSPRORINTR interrupt
#define SPI_SSPICR_RORIC_RESET _u(0x0)
#define SPI_SSPICR_RORIC_BITS _u(0x00000001)
#define SPI_SSPICR_RORIC_MSB _u(0)
#define SPI_SSPICR_RORIC_LSB _u(0)
#define SPI_SSPICR_RORIC_ACCESS "WC"
// =============================================================================
// Register : SPI_SSPDMACR
// Description : DMA control register, SSPDMACR on page 3-12
#define SPI_SSPDMACR_OFFSET _u(0x00000024)
#define SPI_SSPDMACR_BITS _u(0x00000003)
#define SPI_SSPDMACR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_TXDMAE
// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
// transmit FIFO is enabled.
#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0)
#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002)
#define SPI_SSPDMACR_TXDMAE_MSB _u(1)
#define SPI_SSPDMACR_TXDMAE_LSB _u(1)
#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_RXDMAE
// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
// receive FIFO is enabled.
#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0)
#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001)
#define SPI_SSPDMACR_RXDMAE_MSB _u(0)
#define SPI_SSPDMACR_RXDMAE_LSB _u(0)
#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPPERIPHID0
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
#define SPI_SSPPERIPHID0_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID0_RESET _u(0x00000022)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID0_PARTNUMBER0
// Description : These bits read back as 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22)
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7)
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0)
#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID1
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
#define SPI_SSPPERIPHID1_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID1_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_DESIGNER0
// Description : These bits read back as 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1)
#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7)
#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4)
#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_PARTNUMBER1
// Description : These bits read back as 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3)
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID2
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
#define SPI_SSPPERIPHID2_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID2_RESET _u(0x00000034)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_REVISION
// Description : These bits return the peripheral revision
#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3)
#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0)
#define SPI_SSPPERIPHID2_REVISION_MSB _u(7)
#define SPI_SSPPERIPHID2_REVISION_LSB _u(4)
#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_DESIGNER1
// Description : These bits read back as 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4)
#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3)
#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0)
#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID3
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
#define SPI_SSPPERIPHID3_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID3_CONFIGURATION
// Description : These bits read back as 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00)
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7)
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0)
#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID0
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
#define SPI_SSPPCELLID0_BITS _u(0x000000ff)
#define SPI_SSPPCELLID0_RESET _u(0x0000000d)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID0_SSPPCELLID0
// Description : These bits read back as 0x0D
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d)
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff)
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7)
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0)
#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID1
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
#define SPI_SSPPCELLID1_BITS _u(0x000000ff)
#define SPI_SSPPCELLID1_RESET _u(0x000000f0)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID1_SSPPCELLID1
// Description : These bits read back as 0xF0
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0)
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff)
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7)
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0)
#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID2
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
#define SPI_SSPPCELLID2_BITS _u(0x000000ff)
#define SPI_SSPPCELLID2_RESET _u(0x00000005)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID2_SSPPCELLID2
// Description : These bits read back as 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05)
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff)
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7)
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0)
#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID3
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
#define SPI_SSPPCELLID3_BITS _u(0x000000ff)
#define SPI_SSPPCELLID3_RESET _u(0x000000b1)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID3_SSPPCELLID3
// Description : These bits read back as 0xB1
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1)
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff)
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7)
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SPI_H

279
lib/pico-sdk/rp2350/hardware/regs/syscfg.h Normal file
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@@ -0,0 +1,279 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SYSCFG
// Version : 1
// Bus type : apb
// Description : Register block for various chip control signals
// =============================================================================
#ifndef _HARDWARE_REGS_SYSCFG_H
#define _HARDWARE_REGS_SYSCFG_H
// =============================================================================
// Register : SYSCFG_PROC_CONFIG
// Description : Configuration for processors
#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000000)
#define SYSCFG_PROC_CONFIG_BITS _u(0x00000003)
#define SYSCFG_PROC_CONFIG_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
// Description : Indication that proc1 has halted
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
// Description : Indication that proc0 has halted
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS
// Description : For each bit, if 1, bypass the input synchronizer between that
// GPIO
// and the GPIO input register in the SIO. The input synchronizers
// should
// generally be unbypassed, to avoid injecting metastabilities
// into processors.
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 0...31.
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x00000004)
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0xffffffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_GPIO
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_RESET _u(0x00000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_BITS _u(0xffffffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_MSB _u(31)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
// Description : For each bit, if 1, bypass the input synchronizer between that
// GPIO
// and the GPIO input register in the SIO. The input synchronizers
// should
// generally be unbypassed, to avoid injecting metastabilities
// into processors.
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 32...47. USB GPIO 56..57
// QSPI GPIO 58..63
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000008)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0xff00ffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_BITS _u(0xf0000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_MSB _u(31)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_LSB _u(28)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_BITS _u(0x08000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_MSB _u(27)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_LSB _u(27)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_BITS _u(0x04000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_MSB _u(26)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_LSB _u(26)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_BITS _u(0x02000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_MSB _u(25)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_LSB _u(25)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_BITS _u(0x01000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_MSB _u(24)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_LSB _u(24)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_RESET _u(0x0000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_BITS _u(0x0000ffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_MSB _u(15)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_DBGFORCE
// Description : Directly control the chip SWD debug port
#define SYSCFG_DBGFORCE_OFFSET _u(0x0000000c)
#define SYSCFG_DBGFORCE_BITS _u(0x0000000f)
#define SYSCFG_DBGFORCE_RESET _u(0x00000006)
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_ATTACH
// Description : Attach chip debug port to syscfg controls, and disconnect it
// from external SWD pads.
#define SYSCFG_DBGFORCE_ATTACH_RESET _u(0x0)
#define SYSCFG_DBGFORCE_ATTACH_BITS _u(0x00000008)
#define SYSCFG_DBGFORCE_ATTACH_MSB _u(3)
#define SYSCFG_DBGFORCE_ATTACH_LSB _u(3)
#define SYSCFG_DBGFORCE_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWCLK
// Description : Directly drive SWCLK, if ATTACH is set
#define SYSCFG_DBGFORCE_SWCLK_RESET _u(0x1)
#define SYSCFG_DBGFORCE_SWCLK_BITS _u(0x00000004)
#define SYSCFG_DBGFORCE_SWCLK_MSB _u(2)
#define SYSCFG_DBGFORCE_SWCLK_LSB _u(2)
#define SYSCFG_DBGFORCE_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWDI
// Description : Directly drive SWDIO input, if ATTACH is set
#define SYSCFG_DBGFORCE_SWDI_RESET _u(0x1)
#define SYSCFG_DBGFORCE_SWDI_BITS _u(0x00000002)
#define SYSCFG_DBGFORCE_SWDI_MSB _u(1)
#define SYSCFG_DBGFORCE_SWDI_LSB _u(1)
#define SYSCFG_DBGFORCE_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWDO
// Description : Observe the value of SWDIO output.
#define SYSCFG_DBGFORCE_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_SWDO_BITS _u(0x00000001)
#define SYSCFG_DBGFORCE_SWDO_MSB _u(0)
#define SYSCFG_DBGFORCE_SWDO_LSB _u(0)
#define SYSCFG_DBGFORCE_SWDO_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_MEMPOWERDOWN
// Description : Control PD pins to memories.
// Set high to put memories to a low power state. In this state
// the memories will retain contents but not be accessible
// Use with caution
#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000010)
#define SYSCFG_MEMPOWERDOWN_BITS _u(0x00001fff)
#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_BOOTRAM
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_BITS _u(0x00001000)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_MSB _u(12)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_LSB _u(12)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_ROM
#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000800)
#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(11)
#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(11)
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_USB
#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000400)
#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(10)
#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(10)
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM9
#define SYSCFG_MEMPOWERDOWN_SRAM9_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM9_BITS _u(0x00000200)
#define SYSCFG_MEMPOWERDOWN_SRAM9_MSB _u(9)
#define SYSCFG_MEMPOWERDOWN_SRAM9_LSB _u(9)
#define SYSCFG_MEMPOWERDOWN_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM8
#define SYSCFG_MEMPOWERDOWN_SRAM8_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM8_BITS _u(0x00000100)
#define SYSCFG_MEMPOWERDOWN_SRAM8_MSB _u(8)
#define SYSCFG_MEMPOWERDOWN_SRAM8_LSB _u(8)
#define SYSCFG_MEMPOWERDOWN_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM7
#define SYSCFG_MEMPOWERDOWN_SRAM7_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM7_BITS _u(0x00000080)
#define SYSCFG_MEMPOWERDOWN_SRAM7_MSB _u(7)
#define SYSCFG_MEMPOWERDOWN_SRAM7_LSB _u(7)
#define SYSCFG_MEMPOWERDOWN_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM6
#define SYSCFG_MEMPOWERDOWN_SRAM6_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM6_BITS _u(0x00000040)
#define SYSCFG_MEMPOWERDOWN_SRAM6_MSB _u(6)
#define SYSCFG_MEMPOWERDOWN_SRAM6_LSB _u(6)
#define SYSCFG_MEMPOWERDOWN_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_AUXCTRL
// Description : Auxiliary system control register
// * Bits 7:2: Reserved
//
// * Bit 1: When clear, the LPOSC output is XORed into the TRNG
// ROSC output as an additional, uncorrelated entropy source. When
// set, this behaviour is disabled.
//
// * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting
// its WDRESET input. This must be set before initiating a
// watchdog reset of the RSM from a stage that includes CLOCKS, if
// POWMAN is running from clk_ref at the point that the watchdog
// reset takes place. Otherwise, the short pulse generated on
// clk_ref by the reset of the CLOCKS block may affect POWMAN
// register state.
#define SYSCFG_AUXCTRL_OFFSET _u(0x00000014)
#define SYSCFG_AUXCTRL_BITS _u(0x000000ff)
#define SYSCFG_AUXCTRL_RESET _u(0x00000000)
#define SYSCFG_AUXCTRL_MSB _u(7)
#define SYSCFG_AUXCTRL_LSB _u(0)
#define SYSCFG_AUXCTRL_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_SYSCFG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SYSINFO
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_SYSINFO_H
#define _HARDWARE_REGS_SYSINFO_H
// =============================================================================
// Register : SYSINFO_CHIP_ID
// Description : JEDEC JEP-106 compliant chip identifier.
#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
#define SYSINFO_CHIP_ID_BITS _u(0xffffffff)
#define SYSINFO_CHIP_ID_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_REVISION
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000)
#define SYSINFO_CHIP_ID_REVISION_MSB _u(31)
#define SYSINFO_CHIP_ID_REVISION_LSB _u(28)
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_PART
#define SYSINFO_CHIP_ID_PART_RESET "-"
#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000)
#define SYSINFO_CHIP_ID_PART_MSB _u(27)
#define SYSINFO_CHIP_ID_PART_LSB _u(12)
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_MANUFACTURER
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000ffe)
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11)
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(1)
#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_STOP_BIT
#define SYSINFO_CHIP_ID_STOP_BIT_RESET _u(0x1)
#define SYSINFO_CHIP_ID_STOP_BIT_BITS _u(0x00000001)
#define SYSINFO_CHIP_ID_STOP_BIT_MSB _u(0)
#define SYSINFO_CHIP_ID_STOP_BIT_LSB _u(0)
#define SYSINFO_CHIP_ID_STOP_BIT_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PACKAGE_SEL
#define SYSINFO_PACKAGE_SEL_OFFSET _u(0x00000004)
#define SYSINFO_PACKAGE_SEL_BITS _u(0x00000001)
#define SYSINFO_PACKAGE_SEL_RESET _u(0x00000000)
#define SYSINFO_PACKAGE_SEL_MSB _u(0)
#define SYSINFO_PACKAGE_SEL_LSB _u(0)
#define SYSINFO_PACKAGE_SEL_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PLATFORM
// Description : Platform register. Allows software to know what environment it
// is running in during pre-production development. Post-
// production, the PLATFORM is always ASIC, non-SIM.
#define SYSINFO_PLATFORM_OFFSET _u(0x00000008)
#define SYSINFO_PLATFORM_BITS _u(0x0000001f)
#define SYSINFO_PLATFORM_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_GATESIM
#define SYSINFO_PLATFORM_GATESIM_RESET "-"
#define SYSINFO_PLATFORM_GATESIM_BITS _u(0x00000010)
#define SYSINFO_PLATFORM_GATESIM_MSB _u(4)
#define SYSINFO_PLATFORM_GATESIM_LSB _u(4)
#define SYSINFO_PLATFORM_GATESIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_BATCHSIM
#define SYSINFO_PLATFORM_BATCHSIM_RESET "-"
#define SYSINFO_PLATFORM_BATCHSIM_BITS _u(0x00000008)
#define SYSINFO_PLATFORM_BATCHSIM_MSB _u(3)
#define SYSINFO_PLATFORM_BATCHSIM_LSB _u(3)
#define SYSINFO_PLATFORM_BATCHSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_HDLSIM
#define SYSINFO_PLATFORM_HDLSIM_RESET "-"
#define SYSINFO_PLATFORM_HDLSIM_BITS _u(0x00000004)
#define SYSINFO_PLATFORM_HDLSIM_MSB _u(2)
#define SYSINFO_PLATFORM_HDLSIM_LSB _u(2)
#define SYSINFO_PLATFORM_HDLSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_ASIC
#define SYSINFO_PLATFORM_ASIC_RESET "-"
#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002)
#define SYSINFO_PLATFORM_ASIC_MSB _u(1)
#define SYSINFO_PLATFORM_ASIC_LSB _u(1)
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_FPGA
#define SYSINFO_PLATFORM_FPGA_RESET "-"
#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001)
#define SYSINFO_PLATFORM_FPGA_MSB _u(0)
#define SYSINFO_PLATFORM_FPGA_LSB _u(0)
#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_GITREF_RP2350
// Description : Git hash of the chip source. Used to identify chip version.
#define SYSINFO_GITREF_RP2350_OFFSET _u(0x00000014)
#define SYSINFO_GITREF_RP2350_BITS _u(0xffffffff)
#define SYSINFO_GITREF_RP2350_RESET "-"
#define SYSINFO_GITREF_RP2350_MSB _u(31)
#define SYSINFO_GITREF_RP2350_LSB _u(0)
#define SYSINFO_GITREF_RP2350_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SYSINFO_H

48
lib/pico-sdk/rp2350/hardware/regs/tbman.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TBMAN
// Version : 1
// Bus type : apb
// Description : For managing simulation testbenches
// =============================================================================
#ifndef _HARDWARE_REGS_TBMAN_H
#define _HARDWARE_REGS_TBMAN_H
// =============================================================================
// Register : TBMAN_PLATFORM
// Description : Indicates the type of platform in use
#define TBMAN_PLATFORM_OFFSET _u(0x00000000)
#define TBMAN_PLATFORM_BITS _u(0x00000007)
#define TBMAN_PLATFORM_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_HDLSIM
// Description : Indicates the platform is a simulation
#define TBMAN_PLATFORM_HDLSIM_RESET _u(0x0)
#define TBMAN_PLATFORM_HDLSIM_BITS _u(0x00000004)
#define TBMAN_PLATFORM_HDLSIM_MSB _u(2)
#define TBMAN_PLATFORM_HDLSIM_LSB _u(2)
#define TBMAN_PLATFORM_HDLSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_FPGA
// Description : Indicates the platform is an FPGA
#define TBMAN_PLATFORM_FPGA_RESET _u(0x0)
#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002)
#define TBMAN_PLATFORM_FPGA_MSB _u(1)
#define TBMAN_PLATFORM_FPGA_LSB _u(1)
#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_ASIC
// Description : Indicates the platform is an ASIC
#define TBMAN_PLATFORM_ASIC_RESET _u(0x1)
#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001)
#define TBMAN_PLATFORM_ASIC_MSB _u(0)
#define TBMAN_PLATFORM_ASIC_LSB _u(0)
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TBMAN_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TICKS
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_TICKS_H
#define _HARDWARE_REGS_TICKS_H
// =============================================================================
// Register : TICKS_PROC0_CTRL
// Description : Controls the tick generator
#define TICKS_PROC0_CTRL_OFFSET _u(0x00000000)
#define TICKS_PROC0_CTRL_BITS _u(0x00000003)
#define TICKS_PROC0_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_PROC0_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_PROC0_CTRL_RUNNING_RESET "-"
#define TICKS_PROC0_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_PROC0_CTRL_RUNNING_MSB _u(1)
#define TICKS_PROC0_CTRL_RUNNING_LSB _u(1)
#define TICKS_PROC0_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_PROC0_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_PROC0_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_PROC0_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_PROC0_CTRL_ENABLE_MSB _u(0)
#define TICKS_PROC0_CTRL_ENABLE_LSB _u(0)
#define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC0_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004)
#define TICKS_PROC0_CYCLES_BITS _u(0x000001ff)
#define TICKS_PROC0_CYCLES_RESET _u(0x00000000)
#define TICKS_PROC0_CYCLES_MSB _u(8)
#define TICKS_PROC0_CYCLES_LSB _u(0)
#define TICKS_PROC0_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC0_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_PROC0_COUNT_OFFSET _u(0x00000008)
#define TICKS_PROC0_COUNT_BITS _u(0x000001ff)
#define TICKS_PROC0_COUNT_RESET "-"
#define TICKS_PROC0_COUNT_MSB _u(8)
#define TICKS_PROC0_COUNT_LSB _u(0)
#define TICKS_PROC0_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_PROC1_CTRL
// Description : Controls the tick generator
#define TICKS_PROC1_CTRL_OFFSET _u(0x0000000c)
#define TICKS_PROC1_CTRL_BITS _u(0x00000003)
#define TICKS_PROC1_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_PROC1_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_PROC1_CTRL_RUNNING_RESET "-"
#define TICKS_PROC1_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_PROC1_CTRL_RUNNING_MSB _u(1)
#define TICKS_PROC1_CTRL_RUNNING_LSB _u(1)
#define TICKS_PROC1_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_PROC1_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_PROC1_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_PROC1_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_PROC1_CTRL_ENABLE_MSB _u(0)
#define TICKS_PROC1_CTRL_ENABLE_LSB _u(0)
#define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC1_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010)
#define TICKS_PROC1_CYCLES_BITS _u(0x000001ff)
#define TICKS_PROC1_CYCLES_RESET _u(0x00000000)
#define TICKS_PROC1_CYCLES_MSB _u(8)
#define TICKS_PROC1_CYCLES_LSB _u(0)
#define TICKS_PROC1_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC1_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_PROC1_COUNT_OFFSET _u(0x00000014)
#define TICKS_PROC1_COUNT_BITS _u(0x000001ff)
#define TICKS_PROC1_COUNT_RESET "-"
#define TICKS_PROC1_COUNT_MSB _u(8)
#define TICKS_PROC1_COUNT_LSB _u(0)
#define TICKS_PROC1_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_TIMER0_CTRL
// Description : Controls the tick generator
#define TICKS_TIMER0_CTRL_OFFSET _u(0x00000018)
#define TICKS_TIMER0_CTRL_BITS _u(0x00000003)
#define TICKS_TIMER0_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER0_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_TIMER0_CTRL_RUNNING_RESET "-"
#define TICKS_TIMER0_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_TIMER0_CTRL_RUNNING_MSB _u(1)
#define TICKS_TIMER0_CTRL_RUNNING_LSB _u(1)
#define TICKS_TIMER0_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER0_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_TIMER0_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_TIMER0_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_TIMER0_CTRL_ENABLE_MSB _u(0)
#define TICKS_TIMER0_CTRL_ENABLE_LSB _u(0)
#define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER0_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c)
#define TICKS_TIMER0_CYCLES_BITS _u(0x000001ff)
#define TICKS_TIMER0_CYCLES_RESET _u(0x00000000)
#define TICKS_TIMER0_CYCLES_MSB _u(8)
#define TICKS_TIMER0_CYCLES_LSB _u(0)
#define TICKS_TIMER0_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER0_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020)
#define TICKS_TIMER0_COUNT_BITS _u(0x000001ff)
#define TICKS_TIMER0_COUNT_RESET "-"
#define TICKS_TIMER0_COUNT_MSB _u(8)
#define TICKS_TIMER0_COUNT_LSB _u(0)
#define TICKS_TIMER0_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_TIMER1_CTRL
// Description : Controls the tick generator
#define TICKS_TIMER1_CTRL_OFFSET _u(0x00000024)
#define TICKS_TIMER1_CTRL_BITS _u(0x00000003)
#define TICKS_TIMER1_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER1_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_TIMER1_CTRL_RUNNING_RESET "-"
#define TICKS_TIMER1_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_TIMER1_CTRL_RUNNING_MSB _u(1)
#define TICKS_TIMER1_CTRL_RUNNING_LSB _u(1)
#define TICKS_TIMER1_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER1_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_TIMER1_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_TIMER1_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_TIMER1_CTRL_ENABLE_MSB _u(0)
#define TICKS_TIMER1_CTRL_ENABLE_LSB _u(0)
#define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER1_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028)
#define TICKS_TIMER1_CYCLES_BITS _u(0x000001ff)
#define TICKS_TIMER1_CYCLES_RESET _u(0x00000000)
#define TICKS_TIMER1_CYCLES_MSB _u(8)
#define TICKS_TIMER1_CYCLES_LSB _u(0)
#define TICKS_TIMER1_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER1_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c)
#define TICKS_TIMER1_COUNT_BITS _u(0x000001ff)
#define TICKS_TIMER1_COUNT_RESET "-"
#define TICKS_TIMER1_COUNT_MSB _u(8)
#define TICKS_TIMER1_COUNT_LSB _u(0)
#define TICKS_TIMER1_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_WATCHDOG_CTRL
// Description : Controls the tick generator
#define TICKS_WATCHDOG_CTRL_OFFSET _u(0x00000030)
#define TICKS_WATCHDOG_CTRL_BITS _u(0x00000003)
#define TICKS_WATCHDOG_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_WATCHDOG_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_WATCHDOG_CTRL_RUNNING_RESET "-"
#define TICKS_WATCHDOG_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_WATCHDOG_CTRL_RUNNING_MSB _u(1)
#define TICKS_WATCHDOG_CTRL_RUNNING_LSB _u(1)
#define TICKS_WATCHDOG_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_WATCHDOG_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_WATCHDOG_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_WATCHDOG_CTRL_ENABLE_MSB _u(0)
#define TICKS_WATCHDOG_CTRL_ENABLE_LSB _u(0)
#define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_WATCHDOG_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034)
#define TICKS_WATCHDOG_CYCLES_BITS _u(0x000001ff)
#define TICKS_WATCHDOG_CYCLES_RESET _u(0x00000000)
#define TICKS_WATCHDOG_CYCLES_MSB _u(8)
#define TICKS_WATCHDOG_CYCLES_LSB _u(0)
#define TICKS_WATCHDOG_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_WATCHDOG_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038)
#define TICKS_WATCHDOG_COUNT_BITS _u(0x000001ff)
#define TICKS_WATCHDOG_COUNT_RESET "-"
#define TICKS_WATCHDOG_COUNT_MSB _u(8)
#define TICKS_WATCHDOG_COUNT_LSB _u(0)
#define TICKS_WATCHDOG_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_RISCV_CTRL
// Description : Controls the tick generator
#define TICKS_RISCV_CTRL_OFFSET _u(0x0000003c)
#define TICKS_RISCV_CTRL_BITS _u(0x00000003)
#define TICKS_RISCV_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_RISCV_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_RISCV_CTRL_RUNNING_RESET "-"
#define TICKS_RISCV_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_RISCV_CTRL_RUNNING_MSB _u(1)
#define TICKS_RISCV_CTRL_RUNNING_LSB _u(1)
#define TICKS_RISCV_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_RISCV_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_RISCV_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_RISCV_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_RISCV_CTRL_ENABLE_MSB _u(0)
#define TICKS_RISCV_CTRL_ENABLE_LSB _u(0)
#define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_RISCV_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040)
#define TICKS_RISCV_CYCLES_BITS _u(0x000001ff)
#define TICKS_RISCV_CYCLES_RESET _u(0x00000000)
#define TICKS_RISCV_CYCLES_MSB _u(8)
#define TICKS_RISCV_CYCLES_LSB _u(0)
#define TICKS_RISCV_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_RISCV_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_RISCV_COUNT_OFFSET _u(0x00000044)
#define TICKS_RISCV_COUNT_BITS _u(0x000001ff)
#define TICKS_RISCV_COUNT_RESET "-"
#define TICKS_RISCV_COUNT_MSB _u(8)
#define TICKS_RISCV_COUNT_LSB _u(0)
#define TICKS_RISCV_COUNT_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TICKS_H

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lib/pico-sdk/rp2350/hardware/regs/timer.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TIMER
// Version : 1
// Bus type : apb
// Description : Controls time and alarms
//
// time is a 64 bit value indicating the time since power-on
//
// timeh is the top 32 bits of time & timel is the bottom 32
// bits to change time write to timelw before timehw to read
// time read from timelr before timehr
//
// An alarm is set by setting alarm_enable and writing to the
// corresponding alarm register When an alarm is pending, the
// corresponding alarm_running signal will be high An alarm can
// be cancelled before it has finished by clearing the
// alarm_enable When an alarm fires, the corresponding
// alarm_irq is set and alarm_running is cleared To clear the
// interrupt write a 1 to the corresponding alarm_irq The timer
// can be locked to prevent writing
// =============================================================================
#ifndef _HARDWARE_REGS_TIMER_H
#define _HARDWARE_REGS_TIMER_H
// =============================================================================
// Register : TIMER_TIMEHW
// Description : Write to bits 63:32 of time always write timelw before timehw
#define TIMER_TIMEHW_OFFSET _u(0x00000000)
#define TIMER_TIMEHW_BITS _u(0xffffffff)
#define TIMER_TIMEHW_RESET _u(0x00000000)
#define TIMER_TIMEHW_MSB _u(31)
#define TIMER_TIMEHW_LSB _u(0)
#define TIMER_TIMEHW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMELW
// Description : Write to bits 31:0 of time writes do not get copied to time
// until timehw is written
#define TIMER_TIMELW_OFFSET _u(0x00000004)
#define TIMER_TIMELW_BITS _u(0xffffffff)
#define TIMER_TIMELW_RESET _u(0x00000000)
#define TIMER_TIMELW_MSB _u(31)
#define TIMER_TIMELW_LSB _u(0)
#define TIMER_TIMELW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMEHR
// Description : Read from bits 63:32 of time always read timelr before timehr
#define TIMER_TIMEHR_OFFSET _u(0x00000008)
#define TIMER_TIMEHR_BITS _u(0xffffffff)
#define TIMER_TIMEHR_RESET _u(0x00000000)
#define TIMER_TIMEHR_MSB _u(31)
#define TIMER_TIMEHR_LSB _u(0)
#define TIMER_TIMEHR_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMELR
// Description : Read from bits 31:0 of time
#define TIMER_TIMELR_OFFSET _u(0x0000000c)
#define TIMER_TIMELR_BITS _u(0xffffffff)
#define TIMER_TIMELR_RESET _u(0x00000000)
#define TIMER_TIMELR_MSB _u(31)
#define TIMER_TIMELR_LSB _u(0)
#define TIMER_TIMELR_ACCESS "RO"
// =============================================================================
// Register : TIMER_ALARM0
// Description : Arm alarm 0, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM0_OFFSET _u(0x00000010)
#define TIMER_ALARM0_BITS _u(0xffffffff)
#define TIMER_ALARM0_RESET _u(0x00000000)
#define TIMER_ALARM0_MSB _u(31)
#define TIMER_ALARM0_LSB _u(0)
#define TIMER_ALARM0_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM1
// Description : Arm alarm 1, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM1_OFFSET _u(0x00000014)
#define TIMER_ALARM1_BITS _u(0xffffffff)
#define TIMER_ALARM1_RESET _u(0x00000000)
#define TIMER_ALARM1_MSB _u(31)
#define TIMER_ALARM1_LSB _u(0)
#define TIMER_ALARM1_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM2
// Description : Arm alarm 2, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM2_OFFSET _u(0x00000018)
#define TIMER_ALARM2_BITS _u(0xffffffff)
#define TIMER_ALARM2_RESET _u(0x00000000)
#define TIMER_ALARM2_MSB _u(31)
#define TIMER_ALARM2_LSB _u(0)
#define TIMER_ALARM2_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM3
// Description : Arm alarm 3, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM3_OFFSET _u(0x0000001c)
#define TIMER_ALARM3_BITS _u(0xffffffff)
#define TIMER_ALARM3_RESET _u(0x00000000)
#define TIMER_ALARM3_MSB _u(31)
#define TIMER_ALARM3_LSB _u(0)
#define TIMER_ALARM3_ACCESS "RW"
// =============================================================================
// Register : TIMER_ARMED
// Description : Indicates the armed/disarmed status of each alarm. A write to
// the corresponding ALARMx register arms the alarm. Alarms
// automatically disarm upon firing, but writing ones here will
// disarm immediately without waiting to fire.
#define TIMER_ARMED_OFFSET _u(0x00000020)
#define TIMER_ARMED_BITS _u(0x0000000f)
#define TIMER_ARMED_RESET _u(0x00000000)
#define TIMER_ARMED_MSB _u(3)
#define TIMER_ARMED_LSB _u(0)
#define TIMER_ARMED_ACCESS "WC"
// =============================================================================
// Register : TIMER_TIMERAWH
// Description : Raw read from bits 63:32 of time (no side effects)
#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
#define TIMER_TIMERAWH_BITS _u(0xffffffff)
#define TIMER_TIMERAWH_RESET _u(0x00000000)
#define TIMER_TIMERAWH_MSB _u(31)
#define TIMER_TIMERAWH_LSB _u(0)
#define TIMER_TIMERAWH_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMERAWL
// Description : Raw read from bits 31:0 of time (no side effects)
#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
#define TIMER_TIMERAWL_BITS _u(0xffffffff)
#define TIMER_TIMERAWL_RESET _u(0x00000000)
#define TIMER_TIMERAWL_MSB _u(31)
#define TIMER_TIMERAWL_LSB _u(0)
#define TIMER_TIMERAWL_ACCESS "RO"
// =============================================================================
// Register : TIMER_DBGPAUSE
// Description : Set bits high to enable pause when the corresponding debug
// ports are active
#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
#define TIMER_DBGPAUSE_BITS _u(0x00000006)
#define TIMER_DBGPAUSE_RESET _u(0x00000007)
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG1
// Description : Pause when processor 1 is in debug mode
#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1)
#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004)
#define TIMER_DBGPAUSE_DBG1_MSB _u(2)
#define TIMER_DBGPAUSE_DBG1_LSB _u(2)
#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG0
// Description : Pause when processor 0 is in debug mode
#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1)
#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002)
#define TIMER_DBGPAUSE_DBG0_MSB _u(1)
#define TIMER_DBGPAUSE_DBG0_LSB _u(1)
#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
// =============================================================================
// Register : TIMER_PAUSE
// Description : Set high to pause the timer
#define TIMER_PAUSE_OFFSET _u(0x00000030)
#define TIMER_PAUSE_BITS _u(0x00000001)
#define TIMER_PAUSE_RESET _u(0x00000000)
#define TIMER_PAUSE_MSB _u(0)
#define TIMER_PAUSE_LSB _u(0)
#define TIMER_PAUSE_ACCESS "RW"
// =============================================================================
// Register : TIMER_LOCKED
// Description : Set locked bit to disable write access to timer Once set,
// cannot be cleared (without a reset)
#define TIMER_LOCKED_OFFSET _u(0x00000034)
#define TIMER_LOCKED_BITS _u(0x00000001)
#define TIMER_LOCKED_RESET _u(0x00000000)
#define TIMER_LOCKED_MSB _u(0)
#define TIMER_LOCKED_LSB _u(0)
#define TIMER_LOCKED_ACCESS "RW"
// =============================================================================
// Register : TIMER_SOURCE
// Description : Selects the source for the timer. Defaults to the normal tick
// configured in the ticks block (typically configured to 1
// microsecond). Writing to 1 will ignore the tick and count
// clk_sys cycles instead.
#define TIMER_SOURCE_OFFSET _u(0x00000038)
#define TIMER_SOURCE_BITS _u(0x00000001)
#define TIMER_SOURCE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_SOURCE_CLK_SYS
// 0x0 -> TICK
// 0x1 -> CLK_SYS
#define TIMER_SOURCE_CLK_SYS_RESET _u(0x0)
#define TIMER_SOURCE_CLK_SYS_BITS _u(0x00000001)
#define TIMER_SOURCE_CLK_SYS_MSB _u(0)
#define TIMER_SOURCE_CLK_SYS_LSB _u(0)
#define TIMER_SOURCE_CLK_SYS_ACCESS "RW"
#define TIMER_SOURCE_CLK_SYS_VALUE_TICK _u(0x0)
#define TIMER_SOURCE_CLK_SYS_VALUE_CLK_SYS _u(0x1)
// =============================================================================
// Register : TIMER_INTR
// Description : Raw Interrupts
#define TIMER_INTR_OFFSET _u(0x0000003c)
#define TIMER_INTR_BITS _u(0x0000000f)
#define TIMER_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_3
#define TIMER_INTR_ALARM_3_RESET _u(0x0)
#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTR_ALARM_3_MSB _u(3)
#define TIMER_INTR_ALARM_3_LSB _u(3)
#define TIMER_INTR_ALARM_3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_2
#define TIMER_INTR_ALARM_2_RESET _u(0x0)
#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTR_ALARM_2_MSB _u(2)
#define TIMER_INTR_ALARM_2_LSB _u(2)
#define TIMER_INTR_ALARM_2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_1
#define TIMER_INTR_ALARM_1_RESET _u(0x0)
#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTR_ALARM_1_MSB _u(1)
#define TIMER_INTR_ALARM_1_LSB _u(1)
#define TIMER_INTR_ALARM_1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_0
#define TIMER_INTR_ALARM_0_RESET _u(0x0)
#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTR_ALARM_0_MSB _u(0)
#define TIMER_INTR_ALARM_0_LSB _u(0)
#define TIMER_INTR_ALARM_0_ACCESS "WC"
// =============================================================================
// Register : TIMER_INTE
// Description : Interrupt Enable
#define TIMER_INTE_OFFSET _u(0x00000040)
#define TIMER_INTE_BITS _u(0x0000000f)
#define TIMER_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_3
#define TIMER_INTE_ALARM_3_RESET _u(0x0)
#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTE_ALARM_3_MSB _u(3)
#define TIMER_INTE_ALARM_3_LSB _u(3)
#define TIMER_INTE_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_2
#define TIMER_INTE_ALARM_2_RESET _u(0x0)
#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTE_ALARM_2_MSB _u(2)
#define TIMER_INTE_ALARM_2_LSB _u(2)
#define TIMER_INTE_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_1
#define TIMER_INTE_ALARM_1_RESET _u(0x0)
#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTE_ALARM_1_MSB _u(1)
#define TIMER_INTE_ALARM_1_LSB _u(1)
#define TIMER_INTE_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_0
#define TIMER_INTE_ALARM_0_RESET _u(0x0)
#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTE_ALARM_0_MSB _u(0)
#define TIMER_INTE_ALARM_0_LSB _u(0)
#define TIMER_INTE_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTF
// Description : Interrupt Force
#define TIMER_INTF_OFFSET _u(0x00000044)
#define TIMER_INTF_BITS _u(0x0000000f)
#define TIMER_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_3
#define TIMER_INTF_ALARM_3_RESET _u(0x0)
#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTF_ALARM_3_MSB _u(3)
#define TIMER_INTF_ALARM_3_LSB _u(3)
#define TIMER_INTF_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_2
#define TIMER_INTF_ALARM_2_RESET _u(0x0)
#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTF_ALARM_2_MSB _u(2)
#define TIMER_INTF_ALARM_2_LSB _u(2)
#define TIMER_INTF_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_1
#define TIMER_INTF_ALARM_1_RESET _u(0x0)
#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTF_ALARM_1_MSB _u(1)
#define TIMER_INTF_ALARM_1_LSB _u(1)
#define TIMER_INTF_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_0
#define TIMER_INTF_ALARM_0_RESET _u(0x0)
#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTF_ALARM_0_MSB _u(0)
#define TIMER_INTF_ALARM_0_LSB _u(0)
#define TIMER_INTF_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTS
// Description : Interrupt status after masking & forcing
#define TIMER_INTS_OFFSET _u(0x00000048)
#define TIMER_INTS_BITS _u(0x0000000f)
#define TIMER_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_3
#define TIMER_INTS_ALARM_3_RESET _u(0x0)
#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTS_ALARM_3_MSB _u(3)
#define TIMER_INTS_ALARM_3_LSB _u(3)
#define TIMER_INTS_ALARM_3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_2
#define TIMER_INTS_ALARM_2_RESET _u(0x0)
#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTS_ALARM_2_MSB _u(2)
#define TIMER_INTS_ALARM_2_LSB _u(2)
#define TIMER_INTS_ALARM_2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_1
#define TIMER_INTS_ALARM_1_RESET _u(0x0)
#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTS_ALARM_1_MSB _u(1)
#define TIMER_INTS_ALARM_1_LSB _u(1)
#define TIMER_INTS_ALARM_1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_0
#define TIMER_INTS_ALARM_0_RESET _u(0x0)
#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTS_ALARM_0_MSB _u(0)
#define TIMER_INTS_ALARM_0_LSB _u(0)
#define TIMER_INTS_ALARM_0_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TIMER_H

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lib/pico-sdk/rp2350/hardware/regs/trng.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TRNG
// Version : 1
// Bus type : apb
// Description : ARM TrustZone RNG register block
// =============================================================================
#ifndef _HARDWARE_REGS_TRNG_H
#define _HARDWARE_REGS_TRNG_H
// =============================================================================
// Register : TRNG_RNG_IMR
// Description : Interrupt masking.
#define TRNG_RNG_IMR_OFFSET _u(0x00000100)
#define TRNG_RNG_IMR_BITS _u(0xffffffff)
#define TRNG_RNG_IMR_RESET _u(0x0000000f)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_RESERVED
// Description : RESERVED
#define TRNG_RNG_IMR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_IMR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_IMR_RESERVED_MSB _u(31)
#define TRNG_RNG_IMR_RESERVED_LSB _u(4)
#define TRNG_RNG_IMR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_VN_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS _u(0x00000008)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB _u(3)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB _u(3)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_CRNGT_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS _u(0x00000004)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB _u(2)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB _u(2)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS _u(0x00000002)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB _u(1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB _u(1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_EHR_VALID_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS _u(0x00000001)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB _u(0)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB _u(0)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_ISR
// Description : RNG status register. If corresponding RNG_IMR bit is unmasked,
// an interrupt will be generated.
#define TRNG_RNG_ISR_OFFSET _u(0x00000104)
#define TRNG_RNG_ISR_BITS _u(0xffffffff)
#define TRNG_RNG_ISR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_RESERVED
// Description : RESERVED
#define TRNG_RNG_ISR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_ISR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_ISR_RESERVED_MSB _u(31)
#define TRNG_RNG_ISR_RESERVED_LSB _u(4)
#define TRNG_RNG_ISR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_VN_ERR
// Description : 1'b1 indicates Von Neuman error. Error in von Neuman occurs if
// 32 consecutive collected bits are identical, ZERO or ONE.
#define TRNG_RNG_ISR_VN_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_VN_ERR_BITS _u(0x00000008)
#define TRNG_RNG_ISR_VN_ERR_MSB _u(3)
#define TRNG_RNG_ISR_VN_ERR_LSB _u(3)
#define TRNG_RNG_ISR_VN_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_CRNGT_ERR
// Description : 1'b1 indicates CRNGT in the RNG test failed. Failure occurs
// when two consecutive blocks of 16 collected bits are equal.
#define TRNG_RNG_ISR_CRNGT_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_CRNGT_ERR_BITS _u(0x00000004)
#define TRNG_RNG_ISR_CRNGT_ERR_MSB _u(2)
#define TRNG_RNG_ISR_CRNGT_ERR_LSB _u(2)
#define TRNG_RNG_ISR_CRNGT_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_AUTOCORR_ERR
// Description : 1'b1 indicates Autocorrelation test failed four times in a row.
// When set, RNG cease from functioning until next reset.
#define TRNG_RNG_ISR_AUTOCORR_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_AUTOCORR_ERR_BITS _u(0x00000002)
#define TRNG_RNG_ISR_AUTOCORR_ERR_MSB _u(1)
#define TRNG_RNG_ISR_AUTOCORR_ERR_LSB _u(1)
#define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_EHR_VALID
// Description : 1'b1 indicates that 192 bits have been collected in the RNG,
// and are ready to be read.
#define TRNG_RNG_ISR_EHR_VALID_RESET _u(0x0)
#define TRNG_RNG_ISR_EHR_VALID_BITS _u(0x00000001)
#define TRNG_RNG_ISR_EHR_VALID_MSB _u(0)
#define TRNG_RNG_ISR_EHR_VALID_LSB _u(0)
#define TRNG_RNG_ISR_EHR_VALID_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_ICR
// Description : Interrupt/status bit clear Register.
#define TRNG_RNG_ICR_OFFSET _u(0x00000108)
#define TRNG_RNG_ICR_BITS _u(0xffffffff)
#define TRNG_RNG_ICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_RESERVED
// Description : RESERVED
#define TRNG_RNG_ICR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_ICR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_ICR_RESERVED_MSB _u(31)
#define TRNG_RNG_ICR_RESERVED_LSB _u(4)
#define TRNG_RNG_ICR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_VN_ERR
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_VN_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_VN_ERR_BITS _u(0x00000008)
#define TRNG_RNG_ICR_VN_ERR_MSB _u(3)
#define TRNG_RNG_ICR_VN_ERR_LSB _u(3)
#define TRNG_RNG_ICR_VN_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_CRNGT_ERR
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_CRNGT_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_CRNGT_ERR_BITS _u(0x00000004)
#define TRNG_RNG_ICR_CRNGT_ERR_MSB _u(2)
#define TRNG_RNG_ICR_CRNGT_ERR_LSB _u(2)
#define TRNG_RNG_ICR_CRNGT_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_AUTOCORR_ERR
// Description : Cannot be cleared by SW! Only RNG reset clears this bit.
#define TRNG_RNG_ICR_AUTOCORR_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_AUTOCORR_ERR_BITS _u(0x00000002)
#define TRNG_RNG_ICR_AUTOCORR_ERR_MSB _u(1)
#define TRNG_RNG_ICR_AUTOCORR_ERR_LSB _u(1)
#define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_EHR_VALID
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_EHR_VALID_RESET _u(0x0)
#define TRNG_RNG_ICR_EHR_VALID_BITS _u(0x00000001)
#define TRNG_RNG_ICR_EHR_VALID_MSB _u(0)
#define TRNG_RNG_ICR_EHR_VALID_LSB _u(0)
#define TRNG_RNG_ICR_EHR_VALID_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_CONFIG
// Description : Selecting the inverter-chain length.
#define TRNG_TRNG_CONFIG_OFFSET _u(0x0000010c)
#define TRNG_TRNG_CONFIG_BITS _u(0xffffffff)
#define TRNG_TRNG_CONFIG_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_CONFIG_RESERVED
// Description : RESERVED
#define TRNG_TRNG_CONFIG_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_CONFIG_RESERVED_BITS _u(0xfffffffc)
#define TRNG_TRNG_CONFIG_RESERVED_MSB _u(31)
#define TRNG_TRNG_CONFIG_RESERVED_LSB _u(2)
#define TRNG_TRNG_CONFIG_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_CONFIG_RND_SRC_SEL
// Description : Selects the number of inverters (out of four possible
// selections) in the ring oscillator (the entropy source).
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET _u(0x0)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS _u(0x00000003)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB _u(1)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB _u(0)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_VALID
// Description : 192 bit collection indication.
#define TRNG_TRNG_VALID_OFFSET _u(0x00000110)
#define TRNG_TRNG_VALID_BITS _u(0xffffffff)
#define TRNG_TRNG_VALID_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_VALID_RESERVED
// Description : RESERVED
#define TRNG_TRNG_VALID_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_VALID_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_VALID_RESERVED_MSB _u(31)
#define TRNG_TRNG_VALID_RESERVED_LSB _u(1)
#define TRNG_TRNG_VALID_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_VALID_EHR_VALID
// Description : 1'b1 indicates that collection of bits in the RNG is completed,
// and data can be read from EHR_DATA register.
#define TRNG_TRNG_VALID_EHR_VALID_RESET _u(0x0)
#define TRNG_TRNG_VALID_EHR_VALID_BITS _u(0x00000001)
#define TRNG_TRNG_VALID_EHR_VALID_MSB _u(0)
#define TRNG_TRNG_VALID_EHR_VALID_LSB _u(0)
#define TRNG_TRNG_VALID_EHR_VALID_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA0
// Description : RNG collected bits.
// Bits [31:0] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA0_OFFSET _u(0x00000114)
#define TRNG_EHR_DATA0_BITS _u(0xffffffff)
#define TRNG_EHR_DATA0_RESET _u(0x00000000)
#define TRNG_EHR_DATA0_MSB _u(31)
#define TRNG_EHR_DATA0_LSB _u(0)
#define TRNG_EHR_DATA0_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA1
// Description : RNG collected bits.
// Bits [63:32] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA1_OFFSET _u(0x00000118)
#define TRNG_EHR_DATA1_BITS _u(0xffffffff)
#define TRNG_EHR_DATA1_RESET _u(0x00000000)
#define TRNG_EHR_DATA1_MSB _u(31)
#define TRNG_EHR_DATA1_LSB _u(0)
#define TRNG_EHR_DATA1_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA2
// Description : RNG collected bits.
// Bits [95:64] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA2_OFFSET _u(0x0000011c)
#define TRNG_EHR_DATA2_BITS _u(0xffffffff)
#define TRNG_EHR_DATA2_RESET _u(0x00000000)
#define TRNG_EHR_DATA2_MSB _u(31)
#define TRNG_EHR_DATA2_LSB _u(0)
#define TRNG_EHR_DATA2_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA3
// Description : RNG collected bits.
// Bits [127:96] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA3_OFFSET _u(0x00000120)
#define TRNG_EHR_DATA3_BITS _u(0xffffffff)
#define TRNG_EHR_DATA3_RESET _u(0x00000000)
#define TRNG_EHR_DATA3_MSB _u(31)
#define TRNG_EHR_DATA3_LSB _u(0)
#define TRNG_EHR_DATA3_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA4
// Description : RNG collected bits.
// Bits [159:128] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA4_OFFSET _u(0x00000124)
#define TRNG_EHR_DATA4_BITS _u(0xffffffff)
#define TRNG_EHR_DATA4_RESET _u(0x00000000)
#define TRNG_EHR_DATA4_MSB _u(31)
#define TRNG_EHR_DATA4_LSB _u(0)
#define TRNG_EHR_DATA4_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA5
// Description : RNG collected bits.
// Bits [191:160] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA5_OFFSET _u(0x00000128)
#define TRNG_EHR_DATA5_BITS _u(0xffffffff)
#define TRNG_EHR_DATA5_RESET _u(0x00000000)
#define TRNG_EHR_DATA5_MSB _u(31)
#define TRNG_EHR_DATA5_LSB _u(0)
#define TRNG_EHR_DATA5_ACCESS "RO"
// =============================================================================
// Register : TRNG_RND_SOURCE_ENABLE
// Description : Enable signal for the random source.
#define TRNG_RND_SOURCE_ENABLE_OFFSET _u(0x0000012c)
#define TRNG_RND_SOURCE_ENABLE_BITS _u(0xffffffff)
#define TRNG_RND_SOURCE_ENABLE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RND_SOURCE_ENABLE_RESERVED
// Description : RESERVED
#define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET _u(0x00000000)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB _u(31)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB _u(1)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RND_SOURCE_ENABLE_RND_SRC_EN
// Description : * 1'b1 - entropy source is enabled. *1'b0 - entropy source is
// disabled
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET _u(0x0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS _u(0x00000001)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB _u(0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB _u(0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS "RW"
// =============================================================================
// Register : TRNG_SAMPLE_CNT1
// Description : Counts clocks between sampling of random bit.
#define TRNG_SAMPLE_CNT1_OFFSET _u(0x00000130)
#define TRNG_SAMPLE_CNT1_BITS _u(0xffffffff)
#define TRNG_SAMPLE_CNT1_RESET _u(0x0000ffff)
// -----------------------------------------------------------------------------
// Field : TRNG_SAMPLE_CNT1_SAMPLE_CNTR1
// Description : Sets the number of rng_clk cycles between two consecutive ring
// oscillator samples. Note! If the Von-Neuman is bypassed, the
// minimum value for sample counter must not be less then decimal
// seventeen
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET _u(0x0000ffff)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS _u(0xffffffff)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB _u(31)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB _u(0)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS "RW"
// =============================================================================
// Register : TRNG_AUTOCORR_STATISTIC
// Description : Statistic about Autocorrelation test activations.
#define TRNG_AUTOCORR_STATISTIC_OFFSET _u(0x00000134)
#define TRNG_AUTOCORR_STATISTIC_BITS _u(0xffffffff)
#define TRNG_AUTOCORR_STATISTIC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_RESERVED
// Description : RESERVED
#define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET _u(0x000)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS _u(0xffc00000)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB _u(31)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB _u(22)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS
// Description : Count each time an autocorrelation test fails. Any write to the
// register reset the counter. Stop collecting statistic if one of
// the counters reached the limit.
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET _u(0x00)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS _u(0x003fc000)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB _u(21)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB _u(14)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS
// Description : Count each time an autocorrelation test starts. Any write to
// the register reset the counter. Stop collecting statistic if
// one of the counters reached the limit.
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET _u(0x0000)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS _u(0x00003fff)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB _u(13)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB _u(0)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_DEBUG_CONTROL
// Description : Debug register.
#define TRNG_TRNG_DEBUG_CONTROL_OFFSET _u(0x00000138)
#define TRNG_TRNG_DEBUG_CONTROL_BITS _u(0x0000000f)
#define TRNG_TRNG_DEBUG_CONTROL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS
// Description : When set, the autocorrelation test in the TRNG module is
// bypassed.
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS _u(0x00000008)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB _u(3)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB _u(3)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS
// Description : When set, the CRNGT test in the RNG is bypassed.
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS _u(0x00000004)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB _u(2)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB _u(2)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS
// Description : When set, the Von-Neuman balancer is bypassed (including the 32
// consecutive bits test).
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS _u(0x00000002)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB _u(1)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB _u(1)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_RESERVED
// Description : N/A
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS _u(0x00000001)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB _u(0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB _u(0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS "RO"
// =============================================================================
// Register : TRNG_TRNG_SW_RESET
// Description : Generate internal SW reset within the RNG block.
#define TRNG_TRNG_SW_RESET_OFFSET _u(0x00000140)
#define TRNG_TRNG_SW_RESET_BITS _u(0xffffffff)
#define TRNG_TRNG_SW_RESET_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_SW_RESET_RESERVED
// Description : RESERVED
#define TRNG_TRNG_SW_RESET_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_SW_RESET_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_SW_RESET_RESERVED_MSB _u(31)
#define TRNG_TRNG_SW_RESET_RESERVED_LSB _u(1)
#define TRNG_TRNG_SW_RESET_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_SW_RESET_TRNG_SW_RESET
// Description : Writing 1'b1 to this register causes an internal RNG reset.
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET _u(0x0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS _u(0x00000001)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB _u(0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB _u(0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_DEBUG_EN_INPUT
// Description : Enable the RNG debug mode
#define TRNG_RNG_DEBUG_EN_INPUT_OFFSET _u(0x000001b4)
#define TRNG_RNG_DEBUG_EN_INPUT_BITS _u(0xffffffff)
#define TRNG_RNG_DEBUG_EN_INPUT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_DEBUG_EN_INPUT_RESERVED
// Description : RESERVED
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET _u(0x00000000)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB _u(31)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB _u(1)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN
// Description : * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET _u(0x0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS _u(0x00000001)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB _u(0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB _u(0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_BUSY
// Description : RNG Busy indication.
#define TRNG_TRNG_BUSY_OFFSET _u(0x000001b8)
#define TRNG_TRNG_BUSY_BITS _u(0xffffffff)
#define TRNG_TRNG_BUSY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_BUSY_RESERVED
// Description : RESERVED
#define TRNG_TRNG_BUSY_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_BUSY_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_BUSY_RESERVED_MSB _u(31)
#define TRNG_TRNG_BUSY_RESERVED_LSB _u(1)
#define TRNG_TRNG_BUSY_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_BUSY_TRNG_BUSY
// Description : Reflects rng_busy status.
#define TRNG_TRNG_BUSY_TRNG_BUSY_RESET _u(0x0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_BITS _u(0x00000001)
#define TRNG_TRNG_BUSY_TRNG_BUSY_MSB _u(0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_LSB _u(0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS "RO"
// =============================================================================
// Register : TRNG_RST_BITS_COUNTER
// Description : Reset the counter of collected bits in the RNG.
#define TRNG_RST_BITS_COUNTER_OFFSET _u(0x000001bc)
#define TRNG_RST_BITS_COUNTER_BITS _u(0xffffffff)
#define TRNG_RST_BITS_COUNTER_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RST_BITS_COUNTER_RESERVED
// Description : RESERVED
#define TRNG_RST_BITS_COUNTER_RESERVED_RESET _u(0x00000000)
#define TRNG_RST_BITS_COUNTER_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RST_BITS_COUNTER_RESERVED_MSB _u(31)
#define TRNG_RST_BITS_COUNTER_RESERVED_LSB _u(1)
#define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER
// Description : Writing any value to this address will reset the bits counter
// and RNG valid registers. RND_SORCE_ENABLE register must be
// unset in order for the reset to take place.
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET _u(0x0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS _u(0x00000001)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB _u(0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB _u(0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_VERSION
// Description : Displays the version settings of the TRNG.
#define TRNG_RNG_VERSION_OFFSET _u(0x000001c0)
#define TRNG_RNG_VERSION_BITS _u(0xffffffff)
#define TRNG_RNG_VERSION_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RESERVED
// Description : RESERVED
#define TRNG_RNG_VERSION_RESERVED_RESET _u(0x000000)
#define TRNG_RNG_VERSION_RESERVED_BITS _u(0xffffff00)
#define TRNG_RNG_VERSION_RESERVED_MSB _u(31)
#define TRNG_RNG_VERSION_RESERVED_LSB _u(8)
#define TRNG_RNG_VERSION_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RNG_USE_5_SBOXES
// Description : * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET _u(0x0)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS _u(0x00000080)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB _u(7)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB _u(7)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RESEEDING_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS _u(0x00000040)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB _u(6)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB _u(6)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_KAT_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_KAT_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_KAT_EXISTS_BITS _u(0x00000020)
#define TRNG_RNG_VERSION_KAT_EXISTS_MSB _u(5)
#define TRNG_RNG_VERSION_KAT_EXISTS_LSB _u(5)
#define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_PRNG_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_PRNG_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_PRNG_EXISTS_BITS _u(0x00000010)
#define TRNG_RNG_VERSION_PRNG_EXISTS_MSB _u(4)
#define TRNG_RNG_VERSION_PRNG_EXISTS_LSB _u(4)
#define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET _u(0x0)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS _u(0x00000008)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB _u(3)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB _u(3)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_AUTOCORR_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS _u(0x00000004)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB _u(2)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB _u(2)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_CRNGT_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS _u(0x00000002)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB _u(1)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB _u(1)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_EHR_WIDTH_192
// Description : * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR
#define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET _u(0x0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS _u(0x00000001)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB _u(0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB _u(0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_0
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_0_OFFSET _u(0x000001e0)
#define TRNG_RNG_BIST_CNTR_0_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_0_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_1
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_1_OFFSET _u(0x000001e4)
#define TRNG_RNG_BIST_CNTR_1_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_1_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_2
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_2_OFFSET _u(0x000001e8)
#define TRNG_RNG_BIST_CNTR_2_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_2_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TRNG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : WATCHDOG
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_WATCHDOG_H
#define _HARDWARE_REGS_WATCHDOG_H
// =============================================================================
// Register : WATCHDOG_CTRL
// Description : Watchdog control
// The rst_wdsel register determines which subsystems are reset
// when the watchdog is triggered.
// The watchdog can be triggered in software.
#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
#define WATCHDOG_CTRL_BITS _u(0xc7ffffff)
#define WATCHDOG_CTRL_RESET _u(0x07000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TRIGGER
// Description : Trigger a watchdog reset
#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0)
#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000)
#define WATCHDOG_CTRL_TRIGGER_MSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_LSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_ENABLE
// Description : When not enabled the watchdog timer is paused
#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000)
#define WATCHDOG_CTRL_ENABLE_MSB _u(30)
#define WATCHDOG_CTRL_ENABLE_LSB _u(30)
#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG1
// Description : Pause the watchdog timer when processor 1 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000)
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG0
// Description : Pause the watchdog timer when processor 0 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000)
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_JTAG
// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000)
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TIME
// Description : Indicates the time in usec before a watchdog reset will be
// triggered
#define WATCHDOG_CTRL_TIME_RESET _u(0x000000)
#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff)
#define WATCHDOG_CTRL_TIME_MSB _u(23)
#define WATCHDOG_CTRL_TIME_LSB _u(0)
#define WATCHDOG_CTRL_TIME_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_LOAD
// Description : Load the watchdog timer. The maximum setting is 0xffffff which
// corresponds to approximately 16 seconds.
#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
#define WATCHDOG_LOAD_BITS _u(0x00ffffff)
#define WATCHDOG_LOAD_RESET _u(0x00000000)
#define WATCHDOG_LOAD_MSB _u(23)
#define WATCHDOG_LOAD_LSB _u(0)
#define WATCHDOG_LOAD_ACCESS "WF"
// =============================================================================
// Register : WATCHDOG_REASON
// Description : Logs the reason for the last reset. Both bits are zero for the
// case of a hardware reset.
//
// Additionally, as of RP2350, a debugger warm reset of either
// core (SYSRESETREQ or hartreset) will also clear the watchdog
// reason register, so that software loaded under the debugger
// following a watchdog timeout will not continue to see the
// timeout condition.
#define WATCHDOG_REASON_OFFSET _u(0x00000008)
#define WATCHDOG_REASON_BITS _u(0x00000003)
#define WATCHDOG_REASON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_FORCE
#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
#define WATCHDOG_REASON_FORCE_MSB _u(1)
#define WATCHDOG_REASON_FORCE_LSB _u(1)
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_TIMER
#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
#define WATCHDOG_REASON_TIMER_MSB _u(0)
#define WATCHDOG_REASON_TIMER_LSB _u(0)
#define WATCHDOG_REASON_TIMER_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_SCRATCH0
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH0_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH0_MSB _u(31)
#define WATCHDOG_SCRATCH0_LSB _u(0)
#define WATCHDOG_SCRATCH0_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH1
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH1_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH1_MSB _u(31)
#define WATCHDOG_SCRATCH1_LSB _u(0)
#define WATCHDOG_SCRATCH1_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH2
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH2_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH2_MSB _u(31)
#define WATCHDOG_SCRATCH2_LSB _u(0)
#define WATCHDOG_SCRATCH2_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH3
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH3_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH3_MSB _u(31)
#define WATCHDOG_SCRATCH3_LSB _u(0)
#define WATCHDOG_SCRATCH3_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH4
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH4_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH4_MSB _u(31)
#define WATCHDOG_SCRATCH4_LSB _u(0)
#define WATCHDOG_SCRATCH4_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH5
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH5_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH5_MSB _u(31)
#define WATCHDOG_SCRATCH5_LSB _u(0)
#define WATCHDOG_SCRATCH5_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH6
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH6_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH6_MSB _u(31)
#define WATCHDOG_SCRATCH6_LSB _u(0)
#define WATCHDOG_SCRATCH6_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH7
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH7_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH7_MSB _u(31)
#define WATCHDOG_SCRATCH7_LSB _u(0)
#define WATCHDOG_SCRATCH7_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_WATCHDOG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XIP
// Version : 1
// Bus type : ahb
// Description : QSPI flash execute-in-place block
// =============================================================================
#ifndef _HARDWARE_REGS_XIP_H
#define _HARDWARE_REGS_XIP_H
// =============================================================================
// Register : XIP_CTRL
// Description : Cache control register. Read-only from a Non-secure context.
#define XIP_CTRL_OFFSET _u(0x00000000)
#define XIP_CTRL_BITS _u(0x00000ffb)
#define XIP_CTRL_RESET _u(0x00000083)
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_WRITABLE_M1
// Description : If 1, enable writes to XIP memory window 1 (addresses
// 0x11000000 through 0x11ffffff, and their uncached mirrors). If
// 0, this region is read-only.
//
// XIP memory is *read-only by default*. This bit must be set to
// enable writes if a RAM device is attached on QSPI chip select
// 1.
//
// The default read-only behaviour avoids two issues with writing
// to a read-only QSPI device (e.g. flash). First, a write will
// initially appear to succeed due to caching, but the data will
// eventually be lost when the written line is evicted, causing
// unpredictable behaviour.
//
// Second, when a written line is evicted, it will cause a write
// command to be issued to the flash, which can break the flash
// out of its continuous read mode. After this point, flash reads
// will return garbage. This is a security concern, as it allows
// Non-secure software to break Secure flash reads if it has
// permission to write to any flash address.
//
// Note the read-only behaviour is implemented by downgrading
// writes to reads, so writes will still cause allocation of an
// address, but have no other effect.
#define XIP_CTRL_WRITABLE_M1_RESET _u(0x0)
#define XIP_CTRL_WRITABLE_M1_BITS _u(0x00000800)
#define XIP_CTRL_WRITABLE_M1_MSB _u(11)
#define XIP_CTRL_WRITABLE_M1_LSB _u(11)
#define XIP_CTRL_WRITABLE_M1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_WRITABLE_M0
// Description : If 1, enable writes to XIP memory window 0 (addresses
// 0x10000000 through 0x10ffffff, and their uncached mirrors). If
// 0, this region is read-only.
//
// XIP memory is *read-only by default*. This bit must be set to
// enable writes if a RAM device is attached on QSPI chip select
// 0.
//
// The default read-only behaviour avoids two issues with writing
// to a read-only QSPI device (e.g. flash). First, a write will
// initially appear to succeed due to caching, but the data will
// eventually be lost when the written line is evicted, causing
// unpredictable behaviour.
//
// Second, when a written line is evicted, it will cause a write
// command to be issued to the flash, which can break the flash
// out of its continuous read mode. After this point, flash reads
// will return garbage. This is a security concern, as it allows
// Non-secure software to break Secure flash reads if it has
// permission to write to any flash address.
//
// Note the read-only behaviour is implemented by downgrading
// writes to reads, so writes will still cause allocation of an
// address, but have no other effect.
#define XIP_CTRL_WRITABLE_M0_RESET _u(0x0)
#define XIP_CTRL_WRITABLE_M0_BITS _u(0x00000400)
#define XIP_CTRL_WRITABLE_M0_MSB _u(10)
#define XIP_CTRL_WRITABLE_M0_LSB _u(10)
#define XIP_CTRL_WRITABLE_M0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_SPLIT_WAYS
// Description : When 1, route all cached+Secure accesses to way 0 of the cache,
// and route all cached+Non-secure accesses to way 1 of the cache.
//
// This partitions the cache into two half-sized direct-mapped
// regions, such that Non-secure code can not observe cache line
// state changes caused by Secure execution.
//
// A full cache flush is required when changing the value of
// SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is
// 0, so that both cache ways are accessible for invalidation.
#define XIP_CTRL_SPLIT_WAYS_RESET _u(0x0)
#define XIP_CTRL_SPLIT_WAYS_BITS _u(0x00000200)
#define XIP_CTRL_SPLIT_WAYS_MSB _u(9)
#define XIP_CTRL_SPLIT_WAYS_LSB _u(9)
#define XIP_CTRL_SPLIT_WAYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_MAINT_NONSEC
// Description : When 0, Non-secure accesses to the cache maintenance address
// window (addr[27] == 1, addr[26] == 0) will generate a bus
// error. When 1, Non-secure accesses can perform cache
// maintenance operations by writing to the cache maintenance
// address window.
//
// Cache maintenance operations may be used to corrupt Secure data
// by invalidating cache lines inappropriately, or map Secure
// content into a Non-secure region by pinning cache lines.
// Therefore this bit should generally be set to 0, unless Secure
// code is not using the cache.
//
// Care should also be taken to clear the cache data memory and
// tag memory before granting maintenance operations to Non-secure
// code.
#define XIP_CTRL_MAINT_NONSEC_RESET _u(0x0)
#define XIP_CTRL_MAINT_NONSEC_BITS _u(0x00000100)
#define XIP_CTRL_MAINT_NONSEC_MSB _u(8)
#define XIP_CTRL_MAINT_NONSEC_LSB _u(8)
#define XIP_CTRL_MAINT_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNTRANSLATED_NONSEC
// Description : When 1, Non-secure accesses to the uncached, untranslated
// window (addr[27:26] == 3) will generate a bus error.
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_RESET _u(0x1)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_BITS _u(0x00000080)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_MSB _u(7)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_LSB _u(7)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNTRANSLATED_SEC
// Description : When 1, Secure accesses to the uncached, untranslated window
// (addr[27:26] == 3) will generate a bus error.
#define XIP_CTRL_NO_UNTRANSLATED_SEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_BITS _u(0x00000040)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_MSB _u(6)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_LSB _u(6)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNCACHED_NONSEC
// Description : When 1, Non-secure accesses to the uncached window (addr[27:26]
// == 1) will generate a bus error. This may reduce the number of
// SAU/MPU/PMP regions required to protect flash contents.
//
// Note this does not disable access to the uncached, untranslated
// window -- see NO_UNTRANSLATED_SEC.
#define XIP_CTRL_NO_UNCACHED_NONSEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNCACHED_NONSEC_BITS _u(0x00000020)
#define XIP_CTRL_NO_UNCACHED_NONSEC_MSB _u(5)
#define XIP_CTRL_NO_UNCACHED_NONSEC_LSB _u(5)
#define XIP_CTRL_NO_UNCACHED_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNCACHED_SEC
// Description : When 1, Secure accesses to the uncached window (addr[27:26] ==
// 1) will generate a bus error. This may reduce the number of
// SAU/MPU/PMP regions required to protect flash contents.
//
// Note this does not disable access to the uncached, untranslated
// window -- see NO_UNTRANSLATED_SEC.
#define XIP_CTRL_NO_UNCACHED_SEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNCACHED_SEC_BITS _u(0x00000010)
#define XIP_CTRL_NO_UNCACHED_SEC_MSB _u(4)
#define XIP_CTRL_NO_UNCACHED_SEC_LSB _u(4)
#define XIP_CTRL_NO_UNCACHED_SEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_POWER_DOWN
// Description : When 1, the cache memories are powered down. They retain state,
// but can not be accessed. This reduces static power dissipation.
// Writing 1 to this bit forces CTRL_EN_SECURE and
// CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when
// powered down.
#define XIP_CTRL_POWER_DOWN_RESET _u(0x0)
#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008)
#define XIP_CTRL_POWER_DOWN_MSB _u(3)
#define XIP_CTRL_POWER_DOWN_LSB _u(3)
#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN_NONSECURE
// Description : When 1, enable the cache for Non-secure accesses. When enabled,
// Non-secure XIP accesses to the cached (addr[26] == 0) window
// will query the cache, and QSPI accesses are performed only if
// the requested data is not present. When disabled, Secure access
// ignore the cache contents, and always access the QSPI
// interface.
//
// Accesses to the uncached (addr[26] == 1) window will never
// query the cache, irrespective of this bit.
#define XIP_CTRL_EN_NONSECURE_RESET _u(0x1)
#define XIP_CTRL_EN_NONSECURE_BITS _u(0x00000002)
#define XIP_CTRL_EN_NONSECURE_MSB _u(1)
#define XIP_CTRL_EN_NONSECURE_LSB _u(1)
#define XIP_CTRL_EN_NONSECURE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN_SECURE
// Description : When 1, enable the cache for Secure accesses. When enabled,
// Secure XIP accesses to the cached (addr[26] == 0) window will
// query the cache, and QSPI accesses are performed only if the
// requested data is not present. When disabled, Secure access
// ignore the cache contents, and always access the QSPI
// interface.
//
// Accesses to the uncached (addr[26] == 1) window will never
// query the cache, irrespective of this bit.
//
// There is no cache-as-SRAM address window. Cache lines are
// allocated for SRAM-like use by individually pinning them, and
// keeping the cache enabled.
#define XIP_CTRL_EN_SECURE_RESET _u(0x1)
#define XIP_CTRL_EN_SECURE_BITS _u(0x00000001)
#define XIP_CTRL_EN_SECURE_MSB _u(0)
#define XIP_CTRL_EN_SECURE_LSB _u(0)
#define XIP_CTRL_EN_SECURE_ACCESS "RW"
// =============================================================================
// Register : XIP_STAT
#define XIP_STAT_OFFSET _u(0x00000008)
#define XIP_STAT_BITS _u(0x00000006)
#define XIP_STAT_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_FULL
// Description : When 1, indicates the XIP streaming FIFO is completely full.
// The streaming FIFO is 2 entries deep, so the full and empty
// flag allow its level to be ascertained.
#define XIP_STAT_FIFO_FULL_RESET _u(0x0)
#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004)
#define XIP_STAT_FIFO_FULL_MSB _u(2)
#define XIP_STAT_FIFO_FULL_LSB _u(2)
#define XIP_STAT_FIFO_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_EMPTY
// Description : When 1, indicates the XIP streaming FIFO is completely empty.
#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1)
#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002)
#define XIP_STAT_FIFO_EMPTY_MSB _u(1)
#define XIP_STAT_FIFO_EMPTY_LSB _u(1)
#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
// =============================================================================
// Register : XIP_CTR_HIT
// Description : Cache Hit counter
// A 32 bit saturating counter that increments upon each cache
// hit,
// i.e. when an XIP access is serviced directly from cached data.
// Write any value to clear.
#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
#define XIP_CTR_HIT_BITS _u(0xffffffff)
#define XIP_CTR_HIT_RESET _u(0x00000000)
#define XIP_CTR_HIT_MSB _u(31)
#define XIP_CTR_HIT_LSB _u(0)
#define XIP_CTR_HIT_ACCESS "WC"
// =============================================================================
// Register : XIP_CTR_ACC
// Description : Cache Access counter
// A 32 bit saturating counter that increments upon each XIP
// access,
// whether the cache is hit or not. This includes noncacheable
// accesses.
// Write any value to clear.
#define XIP_CTR_ACC_OFFSET _u(0x00000010)
#define XIP_CTR_ACC_BITS _u(0xffffffff)
#define XIP_CTR_ACC_RESET _u(0x00000000)
#define XIP_CTR_ACC_MSB _u(31)
#define XIP_CTR_ACC_LSB _u(0)
#define XIP_CTR_ACC_ACCESS "WC"
// =============================================================================
// Register : XIP_STREAM_ADDR
// Description : FIFO stream address
// The address of the next word to be streamed from flash to the
// streaming FIFO.
// Increments automatically after each flash access.
// Write the initial access address here before starting a
// streaming read.
#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
#define XIP_STREAM_ADDR_BITS _u(0xfffffffc)
#define XIP_STREAM_ADDR_RESET _u(0x00000000)
#define XIP_STREAM_ADDR_MSB _u(31)
#define XIP_STREAM_ADDR_LSB _u(2)
#define XIP_STREAM_ADDR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_CTR
// Description : FIFO stream control
// Write a nonzero value to start a streaming read. This will then
// progress in the background, using flash idle cycles to transfer
// a linear data block from flash to the streaming FIFO.
// Decrements automatically (1 at a time) as the stream
// progresses, and halts on reaching 0.
// Write 0 to halt an in-progress stream, and discard any in-
// flight
// read, so that a new stream can immediately be started (after
// draining the FIFO and reinitialising STREAM_ADDR)
#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
#define XIP_STREAM_CTR_BITS _u(0x003fffff)
#define XIP_STREAM_CTR_RESET _u(0x00000000)
#define XIP_STREAM_CTR_MSB _u(21)
#define XIP_STREAM_CTR_LSB _u(0)
#define XIP_STREAM_CTR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_FIFO
// Description : FIFO stream data
// Streamed data is buffered here, for retrieval by the system
// DMA.
// This FIFO can also be accessed via the XIP_AUX slave, to avoid
// exposing
// the DMA to bus stalls caused by other XIP traffic.
#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
#define XIP_STREAM_FIFO_BITS _u(0xffffffff)
#define XIP_STREAM_FIFO_RESET _u(0x00000000)
#define XIP_STREAM_FIFO_MSB _u(31)
#define XIP_STREAM_FIFO_LSB _u(0)
#define XIP_STREAM_FIFO_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_XIP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XIP_AUX
// Version : 1
// Bus type : ahb
// Description : Auxiliary DMA access to XIP FIFOs, via fast AHB bus access
// =============================================================================
#ifndef _HARDWARE_REGS_XIP_AUX_H
#define _HARDWARE_REGS_XIP_AUX_H
// =============================================================================
// Register : XIP_AUX_STREAM
// Description : Read the XIP stream FIFO (fast bus access to
// XIP_CTRL_STREAM_FIFO)
#define XIP_AUX_STREAM_OFFSET _u(0x00000000)
#define XIP_AUX_STREAM_BITS _u(0xffffffff)
#define XIP_AUX_STREAM_RESET _u(0x00000000)
#define XIP_AUX_STREAM_MSB _u(31)
#define XIP_AUX_STREAM_LSB _u(0)
#define XIP_AUX_STREAM_ACCESS "RF"
// =============================================================================
// Register : XIP_AUX_QMI_DIRECT_TX
// Description : Write to the QMI direct-mode TX FIFO (fast bus access to
// QMI_DIRECT_TX)
#define XIP_AUX_QMI_DIRECT_TX_OFFSET _u(0x00000004)
#define XIP_AUX_QMI_DIRECT_TX_BITS _u(0x001fffff)
#define XIP_AUX_QMI_DIRECT_TX_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_NOPUSH
// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO
// entry.
//
// Useful to avoid garbage appearing in the RX FIFO when pushing
// the command at the beginning of a SPI transfer.
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_MSB _u(20)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_LSB _u(20)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_OE
// Description : Output enable (active-high). For single width (SPI), this field
// is ignored, and SD0 is always set to output, with SD1 always
// set to input.
//
// For dual and quad width (DSPI/QSPI), this sets whether the
// relevant SDx pads are set to output whilst transferring this
// FIFO record. In this case the command/address should have OE
// set, and the data transfer should have OE set or clear
// depending on the direction of the transfer.
#define XIP_AUX_QMI_DIRECT_TX_OE_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_OE_BITS _u(0x00080000)
#define XIP_AUX_QMI_DIRECT_TX_OE_MSB _u(19)
#define XIP_AUX_QMI_DIRECT_TX_OE_LSB _u(19)
#define XIP_AUX_QMI_DIRECT_TX_OE_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_DWIDTH
// Description : Data width. If 0, hardware will transmit the 8 LSBs of the
// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs
// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and
// 16-bit transfers can be mixed freely.
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_MSB _u(18)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_LSB _u(18)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_IWIDTH
// Description : Configure whether this FIFO record is transferred with
// single/dual/quad interface width (0/1/2). Different widths can
// be mixed freely.
// 0x0 -> Single width
// 0x1 -> Dual width
// 0x2 -> Quad width
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_MSB _u(17)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_LSB _u(16)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_ACCESS "WF"
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2)
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_DATA
// Description : Data pushed here will be clocked out falling edges of SCK (or
// before the very first rising edge of SCK, if this is the first
// pulse). For each byte clocked out, the interface will
// simultaneously sample one byte, on rising edges of SCK, and
// push this to the DIRECT_RX FIFO.
//
// For 16-bit data, the least-significant byte is transmitted
// first.
#define XIP_AUX_QMI_DIRECT_TX_DATA_RESET _u(0x0000)
#define XIP_AUX_QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff)
#define XIP_AUX_QMI_DIRECT_TX_DATA_MSB _u(15)
#define XIP_AUX_QMI_DIRECT_TX_DATA_LSB _u(0)
#define XIP_AUX_QMI_DIRECT_TX_DATA_ACCESS "WF"
// =============================================================================
// Register : XIP_AUX_QMI_DIRECT_RX
// Description : Read from the QMI direct-mode RX FIFO (fast bus access to
// QMI_DIRECT_RX)
// With each byte clocked out on the serial interface, one byte
// will simultaneously be clocked in, and will appear in this
// FIFO. The serial interface will stall when this FIFO is full,
// to avoid dropping data.
//
// When 16-bit data is pushed into the TX FIFO, the corresponding
// RX FIFO push will also contain 16 bits of data. The least-
// significant byte is the first one received.
#define XIP_AUX_QMI_DIRECT_RX_OFFSET _u(0x00000008)
#define XIP_AUX_QMI_DIRECT_RX_BITS _u(0x0000ffff)
#define XIP_AUX_QMI_DIRECT_RX_RESET _u(0x00000000)
#define XIP_AUX_QMI_DIRECT_RX_MSB _u(15)
#define XIP_AUX_QMI_DIRECT_RX_LSB _u(0)
#define XIP_AUX_QMI_DIRECT_RX_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_XIP_AUX_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XOSC
// Version : 1
// Bus type : apb
// Description : Controls the crystal oscillator
// =============================================================================
#ifndef _HARDWARE_REGS_XOSC_H
#define _HARDWARE_REGS_XOSC_H
// =============================================================================
// Register : XOSC_CTRL
// Description : Crystal Oscillator Control
#define XOSC_CTRL_OFFSET _u(0x00000000)
#define XOSC_CTRL_BITS _u(0x00ffffff)
#define XOSC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_ENABLE
// Description : On power-up this field is initialised to DISABLE and the chip
// runs from the ROSC.
// If the chip has subsequently been programmed to run from the
// XOSC then setting this field to DISABLE may lock-up the chip.
// If this is a concern then run the clk_ref from the ROSC and
// enable the clk_sys RESUS feature.
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will retain the previous
// value. The actual value being used can be read from
// STATUS_ENABLED
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define XOSC_CTRL_ENABLE_RESET "-"
#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000)
#define XOSC_CTRL_ENABLE_MSB _u(23)
#define XOSC_CTRL_ENABLE_LSB _u(12)
#define XOSC_CTRL_ENABLE_ACCESS "RW"
#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_FREQ_RANGE
// Description : The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will retain the previous
// value. The actual value being used can be read from
// STATUS_FREQ_RANGE
// 0xaa0 -> 1_15MHZ
// 0xaa1 -> 10_30MHZ
// 0xaa2 -> 25_60MHZ
// 0xaa3 -> 40_100MHZ
#define XOSC_CTRL_FREQ_RANGE_RESET "-"
#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
#define XOSC_CTRL_FREQ_RANGE_MSB _u(11)
#define XOSC_CTRL_FREQ_RANGE_LSB _u(0)
#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
#define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ _u(0xaa1)
#define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ _u(0xaa2)
#define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ _u(0xaa3)
// =============================================================================
// Register : XOSC_STATUS
// Description : Crystal Oscillator Status
#define XOSC_STATUS_OFFSET _u(0x00000004)
#define XOSC_STATUS_BITS _u(0x81001003)
#define XOSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define XOSC_STATUS_STABLE_RESET _u(0x0)
#define XOSC_STATUS_STABLE_BITS _u(0x80000000)
#define XOSC_STATUS_STABLE_MSB _u(31)
#define XOSC_STATUS_STABLE_LSB _u(31)
#define XOSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or DORMANT
#define XOSC_STATUS_BADWRITE_RESET _u(0x0)
#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define XOSC_STATUS_BADWRITE_MSB _u(24)
#define XOSC_STATUS_BADWRITE_LSB _u(24)
#define XOSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable,
// resets to 0
#define XOSC_STATUS_ENABLED_RESET "-"
#define XOSC_STATUS_ENABLED_BITS _u(0x00001000)
#define XOSC_STATUS_ENABLED_MSB _u(12)
#define XOSC_STATUS_ENABLED_LSB _u(12)
#define XOSC_STATUS_ENABLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_FREQ_RANGE
// Description : The current frequency range setting
// 0x0 -> 1_15MHZ
// 0x1 -> 10_30MHZ
// 0x2 -> 25_60MHZ
// 0x3 -> 40_100MHZ
#define XOSC_STATUS_FREQ_RANGE_RESET "-"
#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003)
#define XOSC_STATUS_FREQ_RANGE_MSB _u(1)
#define XOSC_STATUS_FREQ_RANGE_LSB _u(0)
#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
#define XOSC_STATUS_FREQ_RANGE_VALUE_10_30MHZ _u(0x1)
#define XOSC_STATUS_FREQ_RANGE_VALUE_25_60MHZ _u(0x2)
#define XOSC_STATUS_FREQ_RANGE_VALUE_40_100MHZ _u(0x3)
// =============================================================================
// Register : XOSC_DORMANT
// Description : Crystal Oscillator pause control
// This is used to save power by pausing the XOSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// Warning: stop the PLLs before selecting dormant mode
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> dormant
// 0x77616b65 -> WAKE
#define XOSC_DORMANT_OFFSET _u(0x00000008)
#define XOSC_DORMANT_BITS _u(0xffffffff)
#define XOSC_DORMANT_RESET "-"
#define XOSC_DORMANT_MSB _u(31)
#define XOSC_DORMANT_LSB _u(0)
#define XOSC_DORMANT_ACCESS "RW"
#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : XOSC_STARTUP
// Description : Controls the startup delay
#define XOSC_STARTUP_OFFSET _u(0x0000000c)
#define XOSC_STARTUP_BITS _u(0x00103fff)
#define XOSC_STARTUP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4, just in case. The reset
// value is controlled by a mask-programmable tiecell and is
// provided in case we are booting from XOSC and the default
// startup delay is insufficient. The reset value is 0x0.
#define XOSC_STARTUP_X4_RESET "-"
#define XOSC_STARTUP_X4_BITS _u(0x00100000)
#define XOSC_STARTUP_X4_MSB _u(20)
#define XOSC_STARTUP_X4_LSB _u(20)
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period. The reset value of 0xc4
// corresponds to approx 50 000 cycles.
#define XOSC_STARTUP_DELAY_RESET "-"
#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
#define XOSC_STARTUP_DELAY_MSB _u(13)
#define XOSC_STARTUP_DELAY_LSB _u(0)
#define XOSC_STARTUP_DELAY_ACCESS "RW"
// =============================================================================
// Register : XOSC_COUNT
// Description : A down counter running at the xosc frequency which counts to
// zero and stops.
// Can be used for short software pauses when setting up time
// sensitive hardware.
// To start the counter, write a non-zero value. Reads will return
// 1 while the count is running and 0 when it has finished.
// Minimum count value is 4. Count values <4 will be treated as
// count value =4.
// Note that synchronisation to the register clock domain costs 2
// register clock cycles and the counter cannot compensate for
// that.
#define XOSC_COUNT_OFFSET _u(0x00000010)
#define XOSC_COUNT_BITS _u(0x0000ffff)
#define XOSC_COUNT_RESET _u(0x00000000)
#define XOSC_COUNT_MSB _u(15)
#define XOSC_COUNT_LSB _u(0)
#define XOSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_XOSC_H