diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 95550a983898..ca8cb84bac5f 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -165,6 +165,5 @@ config ROCKCHIP_DW_HDCP2
 	  Designware HDCP2 Controller.
 
 source "drivers/gpu/drm/rockchip/rk618/Kconfig"
-source "drivers/gpu/drm/rockchip/rk628/Kconfig"
 
 endif
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index 7aa90fa2002c..a211c295664b 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -31,4 +31,3 @@ rockchipdrm-$(CONFIG_DRM_ROCKCHIP_VVOP) += rockchip_drm_vvop.o
 obj-$(CONFIG_ROCKCHIP_DW_HDCP2) += dw_hdcp2.o
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o
 obj-$(CONFIG_DRM_ROCKCHIP_RK618) += rk618/
-obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628/
diff --git a/drivers/gpu/drm/rockchip/rk628/Kconfig b/drivers/gpu/drm/rockchip/rk628/Kconfig
deleted file mode 100644
index 41e1fbbe1e61..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/Kconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-
-config DRM_ROCKCHIP_RK628
-	tristate "Rockchip RK628 display bridge driver"
-	depends on DRM_ROCKCHIP
-	depends on MFD_RK628
-	help
-	  Rockchip RK628 display bridge chips driver.
diff --git a/drivers/gpu/drm/rockchip/rk628/Makefile b/drivers/gpu/drm/rockchip/rk628/Makefile
deleted file mode 100644
index 76d768d29776..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the Rockchip RK628 display bridge driver.
-#
-
-obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combrxphy.o \
-				    rk628_combtxphy.o \
-				    rk628_dsi.o \
-				    rk628_gvi.o \
-				    rk628_lvds.o \
-				    rk628_post_process.o \
-				    rk628_rgb.o \
-				    rk628_hdmi.o \
-				    rk628_hdmirx.o
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c b/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c
deleted file mode 100644
index a83eeeaf935f..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Algea Cao <algea.cao@rock-chips.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/reset.h>
-#include <linux/phy/phy.h>
-#include <linux/mfd/rk628.h>
-
-struct rk628_combrxphy {
-	struct device *dev;
-	struct rk628 *parent;
-	struct regmap *regmap;
-	struct clk *pclk;
-	struct reset_control *rstc;
-	bool is_cable_mode;
-};
-
-#define REG(x)			((x) + 0x10000)
-#define COMBRXPHY_MAX_REGISTER	REG(0x6790)
-
-#define MAX_ROUND		6
-#define MAX_DATA_NUM		16
-#define MAX_CHANNEL		3
-#define CLK_DET_TRY_TIMES	10
-#define CLK_STABLE_LOOP_CNT	10
-#define CLK_STABLE_THRESHOLD	6
-
-static int debug;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug, "debug level (0-1)");
-
-static void rk628_combrxphy_set_data_of_round(u32 *data, u32 *data_in)
-{
-	if ((data != NULL) && (data_in != NULL)) {
-		data_in[0] = data[0];
-		data_in[1] = data[7];
-		data_in[2] = data[13];
-		data_in[3] = data[14];
-		data_in[4] = data[15];
-		data_in[5] = data[1];
-		data_in[6] = data[2];
-		data_in[7] = data[3];
-		data_in[8] = data[4];
-		data_in[9] = data[5];
-		data_in[10] = data[6];
-		data_in[11] = data[8];
-		data_in[12] = data[9];
-		data_in[13] = data[10];
-		data_in[14] = data[11];
-		data_in[15] = data[12];
-	}
-}
-
-static void
-rk628_combrxphy_max_zero_of_round(struct rk628_combrxphy *combrxphy,
-				  u32 *data_in, u32 *max_zero, u32 *max_val,
-				  int n, int ch)
-{
-	u32 i;
-	u32 cnt = 0;
-	u32 max_cnt = 0;
-	u32 max_v = 0;
-
-	if (debug > 0) {
-		dev_info(combrxphy->dev,
-			"%s channel:%d, round:%d ====\n",  __func__, ch, n);
-		print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4,
-				data_in, MAX_DATA_NUM * sizeof(u32), false);
-	}
-
-	for (i = 0; i < MAX_DATA_NUM; i++) {
-		if (max_v < data_in[i])
-			max_v = data_in[i];
-	}
-
-	for (i = 0; i < MAX_DATA_NUM; i++) {
-		if (data_in[i] == 0)
-			cnt = cnt + 200;
-		else if ((data_in[i] > 0) && (data_in[i] < 100))
-			cnt = cnt + 100 - data_in[i];
-	}
-	max_cnt = (cnt >= 3200) ? 0 : cnt;
-
-	max_zero[n] = max_cnt;
-	max_val[n] = max_v;
-	dev_dbg(combrxphy->dev,
-		"channel:%d, round:%d, max_zero_cnt:%d, max_val:%#x",
-		ch, n, max_zero[n], max_val[n]);
-}
-
-static int
-rk628_combrxphy_chose_round_for_ch(struct rk628_combrxphy *combrxphy,
-				   u32 *rd_max_zero,
-				   u32 *rd_max_val, int ch)
-{
-	int i, rd = 0;
-	u32 max = 0;
-	u32 max_v = 0;
-
-	if (debug > 0) {
-		dev_info(combrxphy->dev,
-			"%s max cnt of channel:%d ====\n", __func__, ch);
-		print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4,
-				rd_max_zero, MAX_ROUND * sizeof(u32), false);
-
-		dev_info(combrxphy->dev,
-			"%s max value of channel:%d ====\n", __func__, ch);
-		print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4,
-				rd_max_val, MAX_ROUND * sizeof(u32), false);
-	}
-
-	for (i = 0; i < MAX_ROUND; i++) {
-		if (rd_max_zero[i] > max) {
-			max = rd_max_zero[i];
-			max_v = rd_max_val[i];
-			rd = i;
-		} else if (rd_max_zero[i] == max && rd_max_val[i] > max_v) {
-			max = rd_max_zero[i];
-			max_v = rd_max_val[i];
-			rd = i;
-		}
-	}
-
-	dev_dbg(combrxphy->dev, "%s channel:%d, rd:%d\n", __func__, ch, rd);
-	return rd;
-}
-
-static void rk628_combrxphy_get_data_of_round(struct rk628_combrxphy
-					      *combrxphy, u32 *data)
-{
-	u32 i;
-
-	for (i = 0; i < MAX_DATA_NUM; i++)
-		regmap_read(combrxphy->regmap, REG(0x6740 + i * 4), &data[i]);
-}
-
-static void
-rk628_combrxphy_set_dc_gain(struct rk628_combrxphy *combrxphy,
-			    u32 x, u32 y, u32 z)
-{
-	u32 val;
-	u32 dc_gain_ch0, dc_gain_ch1, dc_gain_ch2;
-
-	dev_dbg(combrxphy->dev, "channel dc gain ch0:%d, ch1:%d, ch2:%d\n",
-			x, y, z);
-
-	dc_gain_ch0 = x & 0xf;
-	dc_gain_ch1 = y & 0xf;
-	dc_gain_ch2 = z & 0xf;
-	regmap_read(combrxphy->regmap, REG(0x661c), &val);
-
-	val = (val & 0xff0f0f0f) | (dc_gain_ch0 << 20) | (dc_gain_ch1 << 12) |
-		(dc_gain_ch2 << 4);
-	regmap_write(combrxphy->regmap, REG(0x661c), val);
-}
-
-static void rk628_combrxphy_set_sample_edge_round(struct rk628_combrxphy
-		*combrxphy, u32 x, u32 y, u32 z)
-{
-	u32 val;
-	u32 equ_gain_ch0, equ_gain_ch1, equ_gain_ch2;
-
-	dev_dbg(combrxphy->dev, "channel equ gain ch0:%d, ch1:%d, ch2:%d\n",
-			x, y, z);
-
-	equ_gain_ch0 = (x & 0xf);
-	equ_gain_ch1 = (y & 0xf);
-	equ_gain_ch2 = (z & 0xf);
-	regmap_read(combrxphy->regmap, REG(0x6618), &val);
-	val = (val & 0xff00f0ff) | (equ_gain_ch1 << 20) |
-		(equ_gain_ch0 << 16) | (equ_gain_ch2 << 8);
-	regmap_write(combrxphy->regmap, REG(0x6618), val);
-}
-
-static void rk628_combrxphy_start_sample_edge(struct rk628_combrxphy *combrxphy)
-{
-	u32 val;
-
-	regmap_read(combrxphy->regmap, REG(0x66f0), &val);
-	val &= 0xfffff1ff;
-	regmap_write(combrxphy->regmap, REG(0x66f0), val);
-	regmap_read(combrxphy->regmap, REG(0x66f0), &val);
-	val = (val & 0xfffff1ff) | (0x7 << 9);
-	regmap_write(combrxphy->regmap, REG(0x66f0), val);
-}
-
-static void
-rk628_combrxphy_set_sample_edge_mode(struct rk628_combrxphy *combrxphy,
-				     int ch)
-{
-	u32 val;
-
-	regmap_read(combrxphy->regmap, REG(0x6634), &val);
-	val = val & (~(0xf << ((ch + 1) * 4)));
-	regmap_write(combrxphy->regmap, REG(0x6634), val);
-}
-
-static void rk628_combrxphy_select_channel(struct rk628_combrxphy *combrxphy,
-					  int ch)
-{
-	u32 val;
-
-	regmap_read(combrxphy->regmap, REG(0x6700), &val);
-	val = (val & 0xfffffffc) | (ch & 0x3);
-	regmap_write(combrxphy->regmap, REG(0x6700), val);
-}
-
-static void rk628_combrxphy_cfg_6730(struct rk628_combrxphy *combrxphy)
-{
-	u32 val;
-
-	regmap_read(combrxphy->regmap, REG(0x6730), &val);
-	val = (val & 0xffff0000) | 0x1;
-	regmap_write(combrxphy->regmap, REG(0x6730), val);
-}
-
-static void rk628_combrxphy_sample_edge_procedure_for_cable(
-		struct rk628_combrxphy *combrxphy, u32 cdr_mode)
-{
-	u32 n, ch;
-	u32 data[MAX_DATA_NUM];
-	u32 data_in[MAX_DATA_NUM];
-	u32 round_max_zero[MAX_CHANNEL][MAX_ROUND];
-	u32 round_max_value[MAX_CHANNEL][MAX_ROUND];
-	u32 ch_round[MAX_CHANNEL];
-	u32 edge, dc_gain;
-	u32 rd_offset;
-
-	/* Step1: set sample edge mode for channel 0~2 */
-	for (ch = 0; ch < MAX_CHANNEL; ch++)
-		rk628_combrxphy_set_sample_edge_mode(combrxphy, ch);
-
-	/* step2: once per round */
-	for (ch = 0; ch < MAX_CHANNEL; ch++) {
-		rk628_combrxphy_select_channel(combrxphy, ch);
-		rk628_combrxphy_cfg_6730(combrxphy);
-	}
-
-	/* step3: config sample edge until the end of one frame
-	 * (for example 1080p:2200*1125=32’h25c3f8)
-	 */
-	if (cdr_mode < 16) {
-		dc_gain = 0;
-		rd_offset = 0;
-	} else if (cdr_mode < 18) {
-		dc_gain = 1;
-		rd_offset = 0;
-	} else {
-		dc_gain = 3;
-		rd_offset = 2;
-	}
-
-	/* When the pix clk is the same, the low frame rate resolution is used
-	 * to calculate the sampling window (the frame rate is not less than
-	 * 30). The sampling delay time is configured as 40ms.
-	 */
-	if (cdr_mode <= 1) { /* 27M vic17 720x576P50 */
-		edge = 864 * 625;
-	} else if (cdr_mode <= 4) { /* 59.4M vic81 1680x720P30 */
-		edge = 2640 * 750;
-	} else if (cdr_mode <= 7) { /* 74.25M vic34 1920x1080P30 */
-		edge = 2200 * 1125;
-	} else if (cdr_mode <= 14) { /* 119M vic88 2560x1180P30 */
-		edge = 3520 * 1125;
-	} else if (cdr_mode <= 16) { /* 148.5M vic31 1920x1080P50 */
-		edge = 2640 * 1125;
-	} else if (cdr_mode <= 17) { /* 162M vic89 2560x1080P50 */
-		edge = 3300 * 1125;
-	} else if (cdr_mode <= 18) { /* 297M vic95 3840x2160P30 */
-		edge = 4400 * 2250;
-	} else {		     /* unkonw vic16 1920x1080P60 */
-		edge = 2200 * 1125;
-	}
-
-	dev_info(combrxphy->dev,
-		"cdr_mode:%d, dc_gain:%d, rd_offset:%d, edge:%#x\n",
-		cdr_mode, dc_gain, rd_offset, edge);
-	for (ch = 0; ch < MAX_CHANNEL; ch++) {
-		rk628_combrxphy_select_channel(combrxphy, ch);
-		regmap_write(combrxphy->regmap, REG(0x6708), edge);
-	}
-
-	rk628_combrxphy_set_dc_gain(combrxphy, dc_gain, dc_gain, dc_gain);
-	for (n = rd_offset; n < (rd_offset + MAX_ROUND); n++) {
-		/* step4:set sample edge round value n,n=0(n=0~31) */
-		rk628_combrxphy_set_sample_edge_round(combrxphy, n, n, n);
-		/* step5:start sample edge */
-		rk628_combrxphy_start_sample_edge(combrxphy);
-		/* step6:waiting more than one frame time */
-		usleep_range(40*1000, 41*1000);
-		for (ch = 0; ch < MAX_CHANNEL; ch++) {
-			/* step7: get data of round n */
-			rk628_combrxphy_select_channel(combrxphy, ch);
-			rk628_combrxphy_get_data_of_round(combrxphy, data);
-			rk628_combrxphy_set_data_of_round(data, data_in);
-			/* step8: get the max constant value of round n */
-			rk628_combrxphy_max_zero_of_round(combrxphy, data_in,
-				round_max_zero[ch], round_max_value[ch],
-				n - rd_offset, ch);
-		}
-	}
-
-	/* step9: after finish round, get the max constant value and
-	 * corresponding value n.
-	 */
-	for (ch = 0; ch < MAX_CHANNEL; ch++) {
-		ch_round[ch] = rk628_combrxphy_chose_round_for_ch(combrxphy,
-				round_max_zero[ch], round_max_value[ch], ch)
-				+ rd_offset;
-	}
-	dev_info(combrxphy->dev, "last equ gain ch0:%d, ch1:%d, ch2:%d\n",
-		ch_round[0], ch_round[1], ch_round[2]);
-
-	 /* step10: write result to sample edge round value  */
-	rk628_combrxphy_set_sample_edge_round(combrxphy, ch_round[0],
-		ch_round[1], ch_round[2]);
-
-	/* do step5, step6 again */
-	/* step5:start sample edge */
-	rk628_combrxphy_start_sample_edge(combrxphy);
-	/* step6:waiting more than one frame time */
-	usleep_range(40*1000, 41*1000);
-}
-
-static void
-rk628_combrxphy_sample_edge_procedure(struct rk628_combrxphy *combrxphy,
-				      int f, u32 rd_offset)
-{
-	u32 n, ch;
-	u32 data[MAX_DATA_NUM];
-	u32 data_in[MAX_DATA_NUM];
-	u32 round_max_zero[MAX_CHANNEL][MAX_ROUND];
-	u32 round_max_value[MAX_CHANNEL][MAX_ROUND];
-	u32 ch_round[MAX_CHANNEL];
-	u32 edge, dc_gain;
-
-	dev_dbg(combrxphy->dev, "%s in!", __func__);
-	/* Step1: set sample edge mode for channel 0~2 */
-	for (ch = 0; ch < MAX_CHANNEL; ch++)
-		rk628_combrxphy_set_sample_edge_mode(combrxphy, ch);
-
-	dev_dbg(combrxphy->dev, "step1 set sample edge mode ok!");
-
-	/* step2: once per round */
-	for (ch = 0; ch < MAX_CHANNEL; ch++) {
-		rk628_combrxphy_select_channel(combrxphy, ch);
-		rk628_combrxphy_cfg_6730(combrxphy);
-	}
-	dev_dbg(combrxphy->dev, "step2 once per round ok!");
-
-	/*
-	 * step3:config sample edge until the end of one frame
-	 * (for example 1080p:2200*1125=32’h25c3f8)
-	 */
-	switch (f) {
-	case 27000:
-		edge = 858 * 525;
-		dc_gain = 0;
-		break;
-	case 64000:
-		edge = 1317 * 810;
-		dc_gain = 0;
-		break;
-	case 74250:
-		edge = 1650 * 750;
-		dc_gain = 0;
-		break;
-	case 148500:
-		edge = 2200 * 1125;
-		dc_gain = 1;
-		break;
-	case 297000:
-		dc_gain = 3;
-		edge = 4400 * 2250;
-		break;
-	case 594000:
-		dc_gain = 0xf;
-		edge = 4400 * 2250;
-		break;
-	default:
-		edge = 2200 * 1125;
-		dc_gain = 1;
-		break;
-	}
-	dev_dbg(combrxphy->dev, "===>>> f:%d, edge:%#x", f, edge);
-	for (ch = 0; ch < MAX_CHANNEL; ch++) {
-		rk628_combrxphy_select_channel(combrxphy, ch);
-		regmap_write(combrxphy->regmap, REG(0x6708), edge);
-	}
-	dev_dbg(combrxphy->dev, "step3 cfg sample edge ok!");
-
-	rk628_combrxphy_set_dc_gain(combrxphy, dc_gain, dc_gain, dc_gain);
-
-	for (n = rd_offset; n < (rd_offset + MAX_ROUND); n++) {
-		/* step4:set sample edge round value n,n=0(n=0~31) */
-		rk628_combrxphy_set_sample_edge_round(combrxphy, n, n, n);
-		dev_dbg(combrxphy->dev, "step4 ok!");
-		/* step5:start sample edge */
-		rk628_combrxphy_start_sample_edge(combrxphy);
-		dev_dbg(combrxphy->dev, "step5 ok!");
-		/* step6:waiting more than one frame time */
-		usleep_range(40*1000, 41*1000);
-		for (ch = 0; ch < MAX_CHANNEL; ch++) {
-			/* step7:get data of round n */
-			rk628_combrxphy_select_channel(combrxphy, ch);
-			dev_dbg(combrxphy->dev, "step7 set ch ok!");
-			rk628_combrxphy_get_data_of_round(combrxphy, data);
-			dev_dbg(combrxphy->dev, "step7 get data ok!");
-			rk628_combrxphy_set_data_of_round(data, data_in);
-			dev_dbg(combrxphy->dev, "step7 set data ok!");
-			rk628_combrxphy_max_zero_of_round(combrxphy, data_in,
-							  round_max_zero[ch],
-							  round_max_value[ch],
-							  n - rd_offset, ch);
-		}
-	}
-	for (ch = 0; ch < MAX_CHANNEL; ch++)
-		ch_round[ch] =
-			rk628_combrxphy_chose_round_for_ch(combrxphy,
-							   round_max_zero[ch],
-							   round_max_value[ch],
-							   ch) + rd_offset;
-
-	/*
-	 * step8:after finish round 31, get the max constant value and
-	 * corresponding value n.
-	 * write result to sample edge round value.
-	 */
-	rk628_combrxphy_set_sample_edge_round(combrxphy, ch_round[0],
-					      ch_round[1], ch_round[2]);
-
-	/* do step5, step6 again */
-	dev_dbg(combrxphy->dev, "do step5 step6 again!");
-	rk628_combrxphy_start_sample_edge(combrxphy);
-	usleep_range(40*1000, 41*1000);
-}
-
-static int rk628_combrxphy_try_clk_detect(struct rk628_combrxphy *combrxphy)
-{
-	u32 val, i;
-	int ret;
-
-	ret = -1;
-	reset_control_assert(combrxphy->rstc);
-	usleep_range(10, 20);
-	reset_control_deassert(combrxphy->rstc);
-	usleep_range(10, 20);
-
-	/* step1: set pin_rst_n to 1’b0.wait 1 period(1us).release reset */
-	/* step2: select pll clock src and enable auto check */
-	regmap_read(combrxphy->regmap, REG(0x6630), &val);
-	/* clear bit0 and bit3 */
-	val = val & 0xfffffff6;
-	regmap_write(combrxphy->regmap, REG(0x6630), val);
-	/* step3: select hdmi mode and enable chip, read reg6654,
-	 * make sure auto setup done.
-	 */
-	/* auto fsm reset related */
-	regmap_read(combrxphy->regmap, REG(0x6630), &val);
-	val = val | BIT(24);
-	regmap_write(combrxphy->regmap, REG(0x6630), val);
-	/* pull down ana rstn */
-	regmap_read(combrxphy->regmap, REG(0x66f0), &val);
-	val = val & 0xfffffeff;
-	regmap_write(combrxphy->regmap, REG(0x66f0), val);
-	/* pull down dig rstn */
-	regmap_read(combrxphy->regmap, REG(0x66f4), &val);
-	val = val & 0xfffffffe;
-	regmap_write(combrxphy->regmap, REG(0x66f4), val);
-	/* pull up ana rstn */
-	regmap_read(combrxphy->regmap, REG(0x66f0), &val);
-	val = val | 0x100;
-	regmap_write(combrxphy->regmap, REG(0x66f0), val);
-	/* pull up dig rstn */
-	regmap_read(combrxphy->regmap, REG(0x66f4), &val);
-	val = val  | 0x1;
-	regmap_write(combrxphy->regmap, REG(0x66f4), val);
-
-	regmap_read(combrxphy->regmap, REG(0x66f0), &val);
-	/* set bit0 and bit2 to 1*/
-	val = (val & 0xfffffff8) | 0x5;
-	regmap_write(combrxphy->regmap, REG(0x66f0), val);
-
-	/* auto fsm en = 0 */
-	regmap_read(combrxphy->regmap, REG(0x66f0), &val);
-	/* set bit0 and bit2 to 1*/
-	val = (val & 0xfffffff8) | 0x4;
-	regmap_write(combrxphy->regmap, REG(0x66f0), val);
-
-	for (i = 0; i < 10; i++) {
-		usleep_range(500, 510);
-		regmap_read(combrxphy->regmap, REG(0x6654), &val);
-		if ((val & 0xf0000000) == 0x80000000) {
-			ret = 0;
-			dev_info(combrxphy->dev, "clock detected!");
-			break;
-		}
-	}
-
-	return ret;
-}
-
-static int
-rk628_combrxphy_set_hdmi_mode_for_cable(struct rk628_combrxphy *combrxphy,
-					  int f)
-{
-	u32 val, val_a, val_b, data_a, data_b;
-	u32 i, j, count, ret;
-	u32 cdr_mode, cdr_data, pll_man;
-	u32 tmds_bitrate_per_lane;
-	u32 cdr_data_min, cdr_data_max;
-
-	/*
-	 * use the mode of automatic clock detection, only supports fixed TMDS
-	 * frequency.Refer to register 0x6654[21:16]:
-	 * 5'd31:Error mode
-	 * 5'd30:manual mode detected
-	 * 5'd18:rx3p clock = 297MHz
-	 * 5'd17:rx3p clock = 162MHz
-	 * 5'd16:rx3p clock = 148.5MHz
-	 * 5'd15:rx3p clock = 135MHz
-	 * 5'd14:rx3p clock = 119MHz
-	 * 5'd13:rx3p clock = 108MHz
-	 * 5'd12:rx3p clock = 101MHz
-	 * 5'd11:rx3p clock = 92.8125MHz
-	 * 5'd10:rx3p clock = 88.75MHz
-	 * 5'd9:rx3p clock  = 85.5MHz
-	 * 5'd8:rx3p clock  = 83.5MHz
-	 * 5'd7:rx3p clock  = 74.25MHz
-	 * 5'd6:rx3p clock  = 68.25MHz
-	 * 5'd5:rx3p clock  = 65MHz
-	 * 5'd4:rx3p clock  = 59.4MHz
-	 * 5'd3:rx3p clock  = 40MHz
-	 * 5'd2:rx3p clock  = 33.75MHz
-	 * 5'd1:rx3p clock  = 27MHz
-	 * 5'd0:rx3p clock  = 25.17MHz
-	 */
-
-	const u32 cdr_mode_to_khz[] = {
-		25170,   27000,  33750,  40000,  59400,  65000,  68250,
-		74250,   83500,  85500,  88750,  92812, 101000, 108000,
-		119000, 135000, 148500, 162000, 297000,
-	};
-
-	for (i = 0; i < CLK_DET_TRY_TIMES; i++) {
-		if (rk628_combrxphy_try_clk_detect(combrxphy) >= 0)
-			break;
-		usleep_range(100*1000, 100*1000);
-	}
-	regmap_read(combrxphy->regmap, REG(0x6654), &val);
-	dev_info(combrxphy->dev, "clk det over cnt:%d, reg_0x6654:%#x", i, val);
-
-	regmap_read(combrxphy->regmap, REG(0x6620), &val);
-	if ((i == CLK_DET_TRY_TIMES) ||
-		((val & 0x7f000000) == 0) ||
-		((val & 0x007f0000) == 0) ||
-		((val & 0x00007f00) == 0) ||
-		((val & 0x0000007f) == 0)) {
-		dev_info(combrxphy->dev,
-			"clock detected failed, cfg resistance manual!");
-		regmap_write(combrxphy->regmap, REG(0x6620), 0x66666666);
-		regmap_update_bits(combrxphy->regmap, REG(0x6604), BIT(31),
-				BIT(31));
-		usleep_range(1000, 1100);
-	}
-
-	/* step4: get cdr_mode and cdr_data */
-	for (j = 0; j < CLK_STABLE_LOOP_CNT ; j++) {
-		cdr_data_min = 0xffffffff;
-		cdr_data_max = 0;
-
-		for (i = 0; i < CLK_DET_TRY_TIMES; i++) {
-			regmap_read(combrxphy->regmap, REG(0x6654), &val);
-			cdr_data = val & 0xffff;
-			if (cdr_data <= cdr_data_min)
-				cdr_data_min = cdr_data;
-			if (cdr_data >= cdr_data_max)
-				cdr_data_max = cdr_data;
-			udelay(50);
-		}
-
-		if (((cdr_data_max - cdr_data_min) <= CLK_STABLE_THRESHOLD) &&
-				(cdr_data_min >= 60)) {
-			dev_info(combrxphy->dev, "clock stable!");
-			break;
-		}
-	}
-
-	if (j == CLK_STABLE_LOOP_CNT) {
-		regmap_read(combrxphy->regmap, REG(0x6630), &val_a);
-		regmap_read(combrxphy->regmap, REG(0x6608), &val_b);
-		dev_err(combrxphy->dev,
-			"err, clk not stable, reg_0x6630:%#x, reg_0x6608:%#x",
-			val_a, val_b);
-
-		return -EINVAL;
-	}
-
-	regmap_read(combrxphy->regmap, REG(0x6654), &val);
-	if ((val & 0x1f0000) == 0x1f0000) {
-		regmap_read(combrxphy->regmap, REG(0x6630), &val_a);
-		regmap_read(combrxphy->regmap, REG(0x6608), &val_b);
-		dev_err(combrxphy->dev,
-			"clock error: 0x1f, reg_0x6630:%#x, reg_0x6608:%#x",
-			val_a, val_b);
-
-		return -EINVAL;
-	}
-
-	cdr_mode = (val >> 16) & 0x1f;
-	cdr_data =  val & 0xffff;
-	dev_info(combrxphy->dev, "cdr_mode:%d, cdr_data:%d\n", cdr_mode,
-			cdr_data);
-
-	/* step5: manually configure PLL
-	 * cfg reg 66a8 tmds clock div2 for rgb/yuv444 as default
-	 * reg 662c[16:8] pll_pre_div
-	 */
-	if (f <= 340000) {
-		regmap_write(combrxphy->regmap, REG(0x662c), 0x01000500);
-		regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600);
-	} else {
-		regmap_write(combrxphy->regmap, REG(0x662c), 0x01001400);
-		regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600);
-	}
-
-	/* when tmds bitrate/lane <= 340M, bitrate/lane = pix_clk * 10 */
-	tmds_bitrate_per_lane = cdr_mode_to_khz[cdr_mode] * 10;
-	if (tmds_bitrate_per_lane < 400000)
-		pll_man = 0x7960c;
-	else if (tmds_bitrate_per_lane < 600000)
-		pll_man = 0x7750c;
-	else if (tmds_bitrate_per_lane < 800000)
-		pll_man = 0x7964c;
-	else if (tmds_bitrate_per_lane < 1000000)
-		pll_man = 0x7754c;
-	else if (tmds_bitrate_per_lane < 1600000)
-		pll_man = 0x7a108;
-	else if (tmds_bitrate_per_lane < 2400000)
-		pll_man = 0x73588;
-	else if (tmds_bitrate_per_lane < 3400000)
-		pll_man = 0x7a108;
-	else
-		pll_man = 0x7f0c8;
-
-	dev_info(combrxphy->dev, "cdr_mode:%d, pll_man:%#x\n", cdr_mode,
-			pll_man);
-	regmap_write(combrxphy->regmap, REG(0x6630), pll_man);
-
-	/* step6: EQ and SAMPLE cfg */
-	rk628_combrxphy_sample_edge_procedure_for_cable(combrxphy, cdr_mode);
-
-	/* step7: Deassert fifo reset,enable fifo write and read */
-	/* reset rx_infifo */
-	regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000003);
-	/* rx_infofo wr/rd disable */
-	regmap_write(combrxphy->regmap, REG(0x66b0), 0x00080060);
-	/* deassert rx_infifo reset */
-	regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000083);
-	/* enable rx_infofo wr/rd en */
-	regmap_write(combrxphy->regmap, REG(0x66b0), 0x00380060);
-	/* cfg 0x2260 high_8b to 0x66ac high_8b, low_8b to 0x66b0 low_8b */
-	regmap_update_bits(combrxphy->regmap, REG(0x66ac), GENMASK(31, 24),
-			UPDATE(0x22, 31, 24));
-	usleep_range(5*1000, 6*1000);
-
-	/* step8: check all 3 data channels alignment */
-	count = 0;
-	for (i = 0; i < 100; i++) {
-		usleep_range(100, 110);
-		regmap_read(combrxphy->regmap, REG(0x66b4), &data_a);
-		regmap_read(combrxphy->regmap, REG(0x66b8), &data_b);
-		/* ch0 ch1 ch2 lock */
-		if (((data_a & 0x00ff00ff) == 0x00ff00ff) &&
-			((data_b & 0xff) == 0xff)) {
-			count++;
-		}
-	}
-
-	if (count >= 100) {
-		dev_info(combrxphy->dev, "channel alignment done");
-		dev_info(combrxphy->dev, "rx initial done");
-		ret = 0;
-	} else if (count > 0) {
-		dev_err(combrxphy->dev, "link not stable, count:%d of 100",
-				count);
-		ret = 0;
-	} else {
-		dev_err(combrxphy->dev, "channel alignment failed!");
-		ret = -EINVAL;
-	}
-
-	return ret;
-}
-
-static int rk628_combrxphy_set_hdmi_mode(struct rk628_combrxphy *combrxphy,
-					 int bus_width)
-{
-	u32 val, data_a, data_b, f, val2 = 0;
-	int i, ret, count;
-	u32 pll_man, rd_offset;
-	bool is_yuv420;
-
-	is_yuv420 = bus_width & BIT(30);
-
-	if (is_yuv420)
-		f = (bus_width & 0xffffff) / 2;
-	else
-		f = bus_width & 0xffffff;
-
-	dev_dbg(combrxphy->dev, "f:%d\n", f);
-
-	regmap_read(combrxphy->regmap, REG(0x6630), &val);
-	val &= ~BIT(23);
-	val |= 0x18;
-	regmap_write(combrxphy->regmap, REG(0x6630), val);
-
-	/* enable cal */
-	regmap_read(combrxphy->regmap, REG(0x6610), &val);
-	val |= 0x18000000;
-	regmap_write(combrxphy->regmap, REG(0x6610), val);
-
-	usleep_range(10*1000, 11*1000);
-	/* disable cal */
-	val &= ~BIT(28);
-	val |= BIT(27);
-	regmap_write(combrxphy->regmap, REG(0x6610), val);
-
-	/* save cal val */
-	regmap_read(combrxphy->regmap, REG(0x6614), &val);
-	if (!(val & 0x3f00)) {
-		dev_err(combrxphy->dev, "resistor error\n");
-		return -EINVAL;
-	}
-
-	val &= 0x3f00;
-	val = val >> 8;
-	val2 |= 0x40404040;
-	val2 |= val << 24 | val << 16 | val << 8 | val;
-
-	/* rtm inc */
-	regmap_read(combrxphy->regmap, REG(0x6604), &val);
-	val |= BIT(31);
-	regmap_write(combrxphy->regmap, REG(0x6604), val);
-
-	regmap_write(combrxphy->regmap, REG(0x6620), val2);
-
-	/* rtm en bypass */
-	regmap_read(combrxphy->regmap, REG(0x6600), &val);
-	val |= BIT(7);
-	regmap_write(combrxphy->regmap, REG(0x6600), val);
-
-	/* rtm prot en bypass */
-	regmap_read(combrxphy->regmap, REG(0x6610), &val);
-	val |= 0x80f000;
-	regmap_write(combrxphy->regmap, REG(0x6610), val);
-
-	regmap_read(combrxphy->regmap, REG(0x661c), &val);
-	val |= 0x81000000;
-	regmap_write(combrxphy->regmap, REG(0x661c), val);
-
-	/* enable pll */
-	regmap_read(combrxphy->regmap, REG(0x6630), &val);
-	val &= ~BIT(4);
-	val |= BIT(3);
-	regmap_write(combrxphy->regmap, REG(0x6630), val);
-
-	/* equ en */
-	regmap_read(combrxphy->regmap, REG(0x6618), &val);
-	val |= BIT(4);
-	regmap_write(combrxphy->regmap, REG(0x6618), val);
-
-	regmap_read(combrxphy->regmap, REG(0x6614), &val);
-	val |= 0x10900000;
-	regmap_write(combrxphy->regmap, REG(0x6614), val);
-
-	regmap_read(combrxphy->regmap, REG(0x6610), &val);
-	val |= 0xf00;
-	regmap_write(combrxphy->regmap, REG(0x6610), val);
-
-	regmap_read(combrxphy->regmap, REG(0x6630), &val);
-	val |= 0x870000;
-	regmap_write(combrxphy->regmap, REG(0x6630), val);
-
-	udelay(10);
-
-	/* get cdr_mode,make sure cdr_mode != 5’h1f */
-	regmap_read(combrxphy->regmap, REG(0x6654), &val);
-	if ((val & 0x1f0000) == 0x1f0000)
-		dev_err(combrxphy->dev, "error,clock error!");
-
-	/* manually configure PLL */
-	if (f <= 340000) {
-		regmap_write(combrxphy->regmap, REG(0x662c), 0x01000500);
-		if (is_yuv420)
-			regmap_write(combrxphy->regmap, REG(0x66a8),
-				     0x0000c000);
-		else
-			regmap_write(combrxphy->regmap, REG(0x66a8),
-				     0x0000c600);
-	} else {
-		regmap_write(combrxphy->regmap, REG(0x662c), 0x01001400);
-		regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600);
-	}
-
-	switch (f) {
-	case 27000:
-	case 64000:
-	case 74250:
-		rd_offset = 0;
-		pll_man = 0x7964c;
-		break;
-	case 148500:
-		pll_man = 0x7a1c8;
-		rd_offset = 0;
-		break;
-	case 297000:
-		pll_man = 0x7a108;
-		rd_offset = 2;
-		break;
-	case 594000:
-		pll_man = 0x7f0c8;
-		rd_offset = 4;
-		break;
-	default:
-		pll_man = 0x7964c;
-		rd_offset = 1;
-		break;
-	}
-
-	pll_man  |= BIT(23);
-	regmap_write(combrxphy->regmap, REG(0x6630), pll_man);
-
-	/* EQ and SAMPLE cfg */
-	rk628_combrxphy_sample_edge_procedure(combrxphy, f, rd_offset);
-
-	/* Deassert fifo reset,enable fifo write and read */
-	regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000003);
-	regmap_write(combrxphy->regmap, REG(0x66b0), 0x00080060);
-	regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000083);
-	regmap_write(combrxphy->regmap, REG(0x66b0), 0x00380060);
-	regmap_update_bits(combrxphy->regmap, REG(0x66ac), GENMASK(31, 24),
-			   UPDATE(0x22, 31, 24));
-	usleep_range(10*1000, 11*1000);
-
-	/* check all 3 data channels alignment */
-	count = 0;
-	for (i = 0; i < 100; i++) {
-		udelay(100);
-		regmap_read(combrxphy->regmap, REG(0x66b4), &data_a);
-		regmap_read(combrxphy->regmap, REG(0x66b8), &data_b);
-		/* ch0 ch1 ch2 lock */
-		if (((data_a & 0x00ff00ff) == 0x00ff00ff) &&
-		    ((data_b & 0xff) == 0xff))
-			count++;
-	}
-
-	if (count >= 100) {
-		dev_info(combrxphy->dev, "channel alignment done");
-		ret = 0;
-	} else if (count > 0) {
-		dev_err(combrxphy->dev, "not stable, count:%d of 100", count);
-		ret = -EINVAL;
-	} else {
-		dev_err(combrxphy->dev, "channel alignment failed!");
-		ret = -EINVAL;
-	}
-
-	return ret;
-}
-
-static int rk628_combrxphy_power_on(struct phy *phy)
-{
-	struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy);
-	int f = phy_get_bus_width(phy);
-	int ret;
-
-	/* Bit31 is used to distinguish HDMI cable mode and direct
-	 * connection mode.
-	 * Bit31: 0 -direct connection mode;
-	 *        1 -cable mode;
-	 */
-	combrxphy->is_cable_mode = (f & BIT(31)) ? true : false;
-	dev_dbg(combrxphy->dev, "%s\n", __func__);
-	clk_prepare_enable(combrxphy->pclk);
-	reset_control_assert(combrxphy->rstc);
-	udelay(10);
-	reset_control_deassert(combrxphy->rstc);
-	udelay(10);
-
-	if (combrxphy->is_cable_mode) {
-		f = f & 0x7fffffff;
-		ret = rk628_combrxphy_set_hdmi_mode_for_cable(combrxphy, f);
-	} else {
-		ret = rk628_combrxphy_set_hdmi_mode(combrxphy, f);
-	}
-
-	return ret;
-}
-
-static int rk628_combrxphy_power_off(struct phy *phy)
-{
-	struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy);
-
-	dev_dbg(combrxphy->dev, "%s\n", __func__);
-	reset_control_assert(combrxphy->rstc);
-	udelay(10);
-	clk_disable_unprepare(combrxphy->pclk);
-
-	return 0;
-}
-
-static const struct phy_ops rk628_combrxphy_ops = {
-	.power_on = rk628_combrxphy_power_on,
-	.power_off = rk628_combrxphy_power_off,
-	.owner = THIS_MODULE,
-};
-
-static const struct regmap_range rk628_combrxphy_readable_ranges[] = {
-	regmap_reg_range(REG(0x6600), REG(0x665b)),
-	regmap_reg_range(REG(0x66a0), REG(0x66db)),
-	regmap_reg_range(REG(0x66f0), REG(0x66ff)),
-	regmap_reg_range(REG(0x6700), REG(0x6790)),
-};
-
-static const struct regmap_access_table rk628_combrxphy_readable_table = {
-	.yes_ranges     = rk628_combrxphy_readable_ranges,
-	.n_yes_ranges   = ARRAY_SIZE(rk628_combrxphy_readable_ranges),
-};
-
-static const struct regmap_config rk628_combrxphy_regmap_cfg = {
-	.name = "combrxphy",
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = 4,
-	.max_register = COMBRXPHY_MAX_REGISTER,
-	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
-	.val_format_endian = REGMAP_ENDIAN_LITTLE,
-	.rd_table = &rk628_combrxphy_readable_table,
-};
-
-static int rk628_combrxphy_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_combrxphy *combrxphy;
-	struct phy_provider *phy_provider;
-	struct phy *phy;
-	int ret;
-
-	if (!of_device_is_available(dev->of_node))
-		return -ENODEV;
-
-	combrxphy = devm_kzalloc(dev, sizeof(*combrxphy), GFP_KERNEL);
-	if (!combrxphy)
-		return -ENOMEM;
-
-	combrxphy->dev = dev;
-	combrxphy->parent = rk628;
-	platform_set_drvdata(pdev, combrxphy);
-
-	combrxphy->pclk = devm_clk_get(dev, "pclk");
-	if (IS_ERR(combrxphy->pclk)) {
-		ret = PTR_ERR(combrxphy->pclk);
-		dev_err(dev, "failed to get pclk: %d\n", ret);
-		return ret;
-	}
-
-	combrxphy->rstc = of_reset_control_get(dev->of_node, NULL);
-	if (IS_ERR(combrxphy->rstc)) {
-		ret = PTR_ERR(combrxphy->rstc);
-		dev_err(dev, "failed to get reset control: %d\n", ret);
-		return ret;
-	}
-
-	combrxphy->regmap = devm_regmap_init_i2c(rk628->client,
-						 &rk628_combrxphy_regmap_cfg);
-	if (IS_ERR(combrxphy->regmap)) {
-		ret = PTR_ERR(combrxphy->regmap);
-		dev_err(dev, "failed to allocate host register map: %d\n", ret);
-		return ret;
-	}
-
-	phy = devm_phy_create(dev, NULL, &rk628_combrxphy_ops);
-	if (IS_ERR(phy)) {
-		ret = PTR_ERR(phy);
-		dev_err(dev, "failed to create phy: %d\n", ret);
-		return ret;
-	}
-
-	phy_set_drvdata(phy, combrxphy);
-
-	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	if (IS_ERR(phy_provider)) {
-		ret = PTR_ERR(phy_provider);
-		dev_err(dev, "failed to register phy provider: %d\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static const struct of_device_id rk628_combrxphy_of_match[] = {
-	{ .compatible = "rockchip,rk628-combrxphy", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, rk628_combrxphy_of_match);
-
-static struct platform_driver rk628_combrxphy_driver = {
-	.driver = {
-		.name = "rk628-combrxphy",
-		.of_match_table	= of_match_ptr(rk628_combrxphy_of_match),
-	},
-	.probe = rk628_combrxphy_probe,
-};
-module_platform_driver(rk628_combrxphy_driver);
-
-MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 HDMI Combo RX PHY driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c b/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c
deleted file mode 100644
index cbe7923139b7..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c
+++ /dev/null
@@ -1,520 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Wyon Bi <bivvy.bi@rock-chips.com>
- */
-
-#include <asm/bitsperlong.h>
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/reset.h>
-#include <linux/mfd/rk628.h>
-
-#include "rk628_combtxphy.h"
-
-#define REG(x)			((x) + 0x90000)
-
-#define COMBTXPHY_CON0		REG(0x0000)
-#define SW_TX_IDLE_MASK		GENMASK(29, 20)
-#define SW_TX_IDLE(x)		UPDATE(x, 29, 20)
-#define SW_TX_PD_MASK		GENMASK(17, 8)
-#define SW_TX_PD(x)		UPDATE(x, 17, 8)
-#define SW_BUS_WIDTH_MASK	GENMASK(6, 5)
-#define SW_BUS_WIDTH_7BIT	UPDATE(0x3, 6, 5)
-#define SW_BUS_WIDTH_8BIT	UPDATE(0x2, 6, 5)
-#define SW_BUS_WIDTH_9BIT	UPDATE(0x1, 6, 5)
-#define SW_BUS_WIDTH_10BIT	UPDATE(0x0, 6, 5)
-#define SW_PD_PLL_MASK		BIT(4)
-#define SW_PD_PLL		BIT(4)
-#define SW_GVI_LVDS_EN_MASK	BIT(3)
-#define SW_GVI_LVDS_EN		BIT(3)
-#define SW_MIPI_DSI_EN_MASK	BIT(2)
-#define SW_MIPI_DSI_EN		BIT(2)
-#define SW_MODULEB_EN_MASK	BIT(1)
-#define SW_MODULEB_EN		BIT(1)
-#define SW_MODULEA_EN_MASK	BIT(0)
-#define SW_MODULEA_EN		BIT(0)
-#define COMBTXPHY_CON1		REG(0x0004)
-#define COMBTXPHY_CON2		REG(0x0008)
-#define COMBTXPHY_CON3		REG(0x000c)
-#define COMBTXPHY_CON4		REG(0x0010)
-#define COMBTXPHY_CON5		REG(0x0014)
-#define SW_RATE(x)		UPDATE(x, 26, 24)
-#define SW_REF_DIV(x)		UPDATE(x, 20, 16)
-#define SW_PLL_FB_DIV(x)	UPDATE(x, 14, 10)
-#define SW_PLL_FRAC_DIV(x)	UPDATE(x, 9, 0)
-#define COMBTXPHY_CON6		REG(0x0018)
-#define COMBTXPHY_CON7		REG(0x001c)
-#define SW_TX_RTERM_MASK	GENMASK(22, 20)
-#define SW_TX_RTERM(x)		UPDATE(x, 22, 20)
-#define SW_TX_MODE_MASK		GENMASK(17, 16)
-#define SW_TX_MODE(x)		UPDATE(x, 17, 16)
-#define SW_TX_CTL_CON5_MASK	BIT(10)
-#define SW_TX_CTL_CON5(x)	UPDATE(x, 10, 10)
-#define SW_TX_CTL_CON4_MASK	GENMASK(9, 8)
-#define SW_TX_CTL_CON4(x)	UPDATE(x, 9, 8)
-#define BYPASS_095V_LDO_MASK	BIT(3)
-#define BYPASS_095V_LDO(x)	UPDATE(x, 3, 3)
-#define TX_COM_VOLT_ADJ_MASK	GENMASK(2, 0)
-#define TX_COM_VOLT_ADJ(x)	UPDATE(x, 2, 0)
-#define COMBTXPHY_CON8		REG(0x0020)
-#define COMBTXPHY_CON9		REG(0x0024)
-#define SW_DSI_FSET_EN_MASK	BIT(29)
-#define SW_DSI_FSET_EN		BIT(29)
-#define SW_DSI_RCAL_EN_MASK	BIT(28)
-#define SW_DSI_RCAL_EN		BIT(28)
-#define COMBTXPHY_CON10		REG(0x0028)
-#define TX9_CKDRV_EN		BIT(9)
-#define TX8_CKDRV_EN		BIT(8)
-#define TX7_CKDRV_EN		BIT(7)
-#define TX6_CKDRV_EN		BIT(6)
-#define TX5_CKDRV_EN		BIT(5)
-#define TX4_CKDRV_EN		BIT(4)
-#define TX3_CKDRV_EN		BIT(3)
-#define TX2_CKDRV_EN		BIT(2)
-#define TX1_CKDRV_EN		BIT(1)
-#define TX0_CKDRV_EN		BIT(0)
-#define COMBTXPHY_MAX_REGISTER	COMBTXPHY_CON10
-
-struct rk628_combtxphy {
-	struct device *dev;
-	struct rk628 *parent;
-	struct regmap *grf;
-	struct regmap *regmap;
-	struct clk *pclk;
-	struct clk *ref_clk;
-	struct reset_control *rstc;
-	unsigned int flags;
-
-	u16 frac_div;
-	u8 ref_div;
-	u8 fb_div;
-	u8 rate_div;
-	u8 division_mode;
-};
-
-static int rk628_combtxphy_dsi_power_on(struct rk628_combtxphy *combtxphy)
-{
-	u32 val;
-	int ret;
-
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
-			   SW_MIPI_DSI_EN_MASK,
-			   SW_BUS_WIDTH_8BIT | SW_MIPI_DSI_EN);
-
-	if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
-		regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-				   SW_MODULEA_EN_MASK, SW_MODULEA_EN);
-	if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
-		regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-				   SW_MODULEB_EN_MASK, SW_MODULEB_EN);
-
-	regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
-		     SW_REF_DIV(combtxphy->ref_div - 1) |
-		     SW_PLL_FB_DIV(combtxphy->fb_div) |
-		     SW_PLL_FRAC_DIV(combtxphy->frac_div) |
-		     SW_RATE(combtxphy->rate_div / 2));
-
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_PD_PLL, 0);
-
-	ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS,
-				       val, val & DPHY_PHYLOCK, 0, 1000);
-	if (ret < 0) {
-		dev_err(combtxphy->dev, "phy is not lock\n");
-		return ret;
-	}
-
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON9,
-			   SW_DSI_FSET_EN_MASK | SW_DSI_RCAL_EN_MASK,
-			   SW_DSI_FSET_EN | SW_DSI_RCAL_EN);
-
-	usleep_range(200, 400);
-
-	return 0;
-}
-
-static int rk628_combtxphy_lvds_power_on(struct rk628_combtxphy *combtxphy)
-{
-	u32 val;
-	int ret;
-
-	/* Adjust terminal resistance 133 ohm, bypass 0.95v ldo for driver. */
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON7,
-			   SW_TX_RTERM_MASK | SW_TX_MODE_MASK |
-			   BYPASS_095V_LDO_MASK | TX_COM_VOLT_ADJ_MASK,
-			   SW_TX_RTERM(6) | SW_TX_MODE(3) |
-			   BYPASS_095V_LDO(1) | TX_COM_VOLT_ADJ(0));
-
-	regmap_write(combtxphy->regmap, COMBTXPHY_CON10,
-		     TX7_CKDRV_EN | TX2_CKDRV_EN);
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
-			   SW_MIPI_DSI_EN_MASK,
-			   SW_BUS_WIDTH_7BIT | SW_GVI_LVDS_EN);
-
-	if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
-		regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-				   SW_MODULEA_EN_MASK, SW_MODULEA_EN);
-	if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
-		regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-				   SW_MODULEB_EN_MASK, SW_MODULEB_EN);
-
-	regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
-		     SW_REF_DIV(combtxphy->ref_div - 1) |
-		     SW_PLL_FB_DIV(combtxphy->fb_div) |
-		     SW_PLL_FRAC_DIV(combtxphy->frac_div) |
-		     SW_RATE(combtxphy->rate_div / 2));
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_PD_PLL, 0);
-
-	ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS,
-				       val, val & DPHY_PHYLOCK, 0, 1000);
-	if (ret < 0) {
-		dev_info(combtxphy->dev, "phy is not lock\n");
-		return ret;
-	}
-
-	usleep_range(100, 200);
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_TX_IDLE_MASK | SW_TX_PD_MASK, 0);
-
-	return 0;
-}
-
-static int rk628_combtxphy_gvi_power_on(struct rk628_combtxphy *combtxphy)
-{
-	int ref_div = 0;
-
-	if (combtxphy->ref_div % 2) {
-		ref_div = combtxphy->ref_div - 1;
-	} else {
-		ref_div = BIT(4);
-		ref_div |= combtxphy->ref_div / 2 - 1;
-	}
-	regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
-		     SW_REF_DIV(ref_div) |
-		     SW_PLL_FB_DIV(combtxphy->fb_div) |
-		     SW_PLL_FRAC_DIV(combtxphy->frac_div) |
-		     SW_RATE(combtxphy->rate_div / 2));
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
-			   SW_MIPI_DSI_EN_MASK |
-			   SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
-			   SW_BUS_WIDTH_10BIT | SW_GVI_LVDS_EN |
-			   SW_MODULEB_EN | SW_MODULEA_EN);
-
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_PD_PLL | SW_TX_PD_MASK, 0);
-	usleep_range(100, 200);
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_TX_IDLE_MASK, 0);
-
-	return 0;
-}
-
-int rk628_combtxphy_set_gvi_division_mode(struct phy *phy, u8 mode)
-{
-	struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
-
-	combtxphy->division_mode = mode;
-
-	return 0;
-}
-EXPORT_SYMBOL(rk628_combtxphy_set_gvi_division_mode);
-
-static int rk628_combtxphy_power_on(struct phy *phy)
-{
-	struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
-	enum phy_mode mode = phy_get_mode(phy);
-
-	clk_prepare_enable(combtxphy->pclk);
-	reset_control_assert(combtxphy->rstc);
-	udelay(10);
-	reset_control_deassert(combtxphy->rstc);
-	udelay(10);
-
-	regcache_mark_dirty(combtxphy->regmap);
-	regcache_sync(combtxphy->regmap);
-
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK,
-			   SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
-
-	switch (mode) {
-	case PHY_MODE_MIPI_DPHY:
-		regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
-				   SW_TXPHY_REFCLK_SEL_MASK,
-				   SW_TXPHY_REFCLK_SEL(0));
-		return rk628_combtxphy_dsi_power_on(combtxphy);
-	case PHY_MODE_LVDS:
-		regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
-				   SW_TXPHY_REFCLK_SEL_MASK,
-				   SW_TXPHY_REFCLK_SEL(1));
-		return rk628_combtxphy_lvds_power_on(combtxphy);
-	default:
-		regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
-				   SW_TXPHY_REFCLK_SEL_MASK,
-				   SW_TXPHY_REFCLK_SEL(2));
-		return rk628_combtxphy_gvi_power_on(combtxphy);
-	}
-
-	return 0;
-}
-
-static int rk628_combtxphy_power_off(struct phy *phy)
-{
-	struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
-
-	regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
-			   SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK |
-			   SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
-			   SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
-
-	clk_disable_unprepare(combtxphy->pclk);
-
-	return 0;
-}
-
-static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode,
-				    int submode)
-{
-	struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
-	unsigned int bus_width = phy_get_bus_width(phy);
-	unsigned int frac_rate, fin = 24;
-	unsigned long fvco, fpfd;
-
-	switch (mode) {
-	case PHY_MODE_MIPI_DPHY:
-	{
-		unsigned int fhsc = bus_width >> 8;
-		unsigned int flags = bus_width & 0xff;
-
-		fhsc = fin * (fhsc / fin);
-
-		if (fhsc < 80 || fhsc > 1500)
-			return -EINVAL;
-		else if (fhsc < 375)
-			combtxphy->rate_div = 4;
-		else if (fhsc < 750)
-			combtxphy->rate_div = 2;
-		else
-			combtxphy->rate_div = 1;
-
-		combtxphy->flags = flags;
-
-		fvco = fhsc * 2 * combtxphy->rate_div;
-		combtxphy->ref_div = 1;
-		combtxphy->fb_div = fvco / 8 / fin;
-		frac_rate = fvco - (fin * 8 * combtxphy->fb_div);
-
-		if (frac_rate) {
-			frac_rate <<= 10;
-			frac_rate /= fin * 8;
-			combtxphy->frac_div = frac_rate;
-		} else {
-			combtxphy->frac_div = 0;
-		}
-
-		fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div);
-		fvco *= 8;
-		fvco = DIV_ROUND_UP(fvco, 1024 * combtxphy->ref_div);
-		fhsc = fvco / 2 / combtxphy->rate_div;
-		phy_set_bus_width(phy, fhsc);
-		break;
-	}
-	case PHY_MODE_LVDS:
-	{
-		unsigned int flags = bus_width & 0xff;
-		unsigned int rate = (bus_width >> 8) * 7;
-
-		combtxphy->flags = flags;
-		combtxphy->ref_div = 1;
-		combtxphy->fb_div = 14;
-		combtxphy->frac_div = 0;
-
-		if (rate < 500)
-			combtxphy->rate_div = 4;
-		else if (rate < 1000)
-			combtxphy->rate_div = 2;
-		else
-			combtxphy->rate_div = 1;
-		break;
-	}
-	default:
-	{
-		unsigned int i, delta_freq, best_delta_freq, fb_div;
-		unsigned long ref_clk;
-		unsigned long long pre_clk;
-
-		if (bus_width < 500000 || bus_width > 4000000)
-			return -EINVAL;
-		else if (bus_width < 1000000)
-			combtxphy->rate_div = 4;
-		else if (bus_width < 2000000)
-			combtxphy->rate_div = 2;
-		else
-			combtxphy->rate_div = 1;
-		fvco = bus_width * combtxphy->rate_div;
-		ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */
-		if (combtxphy->division_mode)
-			ref_clk /= 2;
-
-		if (!ref_clk)
-			return -EINVAL;
-
-		/*
-		 * the reference clock at PFD(FPFD = ref_clk / ref_div) about
-		 * 25MHz is recommende, FPFD must range from 16MHz to 35MHz,
-		 * here to find the best rev_div.
-		 */
-		best_delta_freq = ref_clk;
-		for (i = 1; i <= 32; i++) {
-			fpfd = ref_clk / i;
-			delta_freq = abs(fpfd - 25000);
-			if (delta_freq < best_delta_freq) {
-				best_delta_freq = delta_freq;
-				combtxphy->ref_div = i;
-			}
-		}
-
-		/*
-		 * ref_clk / ref_div * 8 * fb_div = FVCO
-		 */
-		pre_clk = (unsigned long long)fvco / 8 * combtxphy->ref_div * 1024;
-		do_div(pre_clk, ref_clk);
-		fb_div = pre_clk / 1024;
-
-		/*
-		 * get the actually frequence
-		 */
-		bus_width = ref_clk / combtxphy->ref_div * 8;
-		bus_width *= fb_div;
-		bus_width /= combtxphy->rate_div;
-
-		combtxphy->frac_div = 0;
-		combtxphy->fb_div = fb_div;
-
-		phy_set_bus_width(phy, bus_width);
-		break;
-	}
-	}
-
-	return 0;
-}
-
-static const struct phy_ops rk628_combtxphy_ops = {
-	.set_mode = rk628_combtxphy_set_mode,
-	.power_on = rk628_combtxphy_power_on,
-	.power_off = rk628_combtxphy_power_off,
-	.owner = THIS_MODULE,
-};
-
-static const struct regmap_range rk628_combtxphy_readable_ranges[] = {
-	regmap_reg_range(COMBTXPHY_CON0, COMBTXPHY_CON10),
-};
-
-static const struct regmap_access_table rk628_combtxphy_readable_table = {
-	.yes_ranges     = rk628_combtxphy_readable_ranges,
-	.n_yes_ranges   = ARRAY_SIZE(rk628_combtxphy_readable_ranges),
-};
-
-static const struct regmap_config rk628_combtxphy_regmap_cfg = {
-	.name = "combtxphy",
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = 4,
-	.cache_type = REGCACHE_RBTREE,
-	.max_register = COMBTXPHY_MAX_REGISTER,
-	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
-	.val_format_endian = REGMAP_ENDIAN_LITTLE,
-	.rd_table = &rk628_combtxphy_readable_table,
-};
-
-static int rk628_combtxphy_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_combtxphy *combtxphy;
-	struct phy_provider *phy_provider;
-	struct phy *phy;
-	int ret;
-
-	combtxphy = devm_kzalloc(dev, sizeof(*combtxphy), GFP_KERNEL);
-	if (!combtxphy)
-		return -ENOMEM;
-
-	combtxphy->dev = dev;
-	combtxphy->parent = rk628;
-	combtxphy->grf = rk628->grf;
-	platform_set_drvdata(pdev, combtxphy);
-
-	combtxphy->pclk = devm_clk_get(dev, "pclk");
-	if (IS_ERR(combtxphy->pclk))
-		return PTR_ERR(combtxphy->pclk);
-
-	combtxphy->ref_clk = devm_clk_get(dev, "ref_clk");
-	if (IS_ERR(combtxphy->ref_clk)) {
-		dev_err(dev, "fail to get ref clk\n");
-		return PTR_ERR(combtxphy->ref_clk);
-	}
-
-	combtxphy->rstc = of_reset_control_get(dev->of_node, NULL);
-	if (IS_ERR(combtxphy->rstc)) {
-		ret = PTR_ERR(combtxphy->rstc);
-		dev_err(dev, "failed to get reset control: %d\n", ret);
-		return ret;
-	}
-
-	combtxphy->regmap = devm_regmap_init_i2c(rk628->client,
-						 &rk628_combtxphy_regmap_cfg);
-	if (IS_ERR(combtxphy->regmap)) {
-		ret = PTR_ERR(combtxphy->regmap);
-		dev_err(dev, "failed to allocate register map: %d\n", ret);
-		return ret;
-	}
-
-	phy = devm_phy_create(dev, NULL, &rk628_combtxphy_ops);
-	if (IS_ERR(phy)) {
-		ret = PTR_ERR(phy);
-		dev_err(dev, "failed to create phy: %d\n", ret);
-		return ret;
-	}
-
-	phy_set_drvdata(phy, combtxphy);
-
-	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	if (IS_ERR(phy_provider)) {
-		ret = PTR_ERR(phy_provider);
-		dev_err(dev, "failed to register phy provider: %d\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static const struct of_device_id rk628_combtxphy_of_match[] = {
-	{ .compatible = "rockchip,rk628-combtxphy", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, rk628_combtxphy_of_match);
-
-static struct platform_driver rk628_combtxphy_driver = {
-	.driver = {
-		.name = "rk628-combtxphy",
-		.of_match_table	= of_match_ptr(rk628_combtxphy_of_match),
-	},
-	.probe = rk628_combtxphy_probe,
-};
-module_platform_driver(rk628_combtxphy_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 GVI/LVDS/MIPI Combo TX PHY driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.h b/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.h
deleted file mode 100644
index 40d785eecd67..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- */
-
-#ifndef RK628_COMBTXPHY_H_
-#define RK628_COMBTXPHY_H_
-
-#include <linux/phy/phy.h>
-
-int rk628_combtxphy_set_gvi_division_mode(struct phy *phy, u8 mode);
-
-#endif
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_dsi.c b/drivers/gpu/drm/rockchip/rk628/rk628_dsi.c
deleted file mode 100644
index 766f156efb98..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_dsi.c
+++ /dev/null
@@ -1,1395 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Wyon Bi <bivvy.bi@rock-chips.com>
- */
-
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/regmap.h>
-#include <linux/mfd/rk628.h>
-#include <linux/reset.h>
-#include <linux/phy/phy.h>
-
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_mipi_dsi.h>
-#include <drm/drm_of.h>
-#include <drm/drm_panel.h>
-
-#include <video/of_display_timing.h>
-#include <video/mipi_display.h>
-#include <video/videomode.h>
-#include <asm/unaligned.h>
-
-#define DSI_VERSION			0x0000
-#define DSI_PWR_UP			0x0004
-#define RESET				0
-#define POWER_UP			BIT(0)
-#define DSI_CLKMGR_CFG			0x0008
-#define TO_CLK_DIVISION(x)		UPDATE(x, 15,  8)
-#define TX_ESC_CLK_DIVISION(x)		UPDATE(x,  7,  0)
-#define DSI_DPI_VCID			0x000c
-#define DPI_VID(x)			UPDATE(x,  1,  0)
-#define DSI_DPI_COLOR_CODING		0x0010
-#define LOOSELY18_EN			BIT(8)
-#define DPI_COLOR_CODING(x)		UPDATE(x,  3,  0)
-#define DSI_DPI_CFG_POL			0x0014
-#define COLORM_ACTIVE_LOW		BIT(4)
-#define SHUTD_ACTIVE_LOW		BIT(3)
-#define HSYNC_ACTIVE_LOW		BIT(2)
-#define VSYNC_ACTIVE_LOW		BIT(1)
-#define DATAEN_ACTIVE_LOW		BIT(0)
-#define DSI_DPI_LP_CMD_TIM		0x0018
-#define OUTVACT_LPCMD_TIME(x)		UPDATE(x, 23, 16)
-#define INVACT_LPCMD_TIME(x)		UPDATE(x,  7,  0)
-#define DSI_PCKHDL_CFG			0x002c
-#define CRC_RX_EN			BIT(4)
-#define ECC_RX_EN			BIT(3)
-#define BTA_EN				BIT(2)
-#define EOTP_RX_EN			BIT(1)
-#define EOTP_TX_EN			BIT(0)
-#define DSI_GEN_VCID			0x0030
-#define DSI_MODE_CFG			0x0034
-#define CMD_VIDEO_MODE(x)		UPDATE(x,  0,  0)
-#define DSI_VID_MODE_CFG		0x0038
-#define VPG_EN				BIT(16)
-#define LP_CMD_EN			BIT(15)
-#define FRAME_BTA_ACK_EN		BIT(14)
-#define LP_HFP_EN			BIT(13)
-#define LP_HBP_EN			BIT(12)
-#define LP_VACT_EN			BIT(11)
-#define LP_VFP_EN			BIT(10)
-#define LP_VBP_EN			BIT(9)
-#define LP_VSA_EN			BIT(8)
-#define VID_MODE_TYPE(x)		UPDATE(x,  1,  0)
-#define DSI_VID_PKT_SIZE		0x003c
-#define VID_PKT_SIZE(x)			UPDATE(x, 13,  0)
-#define DSI_VID_NUM_CHUNKS		0x0040
-#define DSI_VID_NULL_SIZE		0x0044
-#define DSI_VID_HSA_TIME		0x0048
-#define VID_HSA_TIME(x)			UPDATE(x, 11,  0)
-#define DSI_VID_HBP_TIME		0x004c
-#define VID_HBP_TIME(x)			UPDATE(x, 11,  0)
-#define DSI_VID_HLINE_TIME		0x0050
-#define VID_HLINE_TIME(x)		UPDATE(x, 14,  0)
-#define DSI_VID_VSA_LINES		0x0054
-#define VSA_LINES(x)			UPDATE(x,  9,  0)
-#define DSI_VID_VBP_LINES		0x0058
-#define VBP_LINES(x)			UPDATE(x,  9,  0)
-#define DSI_VID_VFP_LINES		0x005c
-#define VFP_LINES(x)			UPDATE(x,  9,  0)
-#define DSI_VID_VACTIVE_LINES		0x0060
-#define V_ACTIVE_LINES(x)		UPDATE(x, 13,  0)
-#define DSI_EDPI_CMD_SIZE		0x0064
-#define EDPI_ALLOWED_CMD_SIZE(x)	UPDATE(x, 15,  0)
-#define DSI_CMD_MODE_CFG		0x0068
-#define MAX_RD_PKT_SIZE			BIT(24)
-#define DCS_LW_TX			BIT(19)
-#define DCS_SR_0P_TX			BIT(18)
-#define DCS_SW_1P_TX			BIT(17)
-#define DCS_SW_0P_TX			BIT(16)
-#define GEN_LW_TX			BIT(14)
-#define GEN_SR_2P_TX			BIT(13)
-#define GEN_SR_1P_TX			BIT(12)
-#define GEN_SR_0P_TX			BIT(11)
-#define GEN_SW_2P_TX			BIT(10)
-#define GEN_SW_1P_TX			BIT(9)
-#define GEN_SW_0P_TX			BIT(8)
-#define ACK_RQST_EN			BIT(1)
-#define TEAR_FX_EN			BIT(0)
-#define DSI_GEN_HDR			0x006c
-#define GEN_WC_MSBYTE(x)		UPDATE(x, 23, 16)
-#define GEN_WC_LSBYTE(x)		UPDATE(x, 15,  8)
-#define GEN_VC(x)			UPDATE(x,  7,  6)
-#define GEN_DT(x)			UPDATE(x,  5,  0)
-#define DSI_GEN_PLD_DATA		0x0070
-#define DSI_CMD_PKT_STATUS		0x0074
-#define GEN_RD_CMD_BUSY			BIT(6)
-#define GEN_PLD_R_FULL			BIT(5)
-#define GEN_PLD_R_EMPTY			BIT(4)
-#define GEN_PLD_W_FULL			BIT(3)
-#define GEN_PLD_W_EMPTY			BIT(2)
-#define GEN_CMD_FULL			BIT(1)
-#define GEN_CMD_EMPTY			BIT(0)
-#define DSI_TO_CNT_CFG			0x0078
-#define HSTX_TO_CNT(x)			UPDATE(x, 31, 16)
-#define LPRX_TO_CNT(x)			UPDATE(x, 15,  0)
-#define DSI_HS_RD_TO_CNT		0x007c
-#define HS_RD_TO_CNT(x)			UPDATE(x, 15,  0)
-#define DSI_LP_RD_TO_CNT		0x0080
-#define LP_RD_TO_CNT(x)			UPDATE(x, 15,  0)
-#define DSI_HS_WR_TO_CNT		0x0084
-#define HS_WR_TO_CNT(x)			UPDATE(x, 15,  0)
-#define DSI_LP_WR_TO_CNT		0x0088
-#define LP_WR_TO_CNT(x)			UPDATE(x, 15,  0)
-#define DSI_BTA_TO_CNT			0x008c
-#define BTA_TO_CNT(x)			UPDATE(x, 15,  0)
-#define DSI_SDF_3D			0x0090
-#define DSI_LPCLK_CTRL			0x0094
-#define AUTO_CLKLANE_CTRL		BIT(1)
-#define PHY_TXREQUESTCLKHS		BIT(0)
-#define DSI_PHY_TMR_LPCLK_CFG		0x0098
-#define PHY_CLKHS2LP_TIME(x)		UPDATE(x, 25, 16)
-#define PHY_CLKLP2HS_TIME(x)		UPDATE(x,  9,  0)
-#define DSI_PHY_TMR_CFG			0x009c
-#define PHY_HS2LP_TIME(x)		UPDATE(x, 31, 24)
-#define PHY_LP2HS_TIME(x)		UPDATE(x, 23, 16)
-#define MAX_RD_TIME(x)			UPDATE(x, 14,  0)
-#define DSI_PHY_RSTZ			0x00a0
-#define PHY_FORCEPLL			BIT(3)
-#define PHY_ENABLECLK			BIT(2)
-#define PHY_RSTZ			BIT(1)
-#define PHY_SHUTDOWNZ			BIT(0)
-#define DSI_PHY_IF_CFG			0x00a4
-#define PHY_STOP_WAIT_TIME(x)		UPDATE(x, 15,  8)
-#define N_LANES(x)			UPDATE(x,  1,  0)
-#define DSI_PHY_STATUS			0x00b0
-#define PHY_STOPSTATE3LANE		BIT(11)
-#define PHY_STOPSTATE2LANE		BIT(9)
-#define PHY_STOPSTATE1LANE		BIT(7)
-#define PHY_STOPSTATE0LANE		BIT(4)
-#define PHY_STOPSTATECLKLANE		BIT(2)
-#define PHY_LOCK			BIT(0)
-#define PHY_STOPSTATELANE		(PHY_STOPSTATE0LANE | \
-					 PHY_STOPSTATECLKLANE)
-#define DSI_INT_ST0			0x00bc
-#define DSI_INT_ST1			0x00c0
-#define DSI_INT_MSK0			0x00c4
-#define DSI_INT_MSK1			0x00c8
-#define DSI_INT_FORCE0			0x00d8
-#define DSI_INT_FORCE1			0x00dc
-#define DSI_MAX_REGISTER		DSI_INT_FORCE1
-
-/* Test Code: 0x44 (HS RX Control of Lane 0) */
-#define HSFREQRANGE(x)			UPDATE(x, 6, 1)
-
-enum dpi_color_coding {
-	DPI_COLOR_CODING_16BIT_1,
-	DPI_COLOR_CODING_16BIT_2,
-	DPI_COLOR_CODING_16BIT_3,
-	DPI_COLOR_CODING_18BIT_1,
-	DPI_COLOR_CODING_18BIT_2,
-	DPI_COLOR_CODING_24BIT,
-};
-
-enum vid_mode_type {
-	VID_MODE_TYPE_NON_BURST_SYNC_PULSES,
-	VID_MODE_TYPE_NON_BURST_SYNC_EVENTS,
-	VID_MODE_TYPE_BURST,
-};
-
-enum operation_mode {
-	VIDEO_MODE,
-	COMMAND_MODE,
-};
-
-struct rk628_dsi_data {
-	u32 reg_base;
-	u8 id;
-};
-
-struct rk628_dsi {
-	struct drm_bridge base;
-	struct drm_connector connector;
-	struct drm_display_mode mode;
-	struct drm_panel *panel;
-
-	struct device *dev;
-	struct rk628 *parent;
-	struct mipi_dsi_host host;
-	struct phy *phy;
-	struct clk *pclk;
-	struct clk *cfgclk;
-	struct reset_control *rst;
-	struct regmap *grf;
-	struct regmap *regmap;
-	struct regmap *testif;
-	struct regmap_config config;
-	struct regmap_access_table rd_table;
-	struct regmap_range range;
-	int irq;
-	u32 reg_base;
-	u8 id;
-
-	struct rk628_dsi *master;
-	struct rk628_dsi *slave;
-	unsigned int lane_mbps;
-	u32 channel;
-	u32 lanes;
-	u32 format;
-	unsigned long mode_flags;
-};
-
-static inline struct rk628_dsi *bridge_to_dsi(struct drm_bridge *b)
-{
-	return container_of(b, struct rk628_dsi, base);
-}
-
-static inline struct rk628_dsi *host_to_dsi(struct mipi_dsi_host *h)
-{
-	return container_of(h, struct rk628_dsi, host);
-}
-
-static inline struct rk628_dsi *connector_to_dsi(struct drm_connector *c)
-{
-	return container_of(c, struct rk628_dsi, connector);
-}
-
-static inline void dsi_write(struct rk628_dsi *dsi, u32 reg, u32 val)
-{
-	regmap_write(dsi->regmap, dsi->reg_base + reg, val);
-}
-
-static inline u32 dsi_read(struct rk628_dsi *dsi, u32 reg)
-{
-	u32 val;
-
-	regmap_read(dsi->regmap, dsi->reg_base + reg, &val);
-
-	return val;
-}
-
-static inline void dsi_update_bits(struct rk628_dsi *dsi, u32 reg, u32 mask,
-				   u32 val)
-{
-	u32 orig, tmp;
-
-	orig = dsi_read(dsi, reg);
-	tmp = orig & ~mask;
-	tmp |= val & mask;
-	dsi_write(dsi, reg, tmp);
-}
-
-static inline void dpishutdn_assert(struct rk628_dsi *dsi)
-{
-	regmap_update_bits(dsi->grf, dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   DPISHUTDN, 1);
-}
-
-static inline void dpishutdn_deassert(struct rk628_dsi *dsi)
-{
-	regmap_update_bits(dsi->grf, dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   DPISHUTDN, 0);
-}
-
-static int genif_wait_w_pld_fifo_not_full(struct rk628_dsi *dsi)
-{
-	u32 sts;
-	int ret;
-
-	ret = regmap_read_poll_timeout(dsi->regmap,
-				       dsi->reg_base + DSI_CMD_PKT_STATUS,
-				       sts, !(sts & GEN_PLD_W_FULL),
-				       0, 1000);
-	if (ret < 0) {
-		dev_err(dsi->dev, "generic write payload fifo is full\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int genif_wait_cmd_fifo_not_full(struct rk628_dsi *dsi)
-{
-	u32 sts;
-	int ret;
-
-	ret = regmap_read_poll_timeout(dsi->regmap,
-				       dsi->reg_base + DSI_CMD_PKT_STATUS,
-				       sts, !(sts & GEN_CMD_FULL),
-				       0, 1000);
-	if (ret < 0) {
-		dev_err(dsi->dev, "generic write cmd fifo is full\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int genif_wait_write_fifo_empty(struct rk628_dsi *dsi)
-{
-	u32 sts;
-	u32 mask;
-	int ret;
-
-	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-	ret = regmap_read_poll_timeout(dsi->regmap,
-				       dsi->reg_base + DSI_CMD_PKT_STATUS,
-				       sts, (sts & mask) == mask,
-				       0, 1000);
-	if (ret < 0) {
-		dev_err(dsi->dev, "generic write fifo is full\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static inline void testif_testclk_assert(struct rk628_dsi *dsi)
-{
-	regmap_update_bits(dsi->grf, dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   PHY_TESTCLK, PHY_TESTCLK);
-	udelay(1);
-}
-
-static inline void testif_testclk_deassert(struct rk628_dsi *dsi)
-{
-	regmap_update_bits(dsi->grf, dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   PHY_TESTCLK, 0);
-	udelay(1);
-}
-
-static inline void testif_testclr_assert(struct rk628_dsi *dsi)
-{
-	regmap_update_bits(dsi->grf, dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   PHY_TESTCLR, PHY_TESTCLR);
-	udelay(1);
-}
-
-static inline void testif_testclr_deassert(struct rk628_dsi *dsi)
-{
-	regmap_update_bits(dsi->grf, dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   PHY_TESTCLR, 0);
-	udelay(1);
-}
-
-static inline void testif_testen_assert(struct rk628_dsi *dsi)
-{
-	regmap_update_bits(dsi->grf, dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   PHY_TESTEN, PHY_TESTEN);
-	udelay(1);
-}
-
-static inline void testif_testen_deassert(struct rk628_dsi *dsi)
-{
-	regmap_update_bits(dsi->grf,  dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   PHY_TESTEN, 0);
-	udelay(1);
-}
-
-static inline void testif_set_data(struct rk628_dsi *dsi, u8 data)
-{
-	regmap_update_bits(dsi->grf, dsi->id ?
-			   GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-			   PHY_TESTDIN_MASK, PHY_TESTDIN(data));
-	udelay(1);
-}
-
-static inline u8 testif_get_data(struct rk628_dsi *dsi)
-{
-	u32 data = 0;
-
-	regmap_read(dsi->grf, dsi->id ?
-		    GRF_DPHY1_STATUS : GRF_DPHY0_STATUS, &data);
-
-	return data >> PHY_TESTDOUT_SHIFT;
-}
-
-static void testif_test_code_write(struct rk628_dsi *dsi, u8 test_code)
-{
-	testif_testclk_assert(dsi);
-	testif_set_data(dsi, test_code);
-	testif_testen_assert(dsi);
-	testif_testclk_deassert(dsi);
-	testif_testen_deassert(dsi);
-}
-
-static void testif_test_data_write(struct rk628_dsi *dsi, u8 test_data)
-{
-	testif_testclk_deassert(dsi);
-	testif_set_data(dsi, test_data);
-	testif_testclk_assert(dsi);
-}
-
-static int testif_write(void *context, unsigned int reg, unsigned int value)
-{
-	struct rk628_dsi *dsi = context;
-	u8 monitor_data;
-
-	testif_test_code_write(dsi, reg);
-	testif_test_data_write(dsi, value);
-	monitor_data = testif_get_data(dsi);
-
-	dev_dbg(dsi->dev,
-		"test_code=0x%02x, test_data=0x%02x, monitor_data=0x%02x\n",
-		reg, value, monitor_data);
-
-	return 0;
-}
-
-static int testif_read(void *context, unsigned int reg, unsigned int *value)
-{
-	struct rk628_dsi *dsi = context;
-
-	testif_test_code_write(dsi, reg);
-	*value = testif_get_data(dsi);
-	testif_test_data_write(dsi, *value);
-
-	return 0;
-}
-
-static inline void mipi_dphy_enableclk_assert(struct rk628_dsi *dsi)
-{
-	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
-	udelay(1);
-}
-
-static inline void mipi_dphy_enableclk_deassert(struct rk628_dsi *dsi)
-{
-	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
-	udelay(1);
-}
-
-static inline void mipi_dphy_shutdownz_assert(struct rk628_dsi *dsi)
-{
-	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
-	udelay(1);
-}
-
-static inline void mipi_dphy_shutdownz_deassert(struct rk628_dsi *dsi)
-{
-	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);
-	udelay(1);
-}
-
-static inline void mipi_dphy_rstz_assert(struct rk628_dsi *dsi)
-{
-	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, 0);
-	udelay(1);
-}
-
-static inline void mipi_dphy_rstz_deassert(struct rk628_dsi *dsi)
-{
-	dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
-	udelay(1);
-}
-
-static void mipi_dphy_init(struct rk628_dsi *dsi)
-{
-	const struct {
-		unsigned long max_lane_mbps;
-		u8 hsfreqrange;
-	} hsfreqrange_table[] = {
-		{  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
-		{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
-		{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
-		{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
-		{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
-		{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
-		{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
-		{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
-		{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
-		{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
-	};
-	u8 hsfreqrange;
-	unsigned int index;
-
-	for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
-		if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps)
-			break;
-
-	if (index == ARRAY_SIZE(hsfreqrange_table))
-		--index;
-
-	hsfreqrange = hsfreqrange_table[index].hsfreqrange;
-	regmap_write(dsi->testif, 0x44, HSFREQRANGE(hsfreqrange));
-}
-
-static int mipi_dphy_power_on(struct rk628_dsi *dsi)
-{
-	unsigned int val, mask;
-	int ret;
-
-	mipi_dphy_enableclk_deassert(dsi);
-	mipi_dphy_shutdownz_assert(dsi);
-	mipi_dphy_rstz_assert(dsi);
-	testif_testclr_assert(dsi);
-
-	/* Set all REQUEST inputs to zero */
-	regmap_write(dsi->grf, dsi->id ?
-		     GRF_MIPI_TX1_CON : GRF_MIPI_TX0_CON,
-		     FORCETXSTOPMODE(0) | FORCERXMODE(0));
-	udelay(1);
-
-	testif_testclr_deassert(dsi);
-	mipi_dphy_init(dsi);
-
-	mipi_dphy_enableclk_assert(dsi);
-	mipi_dphy_shutdownz_deassert(dsi);
-	mipi_dphy_rstz_deassert(dsi);
-	usleep_range(1500, 2000);
-
-	phy_power_on(dsi->phy);
-
-	ret = regmap_read_poll_timeout(dsi->regmap, dsi->reg_base + DSI_PHY_STATUS,
-				       val, val & PHY_LOCK, 0, 1000);
-	if (ret < 0) {
-		dev_err(dsi->dev, "PHY is not locked\n");
-		return ret;
-	}
-
-	usleep_range(100, 200);
-
-	mask = PHY_STOPSTATELANE;
-	ret = regmap_read_poll_timeout(dsi->regmap, dsi->reg_base + DSI_PHY_STATUS,
-				       val, (val & mask) == mask,
-				       0, 1000);
-	if (ret < 0) {
-		dev_err(dsi->dev, "lane module is not in stop state\n");
-		return ret;
-	}
-
-	udelay(10);
-
-	return 0;
-}
-
-static void mipi_dphy_power_off(struct rk628_dsi *dsi)
-{
-	dsi_write(dsi, DSI_PHY_RSTZ, 0);
-	phy_power_off(dsi->phy);
-}
-
-static int rk628_dsi_turn_on_peripheral(struct rk628_dsi *dsi)
-{
-	dpishutdn_assert(dsi);
-	udelay(20);
-	dpishutdn_deassert(dsi);
-
-	return 0;
-}
-
-static int rk628_dsi_shutdown_peripheral(struct rk628_dsi *dsi)
-{
-	dpishutdn_deassert(dsi);
-	udelay(20);
-	dpishutdn_assert(dsi);
-
-	return 0;
-}
-
-static int rk628_dsi_host_attach(struct mipi_dsi_host *host,
-				 struct mipi_dsi_device *device)
-{
-	struct rk628_dsi *dsi = host_to_dsi(host);
-
-	if (device->lanes < 1 || device->lanes > 8)
-		return -EINVAL;
-
-	dsi->lanes = device->lanes;
-	dsi->channel = device->channel;
-	dsi->format = device->format;
-	dsi->mode_flags = device->mode_flags;
-
-	dsi->panel = of_drm_find_panel(device->dev.of_node);
-	if (!dsi->panel)
-		return -EPROBE_DEFER;
-
-	if (dsi->lanes > 4) {
-		struct device *d = bus_find_device_by_name(&platform_bus_type,
-							   NULL, "rk628-dsi1");
-		struct rk628_dsi *slave;
-
-		if (!d)
-			return -EPROBE_DEFER;
-
-		slave = dev_get_drvdata(d);
-		if (!slave)
-			return -EPROBE_DEFER;
-
-		dsi->slave = slave;
-		dsi->lanes /= 2;
-		slave->master = dsi;
-		slave->lanes = dsi->lanes;
-		slave->channel = dsi->channel;
-		slave->format = dsi->format;
-		slave->mode_flags = dsi->mode_flags;
-	}
-
-	return 0;
-}
-
-static int rk628_dsi_host_detach(struct mipi_dsi_host *host,
-				 struct mipi_dsi_device *device)
-{
-	return 0;
-}
-
-static int rk628_dsi_read_from_fifo(struct rk628_dsi *dsi,
-				    const struct mipi_dsi_msg *msg)
-{
-	u8 *payload = msg->rx_buf;
-	unsigned int vrefresh = drm_mode_vrefresh(&dsi->mode);
-	u16 length;
-	u32 val;
-	int ret;
-
-	if (!vrefresh)
-		return -EINVAL;
-
-	ret = regmap_read_poll_timeout(dsi->regmap,
-				       dsi->reg_base + DSI_CMD_PKT_STATUS,
-				       val, !(val & GEN_RD_CMD_BUSY),
-				       0, DIV_ROUND_UP(1000000, vrefresh));
-	if (ret) {
-		dev_err(dsi->dev, "entire response isn't stored in the FIFO\n");
-		return ret;
-	}
-
-	/* Receive payload */
-	for (length = msg->rx_len; length; length -= 4) {
-		ret = regmap_read_poll_timeout(dsi->regmap,
-					       dsi->reg_base + DSI_CMD_PKT_STATUS,
-					       val, !(val & GEN_PLD_R_EMPTY),
-					       0, 1000);
-		if (ret) {
-			dev_err(dsi->dev, "Read payload FIFO is empty\n");
-			return ret;
-		}
-
-		val = dsi_read(dsi, DSI_GEN_PLD_DATA);
-
-		switch (length) {
-		case 3:
-			payload[2] = (val >> 16) & 0xff;
-			fallthrough;
-		case 2:
-			payload[1] = (val >> 8) & 0xff;
-			fallthrough;
-		case 1:
-			payload[0] = val & 0xff;
-			return 0;
-		}
-
-		payload[0] = (val >>  0) & 0xff;
-		payload[1] = (val >>  8) & 0xff;
-		payload[2] = (val >> 16) & 0xff;
-		payload[3] = (val >> 24) & 0xff;
-		payload += 4;
-	}
-
-	return 0;
-}
-
-static ssize_t rk628_dsi_transfer(struct rk628_dsi *dsi,
-				  const struct mipi_dsi_msg *msg)
-{
-	struct mipi_dsi_packet packet;
-	int ret;
-	u32 val;
-
-	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG,
-				ACK_RQST_EN, ACK_RQST_EN);
-
-	if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
-		dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN);
-	} else {
-		dsi_update_bits(dsi, DSI_VID_MODE_CFG, LP_CMD_EN, 0);
-		dsi_update_bits(dsi, DSI_LPCLK_CTRL,
-				PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS);
-	}
-
-	switch (msg->type) {
-	case MIPI_DSI_SHUTDOWN_PERIPHERAL:
-		return rk628_dsi_shutdown_peripheral(dsi);
-	case MIPI_DSI_TURN_ON_PERIPHERAL:
-		return rk628_dsi_turn_on_peripheral(dsi);
-	case MIPI_DSI_DCS_SHORT_WRITE:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				DCS_SW_0P_TX : 0);
-		break;
-	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				DCS_SW_1P_TX : 0);
-		break;
-	case MIPI_DSI_DCS_LONG_WRITE:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				DCS_LW_TX : 0);
-		break;
-	case MIPI_DSI_DCS_READ:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				DCS_SR_0P_TX : 0);
-		break;
-	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, MAX_RD_PKT_SIZE,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				MAX_RD_PKT_SIZE : 0);
-		break;
-	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				GEN_SW_0P_TX : 0);
-		break;
-	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				GEN_SW_1P_TX : 0);
-		break;
-	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				GEN_SW_2P_TX : 0);
-		break;
-	case MIPI_DSI_GENERIC_LONG_WRITE:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				GEN_LW_TX : 0);
-		break;
-	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				GEN_SR_0P_TX : 0);
-		break;
-	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				GEN_SR_1P_TX : 0);
-		break;
-	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
-		dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX,
-				msg->flags & MIPI_DSI_MSG_USE_LPM ?
-				GEN_SR_2P_TX : 0);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* create a packet to the DSI protocol */
-	ret = mipi_dsi_create_packet(&packet, msg);
-	if (ret) {
-		dev_err(dsi->dev, "failed to create packet: %d\n", ret);
-		return ret;
-	}
-
-	/* Send payload */
-	while (packet.payload_length >= 4) {
-		/*
-		 * Alternatively, you can always keep the FIFO
-		 * nearly full by monitoring the FIFO state until
-		 * it is not full, and then writea single word of data.
-		 * This solution is more resource consuming
-		 * but it simultaneously avoids FIFO starvation,
-		 * making it possible to use FIFO sizes smaller than
-		 * the amount of data of the longest packet to be written.
-		 */
-		ret = genif_wait_w_pld_fifo_not_full(dsi);
-		if (ret)
-			return ret;
-
-		val = get_unaligned_le32(packet.payload);
-		dsi_write(dsi, DSI_GEN_PLD_DATA, val);
-
-		packet.payload += 4;
-		packet.payload_length -= 4;
-	}
-
-	val = 0;
-	switch (packet.payload_length) {
-	case 3:
-		val |= packet.payload[2] << 16;
-		fallthrough;
-	case 2:
-		val |= packet.payload[1] << 8;
-		fallthrough;
-	case 1:
-		val |= packet.payload[0];
-		dsi_write(dsi, DSI_GEN_PLD_DATA, val);
-		break;
-	}
-
-	ret = genif_wait_cmd_fifo_not_full(dsi);
-	if (ret)
-		return ret;
-
-	/* Send packet header */
-	val = get_unaligned_le32(packet.header);
-	dsi_write(dsi, DSI_GEN_HDR, val);
-
-	ret = genif_wait_write_fifo_empty(dsi);
-	if (ret)
-		return ret;
-
-	if (msg->rx_len) {
-		ret = rk628_dsi_read_from_fifo(dsi, msg);
-		if (ret < 0)
-			return ret;
-	}
-
-	if (dsi->slave)
-		rk628_dsi_transfer(dsi->slave, msg);
-
-	return msg->tx_len;
-}
-
-static ssize_t rk628_dsi_host_transfer(struct mipi_dsi_host *host,
-				       const struct mipi_dsi_msg *msg)
-{
-	struct rk628_dsi *dsi = host_to_dsi(host);
-
-	return rk628_dsi_transfer(dsi, msg);
-}
-
-static const struct mipi_dsi_host_ops rk628_dsi_host_ops = {
-	.attach = rk628_dsi_host_attach,
-	.detach = rk628_dsi_host_detach,
-	.transfer = rk628_dsi_host_transfer,
-};
-
-static struct drm_encoder *
-rk628_dsi_connector_best_encoder(struct drm_connector *connector)
-{
-	struct rk628_dsi *dsi = connector_to_dsi(connector);
-
-	return dsi->base.encoder;
-}
-
-static int rk628_dsi_connector_get_modes(struct drm_connector *connector)
-{
-	struct rk628_dsi *dsi = connector_to_dsi(connector);
-
-	return drm_panel_get_modes(dsi->panel, connector);
-}
-
-static struct drm_connector_helper_funcs rk628_dsi_connector_helper_funcs = {
-	.get_modes = rk628_dsi_connector_get_modes,
-	.best_encoder = rk628_dsi_connector_best_encoder,
-};
-
-static void rk628_dsi_drm_connector_destroy(struct drm_connector *connector)
-{
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs rk628_dsi_connector_funcs = {
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.destroy = rk628_dsi_drm_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static void rk628_dsi_set_vid_mode(struct rk628_dsi *dsi)
-{
-	struct drm_display_mode *mode = &dsi->mode;
-	unsigned int lanebyteclk = (dsi->lane_mbps * USEC_PER_MSEC) >> 3;
-	unsigned int dpipclk = mode->clock;
-	u32 hline, hsa, hbp, hline_time, hsa_time, hbp_time;
-	u32 vactive, vsa, vfp, vbp;
-	u32 val;
-
-	val = LP_HFP_EN | LP_HBP_EN | LP_VACT_EN | LP_VFP_EN | LP_VBP_EN |
-	      LP_VSA_EN;
-
-	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
-		val &= ~LP_HFP_EN;
-
-	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
-		val &= ~LP_HBP_EN;
-
-	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
-		val |= VID_MODE_TYPE_BURST;
-	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-		val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
-	else
-		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
-
-	dsi_write(dsi, DSI_VID_MODE_CFG, val);
-
-	if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
-		dsi_update_bits(dsi, DSI_LPCLK_CTRL,
-				AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL);
-
-	dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
-
-	vactive = mode->vdisplay;
-	vsa = mode->vsync_end - mode->vsync_start;
-	vfp = mode->vsync_start - mode->vdisplay;
-	vbp = mode->vtotal - mode->vsync_end;
-	hsa = mode->hsync_end - mode->hsync_start;
-	hbp = mode->htotal - mode->hsync_end;
-	hline = mode->htotal;
-
-	hline_time = DIV_ROUND_CLOSEST_ULL(hline * lanebyteclk, dpipclk);
-	dsi_write(dsi, DSI_VID_HLINE_TIME, VID_HLINE_TIME(hline_time));
-	hsa_time = DIV_ROUND_CLOSEST_ULL(hsa * lanebyteclk, dpipclk);
-	dsi_write(dsi, DSI_VID_HSA_TIME, VID_HSA_TIME(hsa_time));
-	hbp_time = DIV_ROUND_CLOSEST_ULL(hbp * lanebyteclk, dpipclk);
-	dsi_write(dsi, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time));
-
-	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
-	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
-	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
-	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
-
-	dsi_write(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(VIDEO_MODE));
-}
-
-static void rk628_dsi_set_cmd_mode(struct rk628_dsi *dsi)
-{
-	struct drm_display_mode *mode = &dsi->mode;
-
-	dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);
-	dsi_write(dsi, DSI_EDPI_CMD_SIZE,
-		  EDPI_ALLOWED_CMD_SIZE(mode->hdisplay));
-	dsi_write(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
-}
-
-static void rk628_dsi_disable(struct rk628_dsi *dsi)
-{
-	dsi_write(dsi, DSI_PWR_UP, RESET);
-	dsi_write(dsi, DSI_LPCLK_CTRL, 0);
-	dsi_write(dsi, DSI_EDPI_CMD_SIZE, 0);
-	dsi_write(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
-	dsi_write(dsi, DSI_PWR_UP, POWER_UP);
-
-	if (dsi->slave)
-		rk628_dsi_disable(dsi->slave);
-}
-
-static void rk628_dsi_post_disable(struct rk628_dsi *dsi)
-{
-	dsi_write(dsi, DSI_INT_MSK0, 0);
-	dsi_write(dsi, DSI_INT_MSK1, 0);
-	dsi_write(dsi, DSI_PWR_UP, RESET);
-	mipi_dphy_power_off(dsi);
-
-	clk_disable_unprepare(dsi->cfgclk);
-	clk_disable_unprepare(dsi->pclk);
-
-	if (dsi->slave)
-		rk628_dsi_post_disable(dsi->slave);
-}
-
-static unsigned int rk628_dsi_get_lane_rate(struct rk628_dsi *dsi)
-{
-	struct device *dev = dsi->dev;
-	const struct drm_display_mode *mode = &dsi->mode;
-	unsigned int max_lane_rate = 1500;
-	unsigned int lane_rate;
-	unsigned int value;
-	int bpp, lanes;
-
-	/* optional override of the desired bandwidth */
-	if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value))
-		return value;
-
-	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
-	if (bpp < 0)
-		bpp = 24;
-
-	lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;
-	lane_rate = mode->clock / 1000 * bpp / lanes;
-	lane_rate = DIV_ROUND_UP(lane_rate * 5, 4);
-
-	if (lane_rate > max_lane_rate)
-		lane_rate = max_lane_rate;
-
-	return lane_rate;
-}
-
-static void rk628_dsi_pre_enable(struct rk628_dsi *dsi)
-{
-	u32 val;
-
-	clk_prepare_enable(dsi->pclk);
-	clk_prepare_enable(dsi->cfgclk);
-	reset_control_assert(dsi->rst);
-	usleep_range(20, 40);
-	reset_control_deassert(dsi->rst);
-	usleep_range(20, 40);
-
-	dsi_write(dsi, DSI_PWR_UP, RESET);
-	dsi_write(dsi, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
-
-	val = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);
-	dsi_write(dsi, DSI_CLKMGR_CFG,
-		  TO_CLK_DIVISION(10) | TX_ESC_CLK_DIVISION(val));
-
-	val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN;
-
-	if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
-		val &= ~EOTP_TX_EN;
-
-	dsi_write(dsi, DSI_PCKHDL_CFG, val);
-
-	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
-	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
-	dsi_write(dsi, DSI_PHY_TMR_CFG,
-		  PHY_HS2LP_TIME(0x14) | PHY_LP2HS_TIME(0x10) |
-		  MAX_RD_TIME(10000));
-	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
-		  PHY_CLKHS2LP_TIME(0x40) | PHY_CLKLP2HS_TIME(0x40));
-	dsi_write(dsi, DSI_PHY_IF_CFG,
-		  PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes - 1));
-
-	mipi_dphy_power_on(dsi);
-
-	dsi_write(dsi, DSI_PWR_UP, POWER_UP);
-
-	dsi_write(dsi, DSI_INT_MSK0, 0x1fffff);
-	dsi_write(dsi, DSI_INT_MSK1, 0x1f7f);
-
-	if (dsi->slave)
-		rk628_dsi_pre_enable(dsi->slave);
-}
-
-static void rk628_dsi_enable(struct rk628_dsi *dsi)
-{
-	struct drm_display_mode *mode = &dsi->mode;
-	u32 val;
-
-	dsi_write(dsi, DSI_PWR_UP, RESET);
-
-	switch (dsi->format) {
-	case MIPI_DSI_FMT_RGB666:
-		val = DPI_COLOR_CODING(DPI_COLOR_CODING_18BIT_2) | LOOSELY18_EN;
-		break;
-	case MIPI_DSI_FMT_RGB666_PACKED:
-		val = DPI_COLOR_CODING(DPI_COLOR_CODING_18BIT_1);
-		break;
-	case MIPI_DSI_FMT_RGB565:
-		val = DPI_COLOR_CODING(DPI_COLOR_CODING_16BIT_1);
-		break;
-	case MIPI_DSI_FMT_RGB888:
-	default:
-		val = DPI_COLOR_CODING(DPI_COLOR_CODING_24BIT);
-		break;
-	}
-
-	dsi_write(dsi, DSI_DPI_COLOR_CODING, val);
-
-	val = 0;
-	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
-		val |= VSYNC_ACTIVE_LOW;
-	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
-		val |= HSYNC_ACTIVE_LOW;
-	dsi_write(dsi, DSI_DPI_CFG_POL, val);
-
-	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
-	dsi_write(dsi, DSI_DPI_LP_CMD_TIM,
-		  OUTVACT_LPCMD_TIME(4) | INVACT_LPCMD_TIME(4));
-
-	dsi_update_bits(dsi, DSI_LPCLK_CTRL,
-			PHY_TXREQUESTCLKHS, PHY_TXREQUESTCLKHS);
-
-	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO)
-		rk628_dsi_set_vid_mode(dsi);
-	else
-		rk628_dsi_set_cmd_mode(dsi);
-
-	dsi_write(dsi, DSI_PWR_UP, POWER_UP);
-
-	if (dsi->slave)
-		rk628_dsi_enable(dsi->slave);
-}
-
-static void rk628_dsi_bridge_enable(struct drm_bridge *bridge)
-{
-	struct rk628_dsi *dsi = bridge_to_dsi(bridge);
-	unsigned int rate = rk628_dsi_get_lane_rate(dsi);
-	int bus_width;
-	int ret;
-
-	regmap_update_bits(dsi->grf, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
-			   SW_OUTPUT_MODE(OUTPUT_MODE_DSI));
-	regmap_update_bits(dsi->grf, GRF_POST_PROC_CON, SW_SPLIT_EN,
-			   dsi->slave ? SW_SPLIT_EN : 0);
-
-	bus_width = rate << 8;
-	if (dsi->slave)
-		bus_width |= COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
-	else if (dsi->id)
-		bus_width |= COMBTXPHY_MODULEB_EN;
-	else
-		bus_width |= COMBTXPHY_MODULEA_EN;
-	phy_set_bus_width(dsi->phy, bus_width);
-
-	ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
-	if (ret) {
-		dev_err(dsi->dev, "failed to set phy mode: %d\n", ret);
-		return;
-	}
-	dsi->lane_mbps = phy_get_bus_width(dsi->phy);
-	if (dsi->slave)
-		dsi->slave->lane_mbps = dsi->lane_mbps;
-
-	rk628_dsi_pre_enable(dsi);
-	drm_panel_prepare(dsi->panel);
-	rk628_dsi_enable(dsi);
-	drm_panel_enable(dsi->panel);
-
-	dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
-		 dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);
-}
-
-static void rk628_dsi_bridge_disable(struct drm_bridge *bridge)
-{
-	struct rk628_dsi *dsi = bridge_to_dsi(bridge);
-
-	drm_panel_disable(dsi->panel);
-	rk628_dsi_disable(dsi);
-	drm_panel_unprepare(dsi->panel);
-	rk628_dsi_post_disable(dsi);
-}
-
-static void rk628_dsi_bridge_mode_set(struct drm_bridge *bridge,
-				      const struct drm_display_mode *mode,
-				      const struct drm_display_mode *adj)
-{
-	struct rk628_dsi *dsi = bridge_to_dsi(bridge);
-
-	drm_mode_copy(&dsi->mode, adj);
-	if (dsi->slave) {
-		dsi->mode.hdisplay /= 2;
-		drm_mode_copy(&dsi->slave->mode, &dsi->mode);
-	}
-}
-
-static int rk628_dsi_bridge_attach(struct drm_bridge *bridge,
-				   enum drm_bridge_attach_flags flags)
-{
-	struct rk628_dsi *dsi = bridge_to_dsi(bridge);
-	struct drm_connector *connector = &dsi->connector;
-	struct drm_device *drm = bridge->dev;
-	int ret;
-
-	if (!dsi->panel)
-		return -EPROBE_DEFER;
-
-	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
-		return 0;
-
-	ret = drm_connector_init(drm, connector, &rk628_dsi_connector_funcs,
-				 DRM_MODE_CONNECTOR_DSI);
-	if (ret) {
-		dev_err(dsi->dev, "Failed to initialize connector with drm\n");
-		return ret;
-	}
-
-	drm_connector_helper_add(connector, &rk628_dsi_connector_helper_funcs);
-	drm_connector_attach_encoder(connector, bridge->encoder);
-
-	return 0;
-}
-
-static const struct drm_bridge_funcs rk628_dsi_bridge_funcs = {
-	.attach = rk628_dsi_bridge_attach,
-	.mode_set = rk628_dsi_bridge_mode_set,
-	.enable = rk628_dsi_bridge_enable,
-	.disable = rk628_dsi_bridge_disable,
-};
-
-static irqreturn_t rk628_dsi_irq_handler(int irq, void *dev_id)
-{
-	struct rk628_dsi *dsi = dev_id;
-	u32 int_st0, int_st1;
-
-	int_st0 = dsi_read(dsi, DSI_INT_ST0);
-	int_st1 = dsi_read(dsi, DSI_INT_ST1);
-
-	if (!int_st0 && !int_st1)
-		return IRQ_NONE;
-
-	dev_info(dsi->dev, "int_st0=0x%08x, int_st1=0x%08x\n",
-		 int_st0, int_st1);
-
-	return IRQ_HANDLED;
-}
-
-static const struct regmap_config testif_regmap_config = {
-	.name = "phy",
-	.reg_bits = 8,
-	.val_bits = 8,
-	.max_register = 0x97,
-	.cache_type = REGCACHE_RBTREE,
-	.reg_write = testif_write,
-	.reg_read = testif_read,
-};
-
-static bool rk628_dsi_register_volatile(struct device *dev, unsigned int reg)
-{
-	reg &= 0xffff;
-
-	switch (reg) {
-	case DSI_GEN_HDR:
-	case DSI_GEN_PLD_DATA:
-	case DSI_CMD_PKT_STATUS:
-	case DSI_PHY_STATUS:
-	case DSI_INT_ST0:
-	case DSI_INT_ST1:
-	case DSI_INT_FORCE0:
-	case DSI_INT_FORCE1:
-		return true;
-	default:
-		return false;
-	}
-}
-
-static int rk628_dsi_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_dsi *dsi;
-	const struct rk628_dsi_data *data = of_device_get_match_data(dev);
-	char name[8];
-	int ret;
-
-	if (!of_device_is_available(dev->of_node))
-		return -ENODEV;
-
-	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
-	if (!dsi)
-		return -ENOMEM;
-
-	dsi->dev = dev;
-	dsi->parent = rk628;
-	dsi->grf = rk628->grf;
-	dsi->reg_base = data->reg_base;
-	dsi->id = data->id;
-	platform_set_drvdata(pdev, dsi);
-
-	dsi->irq = platform_get_irq(pdev, 0);
-	if (dsi->irq < 0)
-		return dsi->irq;
-
-	dsi->pclk = devm_clk_get(dev, "pclk");
-	if (IS_ERR(dsi->pclk)) {
-		ret = PTR_ERR(dsi->pclk);
-		dev_err(dev, "failed to get pclk: %d\n", ret);
-		return ret;
-	}
-
-	dsi->cfgclk = devm_clk_get(dev, "cfg");
-	if (IS_ERR(dsi->cfgclk)) {
-		ret = PTR_ERR(dsi->cfgclk);
-		dev_err(dev, "failed to get cfg clk: %d\n", ret);
-		return ret;
-	}
-
-	dsi->rst = of_reset_control_get(dev->of_node, NULL);
-	if (IS_ERR(dsi->rst)) {
-		ret = PTR_ERR(dsi->rst);
-		dev_err(dev, "failed to get reset control: %d\n", ret);
-		return ret;
-	}
-
-	dsi->phy = devm_of_phy_get(dev, dev->of_node, NULL);
-	if (IS_ERR(dsi->phy)) {
-		ret = PTR_ERR(dsi->phy);
-		dev_err(dev, "failed to get phy: %d\n", ret);
-		return ret;
-	}
-
-	sprintf(name, "dsi%d", dsi->id);
-	dsi->config.name = name;
-	dsi->config.reg_bits = 32;
-	dsi->config.val_bits = 32;
-	dsi->config.reg_stride = 4;
-	dsi->config.cache_type = REGCACHE_RBTREE;
-	dsi->config.max_register = dsi->reg_base + DSI_MAX_REGISTER;
-	dsi->config.reg_format_endian = REGMAP_ENDIAN_LITTLE;
-	dsi->config.val_format_endian = REGMAP_ENDIAN_LITTLE;
-	dsi->config.volatile_reg = rk628_dsi_register_volatile;
-	dsi->range.range_min = dsi->reg_base + DSI_VERSION;
-	dsi->range.range_max = dsi->reg_base + DSI_MAX_REGISTER;
-	dsi->rd_table.yes_ranges = &dsi->range;
-	dsi->rd_table.n_yes_ranges = 1;
-	dsi->config.rd_table = &dsi->rd_table;
-
-	dsi->regmap = devm_regmap_init_i2c(rk628->client, &dsi->config);
-	if (IS_ERR(dsi->regmap)) {
-		ret = PTR_ERR(dsi->regmap);
-		dev_err(dev, "failed to allocate register map: %d\n", ret);
-		return ret;
-	}
-
-	dsi->testif = devm_regmap_init(dev, NULL, dsi, &testif_regmap_config);
-	if (IS_ERR(dsi->testif)) {
-		ret = PTR_ERR(dsi->testif);
-		dev_err(dev, "failed to create testif regmap: %d\n", ret);
-		return ret;
-	}
-
-	ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
-					rk628_dsi_irq_handler, IRQF_ONESHOT,
-					dev_name(dev), dsi);
-	if (ret) {
-		dev_err(dev, "failed to request irq: %d\n", ret);
-		return ret;
-	}
-
-	dsi->base.funcs = &rk628_dsi_bridge_funcs;
-	dsi->base.of_node = dev->of_node;
-	drm_bridge_add(&dsi->base);
-
-	dsi->host.ops = &rk628_dsi_host_ops;
-	dsi->host.dev = dev;
-	ret = mipi_dsi_host_register(&dsi->host);
-	if (ret) {
-		drm_bridge_remove(&dsi->base);
-		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int rk628_dsi_remove(struct platform_device *pdev)
-{
-	struct rk628_dsi *dsi = platform_get_drvdata(pdev);
-
-	mipi_dsi_host_unregister(&dsi->host);
-	drm_bridge_remove(&dsi->base);
-
-	return 0;
-}
-
-static const struct rk628_dsi_data rk628_dsi0_data = {
-	.reg_base = 0x50000,
-	.id = 0,
-};
-
-static const struct rk628_dsi_data rk628_dsi1_data = {
-	.reg_base = 0x60000,
-	.id = 1,
-};
-
-static const struct of_device_id rk628_dsi_of_match[] = {
-	{ .compatible = "rockchip,rk628-dsi0", .data = &rk628_dsi0_data },
-	{ .compatible = "rockchip,rk628-dsi1", .data = &rk628_dsi1_data },
-	{}
-};
-MODULE_DEVICE_TABLE(of, rk628_dsi_of_match);
-
-static struct platform_driver rk628_dsi_driver = {
-	.driver = {
-		.name = "rk628-dsi",
-		.of_match_table = of_match_ptr(rk628_dsi_of_match),
-	},
-	.probe	= rk628_dsi_probe,
-	.remove = rk628_dsi_remove,
-};
-module_platform_driver(rk628_dsi_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 MIPI-DSI driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_gvi.c b/drivers/gpu/drm/rockchip/rk628/rk628_gvi.c
deleted file mode 100644
index 9065e30a5774..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_gvi.c
+++ /dev/null
@@ -1,666 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Sandy Huang <hjc@rock-chips.com>
- */
-
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/media-bus-format.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/mfd/rk628.h>
-
-#include <drm/drm_of.h>
-#include <drm/drm_atomic.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_panel.h>
-#include <video/of_display_timing.h>
-#include <video/videomode.h>
-
-#include "rk628_combtxphy.h"
-
-#define HOSTREG(x)					((x) + 0x80000)
-#define GVI_SYS_CTRL0					HOSTREG(0x0000)
-#define GVI_SYS_CTRL1					HOSTREG(0x0004)
-#define GVI_SYS_CTRL2					HOSTREG(0x0008)
-#define GVI_SYS_CTRL3					HOSTREG(0x000c)
-#define GVI_VERSION					HOSTREG(0x0010)
-#define GVI_SYS_RST					HOSTREG(0x0014)
-#define GVI_LINE_FLAG					HOSTREG(0x0018)
-#define GVI_STATUS					HOSTREG(0x001c)
-#define GVI_PLL_LOCK_TIMEOUT				HOSTREG(0x0030)
-#define GVI_HTPDN_TIMEOUT				HOSTREG(0x0034)
-#define GVI_LOCKN_TIMEOUT				HOSTREG(0x0038)
-#define GVI_WAIT_LOCKN					HOSTREG(0x003C)
-#define GVI_WAIT_HTPDN					HOSTREG(0x0040)
-#define GVI_INTR_EN					HOSTREG(0x0050)
-#define GVI_INTR_CLR					HOSTREG(0x0054)
-#define GVI_INTR_RAW_STATUS				HOSTREG(0x0058)
-#define GVI_INTR_STATUS					HOSTREG(0x005c)
-#define GVI_COLOR_BAR_CTRL				HOSTREG(0x0060)
-#define GVI_COLOR_BAR_HTIMING0				HOSTREG(0x0070)
-#define GVI_COLOR_BAR_HTIMING1				HOSTREG(0x0074)
-#define GVI_COLOR_BAR_VTIMING0				HOSTREG(0x0078)
-#define GVI_COLOR_BAR_VTIMING1				HOSTREG(0x007c)
-
-/* SYS_CTRL0 */
-#define SYS_CTRL0_GVI_EN				BIT(0)
-#define SYS_CTRL0_AUTO_GATING				BIT(1)
-#define SYS_CTRL0_FRM_RST_EN				BIT(2)
-#define SYS_CTRL0_FRM_RST_MODE				BIT(3)
-#define SYS_CTRL0_LANE_NUM_MASK				GENMASK(7, 4)
-#define SYS_CTRL0_LANE_NUM(x)				UPDATE(x, 7, 4)
-#define SYS_CTRL0_BYTE_MODE_MASK			GENMASK(9, 8)
-#define SYS_CTRL0_BYTE_MODE(x)				UPDATE(x, 9, 8)
-#define SYS_CTRL0_SECTION_NUM_MASK			GENMASK(11, 10)
-#define SYS_CTRL0_SECTION_NUM(x)			UPDATE(x, 11, 10)
-#define SYS_CTRL0_CDR_ENDIAN_SWAP			BIT(12)
-#define SYS_CTRL0_PACK_BYTE_SWAP			BIT(13)
-#define SYS_CTRL0_PACK_ENDIAN_SWAP			BIT(14)
-#define SYS_CTRL0_ENC8B10B_ENDIAN_SWAP			BIT(15)
-#define SYS_CTRL0_CDR_EN				BIT(16)
-#define SYS_CTRL0_ALN_EN				BIT(17)
-#define SYS_CTRL0_NOR_EN				BIT(18)
-#define SYS_CTRL0_ALN_NOR_MODE				BIT(19)
-#define SYS_CTRL0_GVI_MASK				GENMASK(19, 16)
-#define SYS_CTRL0_GVI_GN_EN(x)				UPDATE(x, 19, 16)
-
-#define SYS_CTRL0_SCRAMBLER_EN				BIT(20)
-#define SYS_CTRL0_ENCODE8B10B_EN			BIT(21)
-#define SYS_CTRL0_INIT_RD_EN				BIT(22)
-#define SYS_CTRL0_INIT_RD_VALUE				BIT(23)
-#define SYS_CTRL0_FORCE_HTPDN_EN			BIT(24)
-#define SYS_CTRL0_FORCE_HTPDN_VALUE			BIT(25)
-#define SYS_CTRL0_FORCE_PLL_EN				BIT(26)
-#define SYS_CTRL0_FORCE_PLL_VALUE			BIT(27)
-#define SYS_CTRL0_FORCE_LOCKN_EN			BIT(28)
-#define SYS_CTRL0_FORCE_LOCKN_VALUE			BIT(29)
-
-/* SYS_CTRL1 */
-#define SYS_CTRL1_COLOR_DEPTH_MASK			GENMASK(3, 0)
-#define SYS_CTRL1_COLOR_DEPTH(x)			UPDATE(x, 3, 0)
-#define SYS_CTRL1_DUAL_PIXEL_EN				BIT(4)
-#define SYS_CTRL1_TIMING_ALIGN_EN			BIT(8)
-#define SYS_CTRL1_LANE_ALIGN_EN				BIT(9)
-
-#define SYS_CTRL1_DUAL_PIXEL_SWAP			BIT(12)
-#define SYS_CTRL1_RB_SWAP				BIT(13)
-#define SYS_CTRL1_YC_SWAP				BIT(14)
-#define SYS_CTRL1_WHOLE_FRM_EN				BIT(16)
-#define SYS_CTRL1_NOR_PROTECT				BIT(17)
-#define SYS_CTRL1_RD_WCNT_UPDATE			BIT(31)
-
-/* SYS_CTRL2 */
-#define SYS_CTRL2_AFIFO_READ_THOLD_MASK			GENMASK(7, 0)
-#define SYS_CTRL2_AFIFO_READ_THOLD(x)			UPDATE(x, 7, 0)
-#define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD_MASK		GENMASK(23, 16)
-#define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x)		UPDATE(x, 23, 16)
-#define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD_MASK		GENMASK(31, 24)
-#define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x)		UPDATE(x, 31, 24)
-
-/* SYS_CTRL3 */
-#define SYS_CTRL3_LANE0_SEL_MASK			GENMASK(2, 0)
-#define SYS_CTRL3_LANE0_SEL(x)				UPDATE(x, 2, 0)
-#define SYS_CTRL3_LANE1_SEL_MASK			GENMASK(6, 4)
-#define SYS_CTRL3_LANE1_SEL(x)				UPDATE(x, 6, 4)
-#define SYS_CTRL3_LANE2_SEL_MASK			GENMASK(10, 8)
-#define SYS_CTRL3_LANE2_SEL(x)				UPDATE(x, 10, 8)
-#define SYS_CTRL3_LANE3_SEL_MASK			GENMASK(14, 12)
-#define SYS_CTRL3_LANE3_SEL(x)				UPDATE(x, 14, 12)
-#define SYS_CTRL3_LANE4_SEL_MASK			GENMASK(18, 16)
-#define SYS_CTRL3_LANE4_SEL(x)				UPDATE(x, 18, 16)
-#define SYS_CTRL3_LANE5_SEL_MASK			GENMASK(22, 20)
-#define SYS_CTRL3_LANE5_SEL(x)				UPDATE(x, 22, 20)
-#define SYS_CTRL3_LANE6_SEL_MASK			GENMASK(26, 24)
-#define SYS_CTRL3_LANE6_SEL(x)				UPDATE(x, 26, 24)
-#define SYS_CTRL3_LANE7_SEL_MASK			GENMASK(30, 28)
-#define SYS_CTRL3_LANE7_SEL(x)				UPDATE(x, 30, 28)
-/* VERSIION */
-#define VERSION_VERSION(x)				UPDATE(x, 31, 0)
-/* SYS_RESET*/
-#define SYS_RST_SOFT_RST				BIT(0)
-/* LINE_FLAG */
-#define LINE_FLAG_LANE_FLAG0_MASK			GENMASK(15, 0)
-#define LINE_FLAG_LANE_FLAG0(x)				UPDATE(x, 15, 0)
-#define LINE_FLAG_LANE_FLAG1_MASK			GENMASK(31, 16)
-#define LINE_FLAG_LANE_FLAG1(x)				UPDATE(x, 31, 16)
-/* STATUS */
-#define STATUS_HTDPN					BIT(4)
-#define STATUS_LOCKN					BIT(5)
-#define STATUS_PLL_LOCKN				BIT(6)
-#define STATUS_AFIFO0_WCNT_MASK				GENMASK(23, 16)
-#define STATUS_AFIFO0_WCNT(x)				UPDATE(x, 23, 16)
-#define STATUS_AFIFO1_WCNT_MASK				GENMASK(31, 24)
-#define STATUS_AFIFO1_WCNT(x)				UPDATE(x, 31, 24)
-/* PLL_LTIMEOUT */
-#define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT_MASK		GENMASK(31, 0)
-#define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT(x)		UPDATE(x, 31, 0)
-/* HTPDNEOUT */
-#define HTPDN_TIMEOUT_HTPDN_TIME_OUT_MASK		GENMASK(31, 0)
-#define HTPDN_TIMEOUT_HTPDN_TIME_OUT(x)			UPDATE(x, 31, 0)
-/* LOCKNEOUT */
-#define LOCKN_TIMEOUT_LOCKN_TIME_OUT_MASK		GENMASK(31, 0)
-#define LOCKN_TIMEOUT_LOCKN_TIME_OUT(x)			UPDATE(x, 31, 0)
-/* WAIT_LOCKN */
-#define WAIT_LOCKN_WAIT_LOCKN_TIME_MASK			GENMASK(30, 0)
-#define WAIT_LOCKN_WAIT_LOCKN_TIME(x)			UPDATE(x, 30, 0)
-#define WAIT_LOCKN_WAIT_LOCKN_TIME_EN			BIT(31)
-/* WAIT_HTPDN */
-#define WAIT_HTPDN_WAIT_HTPDN_TIME_MASK			GENMASK(30, 0)
-#define WAIT_HTPDN_WAIT_HTPDN_TIME(x)			UPDATE(x, 30, 0)
-#define WAIT_HTPDN_WAIT_HTPDN_EN			BIT(31)
-/* INTR_EN */
-#define INTR_EN_INTR_FRM_ST_EN				BIT(0)
-#define INTR_EN_INTR_PLL_LOCK_EN			BIT(1)
-#define INTR_EN_INTR_HTPDN_EN				BIT(2)
-#define INTR_EN_INTR_LOCKN_EN				BIT(3)
-#define INTR_EN_INTR_PLL_TIMEOUT_EN			BIT(4)
-#define INTR_EN_INTR_HTPDN_TIMEOUT_EN			BIT(5)
-#define INTR_EN_INTR_LOCKN_TIMEOUT_EN			BIT(6)
-#define INTR_EN_INTR_LINE_FLAG0_EN			BIT(8)
-#define INTR_EN_INTR_LINE_FLAG1_EN			BIT(9)
-#define INTR_EN_INTR_AFIFO_OVERFLOW_EN			BIT(10)
-#define INTR_EN_INTR_AFIFO_UNDERFLOW_EN			BIT(11)
-#define INTR_EN_INTR_PLL_ERR_EN				BIT(12)
-#define INTR_EN_INTR_HTPDN_ERR_EN			BIT(13)
-#define INTR_EN_INTR_LOCKN_ERR_EN			BIT(14)
-/* INTR_CLR*/
-#define INTR_CLR_INTR_FRM_ST_CLR			BIT(0)
-#define INTR_CLR_INTR_PLL_LOCK_CLR			BIT(1)
-#define INTR_CLR_INTR_HTPDN_CLR				BIT(2)
-#define INTR_CLR_INTR_LOCKN_CLR				BIT(3)
-#define INTR_CLR_INTR_PLL_TIMEOUT_CLR			BIT(4)
-#define INTR_CLR_INTR_HTPDN_TIMEOUT_CLR			BIT(5)
-#define INTR_CLR_INTR_LOCKN_TIMEOUT_CLR			BIT(6)
-#define INTR_CLR_INTR_LINE_FLAG0_CLR			BIT(8)
-#define INTR_CLR_INTR_LINE_FLAG1_CLR			BIT(9)
-#define INTR_CLR_INTR_AFIFO_OVERFLOW_CLR		BIT(10)
-#define INTR_CLR_INTR_AFIFO_UNDERFLOW_CLR		BIT(11)
-#define INTR_CLR_INTR_PLL_ERR_CLR			BIT(12)
-#define INTR_CLR_INTR_HTPDN_ERR_CLR			BIT(13)
-#define INTR_CLR_INTR_LOCKN_ERR_CLR			BIT(14)
-/* INTR_RAW_STATUS */
-#define INTR_RAW_STATUS_RAW_INTR_FRM_ST			BIT(0)
-#define INTR_RAW_STATUS_RAW_INTR_PLL_LOCK		BIT(1)
-#define INTR_RAW_STATUS_RAW_INTR_HTPDN			BIT(2)
-#define INTR_RAW_STATUS_RAW_INTR_LOCKN			BIT(3)
-#define INTR_RAW_STATUS_RAW_INTR_PLL_TIMEOUT		BIT(4)
-#define INTR_RAW_STATUS_RAW_INTR_HTPDN_TIMEOUT		BIT(5)
-#define INTR_RAW_STATUS_RAW_INTR_LOCKN_TIMEOUT		BIT(6)
-#define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG0		BIT(8)
-#define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG1		BIT(9)
-#define INTR_RAW_STATUS_RAW_INTR_AFIFO_OVERFLOW		BIT(10)
-#define INTR_RAW_STATUS_RAW_INTR_AFIFO_UNDERFLOW	BIT(11)
-#define INTR_RAW_STATUS_RAW_INTR_PLL_ERR		BIT(12)
-#define INTR_RAW_STATUS_RAW_INTR_HTPDN_ERR		BIT(13)
-#define INTR_RAW_STATUS_RAW_INTR_LOCKN_ERR		BIT(14)
-/* INTR_STATUS */
-#define INTR_STATUS_INTR_FRM_ST				BIT(0)
-#define INTR_STATUS_INTR_PLL_LOCK			BIT(1)
-#define INTR_STATUS_INTR_HTPDN				BIT(2)
-#define INTR_STATUS_INTR_LOCKN				BIT(3)
-#define INTR_STATUS_INTR_PLL_TIMEOUT			BIT(4)
-#define INTR_STATUS_INTR_HTPDN_TIMEOUT			BIT(5)
-#define INTR_STATUS_INTR_LOCKN_TIMEOUT			BIT(6)
-#define INTR_STATUS_INTR_LINE_FLAG0			BIT(8)
-#define INTR_STATUS_INTR_LINE_FLAG1			BIT(9)
-#define INTR_STATUS_INTR_AFIFO_OVERFLOW			BIT(10)
-#define INTR_STATUS_INTR_AFIFO_UNDERFLOW		BIT(11)
-#define INTR_STATUS_INTR_PLL_ERR			BIT(12)
-#define INTR_STATUS_INTR_HTPDN_ERR			BIT(13)
-#define INTR_STATUS_INTR_LOCKN_ERR			BIT(14)
-
-/* COLOR_BAR_CTRL */
-#define COLOR_BAR_EN					BIT(0)
-
-#define COLOR_DEPTH_RGB_YUV444_18BIT			0
-#define COLOR_DEPTH_RGB_YUV444_24BIT			1
-#define COLOR_DEPTH_RGB_YUV444_30BIT			2
-#define COLOR_DEPTH_YUV422_16BIT			8
-#define COLOR_DEPTH_YUV422_20BIT			9
-
-enum gvi_byte_mode {
-	GVI_3BYTE_MODE = 0,
-	GVI_4BYTE_MODE,
-	GVI_5BYTE_MODE,
-};
-
-struct rk628_gvi {
-	struct drm_bridge base;
-	struct drm_connector connector;
-	struct drm_panel *panel;
-	struct drm_display_mode mode;
-	struct device *dev;
-	struct regmap *grf;
-	struct regmap *regmap;
-	struct clk *pclk;
-	struct reset_control *rst;
-	struct phy *phy;
-	struct rk628 *parent;
-	u32 lane_mbps;
-	u32 bus_format;
-	u32 lane_num;
-	u8 color_depth;
-	u8 byte_mode;
-	bool division_mode;
-};
-
-static inline struct rk628_gvi *bridge_to_gvi(struct drm_bridge *b)
-{
-	return container_of(b, struct rk628_gvi, base);
-}
-
-static inline struct rk628_gvi *connector_to_gvi(struct drm_connector *c)
-{
-	return container_of(c, struct rk628_gvi, connector);
-}
-
-static struct drm_encoder *rk628_gvi_connector_best_encoder(struct drm_connector
-							    *connector)
-{
-	struct rk628_gvi *gvi = connector_to_gvi(connector);
-
-	return gvi->base.encoder;
-}
-
-static int rk628_gvi_connector_get_modes(struct drm_connector *connector)
-{
-	struct rk628_gvi *gvi = connector_to_gvi(connector);
-	struct drm_display_info *info = &connector->display_info;
-	int num_modes;
-
-	num_modes = drm_panel_get_modes(gvi->panel, connector);
-
-	if (info->num_bus_formats)
-		gvi->bus_format = info->bus_formats[0];
-	else
-		gvi->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
-
-	switch (gvi->bus_format) {
-	case MEDIA_BUS_FMT_RGB666_1X18:
-		gvi->byte_mode = 3;
-		gvi->color_depth = COLOR_DEPTH_RGB_YUV444_18BIT;
-		break;
-	case MEDIA_BUS_FMT_RGB888_1X24:
-		gvi->byte_mode = 4;
-		gvi->color_depth = COLOR_DEPTH_RGB_YUV444_24BIT;
-		break;
-	case MEDIA_BUS_FMT_RGB101010_1X30:
-		gvi->byte_mode = 4;
-		gvi->color_depth = COLOR_DEPTH_RGB_YUV444_30BIT;
-		break;
-	case MEDIA_BUS_FMT_YUYV8_1X16:
-		gvi->byte_mode = 3;
-		gvi->color_depth = COLOR_DEPTH_YUV422_16BIT;
-		break;
-	case MEDIA_BUS_FMT_YUYV10_1X20:
-		gvi->byte_mode = 3;
-		gvi->color_depth = COLOR_DEPTH_YUV422_20BIT;
-		break;
-	default:
-		gvi->byte_mode = 3;
-		gvi->color_depth = COLOR_DEPTH_RGB_YUV444_24BIT;
-		dev_info(gvi->dev, "unsupported bus_format: 0x%x\n",
-			 gvi->bus_format);
-		break;
-	}
-
-	info->edid_hdmi_rgb444_dc_modes = 0;
-	info->edid_hdmi_ycbcr444_dc_modes = 0;
-	info->hdmi.y420_dc_modes = 0;
-	info->color_formats = 0;
-	info->max_tmds_clock = 300000;
-	connector->ycbcr_420_allowed = true;
-
-	num_modes += rk628_scaler_add_src_mode(gvi->parent, connector);
-
-	return num_modes;
-}
-
-static const
-struct drm_connector_helper_funcs rk628_gvi_connector_helper_funcs = {
-	.get_modes = rk628_gvi_connector_get_modes,
-	.best_encoder = rk628_gvi_connector_best_encoder,
-};
-
-static enum drm_connector_status
-rk628_gvi_connector_detect(struct drm_connector *connector, bool force)
-{
-	return connector_status_connected;
-}
-
-static void rk628_gvi_connector_destroy(struct drm_connector *connector)
-{
-	drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs rk628_gvi_connector_funcs = {
-	.detect = rk628_gvi_connector_detect,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.destroy = rk628_gvi_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static unsigned int rk628_gvi_get_lane_rate(struct rk628_gvi *gvi)
-{
-	struct device *dev = gvi->dev;
-	const struct drm_display_mode *mode = &gvi->mode;
-	u32 lane_bit_rate, min_lane_rate = 500000, max_lane_rate = 4000000;
-	u64 total_bw;
-
-	/* optional override of the desired bandwidth */
-	if (!of_property_read_u32
-	    (dev->of_node, "rockchip,lane-rate", &lane_bit_rate))
-		return lane_bit_rate;
-
-	/**
-	 * [ENCODER TOTAL BIT-RATE](bps) = [byte mode](byte) x 10 / [pixel clock](HZ)
-	 *
-	 * lane_bit_rate = [total bit-rate](bps) / [lane number]
-	 *
-	 * 500Mbps <= lane_bit_rate <= 4Gbps
-	 */
-	total_bw = (unsigned long long)gvi->byte_mode * 10 * mode->clock;	/* Kbps */
-	do_div(total_bw, gvi->lane_num);
-	lane_bit_rate = total_bw;
-
-	if (lane_bit_rate < min_lane_rate)
-		lane_bit_rate = min_lane_rate;
-	if (lane_bit_rate > max_lane_rate)
-		lane_bit_rate = max_lane_rate;
-
-	return lane_bit_rate;
-}
-
-static void rk628_gvi_enable_color_bar(struct rk628_gvi *gvi)
-{
-	const struct drm_display_mode *mode = &gvi->mode;
-	struct videomode vm;
-	u16 hsync_len, hact_st, hact_end, htotal;
-	u16 vsync_len, vact_st, vact_end, vtotal;
-
-	drm_display_mode_to_videomode(mode, &vm);
-
-	if (gvi->division_mode) {
-		hsync_len = vm.hsync_len / 2;
-		hact_st = (vm.hsync_len + vm.hback_porch) / 2;
-		hact_end = (vm.hsync_len + vm.hback_porch + vm.hactive) / 2;
-		htotal = mode->htotal / 2;
-	} else {
-		hsync_len = vm.hsync_len;
-		hact_st = vm.hsync_len + vm.hback_porch;
-		hact_end = vm.hsync_len + vm.hback_porch + vm.hactive;
-		htotal = mode->htotal;
-	}
-	vsync_len = vm.vsync_len;
-	vact_st = vsync_len + vm.vback_porch;
-	vact_end = vact_st + vm.vactive;
-	vtotal = mode->vtotal;
-
-	regmap_write(gvi->regmap, GVI_COLOR_BAR_HTIMING0,
-		     hact_st << 16 | hsync_len);
-	regmap_write(gvi->regmap, GVI_COLOR_BAR_HTIMING1,
-		     (htotal - 1) << 16 | hact_end);
-	regmap_write(gvi->regmap, GVI_COLOR_BAR_VTIMING0,
-		     vact_st << 16 | vsync_len);
-	regmap_write(gvi->regmap, GVI_COLOR_BAR_VTIMING1,
-		     (vtotal - 1) << 16 | vact_end);
-	regmap_write_bits(gvi->regmap, GVI_COLOR_BAR_CTRL, COLOR_BAR_EN, 0);
-}
-
-static void rk628_gvi_pre_enable(struct rk628_gvi *gvi)
-{
-	clk_prepare_enable(gvi->pclk);
-
-	/* gvi reset */
-	regmap_write_bits(gvi->regmap, GVI_SYS_RST, SYS_RST_SOFT_RST,
-			  SYS_RST_SOFT_RST);
-	udelay(10);
-	regmap_write_bits(gvi->regmap, GVI_SYS_RST, SYS_RST_SOFT_RST, 0);
-	udelay(10);
-
-	regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_LANE_NUM_MASK,
-			  SYS_CTRL0_LANE_NUM(gvi->lane_num - 1));
-	regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_BYTE_MODE_MASK,
-			  SYS_CTRL0_BYTE_MODE(gvi->byte_mode ==
-					      3 ? 0 : (gvi->byte_mode ==
-						       4 ? 1 : 2)));
-	regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0,
-			  SYS_CTRL0_SECTION_NUM_MASK,
-			  SYS_CTRL0_SECTION_NUM(gvi->division_mode));
-	regmap_update_bits(gvi->grf, GRF_POST_PROC_CON, SW_SPLIT_EN,
-			   gvi->division_mode ? SW_SPLIT_EN : 0);
-	regmap_write_bits(gvi->regmap, GVI_SYS_CTRL1, SYS_CTRL1_DUAL_PIXEL_EN,
-			  gvi->division_mode ? SYS_CTRL1_DUAL_PIXEL_EN : 0);
-
-	regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_FRM_RST_EN, 0);
-	regmap_write_bits(gvi->regmap, GVI_SYS_CTRL1, SYS_CTRL1_LANE_ALIGN_EN, 0);
-}
-
-static void rk628_gvi_post_enable(struct rk628_gvi *gvi)
-{
-	u32 val;
-
-	val = SYS_CTRL0_GVI_EN | SYS_CTRL0_AUTO_GATING;
-	regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, val, 3);
-}
-
-static void rk628_gvi_bridge_enable(struct drm_bridge *bridge)
-{
-	struct rk628_gvi *gvi = bridge_to_gvi(bridge);
-	unsigned int rate = rk628_gvi_get_lane_rate(gvi);
-	int ret;
-
-	regmap_update_bits(gvi->grf, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
-			   SW_OUTPUT_MODE(OUTPUT_MODE_GVI));
-	phy_set_bus_width(gvi->phy, rate);
-	rk628_combtxphy_set_gvi_division_mode(gvi->phy, gvi->division_mode);
-	ret = phy_set_mode(gvi->phy, 0);
-	if (ret) {
-		dev_err(gvi->dev, "failed to set phy mode: %d\n", ret);
-		return;
-	}
-	phy_power_on(gvi->phy);
-	gvi->lane_mbps = phy_get_bus_width(gvi->phy);
-	rk628_gvi_pre_enable(gvi);
-	drm_panel_prepare(gvi->panel);
-	rk628_gvi_enable_color_bar(gvi);
-	rk628_gvi_post_enable(gvi);
-	drm_panel_enable(gvi->panel);
-
-	dev_info(gvi->dev,
-		 "GVI-Link bandwidth: %d x %d Mbps, Byte mode: %d, Color Depty: %d, %s division mode\n",
-		 gvi->lane_mbps, gvi->lane_num, gvi->byte_mode,
-		 gvi->color_depth, gvi->division_mode ? "two" : "one");
-}
-
-static void rk628_gvi_post_disable(struct drm_bridge *bridge)
-{
-	struct rk628_gvi *gvi = bridge_to_gvi(bridge);
-
-	regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_GVI_EN, 0);
-}
-
-static void rk628_gvi_bridge_disable(struct drm_bridge *bridge)
-{
-	struct rk628_gvi *gvi = bridge_to_gvi(bridge);
-
-	drm_panel_disable(gvi->panel);
-	drm_panel_unprepare(gvi->panel);
-	rk628_gvi_post_disable(bridge);
-	clk_disable_unprepare(gvi->pclk);
-	phy_power_off(gvi->phy);
-}
-
-static int rk628_gvi_bridge_attach(struct drm_bridge *bridge,
-				   enum drm_bridge_attach_flags flags)
-{
-	struct rk628_gvi *gvi = bridge_to_gvi(bridge);
-	struct drm_connector *connector = &gvi->connector;
-	struct drm_device *drm = bridge->dev;
-	int ret;
-
-	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
-		return 0;
-
-	ret = drm_connector_init(drm, connector, &rk628_gvi_connector_funcs,
-				 DRM_MODE_CONNECTOR_LVDS);
-	if (ret) {
-		dev_err(gvi->dev, "Failed to initialize connector with drm\n");
-		return ret;
-	}
-
-	drm_connector_helper_add(connector, &rk628_gvi_connector_helper_funcs);
-	drm_connector_attach_encoder(connector, bridge->encoder);
-
-	return 0;
-}
-
-static void rk628_gvi_bridge_mode_set(struct drm_bridge *bridge,
-				      const struct drm_display_mode *mode,
-				      const struct drm_display_mode *adj)
-{
-	struct rk628_gvi *gvi = bridge_to_gvi(bridge);
-
-	rk628_mode_copy(gvi->parent, &gvi->mode, mode);
-
-	dev_info(gvi->dev, "src mode: %dx%d, clk: %d, dst mode: %dx%d, clk: %d\n",
-		 mode->hdisplay, mode->vdisplay, mode->clock,
-		 gvi->mode.hdisplay, gvi->mode.vdisplay, gvi->mode.clock);
-}
-
-static const struct drm_bridge_funcs rk628_gvi_bridge_funcs = {
-	.attach = rk628_gvi_bridge_attach,
-	.enable = rk628_gvi_bridge_enable,
-	.disable = rk628_gvi_bridge_disable,
-	.mode_set = rk628_gvi_bridge_mode_set,
-};
-
-static const struct regmap_range rk628_gvi_readable_ranges[] = {
-	regmap_reg_range(GVI_SYS_CTRL0, GVI_COLOR_BAR_VTIMING1),
-};
-
-static const struct regmap_access_table rk628_gvi_readable_table = {
-	.yes_ranges = rk628_gvi_readable_ranges,
-	.n_yes_ranges = ARRAY_SIZE(rk628_gvi_readable_ranges),
-};
-
-static const struct regmap_config rk628_gvi_regmap_cfg = {
-	.name = "gvi",
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = 4,
-	.max_register = GVI_COLOR_BAR_VTIMING1,
-	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
-	.val_format_endian = REGMAP_ENDIAN_LITTLE,
-	.rd_table = &rk628_gvi_readable_table,
-};
-
-static int rk628_gvi_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_gvi *gvi;
-	int ret = 0;
-
-	if (!of_device_is_available(dev->of_node))
-		return -ENODEV;
-
-	gvi = devm_kzalloc(dev, sizeof(*gvi), GFP_KERNEL);
-	if (!gvi)
-		return -ENOMEM;
-
-	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
-					  &gvi->panel, NULL);
-	if (ret)
-		return ret;
-
-	gvi->dev = dev;
-	gvi->parent = rk628;
-	gvi->division_mode = of_property_read_bool(dev->of_node,
-						   "rockchip,division-mode");
-	ret = of_property_read_u32(dev->of_node, "rockchip,lane-num",
-				   &gvi->lane_num);
-	if (ret) {
-		dev_err(gvi->dev, "Failed to get lane num\n");
-		gvi->lane_num = 4;
-	}
-
-	platform_set_drvdata(pdev, gvi);
-	gvi->grf = rk628->grf;
-	if (!gvi->grf)
-		return -ENODEV;
-
-	gvi->regmap = devm_regmap_init_i2c(rk628->client,
-					   &rk628_gvi_regmap_cfg);
-	if (IS_ERR(gvi->regmap)) {
-		ret = PTR_ERR(gvi->regmap);
-		dev_err(dev, "failed to allocate register map: %d\n", ret);
-		return ret;
-	}
-
-	gvi->pclk = devm_clk_get(dev, "pclk");
-	if (IS_ERR(gvi->pclk)) {
-		ret = PTR_ERR(gvi->pclk);
-		dev_err(dev, "failed to get pclk: %d\n", ret);
-		return ret;
-	}
-
-	gvi->rst = of_reset_control_get(dev->of_node, NULL);
-	if (IS_ERR(gvi->rst)) {
-		ret = PTR_ERR(gvi->rst);
-		dev_err(dev, "failed to get reset control: %d\n", ret);
-		return ret;
-	}
-
-	gvi->phy = devm_of_phy_get(dev, dev->of_node, NULL);
-	if (IS_ERR(gvi->phy)) {
-		ret = PTR_ERR(gvi->phy);
-		dev_err(dev, "failed to get phy: %d\n", ret);
-		return ret;
-	}
-
-	gvi->base.funcs = &rk628_gvi_bridge_funcs;
-	gvi->base.of_node = dev->of_node;
-	drm_bridge_add(&gvi->base);
-
-	return 0;
-}
-
-static int rk628_gvi_remove(struct platform_device *pdev)
-{
-	struct rk628_gvi *gvi = platform_get_drvdata(pdev);
-
-	drm_bridge_remove(&gvi->base);
-
-	return 0;
-}
-
-static const struct of_device_id rk628_gvi_of_match[] = {
-	{.compatible = "rockchip,rk628-gvi",},
-	{},
-};
-
-MODULE_DEVICE_TABLE(of, rk628_gvi_of_match);
-
-static struct platform_driver rk628_gvi_driver = {
-	.driver = {
-		.name = "rk628-gvi",
-		.of_match_table = of_match_ptr(rk628_gvi_of_match),
-	},
-	.probe = rk628_gvi_probe,
-	.remove = rk628_gvi_remove,
-};
-
-module_platform_driver(rk628_gvi_driver);
-
-MODULE_AUTHOR("Sandy Huang <hjc@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 GVI driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_hdmi.c b/drivers/gpu/drm/rockchip/rk628/rk628_hdmi.c
deleted file mode 100644
index 4a8ce4f1a3b8..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_hdmi.c
+++ /dev/null
@@ -1,1623 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Chen Shunqing <csq@rock-chips.com>
- */
-
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/extcon.h>
-#include <linux/extcon-provider.h>
-#include <linux/hdmi.h>
-#include <linux/mfd/rk628.h>
-#include <linux/mfd/syscon.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/of_device.h>
-#include <linux/regmap.h>
-
-#include <drm/drm_of.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_edid.h>
-#include <sound/hdmi-codec.h>
-
-#include "../rockchip_drm_drv.h"
-
-#define HDMI_BASE			0x70000
-#define HDMI_REG_STRIDE			4
-
-#define DDC_SEGMENT_ADDR		0x30
-
-enum PWR_MODE {
-	NORMAL,
-	LOWER_PWR,
-};
-
-#define HDMI_SCL_RATE			(100 * 1000)
-#define DDC_BUS_FREQ_L			0x4b
-#define DDC_BUS_FREQ_H			0x4c
-
-#define HDMI_SYS_CTRL			0x00
-#define RST_ANALOG_MASK			BIT(6)
-#define NOT_RST_ANALOG(x)		UPDATE(x, 6, 6)
-#define RST_DIGITAL_MASK		BIT(5)
-#define NOT_RST_DIGITAL(x)		UPDATE(x, 5, 5)
-#define REG_CLK_INV_MASK		BIT(4)
-#define REG_CLK_INV(x)			UPDATE(x, 4, 4)
-#define VCLK_INV_MASK			BIT(3)
-#define VCLK_INV(x)			UPDATE(x, 3, 3)
-#define REG_CLK_SOURCE_MASK		BIT(2)
-#define REG_CLK_SOURCE(x)		UPDATE(x, 2, 2)
-#define POWER_MASK			BIT(1)
-#define PWR_OFF(x)			UPDATE(x, 1, 1)
-#define INT_POL_MASK			BIT(0)
-#define INT_POL(x)			UPDATE(x, 0, 0)
-
-#define HDMI_VIDEO_CONTROL1		0x01
-#define VIDEO_INPUT_FORMAT_MASK		GENMASK(3, 1)
-#define VIDEO_INPUT_SDR_RGB444		UPDATE(0x0, 3, 1)
-#define VIDEO_INPUT_DDR_RGB444		UPDATE(0x5, 3, 1)
-#define VIDEO_INPUT_DDR_YCBCR422	UPDATE(0x6, 3, 1)
-#define DE_SOURCE_MASK			BIT(0)
-#define DE_SOURCE(x)			UPDATE(x, 0, 0)
-
-#define HDMI_VIDEO_CONTROL2		0x02
-#define VIDEO_OUTPUT_COLOR_MASK		GENMASK(7, 6)
-#define VIDEO_OUTPUT_RRGB444		UPDATE(0x0, 7, 6)
-#define VIDEO_OUTPUT_YCBCR444		UPDATE(0x1, 7, 6)
-#define VIDEO_OUTPUT_YCBCR422		UPDATE(0x2, 7, 6)
-#define VIDEO_INPUT_BITS_MASK		GENMASK(5, 4)
-#define VIDEO_INPUT_12BITS		UPDATE(0x0, 5, 4)
-#define VIDEO_INPUT_10BITS		UPDATE(0x1, 5, 4)
-#define VIDEO_INPUT_REVERT		UPDATE(0x2, 5, 4)
-#define VIDEO_INPUT_8BITS		UPDATE(0x3, 5, 4)
-#define VIDEO_INPUT_CSP_MASK		BIT(1)
-#define VIDEO_INPUT_CSP(x)		UPDATE(x, 0, 0)
-
-#define HDMI_VIDEO_CONTROL		0x03
-#define VIDEO_AUTO_CSC_MASK		BIT(7)
-#define VIDEO_AUTO_CSC(x)		UPDATE(x, 7, 7)
-#define VIDEO_C0_C2_SWAP_MASK		BIT(0)
-#define VIDEO_C0_C2_SWAP(x)		UPDATE(x, 0, 0)
-enum {
-	C0_C2_CHANGE_ENABLE = 0,
-	C0_C2_CHANGE_DISABLE = 1,
-	AUTO_CSC_DISABLE = 0,
-	AUTO_CSC_ENABLE = 1,
-};
-
-#define HDMI_VIDEO_CONTROL3		0x04
-#define COLOR_DEPTH_NOT_INDICATED_MASK	BIT(4)
-#define COLOR_DEPTH_NOT_INDICATED(x)	UPDATE(x, 4, 4)
-#define SOF_MASK			BIT(3)
-#define SOF_DISABLE(x)			UPDATE(x, 3, 3)
-#define CSC_MASK			BIT(0)
-#define CSC_ENABLE(x)			UPDATE(x, 0, 0)
-
-#define HDMI_AV_MUTE			0x05
-#define AVMUTE_CLEAR_MASK		BIT(7)
-#define AVMUTE_CLEAR(x)			UPDATE(x, 7, 7)
-#define AVMUTE_ENABLE_MASK		BIT(6)
-#define AVMUTE_ENABLE(x)		UPDATE(x, 6, 6)
-#define AUDIO_PD_MASK			BIT(2)
-#define AUDIO_PD(x)			UPDATE(x, 2, 2)
-#define AUDIO_MUTE_MASK			BIT(1)
-#define AUDIO_MUTE(x)			UPDATE(x, 1, 1)
-#define VIDEO_BLACK_MASK		BIT(0)
-#define VIDEO_MUTE(x)			UPDATE(x, 0, 0)
-
-#define HDMI_VIDEO_TIMING_CTL		0x08
-#define HSYNC_POLARITY(x)		UPDATE(x, 3, 3)
-#define VSYNC_POLARITY(x)		UPDATE(x, 2, 2)
-#define INETLACE(x)			UPDATE(x, 1, 1)
-#define EXTERANL_VIDEO(x)		UPDATE(x, 0, 0)
-
-#define HDMI_VIDEO_EXT_HTOTAL_L		0x09
-#define HDMI_VIDEO_EXT_HTOTAL_H		0x0a
-#define HDMI_VIDEO_EXT_HBLANK_L		0x0b
-#define HDMI_VIDEO_EXT_HBLANK_H		0x0c
-#define HDMI_VIDEO_EXT_HDELAY_L		0x0d
-#define HDMI_VIDEO_EXT_HDELAY_H		0x0e
-#define HDMI_VIDEO_EXT_HDURATION_L	0x0f
-#define HDMI_VIDEO_EXT_HDURATION_H	0x10
-#define HDMI_VIDEO_EXT_VTOTAL_L		0x11
-#define HDMI_VIDEO_EXT_VTOTAL_H		0x12
-#define HDMI_VIDEO_EXT_VBLANK		0x13
-#define HDMI_VIDEO_EXT_VDELAY		0x14
-#define HDMI_VIDEO_EXT_VDURATION	0x15
-
-#define HDMI_VIDEO_CSC_COEF		0x18
-
-#define HDMI_AUDIO_CTRL1		0x35
-enum {
-	CTS_SOURCE_INTERNAL = 0,
-	CTS_SOURCE_EXTERNAL = 1,
-};
-
-#define CTS_SOURCE(x)			UPDATE(x, 7, 7)
-
-enum {
-	DOWNSAMPLE_DISABLE = 0,
-	DOWNSAMPLE_1_2 = 1,
-	DOWNSAMPLE_1_4 = 2,
-};
-
-#define DOWN_SAMPLE(x)			UPDATE(x, 6, 5)
-
-enum {
-	AUDIO_SOURCE_IIS = 0,
-	AUDIO_SOURCE_SPDIF = 1,
-};
-
-#define AUDIO_SOURCE(x)			UPDATE(x, 4, 3)
-#define MCLK_ENABLE(x)			UPDATE(x, 2, 2)
-
-enum {
-	MCLK_128FS = 0,
-	MCLK_256FS = 1,
-	MCLK_384FS = 2,
-	MCLK_512FS = 3,
-};
-
-#define MCLK_RATIO(x)			UPDATE(x, 1, 0)
-
-#define AUDIO_SAMPLE_RATE		0x37
-enum {
-	AUDIO_32K = 0x3,
-	AUDIO_441K = 0x0,
-	AUDIO_48K = 0x2,
-	AUDIO_882K = 0x8,
-	AUDIO_96K = 0xa,
-	AUDIO_1764K = 0xc,
-	AUDIO_192K = 0xe,
-};
-
-#define AUDIO_I2S_MODE			0x38
-enum {
-	I2S_CHANNEL_1_2 = 1,
-	I2S_CHANNEL_3_4 = 3,
-	I2S_CHANNEL_5_6 = 7,
-	I2S_CHANNEL_7_8 = 0xf
-};
-
-#define I2S_CHANNEL(x)			UPDATE(x, 5, 2)
-
-enum {
-	I2S_STANDARD = 0,
-	I2S_LEFT_JUSTIFIED = 1,
-	I2S_RIGHT_JUSTIFIED = 2,
-};
-
-#define I2S_MODE(x)			UPDATE(x, 1, 0)
-
-#define AUDIO_I2S_MAP			0x39
-#define AUDIO_I2S_SWAPS_SPDIF		0x3a
-#define N_32K				0x1000
-#define N_441K				0x1880
-#define N_882K				0x3100
-#define N_1764K				0x6200
-#define N_48K				0x1800
-#define N_96K				0x3000
-#define N_192K				0x6000
-
-#define HDMI_AUDIO_CHANNEL_STATUS	0x3e
-#define AUDIO_STATUS_NLPCM_MASK		BIT(7)
-#define AUDIO_STATUS_NLPCM(x)		UPDATE(x, 7, 7)
-#define AUDIO_STATUS_USE_MASK		BIT(6)
-#define AUDIO_STATUS_COPYRIGHT_MASK	BIT(5)
-#define AUDIO_STATUS_ADDITION_MASK	GENMASK(3, 2)
-#define AUDIO_STATUS_CLK_ACCURACY_MASK	GENMASK(1, 1)
-
-#define AUDIO_N_H			0x3f
-#define AUDIO_N_M			0x40
-#define AUDIO_N_L			0x41
-
-#define HDMI_AUDIO_CTS_H		0x45
-#define HDMI_AUDIO_CTS_M		0x46
-#define HDMI_AUDIO_CTS_L		0x47
-
-#define HDMI_DDC_CLK_L			0x4b
-#define HDMI_DDC_CLK_H			0x4c
-
-#define HDMI_EDID_SEGMENT_POINTER	0x4d
-#define HDMI_EDID_WORD_ADDR		0x4e
-#define HDMI_EDID_FIFO_OFFSET		0x4f
-#define HDMI_EDID_FIFO_ADDR		0x50
-
-#define HDMI_PACKET_SEND_MANUAL		0x9c
-#define HDMI_PACKET_SEND_AUTO		0x9d
-#define PACKET_GCP_EN_MASK		BIT(7)
-#define PACKET_GCP_EN(x)		UPDATE(x, 7, 7)
-#define PACKET_MSI_EN_MASK		BIT(6)
-#define PACKET_MSI_EN(x)		UPDATE(x, 6, 6)
-#define PACKET_SDI_EN_MASK		BIT(5)
-#define PACKET_SDI_EN(x)		UPDATE(x, 5, 5)
-#define PACKET_VSI_EN_MASK		BIT(4)
-#define PACKET_VSI_EN(x)		UPDATE(x, 4, 4)
-
-#define HDMI_CONTROL_PACKET_BUF_INDEX	0x9f
-enum {
-	INFOFRAME_VSI = 0x05,
-	INFOFRAME_AVI = 0x06,
-	INFOFRAME_AAI = 0x08,
-};
-
-#define HDMI_CONTROL_PACKET_ADDR	0xa0
-#define HDMI_MAXIMUM_INFO_FRAME_SIZE	0x11
-enum {
-	AVI_COLOR_MODE_RGB = 0,
-	AVI_COLOR_MODE_YCBCR422 = 1,
-	AVI_COLOR_MODE_YCBCR444 = 2,
-	AVI_COLORIMETRY_NO_DATA = 0,
-
-	AVI_COLORIMETRY_SMPTE_170M = 1,
-	AVI_COLORIMETRY_ITU709 = 2,
-	AVI_COLORIMETRY_EXTENDED = 3,
-
-	AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
-	AVI_CODED_FRAME_ASPECT_4_3 = 1,
-	AVI_CODED_FRAME_ASPECT_16_9 = 2,
-
-	ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
-	ACTIVE_ASPECT_RATE_4_3 = 0x09,
-	ACTIVE_ASPECT_RATE_16_9 = 0x0A,
-	ACTIVE_ASPECT_RATE_14_9 = 0x0B,
-};
-
-#define HDMI_HDCP_CTRL			0x52
-#define HDMI_DVI_MASK			BIT(1)
-#define HDMI_DVI(x)			UPDATE(x, 1, 1)
-
-#define HDMI_INTERRUPT_MASK1		0xc0
-#define INT_EDID_READY_MASK		BIT(2)
-#define HDMI_INTERRUPT_STATUS1		0xc1
-#define	INT_ACTIVE_VSYNC_MASK		BIT(5)
-#define INT_EDID_READY			BIT(2)
-
-#define HDMI_INTERRUPT_MASK2		0xc2
-#define HDMI_INTERRUPT_STATUS2		0xc3
-#define INT_HDCP_ERR			BIT(7)
-#define INT_BKSV_FLAG			BIT(6)
-#define INT_HDCP_OK			BIT(4)
-
-#define HDMI_STATUS			0xc8
-#define HOTPLUG_STATUS			BIT(7)
-#define MASK_INT_HOTPLUG_MASK		BIT(5)
-#define MASK_INT_HOTPLUG(x)		UPDATE(x, 5, 5)
-#define INT_HOTPLUG			BIT(1)
-
-#define HDMI_COLORBAR                   0xc9
-
-#define HDMI_PHY_SYNC			0xce
-#define HDMI_PHY_SYS_CTL		0xe0
-#define TMDS_CLK_SOURCE_MASK		BIT(5)
-#define TMDS_CLK_SOURCE(x)		UPDATE(x, 5, 5)
-#define PHASE_CLK_MASK			BIT(4)
-#define PHASE_CLK(x)			UPDATE(x, 4, 4)
-#define TMDS_PHASE_SEL_MASK		BIT(3)
-#define TMDS_PHASE_SEL(x)		UPDATE(x, 3, 3)
-#define BANDGAP_PWR_MASK		BIT(2)
-#define BANDGAP_PWR(x)			UPDATE(x, 2, 2)
-#define PLL_PWR_DOWN_MASK		BIT(1)
-#define PLL_PWR_DOWN(x)			UPDATE(x, 1, 1)
-#define TMDS_CHG_PWR_DOWN_MASK		BIT(0)
-#define TMDS_CHG_PWR_DOWN(x)		UPDATE(x, 0, 0)
-
-#define HDMI_PHY_CHG_PWR		0xe1
-#define CLK_CHG_PWR(x)			UPDATE(x, 3, 3)
-#define DATA_CHG_PWR(x)			UPDATE(x, 2, 0)
-
-#define HDMI_PHY_DRIVER			0xe2
-#define CLK_MAIN_DRIVER(x)		UPDATE(x, 7, 4)
-#define DATA_MAIN_DRIVER(x)		UPDATE(x, 3, 0)
-
-#define HDMI_PHY_PRE_EMPHASIS		0xe3
-#define PRE_EMPHASIS(x)			UPDATE(x, 6, 4)
-#define CLK_PRE_DRIVER(x)		UPDATE(x, 3, 2)
-#define DATA_PRE_DRIVER(x)		UPDATE(x, 1, 0)
-
-#define PHY_FEEDBACK_DIV_RATIO_LOW	0xe7
-#define FEEDBACK_DIV_LOW(x)		UPDATE(x, 7, 0)
-#define PHY_FEEDBACK_DIV_RATIO_HIGH	0xe8
-#define FEEDBACK_DIV_HIGH(x)		UPDATE(x, 0, 0)
-
-#define HDMI_PHY_PRE_DIV_RATIO		0xed
-#define PRE_DIV_RATIO(x)		UPDATE(x, 4, 0)
-
-#define HDMI_CEC_CTRL			0xd0
-#define ADJUST_FOR_HISENSE_MASK		BIT(6)
-#define REJECT_RX_BROADCAST_MASK	BIT(5)
-#define BUSFREETIME_ENABLE_MASK		BIT(2)
-#define REJECT_RX_MASK			BIT(1)
-#define START_TX_MASK			BIT(0)
-
-#define HDMI_CEC_DATA			0xd1
-#define HDMI_CEC_TX_OFFSET		0xd2
-#define HDMI_CEC_RX_OFFSET		0xd3
-#define HDMI_CEC_CLK_H			0xd4
-#define HDMI_CEC_CLK_L			0xd5
-#define HDMI_CEC_TX_LENGTH		0xd6
-#define HDMI_CEC_RX_LENGTH		0xd7
-#define HDMI_CEC_TX_INT_MASK		0xd8
-#define TX_DONE_MASK			BIT(3)
-#define TX_NOACK_MASK			BIT(2)
-#define TX_BROADCAST_REJ_MASK		BIT(1)
-#define TX_BUSNOTFREE_MASK		BIT(0)
-
-#define HDMI_CEC_RX_INT_MASK		0xd9
-#define RX_LA_ERR_MASK			BIT(4)
-#define RX_GLITCH_MASK			BIT(3)
-#define RX_DONE_MASK			BIT(0)
-
-#define HDMI_CEC_TX_INT			0xda
-#define HDMI_CEC_RX_INT			0xdb
-#define HDMI_CEC_BUSFREETIME_L		0xdc
-#define HDMI_CEC_BUSFREETIME_H		0xdd
-#define HDMI_CEC_LOGICADDR		0xde
-
-#define HDMI_REG(x)			(HDMI_BASE + (x) * HDMI_REG_STRIDE)
-#define HDMI_MAX_REG			HDMI_REG(0xed)
-
-struct audio_info {
-	int sample_rate;
-	int channels;
-	int sample_width;
-};
-
-struct hdmi_data_info {
-	int vic;
-	bool sink_is_hdmi;
-	bool sink_has_audio;
-	unsigned int enc_in_format;
-	unsigned int enc_out_format;
-	unsigned int colorimetry;
-};
-
-struct rk628_hdmi_i2c {
-	struct i2c_adapter adap;
-	u8 ddc_addr;
-	u8 segment_addr;
-	/* i2c lock */
-	struct mutex lock;
-};
-
-struct rk628_hdmi_phy_config {
-	unsigned long mpixelclock;
-	u8 pre_emphasis;	/* pre-emphasis value */
-	u8 vlev_ctr;		/* voltage level control */
-};
-
-struct rk628_hdmi {
-	struct device *dev;
-	int irq;
-	struct regmap *grf;
-	struct regmap *regmap;
-	struct rk628 *parent;
-	struct clk *pclk;
-	struct clk *dclk;
-
-	struct drm_bridge bridge;
-	struct drm_connector connector;
-
-	struct rk628_hdmi_i2c *i2c;
-	struct i2c_adapter *ddc;
-
-	unsigned int tmds_rate;
-
-	struct platform_device *audio_pdev;
-	bool audio_enable;
-
-	struct hdmi_data_info	hdmi_data;
-	struct drm_display_mode previous_mode;
-
-	struct rockchip_drm_sub_dev sub_dev;
-	struct extcon_dev *extcon;
-};
-
-static const unsigned int rk628_hdmi_cable[] = {
-	EXTCON_DISP_HDMI,
-	EXTCON_NONE,
-};
-
-enum {
-	CSC_ITU601_16_235_TO_RGB_0_255_8BIT,
-	CSC_ITU601_0_255_TO_RGB_0_255_8BIT,
-	CSC_ITU709_16_235_TO_RGB_0_255_8BIT,
-	CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
-	CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
-	CSC_RGB_0_255_TO_RGB_16_235_8BIT,
-};
-
-static const char coeff_csc[][24] = {
-	/*
-	 * YUV2RGB:601 SD mode(Y[16:235], UV[16:240], RGB[0:255]):
-	 *   R = 1.164*Y + 1.596*V - 204
-	 *   G = 1.164*Y - 0.391*U - 0.813*V + 154
-	 *   B = 1.164*Y + 2.018*U - 258
-	 */
-	{
-		0x04, 0xa7, 0x00, 0x00, 0x06, 0x62, 0x02, 0xcc,
-		0x04, 0xa7, 0x11, 0x90, 0x13, 0x40, 0x00, 0x9a,
-		0x04, 0xa7, 0x08, 0x12, 0x00, 0x00, 0x03, 0x02
-	},
-	/*
-	 * YUV2RGB:601 SD mode(YUV[0:255],RGB[0:255]):
-	 *   R = Y + 1.402*V - 248
-	 *   G = Y - 0.344*U - 0.714*V + 135
-	 *   B = Y + 1.772*U - 227
-	 */
-	{
-		0x04, 0x00, 0x00, 0x00, 0x05, 0x9b, 0x02, 0xf8,
-		0x04, 0x00, 0x11, 0x60, 0x12, 0xdb, 0x00, 0x87,
-		0x04, 0x00, 0x07, 0x16, 0x00, 0x00, 0x02, 0xe3
-	},
-	/*
-	 * YUV2RGB:709 HD mode(Y[16:235],UV[16:240],RGB[0:255]):
-	 *   R = 1.164*Y + 1.793*V - 248
-	 *   G = 1.164*Y - 0.213*U - 0.534*V + 77
-	 *   B = 1.164*Y + 2.115*U - 289
-	 */
-	{
-		0x04, 0xa7, 0x00, 0x00, 0x07, 0x2c, 0x02, 0xf8,
-		0x04, 0xa7, 0x10, 0xda, 0x12, 0x22, 0x00, 0x4d,
-		0x04, 0xa7, 0x08, 0x74, 0x00, 0x00, 0x03, 0x21
-	},
-
-	/*
-	 * RGB2YUV:601 SD mode:
-	 *   Cb = -0.291G - 0.148R + 0.439B + 128
-	 *   Y  = 0.504G  + 0.257R + 0.098B + 16
-	 *   Cr = -0.368G + 0.439R - 0.071B + 128
-	 */
-	{
-		0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
-		0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
-		0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
-	},
-	/*
-	 * RGB2YUV:709 HD mode:
-	 *   Cb = - 0.338G - 0.101R + 0.439B + 128
-	 *   Y  = 0.614G   + 0.183R + 0.062B + 16
-	 *   Cr = - 0.399G + 0.439R - 0.040B + 128
-	 */
-	{
-		0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
-		0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
-		0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
-	},
-	/*
-	 * RGB[0:255]2RGB[16:235]:
-	 *   R' = R x (235-16)/255 + 16;
-	 *   G' = G x (235-16)/255 + 16;
-	 *   B' = B x (235-16)/255 + 16;
-	 */
-	{
-		0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
-		0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
-		0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
-	},
-};
-
-static inline struct rk628_hdmi *bridge_to_hdmi(struct drm_bridge *b)
-{
-	return container_of(b, struct rk628_hdmi, bridge);
-}
-
-static inline struct rk628_hdmi *connector_to_hdmi(struct drm_connector *c)
-{
-	return container_of(c, struct rk628_hdmi, connector);
-}
-
-static inline u32 hdmi_readb(struct rk628_hdmi *hdmi, u32 offset)
-{
-	u32 val;
-
-	regmap_read(hdmi->regmap, (HDMI_BASE + ((offset) * HDMI_REG_STRIDE)),
-		    &val);
-
-	return val;
-}
-
-static inline void hdmi_writeb(struct rk628_hdmi *hdmi, u32 offset, u32 val)
-{
-	regmap_write(hdmi->regmap, (HDMI_BASE + ((offset) * HDMI_REG_STRIDE)),
-		     val);
-}
-
-static inline void hdmi_modb(struct rk628_hdmi *hdmi, u32 offset,
-			     u32 msk, u32 val)
-{
-	u8 temp = hdmi_readb(hdmi, offset) & ~msk;
-
-	temp |= val & msk;
-	hdmi_writeb(hdmi, offset, temp);
-}
-
-static void rk628_hdmi_i2c_init(struct rk628_hdmi *hdmi)
-{
-	int ddc_bus_freq;
-
-	ddc_bus_freq = (hdmi->tmds_rate >> 2) / HDMI_SCL_RATE;
-
-	hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
-	hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
-
-	/* Clear the EDID interrupt flag and mute the interrupt */
-	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
-	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, INT_EDID_READY);
-}
-
-static void rk628_hdmi_sys_power(struct rk628_hdmi *hdmi, bool enable)
-{
-	if (enable)
-		hdmi_modb(hdmi, HDMI_SYS_CTRL, POWER_MASK, PWR_OFF(0));
-	else
-		hdmi_modb(hdmi, HDMI_SYS_CTRL, POWER_MASK, PWR_OFF(1));
-}
-
-static struct rk628_hdmi_phy_config rk628_hdmi_phy_config[] = {
-	/* pixelclk pre-emp vlev */
-	{ 74250000,  0x3f, 0x88 },
-	{ 165000000, 0x3f, 0x88 },
-	{ ~0UL,	     0x00, 0x00 }
-};
-
-static void rk628_hdmi_set_pwr_mode(struct rk628_hdmi *hdmi, int mode)
-{
-	const struct rk628_hdmi_phy_config *phy_config =
-						rk628_hdmi_phy_config;
-
-	switch (mode) {
-	case NORMAL:
-		rk628_hdmi_sys_power(hdmi, false);
-		for (; phy_config->mpixelclock != ~0UL; phy_config++)
-			if (hdmi->tmds_rate <= phy_config->mpixelclock)
-				break;
-		if (!phy_config->mpixelclock)
-			return;
-		hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS,
-			    phy_config->pre_emphasis);
-		hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->vlev_ctr);
-
-		hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
-		hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
-		hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
-		hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
-		hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
-		hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
-
-		rk628_hdmi_sys_power(hdmi, true);
-		break;
-
-	case LOWER_PWR:
-		rk628_hdmi_sys_power(hdmi, false);
-		hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
-		hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
-		hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
-		hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
-		break;
-
-	default:
-		dev_err(hdmi->dev, "Unknown power mode %d\n", mode);
-	}
-}
-
-static void rk628_hdmi_reset(struct rk628_hdmi *hdmi)
-{
-	u32 val;
-	u32 msk;
-
-	hdmi_modb(hdmi, HDMI_SYS_CTRL, RST_DIGITAL_MASK, NOT_RST_DIGITAL(1));
-	usleep_range(100, 110);
-
-	hdmi_modb(hdmi, HDMI_SYS_CTRL, RST_ANALOG_MASK, NOT_RST_ANALOG(1));
-	usleep_range(100, 110);
-
-	msk = REG_CLK_INV_MASK | REG_CLK_SOURCE_MASK | POWER_MASK |
-	      INT_POL_MASK;
-	val = REG_CLK_INV(1) | REG_CLK_SOURCE(1) | PWR_OFF(0) | INT_POL(1);
-	hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
-
-	rk628_hdmi_set_pwr_mode(hdmi, NORMAL);
-}
-
-static int rk628_hdmi_upload_frame(struct rk628_hdmi *hdmi, int setup_rc,
-				   union hdmi_infoframe *frame, u32 frame_index,
-				   u32 mask, u32 disable, u32 enable)
-{
-	if (mask)
-		hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, disable);
-
-	hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, frame_index);
-
-	if (setup_rc >= 0) {
-		u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
-		ssize_t rc, i;
-
-		rc = hdmi_infoframe_pack(frame, packed_frame,
-					 sizeof(packed_frame));
-		if (rc < 0)
-			return rc;
-
-		for (i = 0; i < rc; i++)
-			hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
-				    packed_frame[i]);
-
-		if (mask)
-			hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, enable);
-	}
-
-	return setup_rc;
-}
-
-static int rk628_hdmi_config_video_vsi(struct rk628_hdmi *hdmi,
-				       struct drm_display_mode *mode)
-{
-	union hdmi_infoframe frame;
-	int rc;
-
-	rc = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
-							 &hdmi->connector,
-							 mode);
-
-	return rk628_hdmi_upload_frame(hdmi, rc, &frame,
-				       INFOFRAME_VSI, PACKET_VSI_EN_MASK,
-				       PACKET_VSI_EN(0), PACKET_VSI_EN(1));
-}
-
-static int rk628_hdmi_config_video_avi(struct rk628_hdmi *hdmi,
-				       struct drm_display_mode *mode)
-{
-	union hdmi_infoframe frame;
-	int rc;
-
-	rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
-						      &hdmi->connector, mode);
-
-	if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
-		frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
-	else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
-		frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
-	else
-		frame.avi.colorspace = HDMI_COLORSPACE_RGB;
-
-	if (frame.avi.colorspace != HDMI_COLORSPACE_RGB)
-		frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;
-
-	frame.avi.scan_mode = HDMI_SCAN_MODE_NONE;
-
-	return rk628_hdmi_upload_frame(hdmi, rc, &frame,
-				       INFOFRAME_AVI, 0, 0, 0);
-}
-
-static int rk628_hdmi_config_audio_aai(struct rk628_hdmi *hdmi,
-				       struct audio_info *audio)
-{
-	struct hdmi_audio_infoframe *faudio;
-	union hdmi_infoframe frame;
-	int rc;
-
-	rc = hdmi_audio_infoframe_init(&frame.audio);
-	faudio = (struct hdmi_audio_infoframe *)&frame;
-
-	faudio->channels = audio->channels;
-
-	return rk628_hdmi_upload_frame(hdmi, rc, &frame,
-				       INFOFRAME_AAI, 0, 0, 0);
-}
-
-static int rk628_hdmi_config_video_csc(struct rk628_hdmi *hdmi)
-{
-	struct hdmi_data_info *data = &hdmi->hdmi_data;
-	int c0_c2_change = 0;
-	int csc_enable = 0;
-	int csc_mode = 0;
-	int auto_csc = 0;
-	int value;
-	int i;
-
-	/* Input video mode is SDR RGB24bit, data enable signal from external */
-	hdmi_writeb(hdmi, HDMI_VIDEO_CONTROL1, DE_SOURCE(1) |
-		    VIDEO_INPUT_SDR_RGB444);
-
-	/* Input color hardcode to RGB, and output color hardcode to RGB888 */
-	value = VIDEO_INPUT_8BITS | VIDEO_OUTPUT_RRGB444 |
-		VIDEO_INPUT_CSP(0);
-	hdmi_writeb(hdmi, HDMI_VIDEO_CONTROL2, value);
-
-	if (data->enc_in_format == data->enc_out_format) {
-		if ((data->enc_in_format == HDMI_COLORSPACE_RGB) ||
-		    (data->enc_in_format >= HDMI_COLORSPACE_YUV444)) {
-			value = SOF_DISABLE(1) | COLOR_DEPTH_NOT_INDICATED(1);
-			hdmi_writeb(hdmi, HDMI_VIDEO_CONTROL3, value);
-
-			hdmi_modb(hdmi, HDMI_VIDEO_CONTROL,
-				  VIDEO_AUTO_CSC_MASK | VIDEO_C0_C2_SWAP_MASK,
-				  VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
-				  VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
-			return 0;
-		}
-	}
-
-	if (data->colorimetry == HDMI_COLORIMETRY_ITU_601) {
-		if ((data->enc_in_format == HDMI_COLORSPACE_RGB) &&
-		    (data->enc_out_format == HDMI_COLORSPACE_YUV444)) {
-			csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
-			auto_csc = AUTO_CSC_DISABLE;
-			c0_c2_change = C0_C2_CHANGE_DISABLE;
-			csc_enable = CSC_ENABLE(1);
-		} else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) &&
-			   (data->enc_out_format == HDMI_COLORSPACE_RGB)) {
-			csc_mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
-			auto_csc = AUTO_CSC_ENABLE;
-			c0_c2_change = C0_C2_CHANGE_DISABLE;
-			csc_enable = CSC_ENABLE(0);
-		}
-	} else {
-		if ((data->enc_in_format == HDMI_COLORSPACE_RGB) &&
-		    (data->enc_out_format == HDMI_COLORSPACE_YUV444)) {
-			csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
-			auto_csc = AUTO_CSC_DISABLE;
-			c0_c2_change = C0_C2_CHANGE_DISABLE;
-			csc_enable = CSC_ENABLE(1);
-		} else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) &&
-			   (data->enc_out_format == HDMI_COLORSPACE_RGB)) {
-			csc_mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
-			auto_csc = AUTO_CSC_ENABLE;
-			c0_c2_change = C0_C2_CHANGE_DISABLE;
-			csc_enable = CSC_ENABLE(0);
-		}
-	}
-
-	for (i = 0; i < 24; i++)
-		hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
-			    coeff_csc[csc_mode][i]);
-
-	value = SOF_DISABLE(1) | csc_enable | COLOR_DEPTH_NOT_INDICATED(1);
-	hdmi_writeb(hdmi, HDMI_VIDEO_CONTROL3, value);
-	hdmi_modb(hdmi, HDMI_VIDEO_CONTROL,
-		  VIDEO_AUTO_CSC_MASK | VIDEO_C0_C2_SWAP_MASK,
-		  VIDEO_AUTO_CSC(auto_csc) | VIDEO_C0_C2_SWAP(c0_c2_change));
-
-	return 0;
-}
-
-static int rk628_hdmi_config_video_timing(struct rk628_hdmi *hdmi,
-					  struct drm_display_mode *mode)
-{
-	int value;
-
-	/* Set detail external video timing polarity and interlace mode */
-	value = EXTERANL_VIDEO(1);
-	value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
-		 HSYNC_POLARITY(1) : HSYNC_POLARITY(0);
-	value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
-		 VSYNC_POLARITY(1) : VSYNC_POLARITY(0);
-	value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
-		 INETLACE(1) : INETLACE(0);
-	hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
-
-	/* Set detail external video timing */
-	value = mode->htotal;
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
-
-	value = mode->htotal - mode->hdisplay;
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
-
-	value = mode->htotal - mode->hsync_start;
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
-
-	value = mode->hsync_end - mode->hsync_start;
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
-
-	value = mode->vtotal;
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
-
-	value = mode->vtotal - mode->vdisplay;
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
-
-	value = mode->vtotal - mode->vsync_start;
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
-
-	value = mode->vsync_end - mode->vsync_start;
-	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
-
-	hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
-	hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
-	hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
-
-	return 0;
-}
-
-static int rk628_hdmi_setup(struct rk628_hdmi *hdmi,
-			    struct drm_display_mode *mode)
-{
-	hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
-
-	hdmi->hdmi_data.enc_in_format = HDMI_COLORSPACE_RGB;
-	hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
-
-	if ((hdmi->hdmi_data.vic == 6) || (hdmi->hdmi_data.vic == 7) ||
-	    (hdmi->hdmi_data.vic == 21) || (hdmi->hdmi_data.vic == 22) ||
-	    (hdmi->hdmi_data.vic == 2) || (hdmi->hdmi_data.vic == 3) ||
-	    (hdmi->hdmi_data.vic == 17) || (hdmi->hdmi_data.vic == 18))
-		hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
-	else
-		hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
-
-	/* Mute video and audio output */
-	hdmi_modb(hdmi, HDMI_AV_MUTE, AUDIO_MUTE_MASK | VIDEO_BLACK_MASK,
-		  AUDIO_MUTE(1) | VIDEO_MUTE(1));
-
-	/* Set HDMI Mode */
-	hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
-		    HDMI_DVI(hdmi->hdmi_data.sink_is_hdmi));
-
-	rk628_hdmi_config_video_timing(hdmi, mode);
-
-	rk628_hdmi_config_video_csc(hdmi);
-
-	if (hdmi->hdmi_data.sink_is_hdmi) {
-		rk628_hdmi_config_video_avi(hdmi, mode);
-		rk628_hdmi_config_video_vsi(hdmi, mode);
-	}
-
-	/*
-	 * When IP controller have configured to an accurate video
-	 * timing, then the TMDS clock source would be switched to
-	 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
-	 * clock rate, and reconfigure the DDC clock.
-	 */
-	hdmi->tmds_rate = mode->clock * 1000;
-	rk628_hdmi_i2c_init(hdmi);
-
-	/* Unmute video and audio output */
-	hdmi_modb(hdmi, HDMI_AV_MUTE, VIDEO_BLACK_MASK, VIDEO_MUTE(0));
-	if (hdmi->audio_enable)
-		hdmi_modb(hdmi, HDMI_AV_MUTE, AUDIO_MUTE_MASK, AUDIO_MUTE(0));
-
-	return 0;
-}
-
-static enum drm_connector_status
-rk628_hdmi_connector_detect(struct drm_connector *connector, bool force)
-{
-	struct rk628_hdmi *hdmi = connector_to_hdmi(connector);
-	int status;
-
-	status = hdmi_readb(hdmi, HDMI_STATUS) & HOTPLUG_STATUS;
-	if (status)
-		extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
-	else
-		extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
-
-	return status ? connector_status_connected :
-			connector_status_disconnected;
-}
-
-static bool source_is_bt1120(struct device_node *np)
-{
-	struct device_node *first_remote, *second_remote;
-	bool ret = false;
-
-	first_remote = of_graph_get_remote_node(np, 0, -1);
-	if (!first_remote)
-		return ret;
-
-	if (!of_device_is_available(first_remote)) {
-		of_node_put(first_remote);
-		return ret;
-	}
-
-	second_remote = of_graph_get_remote_node(first_remote, 0, -1);
-	if (!second_remote) {
-		of_node_put(first_remote);
-		return ret;
-	}
-
-	of_node_put(first_remote);
-	if (!of_device_is_available(second_remote)) {
-		of_node_put(second_remote);
-		return ret;
-	}
-
-	if (strstr(of_node_full_name(second_remote), "bt1120-rx"))
-		ret = true;
-
-	of_node_put(second_remote);
-
-	return ret;
-}
-
-static int rk628_hdmi_connector_get_modes(struct drm_connector *connector)
-{
-	struct rk628_hdmi *hdmi = connector_to_hdmi(connector);
-	struct drm_display_info *info = &connector->display_info;
-	struct edid *edid = NULL;
-	int ret = 0;
-
-	if (!hdmi->ddc)
-		return 0;
-
-	clk_prepare_enable(hdmi->dclk);
-	if ((hdmi_readb(hdmi, HDMI_STATUS) & HOTPLUG_STATUS))
-		edid = drm_get_edid(connector, hdmi->ddc);
-	clk_disable_unprepare(hdmi->dclk);
-
-	if (edid) {
-		hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
-		hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
-		drm_connector_update_edid_property(connector, edid);
-		ret = drm_add_edid_modes(connector, edid);
-		kfree(edid);
-	} else {
-		hdmi->hdmi_data.sink_is_hdmi = true;
-		hdmi->hdmi_data.sink_has_audio = true;
-		ret = rockchip_drm_add_modes_noedid(connector);
-		info->edid_hdmi_rgb444_dc_modes = 0;
-		info->edid_hdmi_ycbcr444_dc_modes = 0;
-		info->hdmi.y420_dc_modes = 0;
-		info->color_formats = 0;
-
-		dev_info(hdmi->dev, "failed to get edid\n");
-	}
-
-	if (source_is_bt1120(hdmi->dev->of_node)) {
-		u32 bus_format = MEDIA_BUS_FMT_VYUY8_1X16;
-
-		drm_display_info_set_bus_formats(&connector->display_info,
-						 &bus_format, 1);
-	}
-
-	return ret;
-}
-
-static enum drm_mode_status
-rk628_hdmi_connector_mode_valid(struct drm_connector *connector,
-				struct drm_display_mode *mode)
-{
-	if ((mode->hdisplay == 1920 && mode->vdisplay == 1080) ||
-	    (mode->hdisplay == 1280 && mode->vdisplay == 720))
-		return MODE_OK;
-	else
-		return MODE_BAD;
-}
-
-static struct drm_encoder *
-rk628_hdmi_connector_best_encoder(struct drm_connector *connector)
-{
-	struct rk628_hdmi *hdmi = connector_to_hdmi(connector);
-
-	return hdmi->bridge.encoder;
-}
-
-static int
-rk628_hdmi_probe_single_connector_modes(struct drm_connector *connector,
-					u32 maxX, u32 maxY)
-{
-	return drm_helper_probe_single_connector_modes(connector, 1920, 1080);
-}
-
-static const struct drm_connector_funcs rk628_hdmi_connector_funcs = {
-	.fill_modes = rk628_hdmi_probe_single_connector_modes,
-	.detect = rk628_hdmi_connector_detect,
-	.destroy = drm_connector_cleanup,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static const struct drm_connector_helper_funcs
-rk628_hdmi_connector_helper_funcs = {
-	.get_modes = rk628_hdmi_connector_get_modes,
-	.mode_valid = rk628_hdmi_connector_mode_valid,
-	.best_encoder = rk628_hdmi_connector_best_encoder,
-};
-
-static void rk628_hdmi_bridge_mode_set(struct drm_bridge *bridge,
-				       const struct drm_display_mode *mode,
-				       const struct drm_display_mode *adj_mode)
-{
-	struct rk628_hdmi *hdmi = bridge_to_hdmi(bridge);
-
-	/* Store the display mode for plugin/DPMS poweron events */
-	drm_mode_copy(&hdmi->previous_mode, mode);
-}
-
-static void rk628_hdmi_bridge_enable(struct drm_bridge *bridge)
-{
-	struct rk628_hdmi *hdmi = bridge_to_hdmi(bridge);
-
-	rk628_hdmi_setup(hdmi, &hdmi->previous_mode);
-	rk628_hdmi_set_pwr_mode(hdmi, NORMAL);
-}
-
-static void rk628_hdmi_bridge_disable(struct drm_bridge *bridge)
-{
-	struct rk628_hdmi *hdmi = bridge_to_hdmi(bridge);
-
-	rk628_hdmi_set_pwr_mode(hdmi, LOWER_PWR);
-}
-
-static int rk628_hdmi_bridge_attach(struct drm_bridge *bridge,
-				    enum drm_bridge_attach_flags flags)
-{
-	struct rk628_hdmi *hdmi = bridge_to_hdmi(bridge);
-	struct drm_connector *connector = &hdmi->connector;
-	struct drm_device *drm = bridge->dev;
-	int ret;
-
-	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
-		return 0;
-
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
-
-	ret = drm_connector_init(drm, connector, &rk628_hdmi_connector_funcs,
-				 DRM_MODE_CONNECTOR_HDMIA);
-	if (ret) {
-		dev_err(hdmi->dev, "Failed to initialize connector with drm\n");
-		return ret;
-	}
-
-	drm_connector_helper_add(connector,
-				 &rk628_hdmi_connector_helper_funcs);
-	drm_connector_attach_encoder(connector, bridge->encoder);
-
-	hdmi->sub_dev.connector = &hdmi->connector;
-	hdmi->sub_dev.of_node = hdmi->dev->of_node;
-	rockchip_drm_register_sub_dev(&hdmi->sub_dev);
-
-	return 0;
-}
-
-static void rk628_hdmi_bridge_detach(struct drm_bridge *bridge)
-{
-	struct rk628_hdmi *hdmi = bridge_to_hdmi(bridge);
-
-	rockchip_drm_unregister_sub_dev(&hdmi->sub_dev);
-}
-
-static const struct drm_bridge_funcs rk628_hdmi_bridge_funcs = {
-	.attach = rk628_hdmi_bridge_attach,
-	.detach = rk628_hdmi_bridge_detach,
-	.mode_set = rk628_hdmi_bridge_mode_set,
-	.enable = rk628_hdmi_bridge_enable,
-	.disable = rk628_hdmi_bridge_disable,
-};
-
-static int
-rk628_hdmi_audio_config_set(struct rk628_hdmi *hdmi, struct audio_info *audio)
-{
-	int rate, N, channel;
-
-	if (audio->channels < 3)
-		channel = I2S_CHANNEL_1_2;
-	else if (audio->channels < 5)
-		channel = I2S_CHANNEL_3_4;
-	else if (audio->channels < 7)
-		channel = I2S_CHANNEL_5_6;
-	else
-		channel = I2S_CHANNEL_7_8;
-
-	switch (audio->sample_rate) {
-	case 32000:
-		rate = AUDIO_32K;
-		N = N_32K;
-		break;
-	case 44100:
-		rate = AUDIO_441K;
-		N = N_441K;
-		break;
-	case 48000:
-		rate = AUDIO_48K;
-		N = N_48K;
-		break;
-	case 88200:
-		rate = AUDIO_882K;
-		N = N_882K;
-		break;
-	case 96000:
-		rate = AUDIO_96K;
-		N = N_96K;
-		break;
-	case 176400:
-		rate = AUDIO_1764K;
-		N = N_1764K;
-		break;
-	case 192000:
-		rate = AUDIO_192K;
-		N = N_192K;
-		break;
-	default:
-		dev_err(hdmi->dev, "[%s] not support such sample rate %d\n",
-			__func__, audio->sample_rate);
-		return -ENOENT;
-	}
-
-	/* set_audio source I2S */
-	hdmi_writeb(hdmi, HDMI_AUDIO_CTRL1, 0x01);
-	hdmi_writeb(hdmi, AUDIO_SAMPLE_RATE, rate);
-	hdmi_writeb(hdmi, AUDIO_I2S_MODE,
-		    I2S_MODE(I2S_STANDARD) | I2S_CHANNEL(channel));
-
-	hdmi_writeb(hdmi, AUDIO_I2S_MAP, 0x00);
-	hdmi_writeb(hdmi, AUDIO_I2S_SWAPS_SPDIF, 0);
-
-	/* Set N value */
-	hdmi_writeb(hdmi, AUDIO_N_H, (N >> 16) & 0x0F);
-	hdmi_writeb(hdmi, AUDIO_N_M, (N >> 8) & 0xFF);
-	hdmi_writeb(hdmi, AUDIO_N_L, N & 0xFF);
-
-	/*Set hdmi nlpcm mode to support hdmi bitstream*/
-	hdmi_writeb(hdmi, HDMI_AUDIO_CHANNEL_STATUS, AUDIO_STATUS_NLPCM(0));
-
-	return rk628_hdmi_config_audio_aai(hdmi, audio);
-}
-
-static int rk628_hdmi_audio_hw_params(struct device *dev, void *d,
-				      struct hdmi_codec_daifmt *daifmt,
-				      struct hdmi_codec_params *params)
-{
-	struct rk628_hdmi *hdmi = dev_get_drvdata(dev);
-	struct audio_info audio = {
-		.sample_width = params->sample_width,
-		.sample_rate = params->sample_rate,
-		.channels = params->channels,
-	};
-
-	if (!hdmi->hdmi_data.sink_has_audio) {
-		dev_err(hdmi->dev, "Sink do not support audio!\n");
-		return -ENODEV;
-	}
-
-	if (!hdmi->bridge.encoder->crtc)
-		return -ENODEV;
-
-	switch (daifmt->fmt) {
-	case HDMI_I2S:
-		break;
-	default:
-		dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
-		return -EINVAL;
-	}
-
-	return rk628_hdmi_audio_config_set(hdmi, &audio);
-}
-
-static void rk628_hdmi_audio_shutdown(struct device *dev, void *d)
-{
-	/* do nothing */
-}
-
-static int rk628_hdmi_audio_mute(struct device *dev, void *d, bool mute,
-				 int direction)
-{
-	struct rk628_hdmi *hdmi = dev_get_drvdata(dev);
-
-	if (!hdmi->hdmi_data.sink_has_audio) {
-		dev_err(hdmi->dev, "Sink do not support audio!\n");
-		return -ENODEV;
-	}
-
-	hdmi->audio_enable = !mute;
-
-	if (mute)
-		hdmi_modb(hdmi, HDMI_AV_MUTE, AUDIO_MUTE_MASK | AUDIO_PD_MASK,
-			  AUDIO_MUTE(1) | AUDIO_PD(1));
-	else
-		hdmi_modb(hdmi, HDMI_AV_MUTE, AUDIO_MUTE_MASK | AUDIO_PD_MASK,
-			  AUDIO_MUTE(0) | AUDIO_PD(0));
-
-	return 0;
-}
-
-static int rk628_hdmi_audio_get_eld(struct device *dev, void *d,
-				    u8 *buf, size_t len)
-{
-	struct rk628_hdmi *hdmi = dev_get_drvdata(dev);
-	struct drm_mode_config *config = &hdmi->bridge.dev->mode_config;
-	struct drm_connector *connector;
-	int ret = -ENODEV;
-
-	mutex_lock(&config->mutex);
-	list_for_each_entry(connector, &config->connector_list, head) {
-		if (hdmi->bridge.encoder == connector->encoder) {
-			memcpy(buf, connector->eld,
-			       min(sizeof(connector->eld), len));
-			ret = 0;
-		}
-	}
-	mutex_unlock(&config->mutex);
-
-	return ret;
-}
-
-static const struct hdmi_codec_ops audio_codec_ops = {
-	.hw_params = rk628_hdmi_audio_hw_params,
-	.audio_shutdown = rk628_hdmi_audio_shutdown,
-	.mute_stream = rk628_hdmi_audio_mute,
-	.get_eld = rk628_hdmi_audio_get_eld,
-	.no_capture_mute = 1,
-};
-
-static int rk628_hdmi_audio_codec_init(struct rk628_hdmi *hdmi,
-				       struct device *dev)
-{
-	struct hdmi_codec_pdata codec_data = {
-		.i2s = 1,
-		.ops = &audio_codec_ops,
-		.max_i2s_channels = 8,
-	};
-
-	hdmi->audio_enable = false;
-	hdmi->audio_pdev = platform_device_register_data(dev,
-				HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_NONE,
-				&codec_data, sizeof(codec_data));
-
-	return PTR_ERR_OR_ZERO(hdmi->audio_pdev);
-}
-
-static irqreturn_t rk628_hdmi_irq(int irq, void *dev_id)
-{
-	struct rk628_hdmi *hdmi = dev_id;
-	u8 interrupt;
-
-	interrupt = hdmi_readb(hdmi, HDMI_STATUS);
-	if (!(interrupt & INT_HOTPLUG))
-		return IRQ_HANDLED;
-
-	hdmi_modb(hdmi, HDMI_STATUS, INT_HOTPLUG, INT_HOTPLUG);
-	if (hdmi->connector.dev)
-		drm_helper_hpd_irq_event(hdmi->connector.dev);
-
-	return IRQ_HANDLED;
-}
-
-static int rk628_hdmi_i2c_read(struct rk628_hdmi *hdmi, struct i2c_msg *msgs)
-{
-	int length = msgs->len;
-	u8 *buf = msgs->buf;
-	int i;
-	u32 c;
-
-	for (i = 0; i < 5; i++) {
-		msleep(20);
-		c = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
-		if (c & INT_EDID_READY)
-			break;
-	}
-	if ((c & INT_EDID_READY) == 0)
-		return -EAGAIN;
-
-	while (length--)
-		*buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
-
-	return 0;
-}
-
-static int rk628_hdmi_i2c_write(struct rk628_hdmi *hdmi, struct i2c_msg *msgs)
-{
-	/*
-	 * The DDC module only support read EDID message, so
-	 * we assume that each word write to this i2c adapter
-	 * should be the offset of EDID word address.
-	 */
-	if ((msgs->len != 1) ||
-	    ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR)))
-		return -EINVAL;
-
-	if (msgs->addr == DDC_ADDR)
-		hdmi->i2c->ddc_addr = msgs->buf[0];
-	if (msgs->addr == DDC_SEGMENT_ADDR) {
-		hdmi->i2c->segment_addr = msgs->buf[0];
-		return 0;
-	}
-
-	/* Set edid fifo first addr */
-	hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
-
-	/* Set edid word address 0x00/0x80 */
-	hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
-
-	/* Set edid segment pointer */
-	hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
-
-	return 0;
-}
-
-static int rk628_hdmi_i2c_xfer(struct i2c_adapter *adap,
-			       struct i2c_msg *msgs, int num)
-{
-	struct rk628_hdmi *hdmi = i2c_get_adapdata(adap);
-	struct rk628_hdmi_i2c *i2c = hdmi->i2c;
-	int i, ret = 0;
-
-	mutex_lock(&i2c->lock);
-
-	hdmi->i2c->ddc_addr = 0;
-	hdmi->i2c->segment_addr = 0;
-
-	/* Clear the EDID interrupt flag and unmute the interrupt */
-	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, INT_EDID_READY);
-	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, INT_EDID_READY_MASK);
-
-	for (i = 0; i < num; i++) {
-		dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
-			i + 1, num, msgs[i].len, msgs[i].flags);
-
-		if (msgs[i].flags & I2C_M_RD)
-			ret = rk628_hdmi_i2c_read(hdmi, &msgs[i]);
-		else
-			ret = rk628_hdmi_i2c_write(hdmi, &msgs[i]);
-
-		if (ret < 0)
-			break;
-	}
-
-	if (!ret)
-		ret = num;
-
-	/* Mute HDMI EDID interrupt */
-	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
-	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, INT_EDID_READY);
-
-	mutex_unlock(&i2c->lock);
-
-	return ret;
-}
-
-static u32 rk628_hdmi_i2c_func(struct i2c_adapter *adapter)
-{
-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-static const struct i2c_algorithm rk628_hdmi_algorithm = {
-	.master_xfer	= rk628_hdmi_i2c_xfer,
-	.functionality	= rk628_hdmi_i2c_func,
-};
-
-static struct i2c_adapter *rk628_hdmi_i2c_adapter(struct rk628_hdmi *hdmi)
-{
-	struct i2c_adapter *adap;
-	struct rk628_hdmi_i2c *i2c;
-	int ret;
-
-	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
-	if (!i2c)
-		return ERR_PTR(-ENOMEM);
-
-	mutex_init(&i2c->lock);
-
-	adap = &i2c->adap;
-	adap->class = I2C_CLASS_DDC;
-	adap->owner = THIS_MODULE;
-	adap->dev.parent = hdmi->dev;
-	adap->dev.of_node = hdmi->dev->of_node;
-	adap->algo = &rk628_hdmi_algorithm;
-	strlcpy(adap->name, "RK628 HDMI", sizeof(adap->name));
-	i2c_set_adapdata(adap, hdmi);
-
-	ret = i2c_add_adapter(adap);
-	if (ret) {
-		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
-		devm_kfree(hdmi->dev, i2c);
-		return ERR_PTR(ret);
-	}
-
-	hdmi->i2c = i2c;
-
-	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
-
-	return adap;
-}
-
-static const struct regmap_range rk628_hdmi_volatile_reg_ranges[] = {
-	regmap_reg_range(HDMI_BASE, HDMI_MAX_REG),
-};
-
-static const struct regmap_access_table rk628_hdmi_volatile_regs = {
-	.yes_ranges = rk628_hdmi_volatile_reg_ranges,
-	.n_yes_ranges = ARRAY_SIZE(rk628_hdmi_volatile_reg_ranges),
-};
-
-static bool rk628_is_read_enable_reg(struct device *dev, unsigned int reg)
-{
-	if (reg >= HDMI_BASE && reg <= HDMI_MAX_REG)
-		return true;
-
-	return false;
-}
-
-static bool rk628_hdmi_register_volatile(struct device *dev, unsigned int reg)
-{
-	switch (reg) {
-	case HDMI_REG(HDMI_EDID_FIFO_ADDR):
-	case HDMI_REG(HDMI_INTERRUPT_STATUS1):
-	case HDMI_REG(HDMI_INTERRUPT_STATUS2):
-	case HDMI_REG(HDMI_STATUS):
-	case HDMI_REG(HDMI_CEC_TX_INT):
-	case HDMI_REG(HDMI_CEC_RX_INT):
-		return true;
-	default:
-		return false;
-	}
-}
-
-static const struct regmap_config rk628_hdmi_regmap_config = {
-	.name = "hdmi",
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = HDMI_REG_STRIDE,
-	.max_register = HDMI_MAX_REG,
-	.cache_type = REGCACHE_RBTREE,
-	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
-	.val_format_endian = REGMAP_ENDIAN_LITTLE,
-	.readable_reg = rk628_is_read_enable_reg,
-	.writeable_reg = rk628_is_read_enable_reg,
-	.volatile_reg = rk628_hdmi_register_volatile,
-	.rd_table = &rk628_hdmi_volatile_regs,
-};
-
-static int rk628_hdmi_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_hdmi *hdmi;
-	int irq;
-	int ret;
-
-	if (!of_device_is_available(dev->of_node))
-		return -ENODEV;
-
-	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
-	if (!hdmi)
-		return -ENOMEM;
-
-	hdmi->grf = rk628->grf;
-	if (!hdmi->grf)
-		return -ENODEV;
-
-	hdmi->dev = dev;
-	hdmi->parent = rk628;
-	platform_set_drvdata(pdev, hdmi);
-
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
-
-	hdmi->regmap = devm_regmap_init_i2c(rk628->client,
-					    &rk628_hdmi_regmap_config);
-	if (IS_ERR(hdmi->regmap)) {
-		ret = PTR_ERR(hdmi->regmap);
-		dev_err(dev, "failed to allocate register map: %d\n", ret);
-		return PTR_ERR(hdmi->regmap);
-	}
-
-	hdmi->dclk = devm_clk_get(dev, "dclk");
-	if (IS_ERR(hdmi->dclk)) {
-		dev_err(dev, "Unable to get dclk %ld\n",
-			PTR_ERR(hdmi->dclk));
-		return PTR_ERR(hdmi->dclk);
-	}
-
-	hdmi->pclk = devm_clk_get(dev, "pclk");
-	if (IS_ERR(hdmi->pclk)) {
-		dev_err(dev, "Unable to get pclk %ld\n",
-			PTR_ERR(hdmi->pclk));
-		return PTR_ERR(hdmi->pclk);
-	}
-	clk_prepare_enable(hdmi->pclk);
-
-	/* hdmitx vclk pllref select Pin_vclk */
-	regmap_update_bits(hdmi->grf, GRF_POST_PROC_CON,
-			   SW_HDMITX_VCLK_PLLREF_SEL_MASK,
-			   SW_HDMITX_VCLK_PLLREF_SEL(1));
-	/* set output mode to HDMI */
-	regmap_update_bits(hdmi->grf, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
-			   SW_OUTPUT_MODE(OUTPUT_MODE_HDMI));
-
-	rk628_hdmi_reset(hdmi);
-
-	hdmi->ddc = rk628_hdmi_i2c_adapter(hdmi);
-	if (IS_ERR(hdmi->ddc)) {
-		ret = PTR_ERR(hdmi->ddc);
-		hdmi->ddc = NULL;
-		goto fail;
-	}
-
-	/*
-	 * When IP controller haven't configured to an accurate video
-	 * timing, then the TMDS clock source would be switched to
-	 * PCLK_HDMI, so we need to init the TMDS rate to PCLK rate,
-	 * and reconfigure the DDC clock.
-	 */
-	hdmi->tmds_rate = clk_get_rate(hdmi->pclk);
-
-	rk628_hdmi_i2c_init(hdmi);
-
-	rk628_hdmi_audio_codec_init(hdmi, dev);
-
-	ret = devm_request_threaded_irq(dev, irq, NULL,
-					rk628_hdmi_irq,
-					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-					dev_name(dev), hdmi);
-	if (ret) {
-		dev_err(dev, "failed to request hdmi irq: %d\n", ret);
-		goto fail;
-	}
-
-	/* Unmute hotplug interrupt */
-	hdmi_modb(hdmi, HDMI_STATUS, MASK_INT_HOTPLUG_MASK,
-		  MASK_INT_HOTPLUG(1));
-	hdmi->bridge.funcs = &rk628_hdmi_bridge_funcs;
-	hdmi->bridge.of_node = dev->of_node;
-	drm_bridge_add(&hdmi->bridge);
-
-	hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, rk628_hdmi_cable);
-	if (IS_ERR(hdmi->extcon)) {
-		dev_err(hdmi->dev, "allocate extcon failed\n");
-		ret = PTR_ERR(hdmi->extcon);
-		goto fail;
-	}
-
-	ret = devm_extcon_dev_register(hdmi->dev, hdmi->extcon);
-	if (ret) {
-		dev_err(dev, "failed to register extcon: %d\n", ret);
-		goto fail;
-	}
-
-	ret = extcon_set_property_capability(hdmi->extcon, EXTCON_DISP_HDMI,
-					     EXTCON_PROP_DISP_HPD);
-	if (ret) {
-		dev_err(dev, "failed to set USB property capability: %d\n",
-			ret);
-		goto fail;
-	}
-
-	return 0;
-
-fail:
-	clk_disable_unprepare(hdmi->pclk);
-	return ret;
-}
-
-static int rk628_hdmi_remove(struct platform_device *pdev)
-{
-	struct rk628_hdmi *hdmi = platform_get_drvdata(pdev);
-
-	drm_bridge_remove(&hdmi->bridge);
-	i2c_put_adapter(hdmi->ddc);
-	clk_disable_unprepare(hdmi->pclk);
-
-	return 0;
-}
-
-static const struct of_device_id rk628_hdmi_dt_ids[] = {
-	{ .compatible = "rockchip,rk628-hdmi", },
-	{},
-};
-MODULE_DEVICE_TABLE(of, rk628_hdmi_dt_ids);
-
-static struct platform_driver rk628_hdmi_driver = {
-	.probe  = rk628_hdmi_probe,
-	.remove = rk628_hdmi_remove,
-	.driver = {
-		.name = "rk628-hdmi",
-		.of_match_table = rk628_hdmi_dt_ids,
-	},
-};
-
-module_platform_driver(rk628_hdmi_driver);
-
-MODULE_AUTHOR("Chen Shunqing <csq@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 HDMI driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c b/drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c
deleted file mode 100755
index b74ea238dc00..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c
+++ /dev/null
@@ -1,980 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Algea Cao <algea.cao@rock-chips.com>
- */
-
-#include <linux/clk.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/timer.h>
-#include <linux/workqueue.h>
-#include <linux/mfd/rk628.h>
-#include <linux/phy/phy.h>
-
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_print.h>
-#include <drm/display/drm_dp_helper.h>
-#include <drm/drm_of.h>
-
-#define REG(x)                             ((x) + 0x30000)
-#define HDMI_RX_HDMI_SETUP_CTRL            REG(0x0000)
-#define HOT_PLUG_DETECT_MASK               BIT(0)
-#define HOT_PLUG_DETECT(x)                 UPDATE(x, 0, 0)
-#define HDMI_RX_HDMI_OVR_CTRL              REG(0x0004)
-#define HDMI_RX_HDMI_TIMER_CTRL            REG(0x0008)
-#define HDMI_RX_HDMI_RES_OVR               REG(0x0010)
-#define HDMI_RX_HDMI_RES_STS               REG(0x0014)
-#define HDMI_RX_HDMI_PLL_CTRL              REG(0x0018)
-#define HDMI_RX_HDMI_PLL_FRQSET1           REG(0x001c)
-#define HDMI_RX_HDMI_PLL_FRQSET2           REG(0x0020)
-#define HDMI_RX_HDMI_PLL_PAR1              REG(0x0024)
-#define HDMI_RX_HDMI_PLL_PAR2              REG(0x0028)
-#define HDMI_RX_HDMI_PLL_PAR3              REG(0x002c)
-#define HDMI_RX_HDMI_PLL_LCK_STS           REG(0x0030)
-#define HDMI_RX_HDMI_CLK_CTRL              REG(0x0034)
-#define HDMI_RX_HDMI_PCB_CTRL              REG(0x0038)
-#define SEL_PIXCLKSRC_MASK                 GENMASK(19, 18)
-#define SEL_PIXCLKSRC(x)                   UPDATE(x, 19, 18)
-#define HDMI_RX_HDMI_PHS_CTR               REG(0x0040)
-#define HDMI_RX_HDMI_PHS_USED              REG(0x0044)
-#define HDMI_RX_HDMI_MISC_CTRL             REG(0x0048)
-#define HDMI_RX_HDMI_EQOFF_CTRL            REG(0x004c)
-#define HDMI_RX_HDMI_EQGAIN_CTRL           REG(0x0050)
-#define HDMI_RX_HDMI_EQCAL_STS             REG(0x0054)
-#define HDMI_RX_HDMI_EQRESULT              REG(0x0058)
-#define HDMI_RX_HDMI_EQ_MEAS_CTRL          REG(0x005c)
-#define HDMI_RX_HDMI_WR_CFG                REG(0x0060)
-#define HDMI_RX_HDMI_CTRL                  REG(0x0064)
-#define HDMI_RX_HDMI_MODE_RECOVER          REG(0x0080)
-#define PREAMBLE_CNT_LIMIT_MASK            GENMASK(31, 27)
-#define PREAMBLE_CNT_LIMIT(x)              UPDATE(x, 31, 27)
-#define OESSCTL3_THR_MASK                  GENMASK(20, 19)
-#define OESSCTL3_THR(x)                    UPDATE(x, 20, 19)
-#define SPIKE_FILTER_EN_MASK               BIT(18)
-#define SPIKE_FILTER_EN(x)                 UPDATE(x, 18, 18)
-#define DVI_MODE_HYST_MASK                 GENMASK(17, 13)
-#define DVI_MODE_HYST(x)                   UPDATE(x, 17, 13)
-#define HDMI_MODE_HYST_MASK                GENMASK(12, 8)
-#define HDMI_MODE_HYST(x)                  UPDATE(x, 12, 8)
-#define HDMI_MODE_MASK                     GENMASK(7, 6)
-#define HDMI_MODE(x)                       UPDATE(x, 7, 6)
-#define GB_DET_MASK                        GENMASK(5, 4)
-#define GB_DET(x)                          UPDATE(x, 5, 4)
-#define EESS_OESS_MASK                     GENMASK(3, 2)
-#define EESS_OESS(x)                       UPDATE(x, 3, 2)
-#define SEL_CTL01_MASK                     GENMASK(1, 0)
-#define SEL_CTL01(x)                       UPDATE(x, 1, 0)
-#define HDMI_RX_HDMI_ERROR_PROTECT         REG(0x0084)
-#define RG_BLOCK_OFF_MASK                  BIT(20)
-#define RG_BLOCK_OFF(x)                    UPDATE(x, 20, 20)
-#define BLOCK_OFF_MASK                     BIT(19)
-#define BLOCK_OFF(x)                       UPDATE(x, 19, 19)
-#define VALID_MODE_MASK                    GENMASK(18, 16)
-#define VALID_MODE(x)                      UPDATE(x, 18, 16)
-#define CTRL_FILT_SEN_MASK                 GENMASK(13, 12)
-#define CTRL_FILT_SEN(x)                   UPDATE(x, 13, 12)
-#define VS_FILT_SENS_MASK                  GENMASK(11, 10)
-#define VS_FILT_SENS(x)                    UPDATE(x, 11, 10)
-#define HS_FILT_SENS_MASK                  GENMASK(9, 8)
-#define HS_FILT_SENS(x)                    UPDATE(x, 9, 8)
-#define DE_MEASURE_MODE_MASK               GENMASK(7, 6)
-#define DE_MEASURE_MODE(x)                 UPDATE(x, 7, 6)
-#define DE_REGEN_MASK                      BIT(5)
-#define DE_REGEN(x)                        UPDATE(x, 5, 5)
-#define DE_FILTER_SENS_MASK                GENMASK(4, 3)
-#define DE_FILTER_SENS(x)                  UPDATE(x, 4, 3)
-#define HDMI_RX_HDMI_ERD_STS               REG(0x0088)
-#define HDMI_RX_HDMI_SYNC_CTRL             REG(0x0090)
-#define VS_POL_ADJ_MODE_MASK               GENMASK(4, 3)
-#define VS_POL_ADJ_MODE(x)                 UPDATE(x, 4, 3)
-#define HS_POL_ADJ_MODE_MASK               GENMASK(2, 1)
-#define HS_POL_ADJ_MODE(x)                 UPDATE(x, 2, 1)
-#define HDMI_RX_HDMI_CKM_EVLTM             REG(0x0094)
-#define LOCK_HYST_MASK                     GENMASK(21, 20)
-#define LOCK_HYST(x)                       UPDATE(x, 21, 20)
-#define CLK_HYST_MASK                      GENMASK(18, 16)
-#define CLK_HYST(x)                        UPDATE(x, 18, 16)
-#define EVAL_TIME_MASK                     GENMASK(15, 4)
-#define EVAL_TIME(x)                       UPDATE(x, 15, 4)
-#define HDMI_RX_HDMI_CKM_F                 REG(0x0098)
-#define HDMIRX_MAXFREQ_MASK                GENMASK(31, 16)
-#define HDMIRX_MAXFREQ(x)                  UPDATE(x, 31, 16)
-#define MINFREQ_MASK                       GENMASK(15, 0)
-#define MINFREQ(x)                         UPDATE(x, 15, 0)
-#define HDMI_RX_HDMI_CKM_RESULT            REG(0x009c)
-#define HDMI_RX_HDMI_PVO_CONFIG            REG(0x00a0)
-#define HDMI_RX_HDMI_RESMPL_CTRL           REG(0x00a4)
-#define MAN_VID_DEREPEAT_MASK              GENMASK(4, 1)
-#define MAN_VID_DEREPEAT(x)                UPDATE(x, 4, 1)
-#define AUTO_DEREPEAT_MASK                 BIT(0)
-#define AUTO_DEREPEAT(x)                   UPDATE(x, 0, 0)
-#define HDMI_RX_HDMI_DCM_CTRL              REG(0x00a8)
-#define DCM_DEFAULT_PHASE_MASK             BIT(18)
-#define DCM_DEFAULT_PHASE(x)               UPDATE(x, 18, 18)
-#define DCM_COLOUR_DEPTH_SEL_MASK          BIT(12)
-#define DCM_COLOUR_DEPTH_SEL(x)            UPDATE(x, 12, 12)
-#define DCM_COLOUR_DEPTH_MASK              GENMASK(11, 8)
-#define DCM_COLOUR_DEPTH(x)                UPDATE(x, 11, 8)
-#define DCM_GCP_ZERO_FIELDS_MASK           GENMASK(5, 2)
-#define DCM_GCP_ZERO_FIELDS(x)             UPDATE(x, 5, 2)
-#define HDMI_RX_HDMI_VM_CFG_CH_0_1         REG(0x00b0)
-#define HDMI_RX_HDMI_VM_CFG_CH2            REG(0x00b4)
-#define HDMI_RX_HDMI_SPARE                 REG(0x00b8)
-#define HDMI_RX_HDMI_STS                   REG(0x00bc)
-#define HDMI_RX_HDCP_CTRL                  REG(0x00c0)
-#define HDCP_ENABLE_MASK                   BIT(24)
-#define HDCP_ENABLE(x)                     UPDATE(x, 24, 24)
-#define FREEZE_HDCP_FSM_MASK               BIT(21)
-#define FREEZE_HDCP_FSM(x)                 UPDATE(x, 21, 21)
-#define FREEZE_HDCP_STATE_MASK             GENMASK(20, 15)
-#define FREEZE_HDCP_STATE(x)               UPDATE(x, 20, 15)
-#define HDCP_CTL_MASK                      GENMASK(9, 8)
-#define HDCP_CTL(x)                        UPDATE(x, 9, 8)
-#define HDCP_RI_RATE_MASK                  GENMASK(7, 6)
-#define HDCP_RI_RATE(x)                    UPDATE(x, 7, 6)
-#define KEY_DECRYPT_ENABLE_MASK            BIT(1)
-#define KEY_DECRYPT_ENABLE(x)              UPDATE(x, 1, 1)
-#define HDCP_ENC_EN_MASK                   BIT(0)
-#define HDCP_ENC_EN(x)                     UPDATE(x, 0, 0)
-#define HDMI_RX_HDCP_SETTINGS              REG(0x00c4)
-#define HDMI_RX_HDCP_SEED                  REG(0x00c8)
-#define HDMI_RX_HDCP_BKSV1                 REG(0x00cc)
-#define HDMI_RX_HDCP_BKSV0                 REG(0x00d0)
-#define HDMI_RX_HDCP_KIDX                  REG(0x00d4)
-#define HDMI_RX_HDCP_KEY1                  REG(0x00d8)
-#define HDMI_RX_HDCP_KEY0                  REG(0x00dc)
-#define HDMI_RX_HDCP_DBG                   REG(0x00e0)
-#define HDMI_RX_HDCP_AKSV1                 REG(0x00e4)
-#define HDMI_RX_HDCP_AKSV0                 REG(0x00e8)
-#define HDMI_RX_HDCP_AN1                   REG(0x00ec)
-#define HDMI_RX_HDCP_AN0                   REG(0x00f0)
-#define HDMI_RX_HDCP_EESS_WOO              REG(0x00f4)
-#define HDMI_RX_HDCP_I2C_TIMEOUT           REG(0x00f8)
-#define HDMI_RX_HDCP_STS                   REG(0x00fc)
-#define HDMI_RX_MD_HCTRL1                  REG(0x0140)
-#define HACT_PIX_ITH_MASK                  GENMASK(10, 8)
-#define HACT_PIX_ITH(x)                    UPDATE(x, 10, 8)
-#define HACT_PIX_SRC_MASK                  BIT(5)
-#define HACT_PIX_SRC(x)                    UPDATE(x, 5, 5)
-#define HTOT_PIX_SRC_MASK                  BIT(4)
-#define HTOT_PIX_SRC(x)                    UPDATE(x, 4, 4)
-#define HDMI_RX_MD_HCTRL2                  REG(0x0144)
-#define HS_CLK_ITH_MASK                    GENMASK(14, 12)
-#define HS_CLK_ITH(x)                      UPDATE(x, 14, 12)
-#define HTOT32_CLK_ITH_MASK                GENMASK(9, 8)
-#define HTOT32_CLK_ITH(x)                  UPDATE(x, 9, 8)
-#define VS_ACT_TIME_MASK                   BIT(5)
-#define VS_ACT_TIME(x)                     UPDATE(x, 5, 5)
-#define HS_ACT_TIME_MASK                   GENMASK(4, 3)
-#define HS_ACT_TIME(x)                     UPDATE(x, 4, 3)
-#define H_START_POS_MASK                   GENMASK(1, 0)
-#define H_START_POS(x)                     UPDATE(x, 1, 0)
-#define HDMI_RX_MD_HT0                     REG(0x0148)
-#define HDMI_RX_MD_HT1                     REG(0x014c)
-#define HDMI_RX_MD_HACT_PX                 REG(0x0150)
-#define HDMI_RX_MD_HACT_RSV                REG(0x0154)
-#define HDMI_RX_MD_VCTRL                   REG(0x0158)
-#define V_OFFS_LIN_MODE_MASK               BIT(4)
-#define V_OFFS_LIN_MODE(x)                 UPDATE(x, 4, 4)
-#define V_EDGE_MASK                        BIT(1)
-#define V_EDGE(x)                          UPDATE(x, 1, 1)
-#define V_MODE_MASK                        BIT(0)
-#define V_MODE(x)                          UPDATE(x, 0, 0)
-#define HDMI_RX_MD_VSC                     REG(0x015c)
-#define HDMI_RX_MD_VTC                     REG(0x0160)
-#define HDMI_RX_MD_VOL                     REG(0x0164)
-#define HDMI_RX_MD_VAL                     REG(0x0168)
-#define HDMI_RX_MD_VTH                     REG(0x016c)
-#define VOFS_LIN_ITH_MASK                  GENMASK(11, 10)
-#define VOFS_LIN_ITH(x)                    UPDATE(x, 11, 10)
-#define VACT_LIN_ITH_MASK                  GENMASK(9, 8)
-#define VACT_LIN_ITH(x)                    UPDATE(x, 9, 8)
-#define VTOT_LIN_ITH_MASK                  GENMASK(7, 6)
-#define VTOT_LIN_ITH(x)                    UPDATE(x, 7, 6)
-#define VS_CLK_ITH_MASK                    GENMASK(5, 3)
-#define VS_CLK_ITH(x)                      UPDATE(x, 5, 3)
-#define VTOT_CLK_ITH_MASK                  GENMASK(2, 0)
-#define VTOT_CLK_ITH(x)                    UPDATE(x, 2, 0)
-#define HDMI_RX_MD_VTL                     REG(0x0170)
-#define HDMI_RX_MD_IL_CTRL                 REG(0x0174)
-#define HDMI_RX_MD_IL_SKEW                 REG(0x0178)
-#define HDMI_RX_MD_IL_POL                  REG(0x017c)
-#define FAFIELDDET_EN_MASK                 BIT(2)
-#define FAFIELDDET_EN(x)                   UPDATE(x, 2, 2)
-#define FIELD_POL_MODE_MASK                GENMASK(1, 0)
-#define FIELD_POL_MODE(x)                  UPDATE(x, 1, 0)
-#define HDMI_RX_MD_STS                     REG(0x0180)
-#define HDMI_RX_AUD_CTRL                   REG(0x0200)
-#define HDMI_RX_AUD_PLL_CTRL               REG(0x0208)
-#define PLL_LOCK_TOGGLE_DIV_MASK           GENMASK(27, 24)
-#define PLL_LOCK_TOGGLE_DIV(x)             UPDATE(x, 27, 24)
-#define HDMI_RX_AUD_CLK_CTRL               REG(0x0214)
-#define CTS_N_REF_MASK                     BIT(4)
-#define CTS_N_REF(x)                       UPDATE(x, 4, 4)
-#define HDMI_RX_AUD_CLK_STS                REG(0x023c)
-#define HDMI_RX_AUD_FIFO_CTRL              REG(0x0240)
-#define AFIF_SUBPACKET_DESEL_MASK          GENMASK(27, 24)
-#define AFIF_SUBPACKET_DESEL(x)            UPDATE(x, 27, 24)
-#define AFIF_SUBPACKETS_MASK               BIT(16)
-#define AFIF_SUBPACKETS(x)                 UPDATE(x, 16, 16)
-#define MSA_CHANNEL_DESELECT               BIT(24)
-#define HDMI_RX_AUD_FIFO_TH                REG(0x0244)
-#define AFIF_TH_START_MASK                 GENMASK(26, 18)
-#define AFIF_TH_START(x)                   UPDATE(x, 26, 18)
-#define AFIF_TH_MAX_MASK                   GENMASK(17, 9)
-#define AFIF_TH_MAX(x)                     UPDATE(x, 17, 9)
-#define AFIF_TH_MIN_MASK                   GENMASK(8, 0)
-#define AFIF_TH_MIN(x)                     UPDATE(x, 8, 0)
-#define HDMI_RX_AUD_FIFO_FILL_S            REG(0x0248)
-#define HDMI_RX_AUD_FIFO_CLR_MM            REG(0x024c)
-#define HDMI_RX_AUD_FIFO_FILLSTS           REG(0x0250)
-#define HDMI_RX_AUD_CHEXTR_CTRL            REG(0x0254)
-#define AUD_LAYOUT_CTRL(x)                 UPDATE(x, 1, 0)
-#define HDMI_RX_AUD_MUTE_CTRL              REG(0x0258)
-#define APPLY_INT_MUTE_MASK                BIT(31)
-#define APPLY_INT_MUTE(x)                  UPDATE(x, 31, 31)
-#define APORT_SHDW_CTRL_MASK               GENMASK(22, 21)
-#define APORT_SHDW_CTRL(x)                 UPDATE(x, 22, 21)
-#define AUTO_ACLK_MUTE_MASK                GENMASK(20, 19)
-#define AUTO_ACLK_MUTE(x)                  UPDATE(x, 20, 19)
-#define AUD_MUTE_SPEED_MASK                GENMASK(16, 10)
-#define AUD_MUTE_SPEED(x)                  UPDATE(x, 16, 10)
-#define AUD_AVMUTE_EN_MASK                 BIT(7)
-#define AUD_AVMUTE_EN(x)                   UPDATE(x, 7, 7)
-#define AUD_MUTE_SEL_MASK                  GENMASK(6, 5)
-#define AUD_MUTE_SEL(x)                    UPDATE(x, 6, 5)
-#define AUD_MUTE_MODE_MASK                 GENMASK(4, 3)
-#define AUD_MUTE_MODE(x)                   UPDATE(x, 4, 3)
-#define HDMI_RX_AUD_FIFO_FILLSTS1          REG(0x025c)
-#define HDMI_RX_AUD_SAO_CTRL               REG(0x0260)
-#define I2S_LPCM_BPCUV_MASK                BIT(11)
-#define I2S_LPCM_BPCUV(x)                  UPDATE(x, 11, 11)
-#define I2S_32_16_MASK                     BIT(0)
-#define I2S_32_16(x)                       UPDATE(x, 0, 0)
-#define HDMI_RX_AUD_PAO_CTRL               REG(0x0264)
-#define PAO_RATE_MASK                      GENMASK(17, 16)
-#define PAO_RATE(x)                        UPDATE(x, 17, 16)
-#define HDMI_RX_AUD_SPARE                  REG(0x0268)
-#define HDMI_RX_AUD_FIFO_STS               REG(0x027c)
-#define HDMI_RX_AUDPLL_GEN_CTS             REG(0x0280)
-#define AUDPLL_CTS_MANUAL(x)               UPDATE(x, 19, 0)
-#define HDMI_RX_AUDPLL_GEN_N               REG(0x0284)
-#define AUDPLL_N_MANUAL(x)                 UPDATE(x, 19, 0)
-#define HDMI_RX_AUDPLL_GEN_CTRL_RW1        REG(0x0288)
-#define HDMI_RX_AUDPLL_GEN_CTRL_RW2        REG(0x028c)
-#define HDMI_RX_AUDPLL_GEN_CTRL_W1         REG(0x0298)
-#define HDMI_RX_AUDPLL_GEN_STS_RO1         REG(0x02a0)
-#define HDMI_RX_AUDPLL_GEN_STS_RO2         REG(0x02a4)
-#define HDMI_RX_AUDPLL_SC_NDIVCTSTH        REG(0x02a8)
-#define HDMI_RX_AUDPLL_SC_CTS              REG(0x02ac)
-#define HDMI_RX_AUDPLL_SC_N                REG(0x02b0)
-#define HDMI_RX_AUDPLL_SC_CTRL             REG(0x02b4)
-#define HDMI_RX_AUDPLL_SC_STS1             REG(0x02b8)
-#define HDMI_RX_AUDPLL_SC_STS2             REG(0x02bc)
-#define HDMI_RX_SNPS_PHYG3_CTRL            REG(0x02c0)
-#define PORTSELECT_MASK                    GENMASK(3, 2)
-#define PORTSELECT(x)                      UPDATE(x, 3, 2)
-#define HDMI_RX_I2CM_PHYG3_SLAVE           REG(0x02c4)
-#define HDMI_RX_I2CM_PHYG3_ADDRESS         REG(0x02c8)
-#define HDMI_RX_I2CM_PHYG3_DATAO           REG(0x02cc)
-#define HDMI_RX_I2CM_PHYG3_DATAI           REG(0x02d0)
-#define HDMI_RX_I2CM_PHYG3_OPERATION       REG(0x02d4)
-#define HDMI_RX_I2CM_PHYG3_MODE            REG(0x02d8)
-#define HDMI_RX_I2CM_PHYG3_SOFTRST         REG(0x02dc)
-#define HDMI_RX_I2CM_PHYG3_SS_CNTS         REG(0x02e0)
-#define HDMI_RX_I2CM_PHYG3_FS_HCNT         REG(0x02e4)
-#define HDMI_RX_JTAG_CONF                  REG(0x02ec)
-#define HDMI_RX_JTAG_TAP_TCLK              REG(0x02f0)
-#define HDMI_RX_JTAG_TAP_IN                REG(0x02f4)
-#define HDMI_RX_JTAG_TAP_OUT               REG(0x02f8)
-#define HDMI_RX_JTAG_ADDR                  REG(0x02fc)
-#define HDMI_RX_PDEC_CTRL                  REG(0x0300)
-#define PFIFO_SCORE_FILTER_EN              BIT(31)
-#define PFIFO_SCORE_HDP_IF                 BIT(29)
-#define PFIFO_SCORE_AMP_IF                 BIT(28)
-#define PFIFO_SCORE_NTSCVBI_IF             BIT(27)
-#define PFIFO_SCORE_MPEGS_IF               BIT(26)
-#define PFIFO_SCORE_AUD_IF                 BIT(25)
-#define PFIFO_SCORE_SPD_IF                 BIT(24)
-#define PFIFO_SCORE_AVI_IF                 BIT(23)
-#define PFIFO_SCORE_VS_IF                  BIT(22)
-#define PFIFO_SCORE_GMTP                   BIT(21)
-#define PFIFO_SCORE_ISRC2                  BIT(20)
-#define PFIFO_SCORE_ISRC1                  BIT(19)
-#define PFIFO_SCORE_ACP                    BIT(18)
-#define PFIFO_SCORE_GCP                    BIT(17)
-#define PFIFO_SCORE_ACR                    BIT(16)
-#define GCP_GLOBAVMUTE                     BIT(15)
-#define PD_FIFO_WE                         BIT(4)
-#define PDEC_BCH_EN                        BIT(0)
-#define HDMI_RX_PDEC_FIFO_CFG              REG(0x0304)
-#define PD_FIFO_TH_START_MASK              GENMASK(29, 20)
-#define PD_FIFO_TH_START(x)                UPDATE(x, 29, 20)
-#define PD_FIFO_TH_MAX_MASK                GENMASK(19, 10)
-#define PD_FIFO_TH_MAX(x)                  UPDATE(x, 19, 10)
-#define PD_FIFO_TH_MIN_MASK                GENMASK(9, 0)
-#define PD_FIFO_TH_MIN(x)                  UPDATE(x, 9, 0)
-#define HDMI_RX_PDEC_FIFO_STS              REG(0x0308)
-#define HDMI_RX_PDEC_FIFO_DATA             REG(0x030c)
-#define HDMI_RX_PDEC_AUDIODET_CTRL         REG(0x0310)
-#define AUDIODET_THRESHOLD_MASK            GENMASK(13, 9)
-#define AUDIODET_THRESHOLD(x)              UPDATE(x, 13, 9)
-#define HDMI_RX_PDEC_DBG_ACP               REG(0x031c)
-#define HDMI_RX_PDEC_DBG_ERR_CORR          REG(0x0320)
-#define HDMI_RX_PDEC_FIFO_STS1             REG(0x0324)
-#define HDMI_RX_PDEC_ACRM_CTRL             REG(0x0330)
-#define DELTACTS_IRQTRIG_MASK              GENMASK(4, 2)
-#define DELTACTS_IRQTRIG(x)                UPDATE(x, 4, 2)
-#define HDMI_RX_PDEC_ACRM_MAX              REG(0x0334)
-#define HDMI_RX_PDEC_ACRM_MIN              REG(0x0338)
-#define HDMI_RX_PDEC_ERR_FILTER            REG(0x033c)
-#define HDMI_RX_PDEC_ASP_CTRL              REG(0x0340)
-#define HDMI_RX_PDEC_ASP_ERR               REG(0x0344)
-#define HDMI_RX_PDEC_STS                   REG(0x0360)
-#define HDMI_RX_PDEC_AUD_STS               REG(0x0364)
-#define HDMI_RX_PDEC_VSI_PAYLOAD0          REG(0x0368)
-#define HDMI_RX_PDEC_VSI_PAYLOAD1          REG(0x036c)
-#define HDMI_RX_PDEC_VSI_PAYLOAD2          REG(0x0370)
-#define HDMI_RX_PDEC_VSI_PAYLOAD3          REG(0x0374)
-#define HDMI_RX_PDEC_VSI_PAYLOAD4          REG(0x0378)
-#define HDMI_RX_PDEC_VSI_PAYLOAD5          REG(0x037c)
-#define HDMI_RX_PDEC_GCP_AVMUTE            REG(0x0380)
-#define PKTDEC_GCP_CD_MASK                 GENMASK(7, 4)
-#define HDMI_RX_PDEC_ACR_CTS               REG(0x0390)
-#define HDMI_RX_PDEC_ACR_N                 REG(0x0394)
-#define HDMI_RX_PDEC_AVI_HB                REG(0x03a0)
-#define HDMI_RX_PDEC_AVI_PB                REG(0x03a4)
-#define VID_IDENT_CODE_VIC7                BIT(31)
-#define VID_IDENT_CODE                     GENMASK(30, 24)
-#define VIDEO_FORMAT                       GENMASK(6, 5)
-#define HDMI_RX_PDEC_AVI_TBB               REG(0x03a8)
-#define HDMI_RX_PDEC_AVI_LRB               REG(0x03ac)
-#define HDMI_RX_PDEC_AIF_CTRL              REG(0x03c0)
-#define FC_LFE_EXCHG                       BIT(18)
-#define HDMI_RX_PDEC_AIF_HB                REG(0x03c4)
-#define HDMI_RX_PDEC_AIF_PB0               REG(0x03c8)
-#define HDMI_RX_PDEC_AIF_PB1               REG(0x03cc)
-#define HDMI_RX_PDEC_GMD_HB                REG(0x03d0)
-#define HDMI_RX_PDEC_GMD_PB                REG(0x03d4)
-#define HDMI_RX_PDEC_VSI_ST0               REG(0x03e0)
-#define HDMI_RX_PDEC_VSI_ST1               REG(0x03e4)
-#define HDMI_RX_PDEC_VSI_PB0               REG(0x03e8)
-#define HDMI_RX_PDEC_VSI_PB1               REG(0x03ec)
-#define HDMI_RX_PDEC_VSI_PB2               REG(0x03f0)
-#define HDMI_RX_PDEC_VSI_PB3               REG(0x03f4)
-#define HDMI_RX_PDEC_VSI_PB4               REG(0x03f8)
-#define HDMI_RX_PDEC_VSI_PB5               REG(0x03fc)
-#define HDMI_RX_CEAVID_CONFIG              REG(0x0400)
-#define HDMI_RX_CEAVID_3DCONFIG            REG(0x0404)
-#define HDMI_RX_CEAVID_HCONFIG_LO          REG(0x0408)
-#define HDMI_RX_CEAVID_HCONFIG_HI          REG(0x040c)
-#define HDMI_RX_CEAVID_VCONFIG_LO          REG(0x0410)
-#define HDMI_RX_CEAVID_VCONFIG_HI          REG(0x0414)
-#define HDMI_RX_CEAVID_STATUS              REG(0x0418)
-#define HDMI_RX_PDEC_AMP_HB                REG(0x0480)
-#define HDMI_RX_PDEC_AMP_PAYLOAD0          REG(0x0484)
-#define HDMI_RX_PDEC_AMP_PAYLOAD1          REG(0x0488)
-#define HDMI_RX_PDEC_AMP_PAYLOAD2          REG(0x048c)
-#define HDMI_RX_PDEC_AMP_PAYLOAD3          REG(0x0490)
-#define HDMI_RX_PDEC_AMP_PAYLOAD4          REG(0x0494)
-#define HDMI_RX_PDEC_AMP_PAYLOAD5          REG(0x0498)
-#define HDMI_RX_PDEC_AMP_PAYLOAD6          REG(0x049c)
-#define HDMI_RX_PDEC_NTSCVBI_HB            REG(0x04a0)
-#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD0      REG(0x04a4)
-#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD1      REG(0x04a8)
-#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD2      REG(0x04ac)
-#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD3      REG(0x04b0)
-#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD4      REG(0x04b4)
-#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD5      REG(0x04b8)
-#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD6      REG(0x04bc)
-#define HDMI_RX_PDEC_DRM_HB                REG(0x04c0)
-#define HDMI_RX_PDEC_DRM_PAYLOAD0          REG(0x04c4)
-#define HDMI_RX_PDEC_DRM_PAYLOAD1          REG(0x04c8)
-#define HDMI_RX_PDEC_DRM_PAYLOAD2          REG(0x04cc)
-#define HDMI_RX_PDEC_DRM_PAYLOAD3          REG(0x04d0)
-#define HDMI_RX_PDEC_DRM_PAYLOAD4          REG(0x04d4)
-#define HDMI_RX_PDEC_DRM_PAYLOAD5          REG(0x04d8)
-#define HDMI_RX_PDEC_DRM_PAYLOAD6          REG(0x04dc)
-#define HDMI_RX_MHLMODE_CTRL               REG(0x0500)
-#define HDMI_RX_CDSENSE_STATUS             REG(0x0504)
-#define HDMI_RX_DESERFIFO_CTRL             REG(0x0508)
-#define HDMI_RX_DESER_INTTRSHCTRL          REG(0x050c)
-#define HDMI_RX_DESER_INTCNTCTRL           REG(0x0510)
-#define HDMI_RX_DESER_INTCNT               REG(0x0514)
-#define HDMI_RX_HDCP_RPT_CTRL              REG(0x0600)
-#define HDMI_RX_HDCP_RPT_BSTATUS           REG(0x0604)
-#define HDMI_RX_HDCP_RPT_KSVFIFO_CTRL      REG(0x0608)
-#define HDMI_RX_HDCP_RPT_KSVFIFO1          REG(0x060c)
-#define HDMI_RX_HDCP_RPT_KSVFIFO0          REG(0x0610)
-#define HDMI_RX_HDMI20_CONTROL             REG(0x0800)
-#define HDMI_RX_SCDC_I2CCONFIG             REG(0x0804)
-#define I2CSPIKESUPPR_MASK                 GENMASK(25, 24)
-#define I2CSPIKESUPPR(x)                   UPDATE(x, 25, 24)
-#define HDMI_RX_SCDC_CONFIG                REG(0x0808)
-#define HDMI_RX_CHLOCK_CONFIG              REG(0x080c)
-#define CHLOCKMAXER_MASK                   GENMASK(29, 20)
-#define CHLOCKMAXER(x)                     UPDATE(x, 29, 20)
-#define MILISECTIMERLIMIT_MASK             GENMASK(15, 0)
-#define MILISECTIMERLIMIT(x)               UPDATE(x, 15, 0)
-#define HDMI_RX_HDCP22_CONTROL             REG(0x081c)
-#define HDMI_RX_SCDC_REGS0                 REG(0x0820)
-#define HDMI_RX_SCDC_REGS1                 REG(0x0824)
-#define HDMI_RX_SCDC_REGS2                 REG(0x0828)
-#define HDMI_RX_SCDC_REGS3                 REG(0x082c)
-#define HDMI_RX_SCDC_MANSPEC0              REG(0x0840)
-#define HDMI_RX_SCDC_MANSPEC1              REG(0x0844)
-#define HDMI_RX_SCDC_MANSPEC2              REG(0x0848)
-#define HDMI_RX_SCDC_MANSPEC3              REG(0x084c)
-#define HDMI_RX_SCDC_MANSPEC4              REG(0x0850)
-#define HDMI_RX_SCDC_WRDATA0               REG(0x0860)
-#define MANUFACTUREROUI_MASK               GENMASK(31, 8)
-#define MANUFACTUREROUI(x)                 UPDATE(x, 31, 8)
-#define SINKVERSION_MASK                   GENMASK(7, 0)
-#define SINKVERSION(x)                     UPDATE(x, 7, 0)
-#define HDMI_RX_SCDC_WRDATA1               REG(0x0864)
-#define HDMI_RX_SCDC_WRDATA2               REG(0x0868)
-#define HDMI_RX_SCDC_WRDATA3               REG(0x086c)
-#define HDMI_RX_SCDC_WRDATA4               REG(0x0870)
-#define HDMI_RX_SCDC_WRDATA5               REG(0x0874)
-#define HDMI_RX_SCDC_WRDATA6               REG(0x0878)
-#define HDMI_RX_SCDC_WRDATA7               REG(0x087c)
-#define HDMI_RX_HDMI20_STATUS              REG(0x08e0)
-#define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_IN   REG(0x08e8)
-#define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_OUT  REG(0x08ec)
-#define HDMI_RX_HDCP2_ESM_P0_GPIO_IN       REG(0x08f0)
-#define HDMI_RX_HDCP2_ESM_P0_GPIO_OUT      REG(0x08f4)
-#define HDMI_RX_HDCP22_STATUS              REG(0x08fc)
-#define HDMI_RX_HDMI2_IEN_CLR              REG(0x0f60)
-#define HDMI_RX_HDMI2_IEN_SET              REG(0x0f64)
-#define HDMI_RX_HDMI2_ISTS                 REG(0x0f68)
-#define HDMI_RX_HDMI2_IEN                  REG(0x0f6c)
-#define HDMI_RX_HDMI2_ICLR                 REG(0x0f70)
-#define HDMI_RX_HDMI2_ISET                 REG(0x0f74)
-#define HDMI_RX_PDEC_IEN_CLR               REG(0x0f78)
-#define HDMI_RX_PDEC_IEN_SET               REG(0x0f7c)
-#define HDMI_RX_PDEC_ISTS                  REG(0x0f80)
-#define HDMI_RX_PDEC_IEN                   REG(0x0f84)
-#define HDMI_RX_PDEC_ICLR                  REG(0x0f88)
-#define HDMI_RX_PDEC_ISET                  REG(0x0f8c)
-#define HDMI_RX_AUD_CEC_IEN_CLR            REG(0x0f90)
-#define HDMI_RX_AUD_CEC_IEN_SET            REG(0x0f94)
-#define HDMI_RX_AUD_CEC_ISTS               REG(0x0f98)
-#define HDMI_RX_AUD_CEC_IEN                REG(0x0f9c)
-#define HDMI_RX_AUD_CEC_ICLR               REG(0x0fa0)
-#define HDMI_RX_AUD_CEC_ISET               REG(0x0fa4)
-#define HDMI_RX_AUD_FIFO_IEN_CLR           REG(0x0fa8)
-#define HDMI_RX_AUD_FIFO_IEN_SET           REG(0x0fac)
-#define HDMI_RX_AUD_FIFO_ISTS              REG(0x0fb0)
-#define HDMI_RX_AUD_FIFO_IEN               REG(0x0fb4)
-#define HDMI_RX_AUD_FIFO_ICLR              REG(0x0fb8)
-#define HDMI_RX_AUD_FIFO_ISET              REG(0x0fbc)
-#define HDMI_RX_MD_IEN_CLR                 REG(0x0fc0)
-#define HDMI_RX_MD_IEN_SET                 REG(0x0fc4)
-#define HDMI_RX_MD_ISTS                    REG(0x0fc8)
-#define HDMI_RX_MD_IEN                     REG(0x0fcc)
-#define HDMI_RX_MD_ICLR                    REG(0x0fd0)
-#define HDMI_RX_MD_ISET                    REG(0x0fd4)
-#define HDMI_RX_HDMI_IEN_CLR               REG(0x0fd8)
-#define HDMI_RX_HDMI_IEN_SET               REG(0x0fdc)
-#define HDCP_DKSET_DONE_ENCLR_MASK         BIT(31)
-#define HDCP_DKSET_DONE_ENCLR(x)           UPDATE(x, 31, 31)
-#define HDMI_RX_HDMI_ISTS                  REG(0x0fe0)
-#define HDMI_RX_HDMI_IEN                   REG(0x0fe4)
-#define HDMI_RX_HDMI_ICLR                  REG(0x0fe8)
-#define HDMI_RX_HDMI_ISET                  REG(0x0fec)
-#define HDMI_RX_DMI_SW_RST                 REG(0x0ff0)
-#define HDMI_RX_DMI_DISABLE_IF             REG(0x0ff4)
-#define MAIN_ENABLE                        BIT(0)
-#define MODET_ENABLE                       BIT(1)
-#define HDMI_ENABLE                        BIT(2)
-#define BUS_ENABLE                         BIT(3)
-#define AUD_ENABLE                         BIT(4)
-#define CEC_ENABLE                         BIT(5)
-#define PIXEL_ENABLE                       BIT(6)
-#define VID_ENABLE                         BIT(7)
-#define TMDS_ENABLE_MASK                   BIT(16)
-#define TMDS_ENABLE(x)                     UPDATE(x, 16, 16)
-#define HDMI_RX_DMI_MODULE_ID_EXT          REG(0x0ff8)
-#define HDMI_RX_DMI_MODULE_ID              REG(0x0ffc)
-#define HDMI_RX_CEC_CTRL                   REG(0x1f00)
-#define HDMI_RX_CEC_MASK                   REG(0x1f08)
-#define HDMI_RX_CEC_ADDR_L                 REG(0x1f14)
-#define HDMI_RX_CEC_ADDR_H                 REG(0x1f18)
-#define HDMI_RX_CEC_TX_CNT                 REG(0x1f1c)
-#define HDMI_RX_CEC_RX_CNT                 REG(0x1f20)
-#define HDMI_RX_CEC_TX_DATA_0              REG(0x1f40)
-#define HDMI_RX_CEC_TX_DATA_1              REG(0x1f44)
-#define HDMI_RX_CEC_TX_DATA_2              REG(0x1f48)
-#define HDMI_RX_CEC_TX_DATA_3              REG(0x1f4c)
-#define HDMI_RX_CEC_TX_DATA_4              REG(0x1f50)
-#define HDMI_RX_CEC_TX_DATA_5              REG(0x1f54)
-#define HDMI_RX_CEC_TX_DATA_6              REG(0x1f58)
-#define HDMI_RX_CEC_TX_DATA_7              REG(0x1f5c)
-#define HDMI_RX_CEC_TX_DATA_8              REG(0x1f60)
-#define HDMI_RX_CEC_TX_DATA_9              REG(0x1f64)
-#define HDMI_RX_CEC_TX_DATA_10             REG(0x1f68)
-#define HDMI_RX_CEC_TX_DATA_11             REG(0x1f6c)
-#define HDMI_RX_CEC_TX_DATA_12             REG(0x1f70)
-#define HDMI_RX_CEC_TX_DATA_13             REG(0x1f74)
-#define HDMI_RX_CEC_TX_DATA_14             REG(0x1f78)
-#define HDMI_RX_CEC_TX_DATA_15             REG(0x1f7c)
-#define HDMI_RX_CEC_RX_DATA_0              REG(0x1f80)
-#define HDMI_RX_CEC_RX_DATA_1              REG(0x1f84)
-#define HDMI_RX_CEC_RX_DATA_2              REG(0x1f88)
-#define HDMI_RX_CEC_RX_DATA_3              REG(0x1f8c)
-#define HDMI_RX_CEC_RX_DATA_4              REG(0x1f90)
-#define HDMI_RX_CEC_RX_DATA_5              REG(0x1f94)
-#define HDMI_RX_CEC_RX_DATA_6              REG(0x1f98)
-#define HDMI_RX_CEC_RX_DATA_7              REG(0x1f9c)
-#define HDMI_RX_CEC_RX_DATA_8              REG(0x1fa0)
-#define HDMI_RX_CEC_RX_DATA_9              REG(0x1fa4)
-#define HDMI_RX_CEC_RX_DATA_10             REG(0x1fa8)
-#define HDMI_RX_CEC_RX_DATA_11             REG(0x1fac)
-#define HDMI_RX_CEC_RX_DATA_12             REG(0x1fb0)
-#define HDMI_RX_CEC_RX_DATA_13             REG(0x1fb4)
-#define HDMI_RX_CEC_RX_DATA_14             REG(0x1fb8)
-#define HDMI_RX_CEC_RX_DATA_15             REG(0x1fbc)
-#define HDMI_RX_CEC_LOCK                   REG(0x1fc0)
-#define HDMI_RX_CEC_WAKEUPCTRL             REG(0x1fc4)
-#define HDMI_RX_CBUSSWRESETREQ             REG(0x3000)
-#define HDMI_RX_CBUSENABLEIF               REG(0x3004)
-#define HDMI_RX_CB_LOCKONCLOCK_STS         REG(0x3010)
-#define HDMI_RX_CB_LOCKONCLOCKCLR          REG(0x3014)
-#define HDMI_RX_CBUSIOCTRL                 REG(0x3020)
-#define HDMI_RX_DD_CTRL                    REG(0x3040)
-#define HDMI_RX_DD_OP_CTRL                 REG(0x3044)
-#define HDMI_RX_DD_STS                     REG(0x3048)
-#define HDMI_RX_DD_BYPASS_EN               REG(0x304c)
-#define HDMI_RX_DD_BYPASS_CTRL             REG(0x3050)
-#define HDMI_RX_DD_BYPASS_CBUS             REG(0x3054)
-#define HDMI_RX_LL_TXPCKFIFO               REG(0x3080)
-#define HDMI_RX_LL_RXPCKFIFO_RD_CLR        REG(0x3084)
-#define HDMI_RX_LL_RXPCKFIFO_A             REG(0x3088)
-#define HDMI_RX_LL_RXPCKFIFO_B             REG(0x308c)
-#define HDMI_RX_LL_TXPCKCTRL_0             REG(0x3090)
-#define HDMI_RX_LL_TXPCKCTRL_1             REG(0x3094)
-#define HDMI_RX_LL_PCKFIFO_STS             REG(0x309c)
-#define HDMI_RX_LL_RXPCKCTRL_0             REG(0x30a0)
-#define HDMI_RX_LL_RXPCKCTRL_1             REG(0x30a4)
-#define HDMI_RX_LL_INTTRSHLDCTRL           REG(0x30b0)
-#define HDMI_RX_LL_INTCNTCTRL              REG(0x30b4)
-#define HDMI_RX_LL_INTCNT_0                REG(0x30b8)
-#define HDMI_RX_LL_INTCNT_1                REG(0x30bc)
-#define HDMI_RX_CBHDCP_OPCTRL              REG(0x3100)
-#define HDMI_RX_CBHDCP_WDATA_0             REG(0x3104)
-#define HDMI_RX_CBHDCP_WDATA_1             REG(0x3108)
-#define HDMI_RX_CBHDCP_RDATA_0             REG(0x310c)
-#define HDMI_RX_CBHDCP_RDATA_1             REG(0x3110)
-#define HDMI_RX_CBHDCP_STATUS              REG(0x3114)
-#define HDMI_RX_CBHDCP_DDC_REPORT          REG(0x3118)
-#define HDMI_RX_ISTAT_CB_DD                REG(0x3200)
-#define HDMI_RX_IMASK_CB_DD                REG(0x3204)
-#define HDMI_RX_IFORCE_CB_DD               REG(0x3208)
-#define HDMI_RX_ICLEAR_CB_DD               REG(0x320c)
-#define HDMI_RX_IMUTE_CB_DD                REG(0x3210)
-#define HDMI_RX_ISTAT_CB_LL                REG(0x3220)
-#define HDMI_RX_IMASK_CB_LL                REG(0x3224)
-#define HDMI_RX_IFORCE_CB_LL               REG(0x3228)
-#define HDMI_RX_ICLEAR_CB_LL               REG(0x322c)
-#define HDMI_RX_IMUTE_CB_LL                REG(0x3230)
-#define HDMI_RX_ISTAT_CB_HDCP              REG(0x3240)
-#define HDMI_RX_IMASK_CB_HDCP              REG(0x3244)
-#define HDMI_RX_IFORCE_CB_HDCP             REG(0x3248)
-#define HDMI_RX_ICLEAR_CB_HDCP             REG(0x324c)
-#define HDMI_RX_IMUTE_CB_HDCP              REG(0x3250)
-#define HDMI_RX_ISTAT_CB_MCTRL             REG(0x3260)
-#define HDMI_RX_IMASK_CB_MCTRL             REG(0x3264)
-#define HDMI_RX_IFORCE_CB_MCTRL            REG(0x3268)
-#define HDMI_RX_ICLEAR_CB_MCTRL            REG(0x326c)
-#define HDMI_RX_IMUTE_CB_MCTRL             REG(0x3270)
-#define HDMI_RX_IMASTER_MUTE_CB            REG(0x32e0)
-#define HDMI_RX_IVECTOR_INDEX_CB           REG(0x32e4)
-#define HDMI_RX_MAX_REGISTER               HDMI_RX_IVECTOR_INDEX_CB
-
-struct rk628_hdmirx {
-	struct drm_bridge base;
-	struct drm_bridge *bridge;
-	struct device *dev;
-	struct regmap *regmap;
-	struct regmap *grf;
-	struct phy *phy;
-	struct clk *pclk;
-	struct clk *cec_clk;
-	struct clk *aud_clk;
-	struct clk *imodet_clk;
-	struct reset_control *hdmirx;
-	struct reset_control *hdmirx_pon;
-	struct rk628 *parent;
-	struct drm_display_mode mode;
-};
-
-static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
-	regmap_reg_range(HDMI_RX_HDMI_SETUP_CTRL, HDMI_RX_HDMI_TIMER_CTRL),
-	regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERD_STS),
-	regmap_reg_range(HDMI_RX_MD_HCTRL1, HDMI_RX_MD_STS),
-	regmap_reg_range(HDMI_RX_PDEC_ACRM_CTRL, HDMI_RX_PDEC_ASP_ERR),
-	regmap_reg_range(HDMI_RX_PDEC_AVI_HB, HDMI_RX_PDEC_AVI_LRB),
-	regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_GMD_PB),
-	regmap_reg_range(HDMI_RX_HDMI20_CONTROL, HDMI_RX_CHLOCK_CONFIG),
-	regmap_reg_range(HDMI_RX_SCDC_REGS1, HDMI_RX_SCDC_REGS3),
-	regmap_reg_range(HDMI_RX_SCDC_WRDATA0, HDMI_RX_SCDC_WRDATA7),
-	regmap_reg_range(HDMI_RX_DMI_DISABLE_IF, HDMI_RX_DMI_DISABLE_IF),
-};
-
-static const struct regmap_access_table rk628_hdmirx_readable_table = {
-	.yes_ranges	= rk628_hdmirx_readable_ranges,
-	.n_yes_ranges   = ARRAY_SIZE(rk628_hdmirx_readable_ranges),
-};
-
-static const struct regmap_config rk628_hdmirx_regmap_config = {
-	.name = "hdmirx",
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = 4,
-	.max_register = HDMI_RX_MAX_REGISTER,
-	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
-	.val_format_endian = REGMAP_ENDIAN_LITTLE,
-	.rd_table = &rk628_hdmirx_readable_table,
-};
-
-static inline struct rk628_hdmirx *bridge_to_hdmirx(struct drm_bridge *bridge)
-{
-	return container_of(bridge, struct rk628_hdmirx, base);
-}
-
-static void rk628_hdmirx_ctrl_enable(struct rk628_hdmirx *hdmirx)
-{
-	clk_prepare_enable(hdmirx->pclk);
-	clk_prepare_enable(hdmirx->aud_clk);
-	clk_prepare_enable(hdmirx->imodet_clk);
-
-	reset_control_deassert(hdmirx->hdmirx);
-	reset_control_deassert(hdmirx->hdmirx_pon);
-
-	regmap_update_bits(hdmirx->grf, GRF_SYSTEM_CON0,
-			   SW_INPUT_MODE_MASK,
-			   SW_INPUT_MODE(INPUT_MODE_HDMI));
-
-	regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000101ff);
-
-	regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x00000000);
-	regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0000017f);
-	regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0001017f);
-
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI20_CONTROL, 0x10001f10);
-
-	regmap_update_bits(hdmirx->regmap, HDMI_RX_CHLOCK_CONFIG,
-			   CHLOCKMAXER_MASK | MILISECTIMERLIMIT_MASK,
-			   CHLOCKMAXER(0x1) | MILISECTIMERLIMIT(49500));
-
-	regmap_write(hdmirx->regmap, HDMI_RX_SCDC_CONFIG, 0x00000001);
-	regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000001fe);
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_EVLTM, 0x0016fff0);
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_F, 0xf98a0190);
-
-	regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_MODE_RECOVER,
-			   SPIKE_FILTER_EN_MASK | DVI_MODE_HYST_MASK |
-			   HDMI_MODE_HYST_MASK | HDMI_MODE_MASK |
-			   GB_DET_MASK | EESS_OESS_MASK | SEL_CTL01_MASK,
-			   SPIKE_FILTER_EN(0) |
-			   DVI_MODE_HYST(0) |
-			   HDMI_MODE_HYST(0) |
-			   HDMI_MODE(3) |
-			   GB_DET(2) |
-			   EESS_OESS(0) |
-			   SEL_CTL01(1));
-
-	regmap_write(hdmirx->regmap, HDMI_RX_PDEC_CTRL, 0xbfff8011);
-	regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ASP_CTRL, 0x00000040);
-
-	regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_RESMPL_CTRL,
-			   MAN_VID_DEREPEAT_MASK, MAN_VID_DEREPEAT(1));
-
-	regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_SYNC_CTRL,
-			   VS_POL_ADJ_MODE_MASK | HS_POL_ADJ_MODE_MASK,
-			   VS_POL_ADJ_MODE(2) | HS_POL_ADJ_MODE(2));
-
-	regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ERR_FILTER, 0x00000008);
-
-	regmap_update_bits(hdmirx->regmap, HDMI_RX_SCDC_I2CCONFIG,
-			   I2CSPIKESUPPR_MASK, I2CSPIKESUPPR(1));
-
-	regmap_write(hdmirx->regmap, HDMI_RX_SCDC_CONFIG, 0x00000001);
-	regmap_write(hdmirx->regmap, HDMI_RX_SCDC_WRDATA0, 0xabcdef01);
-
-	regmap_update_bits(hdmirx->regmap, HDMI_RX_CHLOCK_CONFIG,
-			   CHLOCKMAXER_MASK | MILISECTIMERLIMIT_MASK,
-			   CHLOCKMAXER(0x1) | MILISECTIMERLIMIT(49500));
-
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI_ERROR_PROTECT, 0x000d0c98);
-	regmap_write(hdmirx->regmap, HDMI_RX_MD_HCTRL1, 0x00000010);
-	regmap_write(hdmirx->regmap, HDMI_RX_MD_HCTRL2, 0x00001738);
-	regmap_write(hdmirx->regmap, HDMI_RX_MD_VCTRL, 0x00000012);
-	regmap_write(hdmirx->regmap, HDMI_RX_MD_VTH, 0x0000073a);
-	regmap_write(hdmirx->regmap, HDMI_RX_MD_IL_POL, 0x00000004);
-	regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ACRM_CTRL, 0x00000000);
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI_DCM_CTRL, 0x00040414);
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI_PCB_CTRL, 0x00100000);
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI_SETUP_CTRL, 0x0f000fff);
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_EVLTM, 0x00104260);
-	regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_F, 0x0f2d0eed);
-	regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x00000001);
-	udelay(400);
-	regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0001017f);
-	regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_RESMPL_CTRL,
-			   MAN_VID_DEREPEAT_MASK, MAN_VID_DEREPEAT(1));
-	regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000001fe);
-}
-
-static void rk628_hdmirx_ctrl_disable(struct rk628_hdmirx *hdmirx)
-{
-	reset_control_assert(hdmirx->hdmirx);
-	reset_control_assert(hdmirx->hdmirx_pon);
-	clk_disable_unprepare(hdmirx->pclk);
-	clk_disable_unprepare(hdmirx->aud_clk);
-	clk_disable_unprepare(hdmirx->imodet_clk);
-}
-
-static void rk628_hdmirx_bridge_enable(struct drm_bridge *bridge)
-{
-	bool locked;
-	u32 value, i, hact, vact, bus_width, hdisplay, vdisplay;
-	struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
-
-	/* force 594m mode to yuv420 format */
-	if (hdmirx->mode.clock == 594000) {
-		/*
-		 * bit30 is used to indicate whether it is
-		 * yuv420 format
-		 */
-		bus_width = hdmirx->mode.clock | BIT(30);
-		hdisplay = hdmirx->mode.hdisplay / 2;
-	} else {
-		bus_width = hdmirx->mode.clock;
-		hdisplay = hdmirx->mode.hdisplay;
-	}
-
-	vdisplay = hdmirx->mode.vdisplay;
-
-	phy_set_bus_width(hdmirx->phy, bus_width);
-	phy_power_on(hdmirx->phy);
-	usleep_range(10*1000, 11*1000);
-	rk628_hdmirx_ctrl_enable(hdmirx);
-
-	/* if hdmirx ctrl unlock or get incorrect timing, reset ctrl and phy */
-	for (i = 0; i < 5; i++) {
-		usleep_range(100*1000, 110*1000);
-		regmap_read(hdmirx->regmap, HDMI_RX_SCDC_REGS1, &value);
-		dev_dbg(hdmirx->dev, "HDMI_RX_SCDC_REGS1:0x%x\n", value);
-		value = (value >> 8) & 0xf;
-
-		regmap_read(hdmirx->regmap, HDMI_RX_MD_HACT_PX, &hact);
-		regmap_read(hdmirx->regmap, HDMI_RX_MD_VAL, &vact);
-
-		hact = hact & 0xffff;
-		vact = vact & 0xffff;
-		dev_dbg(hdmirx->dev, "hact:%d,vact:%d\n", hact, vact);
-
-		if (value == 0xf && hact == hdisplay && vact == vdisplay)
-			locked = true;
-		else
-			locked = false;
-
-		if (!locked) {
-			rk628_hdmirx_ctrl_disable(hdmirx);
-			usleep_range(10*1000, 11*1000);
-			phy_power_off(hdmirx->phy);
-			usleep_range(10*1000, 11*1000);
-			phy_power_on(hdmirx->phy);
-			usleep_range(10*1000, 11*1000);
-			rk628_hdmirx_ctrl_enable(hdmirx);
-		} else {
-			/* hdmirx ctrl get correct timing, enable output */
-			regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF,
-				     0x000001ff);
-			return;
-		}
-	}
-
-	dev_err(hdmirx->dev, "hdmirx channel can't lock!\n");
-
-}
-
-static void rk628_hdmirx_bridge_disable(struct drm_bridge *bridge)
-{
-	struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
-
-	rk628_hdmirx_ctrl_disable(hdmirx);
-	phy_power_off(hdmirx->phy);
-}
-
-static int rk628_hdmirx_bridge_attach(struct drm_bridge *bridge,
-				      enum drm_bridge_attach_flags flags)
-{
-	struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
-	struct device *dev = hdmirx->dev;
-	int ret;
-
-	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
-					  NULL, &hdmirx->bridge);
-	if (ret) {
-		dev_err(dev, "failed to find next bridge\n");
-		return ret;
-	}
-
-	ret = drm_bridge_attach(bridge->encoder, hdmirx->bridge, bridge, flags);
-	if (ret) {
-		dev_err(dev, "failed to attach bridge\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static void rk628_hdmirx_bridge_mode_set(struct drm_bridge *bridge,
-					 const struct drm_display_mode *mode,
-					 const struct drm_display_mode *adj)
-{
-	struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
-
-	drm_mode_copy(&hdmirx->mode, adj);
-}
-
-static const struct drm_bridge_funcs rk628_hdmirx_bridge_funcs = {
-	.attach = rk628_hdmirx_bridge_attach,
-	.enable = rk628_hdmirx_bridge_enable,
-	.disable = rk628_hdmirx_bridge_disable,
-	.mode_set = rk628_hdmirx_bridge_mode_set,
-};
-
-static int rk628_hdmirx_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct platform_device_info pdevinfo;
-	struct rk628_hdmirx *hdmirx;
-	int ret, irq;
-
-	if (!of_device_is_available(dev->of_node))
-		return -ENODEV;
-
-	hdmirx = devm_kzalloc(dev, sizeof(*hdmirx), GFP_KERNEL);
-	if (!hdmirx)
-		return -ENOMEM;
-
-	hdmirx->dev = dev;
-	hdmirx->parent = rk628;
-	platform_set_drvdata(pdev, hdmirx);
-
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
-
-	hdmirx->grf = rk628->grf;
-	if (!hdmirx->grf)
-		return -ENODEV;
-
-	hdmirx->pclk = devm_clk_get(dev, "pclk");
-	if (IS_ERR(hdmirx->pclk)) {
-		ret = PTR_ERR(hdmirx->pclk);
-		dev_err(dev, "failed to get pclk: %d\n", ret);
-		return ret;
-	}
-
-	hdmirx->cec_clk = devm_clk_get(dev, "cec");
-	if (IS_ERR(hdmirx->cec_clk)) {
-		ret = PTR_ERR(hdmirx->cec_clk);
-		dev_err(dev, "failed to get cec clk: %d\n", ret);
-		return ret;
-	}
-
-	hdmirx->aud_clk = devm_clk_get(dev, "audio");
-	if (IS_ERR(hdmirx->aud_clk)) {
-		ret = PTR_ERR(hdmirx->aud_clk);
-		dev_err(dev, "failed to get audio clk: %d\n", ret);
-		return ret;
-	}
-
-	hdmirx->imodet_clk = devm_clk_get(dev, "imodet");
-	if (IS_ERR(hdmirx->imodet_clk)) {
-		ret = PTR_ERR(hdmirx->imodet_clk);
-		dev_err(dev, "failed to get imodet clk: %d\n", ret);
-		return ret;
-	}
-
-	hdmirx->hdmirx = of_reset_control_get(dev->of_node, "hdmirx");
-	if (IS_ERR(hdmirx->hdmirx)) {
-		ret = PTR_ERR(hdmirx->hdmirx);
-		DRM_DEV_ERROR(dev, "failed to get hdmirx control: %d\n", ret);
-		return ret;
-	}
-
-	hdmirx->hdmirx_pon = of_reset_control_get(dev->of_node, "hdmirx_pon");
-	if (IS_ERR(hdmirx->hdmirx_pon)) {
-		ret = PTR_ERR(hdmirx->hdmirx_pon);
-		DRM_DEV_ERROR(dev, "failed to get hdmirx_pon control: %d\n", ret);
-		return ret;
-	}
-
-	hdmirx->phy = devm_of_phy_get(dev, dev->of_node, NULL);
-	if (IS_ERR(hdmirx->phy)) {
-		ret = PTR_ERR(hdmirx->phy);
-		dev_err(dev, "failed to get phy: %d\n", ret);
-		return ret;
-	}
-
-	hdmirx->regmap = devm_regmap_init_i2c(rk628->client,
-					      &rk628_hdmirx_regmap_config);
-	if (IS_ERR(hdmirx->regmap)) {
-		ret = PTR_ERR(hdmirx->regmap);
-		dev_err(dev, "failed to allocate register map: %d\n", ret);
-		return ret;
-	}
-
-	hdmirx->base.funcs = &rk628_hdmirx_bridge_funcs;
-	hdmirx->base.of_node = dev->of_node;
-	drm_bridge_add(&hdmirx->base);
-
-	memset(&pdevinfo, 0, sizeof(pdevinfo));
-	pdevinfo.parent = dev;
-	pdevinfo.id = PLATFORM_DEVID_AUTO;
-
-	return 0;
-}
-
-static int rk628_hdmirx_remove(struct platform_device *pdev)
-{
-	struct rk628_hdmirx *hdmirx = platform_get_drvdata(pdev);
-
-	drm_bridge_remove(&hdmirx->base);
-
-	return 0;
-}
-
-static const struct of_device_id rk628_hdmirx_of_match[] = {
-	{ .compatible = "rockchip,rk628-hdmirx", },
-	{},
-};
-MODULE_DEVICE_TABLE(of, rk628_hdmirx_of_match);
-
-static struct platform_driver rk628_hdmirx_driver = {
-	.driver = {
-		.name = "rk628-hdmirx",
-		.of_match_table = of_match_ptr(rk628_hdmirx_of_match),
-	},
-	.probe = rk628_hdmirx_probe,
-	.remove = rk628_hdmirx_remove,
-};
-module_platform_driver(rk628_hdmirx_driver);
-
-MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 HDMI RX driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_lvds.c b/drivers/gpu/drm/rockchip/rk628/rk628_lvds.c
deleted file mode 100644
index 57496ff9dec7..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_lvds.c
+++ /dev/null
@@ -1,320 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Wyon Bi <bivvy.bi@rock-chips.com>
- */
-
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/media-bus-format.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/regmap.h>
-#include <linux/mfd/rk628.h>
-#include <linux/phy/phy.h>
-
-#include <drm/drm_of.h>
-#include <drm/drm_atomic.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_panel.h>
-
-#include <video/of_display_timing.h>
-#include <video/videomode.h>
-
-enum lvds_format {
-	LVDS_FORMAT_VESA_24BIT,
-	LVDS_FORMAT_JEIDA_24BIT,
-	LVDS_FORMAT_JEIDA_18BIT,
-	LVDS_FORMAT_VESA_18BIT,
-};
-
-enum lvds_link_type {
-	LVDS_SINGLE_LINK,
-	LVDS_DUAL_LINK_ODD_EVEN_PIXELS,
-	LVDS_DUAL_LINK_EVEN_ODD_PIXELS,
-	LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS,
-	LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS,
-};
-
-struct rk628_lvds {
-	struct drm_bridge base;
-	struct drm_connector connector;
-	struct drm_panel *panel;
-	struct drm_display_mode mode;
-	struct device *dev;
-	struct regmap *grf;
-	struct phy *phy;
-	struct rk628 *parent;
-	enum lvds_format format;
-	enum lvds_link_type link_type;
-};
-
-static inline struct rk628_lvds *bridge_to_lvds(struct drm_bridge *b)
-{
-	return container_of(b, struct rk628_lvds, base);
-}
-
-static inline struct rk628_lvds *connector_to_lvds(struct drm_connector *c)
-{
-	return container_of(c, struct rk628_lvds, connector);
-}
-
-static enum lvds_format rk628_lvds_get_format(u32 bus_format)
-{
-	switch (bus_format) {
-	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
-		return LVDS_FORMAT_JEIDA_24BIT;
-	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
-		return LVDS_FORMAT_VESA_18BIT;
-	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
-	default:
-		return LVDS_FORMAT_VESA_24BIT;
-	}
-}
-
-static enum lvds_link_type rk628_lvds_get_link_type(struct rk628_lvds *lvds)
-{
-	struct device *dev = lvds->dev;
-	const char *str;
-	int ret;
-
-	ret = of_property_read_string(dev->of_node, "rockchip,link-type", &str);
-	if (ret < 0)
-		return LVDS_SINGLE_LINK;
-
-	if (!strcmp(str, "dual-link-odd-even-pixels"))
-		return LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
-	else if (!strcmp(str, "dual-link-even-odd-pixels"))
-		return LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
-	else if (!strcmp(str, "dual-link-left-right-pixels"))
-		return LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS;
-	else if (!strcmp(str, "dual-link-right-left-pixels"))
-		return LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS;
-	else
-		return LVDS_SINGLE_LINK;
-}
-
-static struct drm_encoder *
-rk628_lvds_connector_best_encoder(struct drm_connector *connector)
-{
-	struct rk628_lvds *lvds = connector_to_lvds(connector);
-
-	return lvds->base.encoder;
-}
-
-static int rk628_lvds_connector_get_modes(struct drm_connector *connector)
-{
-	struct rk628_lvds *lvds = connector_to_lvds(connector);
-	struct drm_display_info *info = &connector->display_info;
-	int num_modes = 0;
-
-	num_modes = drm_panel_get_modes(lvds->panel, connector);
-
-	if (info->num_bus_formats)
-		lvds->format = rk628_lvds_get_format(info->bus_formats[0]);
-	else
-		lvds->format = LVDS_FORMAT_VESA_24BIT;
-
-	return num_modes;
-}
-
-static const struct drm_connector_helper_funcs
-rk628_lvds_connector_helper_funcs = {
-	.get_modes = rk628_lvds_connector_get_modes,
-	.best_encoder = rk628_lvds_connector_best_encoder,
-};
-
-static void rk628_lvds_connector_destroy(struct drm_connector *connector)
-{
-	drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs rk628_lvds_connector_funcs = {
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.destroy = rk628_lvds_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static void rk628_lvds_bridge_enable(struct drm_bridge *bridge)
-{
-	struct rk628_lvds *lvds = bridge_to_lvds(bridge);
-	const struct drm_display_mode *mode = &lvds->mode;
-	u32 val, bus_width;
-	int ret;
-
-	regmap_update_bits(lvds->grf, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
-			   SW_OUTPUT_MODE(OUTPUT_MODE_LVDS));
-
-	switch (lvds->link_type) {
-	case LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
-		val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(0) |
-		      SW_LVDS_CON_DUAL_SEL(0);
-		bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
-		break;
-	case LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
-		val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(1) |
-		      SW_LVDS_CON_DUAL_SEL(0);
-		bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
-		break;
-	case LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS:
-		val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(0) |
-		      SW_LVDS_CON_DUAL_SEL(1);
-		regmap_update_bits(lvds->grf, GRF_POST_PROC_CON,
-				   SW_SPLIT_EN, SW_SPLIT_EN);
-		bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
-		break;
-	case LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS:
-		val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(1) |
-		      SW_LVDS_CON_DUAL_SEL(1);
-		regmap_update_bits(lvds->grf, GRF_POST_PROC_CON,
-				   SW_SPLIT_EN, SW_SPLIT_EN);
-		bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
-		break;
-	case LVDS_SINGLE_LINK:
-	default:
-		val = SW_LVDS_CON_CHASEL(0) | SW_LVDS_CON_STARTSEL(0) |
-		      SW_LVDS_CON_DUAL_SEL(0);
-		bus_width = COMBTXPHY_MODULEA_EN;
-		break;
-	}
-
-	val |= SW_LVDS_CON_SELECT(lvds->format) |
-	       SW_LVDS_CON_MSBSEL(0) |
-	       SW_LVDS_CON_CLKINV(0);
-	regmap_write(lvds->grf, GRF_LVDS_TX_CON, val);
-
-	bus_width |= (mode->clock / 1000) << 8;
-	phy_set_bus_width(lvds->phy, bus_width);
-
-	ret = phy_set_mode(lvds->phy, PHY_MODE_LVDS);
-	if (ret) {
-		dev_err(lvds->dev, "failed to set phy mode: %d\n", ret);
-		return;
-	}
-
-	phy_power_on(lvds->phy);
-
-	drm_panel_prepare(lvds->panel);
-	drm_panel_enable(lvds->panel);
-}
-
-static void rk628_lvds_bridge_disable(struct drm_bridge *bridge)
-{
-	struct rk628_lvds *lvds = bridge_to_lvds(bridge);
-
-	drm_panel_disable(lvds->panel);
-	drm_panel_unprepare(lvds->panel);
-	phy_power_off(lvds->phy);
-}
-
-static int rk628_lvds_bridge_attach(struct drm_bridge *bridge,
-				    enum drm_bridge_attach_flags flags)
-{
-	struct rk628_lvds *lvds = bridge_to_lvds(bridge);
-	struct drm_connector *connector = &lvds->connector;
-	struct drm_device *drm = bridge->dev;
-	int ret;
-
-	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
-		return 0;
-
-	ret = drm_connector_init(drm, connector, &rk628_lvds_connector_funcs,
-				 DRM_MODE_CONNECTOR_LVDS);
-	if (ret) {
-		dev_err(lvds->dev, "Failed to initialize connector with drm\n");
-		return ret;
-	}
-
-	drm_connector_helper_add(connector, &rk628_lvds_connector_helper_funcs);
-	drm_connector_attach_encoder(connector, bridge->encoder);
-
-	return 0;
-}
-
-static void rk628_lvds_bridge_mode_set(struct drm_bridge *bridge,
-				       const struct drm_display_mode *mode,
-				       const struct drm_display_mode *adj)
-{
-	struct rk628_lvds *lvds = bridge_to_lvds(bridge);
-
-	drm_mode_copy(&lvds->mode, mode);
-}
-
-static const struct drm_bridge_funcs rk628_lvds_bridge_funcs = {
-	.attach = rk628_lvds_bridge_attach,
-	.enable = rk628_lvds_bridge_enable,
-	.disable = rk628_lvds_bridge_disable,
-	.mode_set = rk628_lvds_bridge_mode_set,
-};
-
-static int rk628_lvds_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_lvds *lvds;
-	int ret;
-
-	if (!of_device_is_available(dev->of_node))
-		return -ENODEV;
-
-	lvds = devm_kzalloc(dev, sizeof(*lvds), GFP_KERNEL);
-	if (!lvds)
-		return -ENOMEM;
-
-	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
-					  &lvds->panel, NULL);
-	if (ret)
-		return ret;
-
-	lvds->dev = dev;
-	lvds->parent = rk628;
-	lvds->grf = rk628->grf;
-	lvds->link_type = rk628_lvds_get_link_type(lvds);
-	platform_set_drvdata(pdev, lvds);
-
-	lvds->phy = devm_of_phy_get(dev, dev->of_node, NULL);
-	if (IS_ERR(lvds->phy)) {
-		ret = PTR_ERR(lvds->phy);
-		dev_err(dev, "failed to get phy: %d\n", ret);
-		return ret;
-	}
-
-	lvds->base.funcs = &rk628_lvds_bridge_funcs;
-	lvds->base.of_node = dev->of_node;
-	drm_bridge_add(&lvds->base);
-
-	return 0;
-}
-
-static int rk628_lvds_remove(struct platform_device *pdev)
-{
-	struct rk628_lvds *lvds = platform_get_drvdata(pdev);
-
-	drm_bridge_remove(&lvds->base);
-
-	return 0;
-}
-
-static const struct of_device_id rk628_lvds_of_match[] = {
-	{ .compatible = "rockchip,rk628-lvds", },
-	{},
-};
-MODULE_DEVICE_TABLE(of, rk628_lvds_of_match);
-
-static struct platform_driver rk628_lvds_driver = {
-	.driver = {
-		.name = "rk628-lvds",
-		.of_match_table = of_match_ptr(rk628_lvds_of_match),
-	},
-	.probe = rk628_lvds_probe,
-	.remove = rk628_lvds_remove,
-};
-module_platform_driver(rk628_lvds_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 LVDS driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c b/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c
deleted file mode 100644
index 80fd257a6471..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_post_process.c
+++ /dev/null
@@ -1,495 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Wyon Bi <bivvy.bi@rock-chips.com>
- */
-
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/mfd/rk628.h>
-#include <video/of_display_timing.h>
-#include <video/videomode.h>
-
-#include <drm/drm_of.h>
-
-enum rk628_mode_sync_pol {
-	MODE_FLAG_NSYNC,
-	MODE_FLAG_PSYNC,
-};
-
-struct rk628_post_process {
-	struct drm_bridge base;
-	struct drm_bridge *bridge;
-	struct drm_display_mode src_mode;
-	struct drm_display_mode dst_mode;
-	struct device *dev;
-	struct regmap *grf;
-	struct clk *sclk_vop;
-	struct clk *clk_rx_read;
-	struct reset_control *rstc_decoder;
-	struct reset_control *rstc_clk_rx;
-	struct reset_control *rstc_vop;
-	struct rk628 *parent;
-	int sync_pol;
-};
-
-static inline struct rk628_post_process *bridge_to_pp(struct drm_bridge *bridge)
-{
-	return container_of(bridge, struct rk628_post_process, base);
-}
-
-static void calc_dsp_frm_hst_vst(const struct videomode *src,
-				 const struct videomode *dst,
-				 u32 *dsp_frame_hst, u32 *dsp_frame_vst)
-{
-	u32 bp_in, bp_out;
-	u32 v_scale_ratio;
-	u64 t_frm_st;
-	u64 t_bp_in, t_bp_out, t_delta, tin;
-	u32 src_pixclock, dst_pixclock;
-	u32 dsp_htotal, src_htotal, src_vtotal;
-
-	src_pixclock = div_u64(1000000000000llu, src->pixelclock);
-	dst_pixclock = div_u64(1000000000000llu, dst->pixelclock);
-
-	src_htotal = src->hsync_len + src->hback_porch + src->hactive +
-		     src->hfront_porch;
-	src_vtotal = src->vsync_len + src->vback_porch + src->vactive +
-		     src->vfront_porch;
-	dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
-		     dst->hfront_porch;
-
-	bp_in = (src->vback_porch + src->vsync_len) * src_htotal +
-		src->hsync_len + src->hback_porch;
-	bp_out = (dst->vback_porch + dst->vsync_len) * dsp_htotal +
-		 dst->hsync_len + dst->hback_porch;
-
-	t_bp_in = bp_in * src_pixclock;
-	t_bp_out = bp_out * dst_pixclock;
-	tin = src_vtotal * src_htotal * src_pixclock;
-
-	v_scale_ratio = src->vactive / dst->vactive;
-	if (v_scale_ratio <= 2)
-		t_delta = 5 * src_htotal * src_pixclock;
-	else
-		t_delta = 12 * src_htotal * src_pixclock;
-
-	if (t_bp_in + t_delta > t_bp_out)
-		t_frm_st = (t_bp_in + t_delta - t_bp_out);
-	else
-		t_frm_st = tin - (t_bp_out - (t_bp_in + t_delta));
-
-	do_div(t_frm_st, src_pixclock);
-	*dsp_frame_hst = do_div(t_frm_st, src_htotal);
-	*dsp_frame_vst = t_frm_st;
-}
-
-static void rk628_post_process_scaler_init(struct rk628_post_process *pp,
-					   const struct drm_display_mode *s,
-					   const struct drm_display_mode *d)
-{
-	struct videomode src, dst;
-	u32 dsp_frame_hst, dsp_frame_vst;
-	u32 scl_hor_mode, scl_ver_mode;
-	u32 scl_v_factor, scl_h_factor;
-	u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
-	u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
-	u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
-	u16 bor_right = 0, bor_left = 0, bor_up = 0, bor_down = 0;
-	u8 hor_down_mode = 0, ver_down_mode = 0;
-
-	drm_display_mode_to_videomode(s, &src);
-	drm_display_mode_to_videomode(d, &dst);
-
-	dsp_htotal = dst.hsync_len + dst.hback_porch + dst.hactive +
-		     dst.hfront_porch;
-	dsp_vtotal = dst.vsync_len + dst.vback_porch + dst.vactive +
-		     dst.vfront_porch;
-	dsp_hs_end = dst.hsync_len;
-	dsp_vs_end = dst.vsync_len;
-	dsp_hbor_end = dst.hsync_len + dst.hback_porch + dst.hactive;
-	dsp_hbor_st = dst.hsync_len + dst.hback_porch;
-	dsp_vbor_end = dst.vsync_len + dst.vback_porch + dst.vactive;
-	dsp_vbor_st = dst.vsync_len + dst.vback_porch;
-	dsp_hact_st = dsp_hbor_st + bor_left;
-	dsp_hact_end = dsp_hbor_end - bor_right;
-	dsp_vact_st = dsp_vbor_st + bor_up;
-	dsp_vact_end = dsp_vbor_end - bor_down;
-
-	calc_dsp_frm_hst_vst(&src, &dst, &dsp_frame_hst, &dsp_frame_vst);
-	dev_dbg(pp->dev, "dsp_frame_vst=%d, dsp_frame_hst=%d\n",
-		dsp_frame_vst, dsp_frame_hst);
-
-	if (src.hactive > dst.hactive) {
-		scl_hor_mode = 2;
-
-		if (hor_down_mode == 0) {
-			if ((src.hactive - 1) / (dst.hactive - 1) > 2)
-				scl_h_factor = ((src.hactive - 1) << 14) /
-					       (dst.hactive - 1);
-			else
-				scl_h_factor = ((src.hactive - 2) << 14) /
-					       (dst.hactive - 1);
-		} else {
-			scl_h_factor = (dst.hactive << 16) /
-				       (src.hactive - 1);
-		}
-
-		dev_dbg(pp->dev, "horizontal scale down\n");
-	} else if (src.hactive == dst.hactive) {
-		scl_hor_mode = 0;
-		scl_h_factor = 0;
-
-		dev_dbg(pp->dev, "horizontal no scale\n");
-	} else {
-		scl_hor_mode = 1;
-		scl_h_factor = ((src.hactive - 1) << 16) / (dst.hactive - 1);
-
-		dev_dbg(pp->dev, "horizontal scale up\n");
-	}
-
-	if (src.vactive > dst.vactive) {
-		scl_ver_mode = 2;
-
-		if (ver_down_mode == 0) {
-			if ((src.vactive - 1) / (dst.vactive - 1) > 2)
-				scl_v_factor = ((src.vactive - 1) << 14) /
-					       (dst.vactive - 1);
-			else
-				scl_v_factor = ((src.vactive - 2) << 14) /
-					       (dst.vactive - 1);
-		} else {
-			scl_v_factor = (dst.vactive << 16) /
-				       (src.vactive - 1);
-		}
-
-		dev_dbg(pp->dev, "vertical scale down\n");
-	} else if (src.vactive == dst.vactive) {
-		scl_ver_mode = 0;
-		scl_v_factor = 0;
-
-		dev_dbg(pp->dev, "vertical no scale\n");
-	} else {
-		scl_ver_mode = 1;
-		scl_v_factor = ((src.vactive - 1) << 16) / (dst.vactive - 1);
-
-		dev_dbg(pp->dev, "vertical scale up\n");
-	}
-
-	regmap_update_bits(pp->grf, GRF_RGB_DEC_CON0,
-			   SW_HRES_MASK, SW_HRES(src.hactive));
-	regmap_write(pp->grf, GRF_SCALER_CON0,
-		     SCL_VER_DOWN_MODE(ver_down_mode) |
-		     SCL_HOR_DOWN_MODE(hor_down_mode) |
-		     SCL_VER_MODE(scl_ver_mode) | SCL_HOR_MODE(scl_hor_mode));
-	regmap_write(pp->grf, GRF_SCALER_CON1,
-		     SCL_V_FACTOR(scl_v_factor) | SCL_H_FACTOR(scl_h_factor));
-	regmap_write(pp->grf, GRF_SCALER_CON2,
-		     DSP_FRAME_VST(dsp_frame_vst) |
-		     DSP_FRAME_HST(dsp_frame_hst));
-	regmap_write(pp->grf, GRF_SCALER_CON3,
-		     DSP_HS_END(dsp_hs_end) | DSP_HTOTAL(dsp_htotal));
-	regmap_write(pp->grf, GRF_SCALER_CON4,
-		     DSP_HACT_END(dsp_hact_end) | DSP_HACT_ST(dsp_hact_st));
-	regmap_write(pp->grf, GRF_SCALER_CON5,
-		     DSP_VS_END(dsp_vs_end) | DSP_VTOTAL(dsp_vtotal));
-	regmap_write(pp->grf, GRF_SCALER_CON6,
-		     DSP_VACT_END(dsp_vact_end) | DSP_VACT_ST(dsp_vact_st));
-	regmap_write(pp->grf, GRF_SCALER_CON7,
-		     DSP_HBOR_END(dsp_hbor_end) | DSP_HBOR_ST(dsp_hbor_st));
-	regmap_write(pp->grf, GRF_SCALER_CON8,
-		     DSP_VBOR_END(dsp_vbor_end) | DSP_VBOR_ST(dsp_vbor_st));
-}
-
-static void rk628_post_process_bridge_pre_enable(struct drm_bridge *bridge)
-{
-	struct rk628_post_process *pp = bridge_to_pp(bridge);
-	struct drm_display_mode *src = &pp->src_mode;
-	struct drm_display_mode *dst = &pp->dst_mode;
-	u64 dst_rate, src_rate;
-
-	reset_control_assert(pp->rstc_decoder);
-	udelay(10);
-	reset_control_deassert(pp->rstc_decoder);
-	udelay(10);
-
-	clk_set_rate(pp->clk_rx_read, src->clock * 1000);
-	clk_prepare_enable(pp->clk_rx_read);
-	reset_control_assert(pp->rstc_clk_rx);
-	udelay(10);
-	reset_control_deassert(pp->rstc_clk_rx);
-	udelay(10);
-
-	src_rate = src->clock * 1000;
-	dst_rate = src_rate * dst->vdisplay * dst->htotal;
-	do_div(dst_rate, src->vdisplay * src->htotal);
-	do_div(dst_rate, 1000);
-	dst->clock = dst_rate;
-
-	clk_set_rate(pp->sclk_vop, dst->clock * 1000);
-	clk_prepare_enable(pp->sclk_vop);
-	reset_control_assert(pp->rstc_vop);
-	udelay(10);
-	reset_control_deassert(pp->rstc_vop);
-	udelay(10);
-
-	regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_VSYNC_POL_MASK,
-			   SW_VSYNC_POL(pp->sync_pol));
-	regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_HSYNC_POL_MASK,
-			   SW_HSYNC_POL(pp->sync_pol));
-
-	rk628_post_process_scaler_init(pp, src, dst);
-}
-
-static void rk628_post_process_bridge_post_disable(struct drm_bridge *bridge)
-{
-
-}
-
-static void rk628_post_process_bridge_enable(struct drm_bridge *bridge)
-{
-	struct rk628_post_process *pp = bridge_to_pp(bridge);
-
-	regmap_write(pp->grf, GRF_SCALER_CON0, SCL_EN(1));
-}
-
-static void rk628_post_process_bridge_disable(struct drm_bridge *bridge)
-{
-	struct rk628_post_process *pp = bridge_to_pp(bridge);
-
-	regmap_write(pp->grf, GRF_SCALER_CON0, SCL_EN(0));
-
-	clk_disable_unprepare(pp->sclk_vop);
-	clk_disable_unprepare(pp->clk_rx_read);
-}
-
-static void rk628_post_process_bridge_mode_set(struct drm_bridge *bridge,
-					       const struct drm_display_mode *mode,
-					       const struct drm_display_mode *adj)
-{
-	struct rk628_post_process *pp = bridge_to_pp(bridge);
-	struct rk628 *rk628 = pp->parent;
-
-	drm_mode_copy(&pp->src_mode, adj);
-
-	if (rk628->dst_mode_valid)
-		drm_mode_copy(&pp->dst_mode, &rk628->dst_mode);
-	else
-		drm_mode_copy(&pp->dst_mode, &pp->src_mode);
-
-	/* hdmirx 4k-60Hz mode only support yuv420 */
-	if (pp->src_mode.clock == 594000)
-		regmap_write(pp->grf, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
-}
-
-static int rk628_post_process_bridge_attach(struct drm_bridge *bridge,
-					    enum drm_bridge_attach_flags flags)
-{
-	struct rk628_post_process *pp = bridge_to_pp(bridge);
-	struct device *dev = pp->dev;
-	int ret;
-
-	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
-					  NULL, &pp->bridge);
-	if (ret)
-		return ret;
-
-	ret = drm_bridge_attach(bridge->encoder, pp->bridge, bridge, flags);
-	if (ret) {
-		dev_err(dev, "failed to attach bridge\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static bool
-rk628_post_process_bridge_mode_fixup(struct drm_bridge *bridge,
-				     const struct drm_display_mode *mode,
-				     struct drm_display_mode *adj)
-{
-	struct rk628_post_process *pp = bridge_to_pp(bridge);
-
-	if (pp->sync_pol == MODE_FLAG_NSYNC) {
-		adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
-		adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
-	} else {
-		adj->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
-		adj->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
-	}
-
-	return true;
-}
-
-static const struct drm_bridge_funcs rk628_post_process_bridge_funcs = {
-	.pre_enable = rk628_post_process_bridge_pre_enable,
-	.post_disable = rk628_post_process_bridge_post_disable,
-	.enable = rk628_post_process_bridge_enable,
-	.disable = rk628_post_process_bridge_disable,
-	.mode_set = rk628_post_process_bridge_mode_set,
-	.mode_fixup = rk628_post_process_bridge_mode_fixup,
-	.attach = rk628_post_process_bridge_attach,
-};
-
-
-/**
- * rk628_scaler_add_src_mode - add source mode for scaler
- * @rk628: parent device
- * @connector: DRM connector
- * If need scale, call the function at last of get_modes.
- */
-int rk628_scaler_add_src_mode(struct rk628 *rk628,
-			      struct drm_connector *connector)
-{
-	struct drm_display_mode *pmode;
-	struct drm_display_mode *dst;
-
-	if (!rk628 || !connector)
-		return 0;
-
-	if (drm_mode_validate_driver(connector->dev, &rk628->src_mode) !=
-	    MODE_OK)
-		return 0;
-
-	list_for_each_entry(pmode, &connector->probed_modes, head) {
-		if (pmode->type & DRM_MODE_TYPE_PREFERRED) {
-			drm_mode_copy(&rk628->dst_mode, pmode);
-			drm_mode_copy(pmode, &rk628->src_mode);
-			pmode->type |= DRM_MODE_TYPE_PREFERRED;
-			rk628->dst_mode_valid = true;
-			break;
-		}
-	}
-	if (rk628->dst_mode_valid) {
-		dst = drm_mode_duplicate(connector->dev, &rk628->dst_mode);
-		dst->type &= ~DRM_MODE_TYPE_PREFERRED;
-		drm_mode_probed_add(connector, dst);
-		return 1;
-	}
-
-	return 0;
-}
-EXPORT_SYMBOL(rk628_scaler_add_src_mode);
-
-/**
- * rk628_mode_copy - rk628 mode copy
- * @rk628: parent device
- * @dst: dst mode
- * @src: src mode
- * Call the function at mode_set, replace drm_mode_copy.
- */
-void rk628_mode_copy(struct rk628 *rk628, struct drm_display_mode *dst,
-		     const struct drm_display_mode *src)
-{
-	if (rk628->dst_mode_valid)
-		drm_mode_copy(dst, &rk628->dst_mode);
-	else
-		drm_mode_copy(dst, src);
-}
-EXPORT_SYMBOL(rk628_mode_copy);
-
-static int rk628_post_process_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_post_process *pp;
-	u32 bus_flags;
-	u32 val;
-	int ret;
-
-	if (!of_device_is_available(dev->of_node))
-		return -ENODEV;
-
-	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
-	if (!pp)
-		return -ENOMEM;
-
-	pp->dev = dev;
-	pp->grf = rk628->grf;
-	platform_set_drvdata(pdev, pp);
-	pp->parent = rk628;
-
-	pp->sclk_vop = devm_clk_get(dev, "sclk_vop");
-	if (IS_ERR(pp->sclk_vop)) {
-		ret = PTR_ERR(pp->sclk_vop);
-		dev_err(dev, "failed to get sclk: %d\n", ret);
-		return ret;
-	}
-
-	pp->clk_rx_read = devm_clk_get(dev, "rx_read");
-	if (IS_ERR(pp->clk_rx_read)) {
-		ret = PTR_ERR(pp->clk_rx_read);
-		dev_err(dev, "failed to get clk_rx_read: %d\n", ret);
-		return ret;
-	}
-
-	pp->rstc_decoder = of_reset_control_get(dev->of_node, "decoder");
-	if (IS_ERR(pp->rstc_decoder)) {
-		ret = PTR_ERR(pp->rstc_decoder);
-		dev_err(dev, "failed to get decoder reset: %d\n", ret);
-		return ret;
-	}
-
-	pp->rstc_clk_rx = of_reset_control_get(dev->of_node, "clk_rx");
-	if (IS_ERR(pp->rstc_clk_rx)) {
-		ret = PTR_ERR(pp->rstc_clk_rx);
-		dev_err(dev, "failed to get clk_rx reset: %d\n", ret);
-		return ret;
-	}
-
-	pp->rstc_vop = of_reset_control_get(dev->of_node, "vop");
-	if (IS_ERR(pp->rstc_vop)) {
-		ret = PTR_ERR(pp->rstc_vop);
-		dev_err(dev, "failed to get vop reset: %d\n", ret);
-		return ret;
-	}
-
-	ret = of_property_read_u32(dev->of_node, "mode-sync-pol", &val);
-	if (ret < 0)
-		pp->sync_pol = MODE_FLAG_PSYNC;
-	else
-		pp->sync_pol = (!val ? MODE_FLAG_NSYNC : MODE_FLAG_PSYNC);
-
-	pp->base.funcs = &rk628_post_process_bridge_funcs;
-	pp->base.of_node = dev->of_node;
-	drm_bridge_add(&pp->base);
-
-	of_get_drm_display_mode(dev->of_node, &rk628->src_mode, &bus_flags,
-				OF_USE_NATIVE_MODE);
-
-	return 0;
-}
-
-static int rk628_post_process_remove(struct platform_device *pdev)
-{
-	struct rk628_post_process *pp = platform_get_drvdata(pdev);
-
-	drm_bridge_remove(&pp->base);
-
-	return 0;
-}
-
-static const struct of_device_id rk628_post_process_of_match[] = {
-	{ .compatible = "rockchip,rk628-post-process", },
-	{},
-};
-MODULE_DEVICE_TABLE(of, rk628_post_process_of_match);
-
-static struct platform_driver rk628_post_process_driver = {
-	.driver = {
-		.name = "rk628-post-process",
-		.of_match_table = of_match_ptr(rk628_post_process_of_match),
-	},
-	.probe = rk628_post_process_probe,
-	.remove = rk628_post_process_remove,
-};
-module_platform_driver(rk628_post_process_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 Post Process driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_rgb.c b/drivers/gpu/drm/rockchip/rk628/rk628_rgb.c
deleted file mode 100644
index df8cc3cee860..000000000000
--- a/drivers/gpu/drm/rockchip/rk628/rk628_rgb.c
+++ /dev/null
@@ -1,378 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Wyon Bi <bivvy.bi@rock-chips.com>
- */
-
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/regmap.h>
-#include <linux/mfd/rk628.h>
-#include <linux/phy/phy.h>
-#include <linux/reset.h>
-
-#include <drm/drm_of.h>
-#include <drm/drm_atomic.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_panel.h>
-
-#include <video/of_display_timing.h>
-#include <video/videomode.h>
-
-enum interface_type {
-	RGB_TX,
-	YUV_RX,
-	YUV_TX,
-	BT1120_RX,
-	BT1120_TX,
-};
-
-struct rk628_rgb {
-	struct drm_bridge base;
-	struct drm_connector connector;
-	struct drm_display_mode mode;
-	struct drm_panel *panel;
-	struct drm_bridge *bridge;
-	struct device *dev;
-	struct regmap *grf;
-	struct rk628 *parent;
-	struct clk *decclk;
-	struct reset_control *rstc;
-	bool dual_edge;
-	enum interface_type interface_type;
-};
-
-static inline struct rk628_rgb *bridge_to_rgb(struct drm_bridge *b)
-{
-	return container_of(b, struct rk628_rgb, base);
-}
-
-static inline struct rk628_rgb *connector_to_rgb(struct drm_connector *c)
-{
-	return container_of(c, struct rk628_rgb, connector);
-}
-
-static enum interface_type rk628_rgb_get_interface_type(struct rk628_rgb *rgb)
-{
-	const struct device_node *of_node = rgb->dev->of_node;
-
-	if (of_device_is_compatible(of_node, "rockchip,rk628-yuv-rx"))
-		return YUV_RX;
-	else if (of_device_is_compatible(of_node, "rockchip,rk628-yuv-tx"))
-		return YUV_TX;
-	else if (of_device_is_compatible(of_node, "rockchip,rk628-bt1120-rx"))
-		return BT1120_RX;
-	else if (of_device_is_compatible(of_node, "rockchip,rk628-bt1120-tx"))
-		return BT1120_TX;
-	else
-		return RGB_TX;
-}
-
-static struct drm_encoder *
-rk628_rgb_connector_best_encoder(struct drm_connector *connector)
-{
-	struct rk628_rgb *rgb = connector_to_rgb(connector);
-
-	return rgb->base.encoder;
-}
-
-static int rk628_rgb_connector_get_modes(struct drm_connector *connector)
-{
-	struct rk628_rgb *rgb = connector_to_rgb(connector);
-
-	return drm_panel_get_modes(rgb->panel, connector);
-}
-
-static const struct drm_connector_helper_funcs
-rk628_rgb_connector_helper_funcs = {
-	.get_modes = rk628_rgb_connector_get_modes,
-	.best_encoder = rk628_rgb_connector_best_encoder,
-};
-
-static void rk628_rgb_connector_destroy(struct drm_connector *connector)
-{
-	drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs rk628_rgb_connector_funcs = {
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.destroy = rk628_rgb_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static void rk628_bt1120_rx_enable(struct rk628_rgb *rgb)
-{
-	const struct drm_display_mode *mode = &rgb->mode;
-
-	reset_control_assert(rgb->rstc);
-	udelay(10);
-	reset_control_deassert(rgb->rstc);
-	udelay(10);
-
-	clk_set_rate(rgb->decclk, mode->clock * 1000);
-	clk_prepare_enable(rgb->decclk);
-
-	if (rgb->dual_edge) {
-		regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON0,
-				   DEC_DUALEDGE_EN, DEC_DUALEDGE_EN);
-
-		regmap_write(rgb->grf,
-			     GRF_BT1120_DCLK_DELAY_CON0, 0x10000000);
-		regmap_write(rgb->grf, GRF_BT1120_DCLK_DELAY_CON1, 0);
-	} else
-		regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON0,
-				   DEC_DUALEDGE_EN, 0);
-
-	regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON1,
-			   SW_SET_X_MASK, SW_SET_X(mode->hdisplay));
-	regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON2,
-			   SW_SET_Y_MASK, SW_SET_Y(mode->vdisplay));
-
-	regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
-			   SW_BT_DATA_OEN_MASK | SW_INPUT_MODE_MASK,
-			   SW_BT_DATA_OEN | SW_INPUT_MODE(INPUT_MODE_BT1120));
-
-	regmap_write(rgb->grf, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
-
-	regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON0,
-			   SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN,
-			   SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN);
-}
-
-static void rk628_bt1120_tx_enable(struct rk628_rgb *rgb)
-{
-	u32 val = 0;
-
-	regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
-			   SW_BT_DATA_OEN_MASK | SW_OUTPUT_MODE_MASK,
-			   SW_OUTPUT_MODE(OUTPUT_MODE_BT1120));
-	regmap_write(rgb->grf, GRF_CSC_CTRL_CON, SW_R2Y_EN(1));
-	regmap_update_bits(rgb->grf, GRF_POST_PROC_CON,
-			   SW_DCLK_OUT_INV_EN, SW_DCLK_OUT_INV_EN);
-
-	if (rgb->dual_edge) {
-		val |= ENC_DUALEDGE_EN(1);
-		regmap_write(rgb->grf, GRF_BT1120_DCLK_DELAY_CON0, 0x10000000);
-		regmap_write(rgb->grf, GRF_BT1120_DCLK_DELAY_CON1, 0);
-	}
-
-	val |= BT1120_UV_SWAP(1);
-	regmap_write(rgb->grf, GRF_RGB_ENC_CON, val);
-
-}
-
-static void rk628_rgb_bridge_enable(struct drm_bridge *bridge)
-{
-	struct rk628_rgb *rgb = bridge_to_rgb(bridge);
-
-	switch (rgb->interface_type) {
-	case YUV_RX:
-		regmap_write(rgb->grf, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
-		regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
-				   SW_BT_DATA_OEN_MASK | SW_INPUT_MODE_MASK,
-				   SW_BT_DATA_OEN | SW_INPUT_MODE(INPUT_MODE_YUV));
-		break;
-	case YUV_TX:
-		regmap_write(rgb->grf, GRF_CSC_CTRL_CON, SW_R2Y_EN(1));
-		regmap_update_bits(rgb->grf, GRF_POST_PROC_CON,
-				   SW_DCLK_OUT_INV_EN, SW_DCLK_OUT_INV_EN);
-
-		regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
-				   SW_BT_DATA_OEN_MASK | SW_OUTPUT_MODE_MASK,
-				   SW_OUTPUT_MODE(OUTPUT_MODE_YUV));
-		break;
-	case BT1120_RX:
-		rk628_bt1120_rx_enable(rgb);
-		break;
-	case BT1120_TX:
-		rk628_bt1120_tx_enable(rgb);
-		break;
-	case RGB_TX:
-	default:
-		regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
-				   SW_BT_DATA_OEN_MASK | SW_OUTPUT_MODE_MASK,
-				   SW_OUTPUT_MODE(OUTPUT_MODE_RGB));
-		regmap_update_bits(rgb->grf, GRF_POST_PROC_CON,
-				   SW_DCLK_OUT_INV_EN, SW_DCLK_OUT_INV_EN);
-		break;
-	}
-
-	if (rgb->panel) {
-		drm_panel_prepare(rgb->panel);
-		drm_panel_enable(rgb->panel);
-	}
-}
-
-static void rk628_rgb_bridge_disable(struct drm_bridge *bridge)
-{
-	struct rk628_rgb *rgb = bridge_to_rgb(bridge);
-
-	if (rgb->panel) {
-		drm_panel_disable(rgb->panel);
-		drm_panel_unprepare(rgb->panel);
-	}
-
-	if (rgb->decclk)
-		clk_disable_unprepare(rgb->decclk);
-
-	if (rgb->rstc)
-		reset_control_assert(rgb->rstc);
-}
-
-static int rk628_rgb_bridge_attach(struct drm_bridge *bridge,
-				   enum drm_bridge_attach_flags flags)
-{
-	struct rk628_rgb *rgb = bridge_to_rgb(bridge);
-	struct drm_connector *connector = &rgb->connector;
-	struct drm_device *drm = bridge->dev;
-	struct device *dev = rgb->dev;
-	int ret;
-
-	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
-					  &rgb->panel, &rgb->bridge);
-	if (ret)
-		return ret;
-
-	if (rgb->interface_type == YUV_RX || rgb->interface_type == BT1120_RX) {
-		if (!rgb->bridge) {
-			dev_err(dev, "decoder failed to find bridge\n");
-			return -EPROBE_DEFER;
-		}
-
-		ret = drm_bridge_attach(bridge->encoder, rgb->bridge, bridge,
-					flags);
-		if (ret) {
-			dev_err(dev, "failed to attach bridge\n");
-			return ret;
-		}
-	} else {
-		if (rgb->bridge) {
-			ret = drm_bridge_attach(bridge->encoder, rgb->bridge,
-						bridge, flags);
-			if (ret) {
-				dev_err(dev, "failed to attach bridge\n");
-				return ret;
-			}
-		}
-
-		if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
-			return 0;
-
-		if (rgb->panel) {
-			ret = drm_connector_init(drm, connector,
-						 &rk628_rgb_connector_funcs,
-						 DRM_MODE_CONNECTOR_DPI);
-			if (ret) {
-				dev_err(dev,
-					"Failed to initialize connector with drm\n");
-				return ret;
-			}
-
-			drm_connector_helper_add(connector,
-						 &rk628_rgb_connector_helper_funcs);
-			drm_connector_attach_encoder(connector,
-							  bridge->encoder);
-		}
-	}
-
-	return 0;
-}
-
-static void rk628_rgb_bridge_mode_set(struct drm_bridge *bridge,
-				      const struct drm_display_mode *mode,
-				      const struct drm_display_mode *adj)
-{
-	struct rk628_rgb *rgb = bridge_to_rgb(bridge);
-
-	drm_mode_copy(&rgb->mode, adj);
-}
-
-static const struct drm_bridge_funcs rk628_rgb_bridge_funcs = {
-	.attach = rk628_rgb_bridge_attach,
-	.enable = rk628_rgb_bridge_enable,
-	.disable = rk628_rgb_bridge_disable,
-	.mode_set = rk628_rgb_bridge_mode_set,
-};
-
-static int rk628_rgb_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_rgb *rgb;
-	int ret;
-
-	if (!of_device_is_available(dev->of_node))
-		return -ENODEV;
-
-	rgb = devm_kzalloc(dev, sizeof(*rgb), GFP_KERNEL);
-	if (!rgb)
-		return -ENOMEM;
-
-	rgb->dev = dev;
-	rgb->parent = rk628;
-	rgb->grf = rk628->grf;
-	rgb->interface_type = rk628_rgb_get_interface_type(rgb);
-	rgb->dual_edge = of_property_read_bool(dev->of_node, "dual-edge");
-	platform_set_drvdata(pdev, rgb);
-
-	if (rgb->interface_type == BT1120_RX) {
-		rgb->decclk = devm_clk_get(dev, "bt1120dec");
-		if (IS_ERR(rgb->decclk)) {
-			ret = PTR_ERR(rgb->decclk);
-			dev_err(dev, "failed to get dec clk: %d\n", ret);
-			return ret;
-		}
-
-		rgb->rstc = of_reset_control_get(dev->of_node, NULL);
-		if (IS_ERR(rgb->rstc)) {
-			ret = PTR_ERR(rgb->rstc);
-			dev_err(dev, "failed to get reset control: %d\n", ret);
-			return ret;
-		}
-	}
-
-	rgb->base.funcs = &rk628_rgb_bridge_funcs;
-	rgb->base.of_node = dev->of_node;
-	drm_bridge_add(&rgb->base);
-
-	return 0;
-}
-
-static int rk628_rgb_remove(struct platform_device *pdev)
-{
-	struct rk628_rgb *rgb = platform_get_drvdata(pdev);
-
-	drm_bridge_remove(&rgb->base);
-
-	return 0;
-}
-
-static const struct of_device_id rk628_rgb_of_match[] = {
-	{ .compatible = "rockchip,rk628-rgb-tx", },
-	{ .compatible = "rockchip,rk628-yuv-rx", },
-	{ .compatible = "rockchip,rk628-yuv-tx", },
-	{ .compatible = "rockchip,rk628-bt1120-rx", },
-	{ .compatible = "rockchip,rk628-bt1120-tx", },
-	{},
-};
-MODULE_DEVICE_TABLE(of, rk628_rgb_of_match);
-
-static struct platform_driver rk628_rgb_driver = {
-	.driver = {
-		.name = "rk628-rgb",
-		.of_match_table = of_match_ptr(rk628_rgb_of_match),
-	},
-	.probe = rk628_rgb_probe,
-	.remove = rk628_rgb_remove,
-};
-module_platform_driver(rk628_rgb_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 RGB driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index a8d994135524..b92a40aa623f 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1229,17 +1229,6 @@ config MFD_RK618
 	help
 	  if you say yes here you get support for the RK618 from Rockchip.
 
-config MFD_RK628
-	tristate "Rockchip RK628 MFD Driver"
-	depends on I2C
-	depends on OF
-	select MFD_CORE
-	select REGMAP_I2C
-	select REGMAP_IRQ
-	select PINCTRL_RK628
-	help
-	  if you say yes here you get support for the RK628 from Rockchip.
-
 config MFD_RK630
 	tristate "RK630 CORE module support"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b482699a05b6..e9f51a5df98f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -226,7 +226,6 @@ obj-$(CONFIG_MFD_VIPERBOARD)    += viperboard.o
 obj-$(CONFIG_MFD_NTXEC)		+= ntxec.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_RK618)		+= rk618.o
-obj-$(CONFIG_MFD_RK628)		+= rk628.o
 obj-$(CONFIG_MFD_RK630)		+= rk630.o
 obj-$(CONFIG_MFD_RK630_I2C)	+= rk630-i2c.o
 obj-$(CONFIG_MFD_RK630_SPI)	+= rk630-spi.o
diff --git a/drivers/mfd/rk628.c b/drivers/mfd/rk628.c
deleted file mode 100644
index 733442fd286a..000000000000
--- a/drivers/mfd/rk628.c
+++ /dev/null
@@ -1,482 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Wyon Bi <bivvy.bi@rock-chips.com>
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/gpio/consumer.h>
-#include <linux/regmap.h>
-#include <linux/mfd/core.h>
-#include <linux/mfd/rk628.h>
-
-enum {
-	RK628_IRQ_HDMITX_HPD_HIGH,
-	RK628_IRQ_HDMITX_HPD_LOW,
-	RK628_IRQ_HDMITX,
-	RK628_IRQ_GVI,
-	RK628_IRQ_DSI1,
-	RK628_IRQ_DSI0,
-	RK628_IRQ_CSI,
-	RK628_IRQ_HDMIRX,
-
-	RK628_IRQ_GPIO0,
-	RK628_IRQ_GPIO1,
-	RK628_IRQ_GPIO2,
-	RK628_IRQ_GPIO3,
-	RK628_IRQ_EFUSE,
-};
-
-static struct resource rk628_gpio_resources[] = {
-	DEFINE_RES_IRQ(RK628_IRQ_GPIO0),
-	DEFINE_RES_IRQ(RK628_IRQ_GPIO1),
-	DEFINE_RES_IRQ(RK628_IRQ_GPIO2),
-	DEFINE_RES_IRQ(RK628_IRQ_GPIO3),
-};
-
-static struct resource rk628_dsi0_resources[] = {
-	DEFINE_RES_IRQ(RK628_IRQ_DSI0),
-};
-
-static struct resource rk628_dsi1_resources[] = {
-	DEFINE_RES_IRQ(RK628_IRQ_DSI1),
-};
-
-static struct resource rk628_csi_resources[] = {
-	DEFINE_RES_IRQ(RK628_IRQ_CSI),
-	DEFINE_RES_IRQ(RK628_IRQ_HDMIRX),
-};
-
-static struct resource rk628_gvi_resources[] = {
-	DEFINE_RES_IRQ(RK628_IRQ_GVI),
-};
-
-static struct resource rk628_hdmi_resources[] = {
-	DEFINE_RES_IRQ(RK628_IRQ_HDMITX),
-	DEFINE_RES_IRQ(RK628_IRQ_HDMITX_HPD_HIGH),
-	DEFINE_RES_IRQ(RK628_IRQ_HDMITX_HPD_LOW),
-};
-
-static struct resource rk628_hdmirx_resources[] = {
-	DEFINE_RES_IRQ(RK628_IRQ_HDMIRX),
-};
-
-static struct resource rk628_efuse_resources[] = {
-	DEFINE_RES_IRQ(RK628_IRQ_EFUSE),
-};
-
-static const struct mfd_cell rk628_devs[] = {
-	{
-		.name = "rk628-cru",
-		.of_compatible = "rockchip,rk628-cru",
-	}, {
-		.name = "rk628-pinctrl",
-		.of_compatible = "rockchip,rk628-pinctrl",
-		.resources = rk628_gpio_resources,
-		.num_resources = ARRAY_SIZE(rk628_gpio_resources),
-	}, {
-		.name = "rk628-combrxphy",
-		.of_compatible = "rockchip,rk628-combrxphy",
-	}, {
-		.name = "rk628-combtxphy",
-		.of_compatible = "rockchip,rk628-combtxphy",
-	}, {
-		.name = "rk628-csi",
-		.of_compatible = "rockchip,rk628-csi",
-		.resources = rk628_csi_resources,
-		.num_resources = ARRAY_SIZE(rk628_csi_resources),
-	}, {
-		.name = "rk628-hdmirx",
-		.of_compatible = "rockchip,rk628-hdmirx",
-		.resources = rk628_hdmirx_resources,
-		.num_resources = ARRAY_SIZE(rk628_hdmirx_resources),
-	}, {
-		.name = "rk628-dsi1",
-		.of_compatible = "rockchip,rk628-dsi1",
-		.resources = rk628_dsi1_resources,
-		.num_resources = ARRAY_SIZE(rk628_dsi1_resources),
-	}, {
-		.name = "rk628-dsi0",
-		.of_compatible = "rockchip,rk628-dsi0",
-		.resources = rk628_dsi0_resources,
-		.num_resources = ARRAY_SIZE(rk628_dsi0_resources),
-	}, {
-		.name = "rk628-rgb-tx",
-		.of_compatible = "rockchip,rk628-rgb-tx",
-	}, {
-		.name = "rk628-yuv-rx",
-		.of_compatible = "rockchip,rk628-yuv-rx",
-	}, {
-		.name = "rk628-yuv-tx",
-		.of_compatible = "rockchip,rk628-yuv-tx",
-	}, {
-		.name = "rk628-bt1120-rx",
-		.of_compatible = "rockchip,rk628-bt1120-rx",
-	}, {
-		.name = "rk628-bt1120-tx",
-		.of_compatible = "rockchip,rk628-bt1120-tx",
-	}, {
-		.name = "rk628-lvds",
-		.of_compatible = "rockchip,rk628-lvds",
-	}, {
-		.name = "rk628-gvi",
-		.of_compatible = "rockchip,rk628-gvi",
-		.resources = rk628_gvi_resources,
-		.num_resources = ARRAY_SIZE(rk628_gvi_resources),
-	}, {
-		.name = "rk628-hdmi",
-		.of_compatible = "rockchip,rk628-hdmi",
-		.resources = rk628_hdmi_resources,
-		.num_resources = ARRAY_SIZE(rk628_hdmi_resources),
-	}, {
-		.name = "rk628-efuse",
-		.of_compatible = "rockchip,rk628-efuse",
-		.resources = rk628_efuse_resources,
-		.num_resources = ARRAY_SIZE(rk628_efuse_resources),
-	}, {
-		.name = "rk628-post-process",
-		.of_compatible = "rockchip,rk628-post-process",
-	},
-};
-
-static const struct regmap_irq rk628_irqs[] = {
-	REGMAP_IRQ_REG(RK628_IRQ_HDMITX_HPD_HIGH, 0, BIT(0)),
-	REGMAP_IRQ_REG(RK628_IRQ_HDMITX_HPD_LOW, 0, BIT(1)),
-	REGMAP_IRQ_REG(RK628_IRQ_HDMITX, 0, BIT(2)),
-	REGMAP_IRQ_REG(RK628_IRQ_GVI, 0, BIT(3)),
-	REGMAP_IRQ_REG(RK628_IRQ_DSI1, 0, BIT(4)),
-	REGMAP_IRQ_REG(RK628_IRQ_DSI0, 0, BIT(5)),
-	REGMAP_IRQ_REG(RK628_IRQ_CSI, 0, BIT(6)),
-	REGMAP_IRQ_REG(RK628_IRQ_HDMIRX, 0, BIT(8)),
-
-	REGMAP_IRQ_REG(RK628_IRQ_GPIO0, 4, BIT(0)),
-	REGMAP_IRQ_REG(RK628_IRQ_GPIO1, 4, BIT(1)),
-	REGMAP_IRQ_REG(RK628_IRQ_GPIO2, 4, BIT(2)),
-	REGMAP_IRQ_REG(RK628_IRQ_GPIO3, 4, BIT(3)),
-	REGMAP_IRQ_REG(RK628_IRQ_EFUSE, 4, BIT(4)),
-};
-
-static struct rk628_irq_chip_data rk628_irq_chip_data = {
-	.name = "rk628",
-	.irqs = rk628_irqs,
-	.num_irqs = ARRAY_SIZE(rk628_irqs),
-	.num_regs = 2,
-	.irq_reg_stride = (GRF_INTR1_STATUS - GRF_INTR0_STATUS) / 4,
-	.reg_stride = 4,
-	.status_base = GRF_INTR0_STATUS,
-	.mask_base = GRF_INTR0_EN,
-	.ack_base = GRF_INTR0_CLR_EN,
-};
-
-static const struct regmap_config rk628_grf_regmap_config = {
-	.name = "grf",
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = 4,
-	.max_register = GRF_MAX_REGISTER,
-	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
-	.val_format_endian = REGMAP_ENDIAN_LITTLE,
-};
-
-static inline const struct regmap_irq *
-irq_to_regmap_irq(struct rk628_irq_chip_data *d, int irq)
-{
-	return &d->irqs[irq];
-}
-
-static void rk628_irq_lock(struct irq_data *data)
-{
-	struct rk628_irq_chip_data *d = irq_data_get_irq_chip_data(data);
-
-	mutex_lock(&d->lock);
-}
-
-static void rk628_irq_sync_unlock(struct irq_data *data)
-{
-	struct rk628_irq_chip_data *d = irq_data_get_irq_chip_data(data);
-	int i;
-	u32 reg, mask, val;
-
-	for (i = 0; i < d->num_regs; i++) {
-		reg = d->mask_base + (i * d->reg_stride * d->irq_reg_stride);
-		mask = d->mask_buf_def[i];
-		val = mask << 16 | (~d->mask_buf[i] & mask);
-		regmap_write(d->map, reg, val);
-	}
-
-	mutex_unlock(&d->lock);
-}
-
-static void rk628_irq_enable(struct irq_data *data)
-{
-	struct rk628_irq_chip_data *d = irq_data_get_irq_chip_data(data);
-	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
-
-	d->mask_buf[irq_data->reg_offset / d->reg_stride] &= ~irq_data->mask;
-}
-
-static void rk628_irq_disable(struct irq_data *data)
-{
-	struct rk628_irq_chip_data *d = irq_data_get_irq_chip_data(data);
-	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
-
-	d->mask_buf[irq_data->reg_offset / d->reg_stride] |= irq_data->mask;
-}
-
-static const struct irq_chip rk628_irq_chip = {
-	.irq_bus_lock = rk628_irq_lock,
-	.irq_bus_sync_unlock = rk628_irq_sync_unlock,
-	.irq_disable = rk628_irq_disable,
-	.irq_enable = rk628_irq_enable,
-};
-
-static irqreturn_t rk628_irq_thread(int irq, void *data)
-{
-	struct rk628_irq_chip_data *d = data;
-	int i;
-	bool handled = false;
-	u32 reg;
-
-	for (i = 0; i < d->num_regs; i++) {
-		reg = d->status_base + (i * d->reg_stride * d->irq_reg_stride);
-		regmap_read(d->map, reg, &d->status_buf[i]);
-	}
-
-	for (i = 0; i < d->num_irqs; i++) {
-		if (d->status_buf[d->irqs[i].reg_offset / d->reg_stride] & d->irqs[i].mask) {
-			handle_nested_irq(irq_find_mapping(d->domain, i));
-			handled = true;
-		}
-	}
-
-	for (i = 0; i < d->num_regs; i++) {
-		if (d->status_buf[i]) {
-			reg = d->ack_base + (i * d->reg_stride * d->irq_reg_stride);
-			regmap_write(d->map, reg,
-				     d->status_buf[i] << 16 | d->status_buf[i]);
-		}
-	}
-
-	if (handled)
-		return IRQ_HANDLED;
-	else
-		return IRQ_NONE;
-}
-
-static int rk628_irq_map(struct irq_domain *h, unsigned int virq,
-			 irq_hw_number_t hw)
-{
-	struct rk628_irq_chip_data *d = h->host_data;
-
-	irq_set_chip_data(virq, d);
-	irq_set_chip(virq, &d->irq_chip);
-	irq_set_nested_thread(virq, 1);
-	irq_set_parent(virq, d->irq);
-	irq_set_noprobe(virq);
-
-	return 0;
-}
-
-static const struct irq_domain_ops rk628_irq_domain_ops = {
-	.map = rk628_irq_map,
-	.xlate = irq_domain_xlate_onetwocell,
-};
-
-static int rk628_irq_init(struct rk628 *rk628, int irq)
-{
-	struct device *dev = rk628->dev;
-	struct rk628_irq_chip_data *d = rk628->irq_data;
-	struct regmap *map = rk628->grf;
-	u32 reg, mask, val;
-	int i;
-	int ret;
-
-	if (d->num_regs <= 0)
-		return -EINVAL;
-
-	d->status_buf = devm_kcalloc(dev, d->num_regs, sizeof(unsigned int),
-				     GFP_KERNEL);
-	if (!d->status_buf)
-		return -ENOMEM;
-
-	d->mask_buf = devm_kcalloc(dev, d->num_regs, sizeof(unsigned int),
-				   GFP_KERNEL);
-	if (!d->mask_buf)
-		return -ENOMEM;
-
-	d->mask_buf_def = devm_kcalloc(dev, d->num_regs, sizeof(unsigned int),
-				       GFP_KERNEL);
-	if (!d->mask_buf_def)
-		return -ENOMEM;
-
-	d->irq_chip = rk628_irq_chip;
-	d->irq_chip.name = d->name;
-	d->irq = irq;
-	d->map = map;
-
-	mutex_init(&d->lock);
-
-	for (i = 0; i < d->num_irqs; i++)
-		d->mask_buf_def[d->irqs[i].reg_offset / d->reg_stride] |= d->irqs[i].mask;
-
-	/* Mask all the interrupts by default */
-	for (i = 0; i < d->num_regs; i++) {
-		d->mask_buf[i] = d->mask_buf_def[i];
-		reg = d->mask_base + (i * d->reg_stride * d->irq_reg_stride);
-		mask = d->mask_buf[i];
-		val = mask << 16 | (~d->mask_buf[i] & mask);
-		regmap_write(d->map, reg, val);
-	}
-
-	d->domain = irq_domain_add_linear(dev->of_node, d->num_irqs,
-					  &rk628_irq_domain_ops, d);
-	if (!d->domain) {
-		dev_err(dev, "Failed to create IRQ domain\n");
-		return -ENOMEM;
-	}
-
-	ret = devm_request_threaded_irq(dev, irq, NULL, rk628_irq_thread,
-					IRQF_ONESHOT, d->name, d);
-	if (ret != 0) {
-		irq_domain_remove(d->domain);
-		dev_err(dev, "Failed to request IRQ %d: %d\n", irq, ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static void rk628_irq_exit(struct rk628 *rk628)
-{
-	struct rk628_irq_chip_data *d = rk628->irq_data;
-	unsigned int virq;
-	int hwirq;
-
-	/* Dispose all virtual irq from irq domain before removing it */
-	for (hwirq = 0; hwirq < d->num_irqs; hwirq++) {
-		/* Ignore hwirq if holes in the IRQ list */
-		if (!d->irqs[hwirq].mask)
-			continue;
-
-		/*
-		 * Find the virtual irq of hwirq on chip and if it is
-		 * there then dispose it
-		 */
-		virq = irq_find_mapping(d->domain, hwirq);
-		if (virq)
-			irq_dispose_mapping(virq);
-	}
-
-	irq_domain_remove(d->domain);
-}
-
-static int
-rk628_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
-{
-	struct device *dev = &client->dev;
-	struct rk628 *rk628;
-	int ret;
-
-	rk628 = devm_kzalloc(dev, sizeof(*rk628), GFP_KERNEL);
-	if (!rk628)
-		return -ENOMEM;
-
-	rk628->dev = dev;
-	rk628->client = client;
-	rk628->irq_data = &rk628_irq_chip_data;
-	i2c_set_clientdata(client, rk628);
-
-	rk628->enable_gpio = devm_gpiod_get_optional(dev, "enable",
-						     GPIOD_OUT_LOW);
-	if (IS_ERR(rk628->enable_gpio)) {
-		ret = PTR_ERR(rk628->enable_gpio);
-		dev_err(dev, "failed to request enable GPIO: %d\n", ret);
-		return ret;
-	}
-
-	rk628->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
-	if (IS_ERR(rk628->reset_gpio)) {
-		ret = PTR_ERR(rk628->reset_gpio);
-		dev_err(dev, "failed to request reset GPIO: %d\n", ret);
-		return ret;
-	}
-
-	gpiod_set_value(rk628->enable_gpio, 1);
-	usleep_range(10000, 11000);
-	gpiod_set_value(rk628->reset_gpio, 0);
-	usleep_range(10000, 11000);
-	gpiod_set_value(rk628->reset_gpio, 1);
-	usleep_range(10000, 11000);
-	gpiod_set_value(rk628->reset_gpio, 0);
-	usleep_range(10000, 11000);
-
-	rk628->grf = devm_regmap_init_i2c(client, &rk628_grf_regmap_config);
-	if (IS_ERR(rk628->grf)) {
-		ret = PTR_ERR(rk628->grf);
-		dev_err(dev, "failed to allocate register map: %d\n", ret);
-		return ret;
-	}
-
-	/* selete int io function */
-	ret = regmap_write(rk628->grf, GRF_GPIO3AB_SEL_CON, 0x30002000);
-	if (ret) {
-		dev_err(dev, "failed to access register: %d\n", ret);
-		return ret;
-	}
-
-	ret = rk628_irq_init(rk628, client->irq);
-	if (ret) {
-		dev_err(dev, "failed to add IRQ chip: %d\n", ret);
-		return ret;
-	}
-
-	ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE,
-			      rk628_devs, ARRAY_SIZE(rk628_devs),
-			      NULL, 0, rk628->irq_data->domain);
-	if (ret) {
-		rk628_irq_exit(rk628);
-		dev_err(dev, "Failed to add MFD children: %d\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static void rk628_i2c_remove(struct i2c_client *client)
-{
-	struct rk628 *rk628 = i2c_get_clientdata(client);
-
-	mfd_remove_devices(rk628->dev);
-	rk628_irq_exit(rk628);
-}
-
-static const struct of_device_id rk628_of_match[] = {
-	{ .compatible = "rockchip,rk628", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, rk628_of_match);
-
-static const struct i2c_device_id rk628_i2c_id[] = {
-	{ "rk628", 0 },
-	{}
-};
-MODULE_DEVICE_TABLE(i2c, rk628_i2c_id);
-
-static struct i2c_driver rk628_i2c_driver = {
-	.driver = {
-		.name = "rk628",
-		.of_match_table = of_match_ptr(rk628_of_match),
-	},
-	.probe = rk628_i2c_probe,
-	.remove = rk628_i2c_remove,
-	.id_table = rk628_i2c_id,
-};
-module_i2c_driver(rk628_i2c_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Rockchip RK628 MFD driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 4d92626bc583..2b2b4f69a535 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -218,18 +218,6 @@ config NVMEM_RAVE_SP_EEPROM
 	help
 	  Say y here to enable Rave SP EEPROM support.
 
-config NVMEM_RK628_EFUSE
-	tristate "RK628 eFuse Support"
-	depends on ARCH_ROCKCHIP || COMPILE_TEST
-	depends on HAS_IOMEM
-	depends on MFD_RK628
-	help
-	  This is a simple drive to dump specified values of Rk628 SoC
-	  from eFuse, such as cpu-leakage.
-
-	  This driver can also be built as a module. If so, the module
-	  will be called nvmem_rk628_efuse.
-
 config NVMEM_RMEM
 	tristate "Reserved Memory Based Driver Support"
 	depends on HAS_IOMEM
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 0609e6e18856..e5306808990e 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -45,8 +45,6 @@ obj-$(CONFIG_NVMEM_QCOM_QFPROM)		+= nvmem_qfprom.o
 nvmem_qfprom-y				:= qfprom.o
 obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM)	+= nvmem-rave-sp-eeprom.o
 nvmem-rave-sp-eeprom-y			:= rave-sp-eeprom.o
-obj-$(CONFIG_NVMEM_RK628_EFUSE)		+= nvmem_rk628_efuse.o
-nvmem_rk628_efuse-y			:= rk628-efuse.o
 obj-$(CONFIG_NVMEM_RMEM) 		+= nvmem-rmem.o
 nvmem-rmem-y				:= rmem.o
 obj-$(CONFIG_NVMEM_ROCKCHIP_EFUSE)	+= nvmem_rockchip_efuse.o
diff --git a/drivers/nvmem/rk628-efuse.c b/drivers/nvmem/rk628-efuse.c
deleted file mode 100644
index 87b5a3c78021..000000000000
--- a/drivers/nvmem/rk628-efuse.c
+++ /dev/null
@@ -1,299 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * RK628 eFuse Driver
- *
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Weixin Zhou <zwx@rock-chips.com>
- */
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/nvmem-provider.h>
-#include <linux/slab.h>
-#include <linux/gpio/consumer.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/mfd/rk628.h>
-
-#define EFUSE_SIZE		64
-
-#define T_CSB_P_S		0
-#define T_PGENB_P_S		(15 + 200)
-#define T_LOAD_P_S		0
-#define T_ADDR_P_S		(15 + 200 + 5)
-#define T_STROBE_P_S		((150 + 2000 + 100) / 9)
-#define T_CSB_P_L		0
-#define T_PGENB_P_L		(15 + 200 + 10 + 200 + 190 + 10)
-#define T_LOAD_P_L		(15 + 200 + 200 + 190 + 10 + 100 + 15)
-#define T_ADDR_P_L		(15 + 200 + 5 + 200 + 5)
-#define T_STROBE_P_L		((150 + 2000 + 100 + 2000) / 9)
-#define T_CSB_R_S		0
-#define T_PGENB_R_S		0
-#define T_LOAD_R_S		15
-#define T_ADDR_R_S		(15 + 9)
-#define T_STROBE_R_S		((150 + 100) / 9)
-#define T_CSB_R_L		0
-#define T_PGENB_R_L		0
-#define T_LOAD_R_L		(15 + 5 + 5 + 10 + 15)
-#define T_ADDR_R_L		(15 + 10 + 5 + 1)
-#define T_STROBE_R_L		((150 + 100 + 50) / 8)
-
-#define T_CSB_P			0x28
-#define T_PGENB_P		0x2c
-#define T_LOAD_P		0x30
-#define T_ADDR_P		0x34
-#define T_STROBE_P		0x38
-#define T_CSB_R			0x3c
-#define T_PGENB_R		0x40
-#define T_LOAD_R		0x44
-#define T_ADDR_R		0x48
-#define T_STROBE_R		0x4c
-#define EFUSE_REVISION		0x50
-
-#define RK628_EFUSE_BASE	0xb0000
-#define RK628_MOD		0x00
-#define RK628_INT_STATUS	0x0018
-#define RK628_DOUT		0x0020
-#define RK628_AUTO_CTRL		0x0024
-#define RK628_USER_MODE		BIT(0)
-#define RK628_INT_FINISH	BIT(0)
-#define RK628_AUTO_ENB		BIT(0)
-#define RK628_AUTO_RD		BIT(1)
-#define RK628_ADDR_ROW		16
-#define RK628_ADDR_COL		22
-#define RK628_A_SHIFT		16
-#define RK628_A_MASK		0x3ff
-#define RK628_NBYTES		1
-
-#define REG_EFUSE_CTRL		0x0000
-#define REG_EFUSE_DOUT		0x0004
-
-struct rk628_efuse_chip {
-	struct device *dev;
-	u32 base;
-	struct clk *clk;
-	struct regmap *regmap;
-	struct gpio_desc *avdd_gpio;
-};
-
-static int rk628_read(struct regmap *regmap, u32 reg)
-{
-	int ret;
-	u32 val;
-	struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap);
-
-	ret = regmap_read(regmap, reg, &val);
-	if (ret) {
-		dev_err(efuse->dev, "rk628-efuse:failed to read reg 0x%x\n", reg);
-		return ret;
-	}
-
-	return val;
-}
-
-static int rk628_write(struct regmap *regmap, u32 val, u32 reg)
-{
-	int ret;
-	struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap);
-
-	ret = regmap_write(regmap, reg, val);
-	if (ret)
-		dev_err(efuse->dev, "rk628-efuse:failed to write reg 0x%x\n", reg);
-
-	return ret;
-}
-
-static void rk628_efuse_timing_init(struct rk628_efuse_chip *efuse)
-{
-	u32 base = efuse->base;
-	/* enable auto mode */
-	rk628_write(efuse->regmap,
-		    rk628_read(efuse->regmap, base + RK628_MOD) & (~RK628_USER_MODE),
-		    base + RK628_MOD);
-
-	/* setup efuse timing */
-	rk628_write(efuse->regmap, (T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);
-	rk628_write(efuse->regmap, (T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);
-	rk628_write(efuse->regmap, (T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);
-	rk628_write(efuse->regmap, (T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);
-	rk628_write(efuse->regmap, (T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);
-	rk628_write(efuse->regmap, (T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);
-	rk628_write(efuse->regmap, (T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);
-	rk628_write(efuse->regmap, (T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);
-	rk628_write(efuse->regmap, (T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R);
-	rk628_write(efuse->regmap, (T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R);
-}
-
-static void rk628_efuse_timing_deinit(struct rk628_efuse_chip *efuse)
-{
-	u32 base = efuse->base;
-	/* disable auto mode */
-	rk628_write(efuse->regmap,
-		    rk628_read(efuse->regmap, base + RK628_MOD) | RK628_USER_MODE, base + RK628_MOD);
-
-	/* clear efuse timing */
-	rk628_write(efuse->regmap, 0, base + T_CSB_P);
-	rk628_write(efuse->regmap, 0, base + T_PGENB_P);
-	rk628_write(efuse->regmap, 0, base + T_LOAD_P);
-	rk628_write(efuse->regmap, 0, base + T_ADDR_P);
-	rk628_write(efuse->regmap, 0, base + T_STROBE_P);
-	rk628_write(efuse->regmap, 0, base + T_CSB_R);
-	rk628_write(efuse->regmap, 0, base + T_PGENB_R);
-	rk628_write(efuse->regmap, 0, base + T_LOAD_R);
-	rk628_write(efuse->regmap, 0, base + T_ADDR_R);
-	rk628_write(efuse->regmap, 0, base + T_STROBE_R);
-}
-
-static int rk628_efuse_read(void *context, unsigned int offset,
-				      void *val, size_t bytes)
-{
-	struct rk628_efuse_chip *efuse = context;
-	unsigned int addr_start, addr_end, addr_offset, addr_len;
-	u32 out_value, status;
-	u8 *buf;
-	int ret, i = 0;
-
-	ret = clk_prepare_enable(efuse->clk);
-	if (ret < 0) {
-		dev_err(efuse->dev, "failed to prepare/enable efuse pclk\n");
-		return ret;
-	}
-
-	addr_start = rounddown(offset, RK628_NBYTES) / RK628_NBYTES;
-	addr_end = roundup(offset + bytes, RK628_NBYTES) / RK628_NBYTES;
-	addr_offset = offset % RK628_NBYTES;
-	addr_len = addr_end - addr_start;
-
-	buf = kzalloc(sizeof(*buf) * addr_len * RK628_NBYTES, GFP_KERNEL);
-	if (!buf) {
-		ret = -ENOMEM;
-		goto nomem;
-	}
-
-	rk628_efuse_timing_init(efuse);
-
-	while (addr_len--) {
-		rk628_write(efuse->regmap, RK628_AUTO_RD | RK628_AUTO_ENB |
-		       ((addr_start++ & RK628_A_MASK) << RK628_A_SHIFT),
-		       efuse->base + RK628_AUTO_CTRL);
-		udelay(2);
-		status = rk628_read(efuse->regmap, efuse->base + RK628_INT_STATUS);
-		if (!(status & RK628_INT_FINISH)) {
-			ret = -EIO;
-			goto err;
-		}
-		out_value = rk628_read(efuse->regmap, efuse->base + RK628_DOUT);
-		rk628_write(efuse->regmap, RK628_INT_FINISH, efuse->base + RK628_INT_STATUS);
-
-		memcpy(&buf[i], &out_value, RK628_NBYTES);
-		i += RK628_NBYTES;
-	}
-	memcpy(val, buf + addr_offset, bytes);
-err:
-	rk628_efuse_timing_deinit(efuse);
-	kfree(buf);
-nomem:
-	clk_disable_unprepare(efuse->clk);
-
-	return ret;
-}
-
-static struct nvmem_config econfig = {
-	.name = "rk628-efuse",
-	.owner = THIS_MODULE,
-	.stride = 1,
-	.word_size = 1,
-	.read_only = true,
-};
-
-static const struct regmap_range rk628_efuse_readable_ranges[] = {
-	regmap_reg_range(RK628_EFUSE_BASE, RK628_EFUSE_BASE + EFUSE_REVISION),
-};
-
-static const struct regmap_access_table rk628_efuse_readable_table = {
-	.yes_ranges     = rk628_efuse_readable_ranges,
-	.n_yes_ranges   = ARRAY_SIZE(rk628_efuse_readable_ranges),
-};
-
-static const struct regmap_config rk628_efuse_regmap_config = {
-	.name = "rk628-efuse",
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = 4,
-	.max_register = RK628_EFUSE_BASE + EFUSE_REVISION,
-	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
-	.val_format_endian = REGMAP_ENDIAN_LITTLE,
-	.rd_table = &rk628_efuse_readable_table,
-};
-
-static const struct of_device_id rk628_efuse_match[] = {
-	{
-		.compatible = "rockchip,rk628-efuse",
-	},
-	{ /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(of, rk628_efuse_match);
-
-static int __init rk628_efuse_probe(struct platform_device *pdev)
-{
-	struct nvmem_device *nvmem;
-	struct rk628_efuse_chip *efuse;
-	struct device *dev = &pdev->dev;
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	int ret;
-
-	efuse = devm_kzalloc(&pdev->dev, sizeof(struct rk628_efuse_chip),
-			     GFP_KERNEL);
-	if (!efuse)
-		return -ENOMEM;
-
-	efuse->regmap = devm_regmap_init_i2c(rk628->client,
-					&rk628_efuse_regmap_config);
-	if (IS_ERR(efuse->regmap)) {
-		ret = PTR_ERR(efuse->regmap);
-		dev_err(dev, "failed to allocate register map: %d\n",
-				   ret);
-		return ret;
-	}
-
-	efuse->clk = devm_clk_get(&pdev->dev, "pclk");
-	if (IS_ERR(efuse->clk)) {
-		dev_err(dev, "failed to get pclk: %ld\n", PTR_ERR(efuse->clk));
-		return PTR_ERR(efuse->clk);
-	}
-
-	efuse->avdd_gpio = devm_gpiod_get_optional(dev, "efuse", GPIOD_OUT_LOW);
-	efuse->base = RK628_EFUSE_BASE;
-	efuse->dev = &pdev->dev;
-	econfig.size = EFUSE_SIZE;
-	econfig.reg_read = (void *)&rk628_efuse_read;
-	econfig.priv = efuse;
-	econfig.dev = efuse->dev;
-	nvmem = devm_nvmem_register(&econfig);
-	if (IS_ERR(nvmem))
-		return PTR_ERR(nvmem);
-
-	platform_set_drvdata(pdev, nvmem);
-
-	return 0;
-}
-
-static struct platform_driver rk628_efuse_driver = {
-	.probe = rk628_efuse_probe,
-	.driver = {
-		.name = "rk628-efuse",
-		.of_match_table = rk628_efuse_match,
-	},
-};
-
-module_platform_driver(rk628_efuse_driver);
-
-MODULE_DESCRIPTION("rk628_efuse driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 79cc1a83c5a8..e6718970d88e 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -414,16 +414,6 @@ config PINCTRL_PISTACHIO
 	help
 	  This support pinctrl and GPIO driver for IMG Pistachio SoC.
 
-config PINCTRL_RK628
-	tristate "Pinctrl and GPIO driver for RK628 PMIC"
-	depends on MFD_RK628
-	select GPIOLIB
-	select PINMUX
-	select GENERIC_PINCONF
-	select REGMAP_IRQ
-	help
-	  This selects the pinctrl driver for RK628.
-
 config PINCTRL_RK805
 	tristate "Pinctrl and GPIO driver for RK805 PMIC"
 	depends on MFD_RK808
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d4c980ff831a..903cd72e510f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_PINCTRL_OXNAS)	+= pinctrl-oxnas.o
 obj-$(CONFIG_PINCTRL_PALMAS)	+= pinctrl-palmas.o
 obj-$(CONFIG_PINCTRL_PIC32)	+= pinctrl-pic32.o
 obj-$(CONFIG_PINCTRL_PISTACHIO)	+= pinctrl-pistachio.o
-obj-$(CONFIG_PINCTRL_RK628)	+= pinctrl-rk628.o
 obj-$(CONFIG_PINCTRL_RK805)	+= pinctrl-rk805.o
 obj-$(CONFIG_PINCTRL_RK806)	+= pinctrl-rk806.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o
diff --git a/drivers/pinctrl/pinctrl-rk628.c b/drivers/pinctrl/pinctrl-rk628.c
deleted file mode 100644
index 6e07be50e6e2..000000000000
--- a/drivers/pinctrl/pinctrl-rk628.c
+++ /dev/null
@@ -1,1696 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Pinctrl driver for Rockchip RK628
- *
- * Copyright (c) 2019, Fuzhou Rockchip Electronics Co., Ltd
- *
- * Author: Weixin Zhou <zwx@rock-chips.com>
- *
- * Based on the pinctrl-rk805/pinctrl-rockchip driver
- */
-
-#include <linux/gpio/driver.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pm.h>
-#include <linux/slab.h>
-#include <linux/clk.h>
-#include <linux/interrupt.h>
-#include <linux/regmap.h>
-#include <linux/mfd/rk628.h>
-
-#include "core.h"
-#include "pinconf.h"
-#include "pinctrl-utils.h"
-
-#define GPIO0_BASE	0xD0000
-#define GPIO1_BASE	0xE0000
-#define GPIO2_BASE	0xF0000
-#define GPIO3_BASE	0x100000
-#define GPIO_MAX_REGISTER	(GPIO3_BASE + GPIO_VER_ID)
-
-/* GPIO control registers */
-#define GPIO_SWPORT_DR_L	0x00
-#define GPIO_SWPORT_DR_H	0x04
-#define GPIO_SWPORT_DDR_L	0x08
-#define GPIO_SWPORT_DDR_H	0x0c
-#define GPIO_INTEN_L		0x10
-#define GPIO_INTEN_H		0x14
-#define GPIO_INTMASK_L		0x18
-#define GPIO_INTMASK_H		0x1c
-#define GPIO_INTTYPE_L		0x20
-#define GPIO_INTTYPE_H		0x24
-#define GPIO_INT_POLARITY_L	0x28
-#define GPIO_INT_POLARITY_H	0x2c
-#define GPIO_INT_BOTHEDGE_L	0x30
-#define GPIO_INT_BOTHEDGE_H	0x34
-#define GPIO_DEBOUNCE_L		0x38
-#define GPIO_DEBOUNCE_H		0x3c
-#define GPIO_DBCLK_DIV_EN_L	0x40
-#define GPIO_DBCLK_DIV_EN_H	0x44
-#define GPIO_INT_STATUS		0x50
-#define GPIO_INT_RAWSTATUS	0x58
-#define GPIO_PORTS_EOI_L	0x60
-#define GPIO_PORTS_EOI_H	0x64
-#define GPIO_EXT_PORT		0x70
-#define GPIO_VER_ID		0x78
-
-#define GPIO_REG_LOW		0x0
-#define GPIO_REG_HIGH		0x1
-
-/* GPIO control registers */
-#define GPIO_INTMASK		0x34
-#define GPIO_PORTS_EOI		0x4c
-
-#define BANK_OFFSET 32
-
-#define IRQ_CHIP(fname)						\
-	[IRQCHIP_##fname] = {					\
-		.name = "rk628-"#fname,				\
-		.irq_bus_lock		= rk628_irq_lock,	\
-		.irq_bus_sync_unlock	= rk628_irq_sync_unlock,\
-		.irq_disable		= rk628_irq_disable,	\
-		.irq_enable		= rk628_irq_enable,	\
-		.irq_set_type		= rk628_irq_set_type,	\
-	}
-
-struct rk628_pin_function {
-	const char *name;
-	const char **groups;
-	unsigned int ngroups;
-	int mux_option;
-};
-
-struct rk628_pin_group {
-	const char *name;
-	const unsigned int pins[1];
-	unsigned int npins;
-	int iomux_base;
-};
-
-struct rk628_pin_bank {
-	char *name;
-	u32 reg_base;
-	u32 nr_pins;
-	struct device_node *of_node;
-	struct pinctrl_gpio_range grange;
-	struct gpio_chip gpio_chip;
-	struct clk *clk;
-	struct rk628_pctrl_info *pci;
-
-	struct irq_chip irq_chip;
-	struct irq_domain *domain;
-	int irq;
-	struct mutex lock;
-	unsigned int mask_regs[2];
-	unsigned int polarity_regs[2];
-	unsigned int level_regs[2];
-	unsigned int bothedge_regs[2];
-};
-
-struct rk628_pctrl_info {
-	struct device *dev;
-	struct pinctrl_dev *pctl;
-	struct pinctrl_desc pinctrl_desc;
-	const struct rk628_pin_function *functions;
-	unsigned int num_functions;
-	const struct rk628_pin_group *groups;
-	int num_groups;
-	const struct pinctrl_pin_desc *pins;
-	unsigned int num_pins;
-	struct regmap *regmap;
-	struct regmap *grf_regmap;
-	struct rk628_pin_bank *pin_banks;
-	u32 nr_banks;
-};
-
-enum rk628_pinmux_option {
-	PINMUX_FUNC0,
-	PINMUX_FUNC1,
-};
-
-#define PINCTRL_GROUP(a, b, c, d) { .name = a, .pins = b, .npins = c, .iomux_base = d}
-#define PINCTRL_BANK(a, b, c) { .name = a, .reg_base = b, .nr_pins = c}
-
-enum rk628_functions {
-	MUX_GPIO,
-};
-
-static const char *gpio_groups[] = {
-	"gpio0a0", "gpio0a1", "gpio0a2", "gpio0a3", "gpio0a4", "gpio0a5",
-	"gpio0a6", "gpio0a7", "gpio0b0", "gpio0b1", "gpio0b2", "gpio0b3",
-	"gpio1a0", "gpio1a1", "gpio1a2", "gpio1a3", "gpio1a4", "gpio1a5",
-	"gpio1a6", "gpio1a7", "gpio1b0", "gpio1b1", "gpio1b2", "gpio1b3",
-	"gpio1b4", "gpio1b5",
-	"gpio2a0", "gpio2a1", "gpio2a2", "gpio2a3", "gpio2a4", "gpio2a5",
-	"gpio2a6", "gpio2a7", "gpio2b0", "gpio2b1", "gpio2b2", "gpio2b3",
-	"gpio2b4", "gpio2b5", "gpio2b6", "gpio2b7", "gpio2c0", "gpio2c1",
-	"gpio2c3", "gpio2c4", "gpio2c5", "gpio2c6", "gpio2c7", "gpio1a0",
-	"gpio3a1", "gpio3a2", "gpio3a3", "gpio3a4", "gpio3a5", "gpio3a6",
-	"gpio3a7", "gpio3b0", "gpio3b1", "gpio3b2", "gpio3b3", "gpio3b4",
-};
-
-static struct rk628_pin_function rk628_functions[] = {
-	{
-		.name = "gpio",
-		.groups = gpio_groups,
-		.ngroups = ARRAY_SIZE(gpio_groups),
-	},
-};
-
-enum {
-	GPIO_HIGH_Z,
-	GPIO_PULL_UP,
-	GPIO_PULL_DOWN,
-};
-
-enum {
-	GPIO0_A0 = BANK_OFFSET * 0,
-	GPIO0_A1,
-	GPIO0_A2,
-	GPIO0_A3,
-	GPIO0_A4,
-	GPIO0_A5,
-	GPIO0_A6,
-	GPIO0_A7,
-	GPIO0_B0,
-	GPIO0_B1,
-	GPIO0_B2,
-	GPIO0_B3,
-	GPIO1_A0 = BANK_OFFSET * 1,
-	GPIO1_A1,
-	GPIO1_A2,
-	GPIO1_A3,
-	GPIO1_A4,
-	GPIO1_A5,
-	GPIO1_A6,
-	GPIO1_A7,
-	GPIO1_B0,
-	GPIO1_B1,
-	GPIO1_B2,
-	GPIO1_B3,
-	GPIO1_B4,
-	GPIO1_B5,
-	GPIO2_A0 = BANK_OFFSET * 2,
-	GPIO2_A1,
-	GPIO2_A2,
-	GPIO2_A3,
-	GPIO2_A4,
-	GPIO2_A5,
-	GPIO2_A6,
-	GPIO2_A7,
-	GPIO2_B0,
-	GPIO2_B1,
-	GPIO2_B2,
-	GPIO2_B3,
-	GPIO2_B4,
-	GPIO2_B5,
-	GPIO2_B6,
-	GPIO2_B7,
-	GPIO2_C0,
-	GPIO2_C1,
-	GPIO2_C2,
-	GPIO2_C3,
-	GPIO2_C4,
-	GPIO2_C5,
-	GPIO2_C6,
-	GPIO2_C7,
-	GPIO3_A0 = BANK_OFFSET * 3,
-	GPIO3_A1,
-	GPIO3_A2,
-	GPIO3_A3,
-	GPIO3_A4,
-	GPIO3_A5,
-	GPIO3_A6,
-	GPIO3_A7,
-	GPIO3_B0,
-	GPIO3_B1,
-	GPIO3_B2,
-	GPIO3_B3,
-	GPIO3_B4,
-	I2SM_SCK = BANK_OFFSET * 4 + 2,
-	I2SM_D,
-	I2SM_LR,
-	RXDDC_SCL,
-	RXDDC_SDA,
-	HDMIRX_CE,
-};
-
-static struct pinctrl_pin_desc rk628_pins_desc[] = {
-	PINCTRL_PIN(GPIO0_A0, "gpio0a0"),
-	PINCTRL_PIN(GPIO0_A1, "gpio0a1"),
-	PINCTRL_PIN(GPIO0_A2, "gpio0a2"),
-	PINCTRL_PIN(GPIO0_A3, "gpio0a3"),
-	PINCTRL_PIN(GPIO0_A4, "gpio0a4"),
-	PINCTRL_PIN(GPIO0_A5, "gpio0a5"),
-	PINCTRL_PIN(GPIO0_A6, "gpio0a6"),
-	PINCTRL_PIN(GPIO0_A7, "gpio0a7"),
-	PINCTRL_PIN(GPIO0_B0, "gpio0b0"),
-	PINCTRL_PIN(GPIO0_B1, "gpio0b1"),
-	PINCTRL_PIN(GPIO0_B2, "gpio0b2"),
-	PINCTRL_PIN(GPIO0_B3, "gpio0b3"),
-
-	PINCTRL_PIN(GPIO1_A0, "gpio1a0"),
-	PINCTRL_PIN(GPIO1_A1, "gpio1a1"),
-	PINCTRL_PIN(GPIO1_A2, "gpio1a2"),
-	PINCTRL_PIN(GPIO1_A3, "gpio1a3"),
-	PINCTRL_PIN(GPIO1_A4, "gpio1a4"),
-	PINCTRL_PIN(GPIO1_A5, "gpio1a5"),
-	PINCTRL_PIN(GPIO1_A6, "gpio1a6"),
-	PINCTRL_PIN(GPIO1_A7, "gpio1a7"),
-	PINCTRL_PIN(GPIO1_B0, "gpio1b0"),
-	PINCTRL_PIN(GPIO1_B1, "gpio1b1"),
-	PINCTRL_PIN(GPIO1_B2, "gpio1b2"),
-	PINCTRL_PIN(GPIO1_B3, "gpio1b3"),
-	PINCTRL_PIN(GPIO1_B4, "gpio1b4"),
-	PINCTRL_PIN(GPIO1_B5, "gpio1b5"),
-
-	PINCTRL_PIN(GPIO2_A0, "gpio2a0"),
-	PINCTRL_PIN(GPIO2_A1, "gpio2a1"),
-	PINCTRL_PIN(GPIO2_A2, "gpio2a2"),
-	PINCTRL_PIN(GPIO2_A3, "gpio2a3"),
-	PINCTRL_PIN(GPIO2_A4, "gpio2a4"),
-	PINCTRL_PIN(GPIO2_A5, "gpio2a5"),
-	PINCTRL_PIN(GPIO2_A6, "gpio2a6"),
-	PINCTRL_PIN(GPIO2_A7, "gpio2a7"),
-	PINCTRL_PIN(GPIO2_B0, "gpio2b0"),
-	PINCTRL_PIN(GPIO2_B1, "gpio2b1"),
-	PINCTRL_PIN(GPIO2_B2, "gpio2b2"),
-	PINCTRL_PIN(GPIO2_B3, "gpio2b3"),
-	PINCTRL_PIN(GPIO2_B4, "gpio2b4"),
-	PINCTRL_PIN(GPIO2_B5, "gpio2b5"),
-	PINCTRL_PIN(GPIO2_B6, "gpio2b6"),
-	PINCTRL_PIN(GPIO2_B7, "gpio2b7"),
-	PINCTRL_PIN(GPIO2_C0, "gpio2c0"),
-	PINCTRL_PIN(GPIO2_C1, "gpio2c1"),
-	PINCTRL_PIN(GPIO2_C2, "gpio2c2"),
-	PINCTRL_PIN(GPIO2_C3, "gpio2c3"),
-	PINCTRL_PIN(GPIO2_C4, "gpio2c4"),
-	PINCTRL_PIN(GPIO2_C5, "gpio2c5"),
-	PINCTRL_PIN(GPIO2_C6, "gpio2c6"),
-	PINCTRL_PIN(GPIO2_C7, "gpio2c7"),
-
-	PINCTRL_PIN(GPIO3_A0, "gpio3a0"),
-	PINCTRL_PIN(GPIO3_A1, "gpio3a1"),
-	PINCTRL_PIN(GPIO3_A2, "gpio3a2"),
-	PINCTRL_PIN(GPIO3_A3, "gpio3a3"),
-	PINCTRL_PIN(GPIO3_A4, "gpio3a4"),
-	PINCTRL_PIN(GPIO3_A5, "gpio3a5"),
-	PINCTRL_PIN(GPIO3_A6, "gpio3a6"),
-	PINCTRL_PIN(GPIO3_A7, "gpio3a7"),
-	PINCTRL_PIN(GPIO3_B0, "gpio3b0"),
-	PINCTRL_PIN(GPIO3_B1, "gpio3b1"),
-	PINCTRL_PIN(GPIO3_B2, "gpio3b2"),
-	PINCTRL_PIN(GPIO3_B3, "gpio3b3"),
-	PINCTRL_PIN(GPIO3_B4, "gpio3b4"),
-
-	PINCTRL_PIN(I2SM_SCK, "i2sm_sck"),
-	PINCTRL_PIN(I2SM_D, "i2sm_d"),
-	PINCTRL_PIN(I2SM_LR, "i2sm_lr"),
-	PINCTRL_PIN(RXDDC_SCL, "rxddc_scl"),
-	PINCTRL_PIN(RXDDC_SDA, "rxddc_sda"),
-	PINCTRL_PIN(HDMIRX_CE, "hdmirx_cec"),
-};
-
-static const struct rk628_pin_group rk628_pin_groups[] = {
-	PINCTRL_GROUP("gpio0a0", { GPIO0_A0 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0a1", { GPIO0_A1 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0a2", { GPIO0_A2 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0a3", { GPIO0_A3 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0a4", { GPIO0_A4 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0a5", { GPIO0_A5 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0a6", { GPIO0_A6 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0a7", { GPIO0_A7 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0b0", { GPIO0_B0 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0b1", { GPIO0_B1 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0b2", { GPIO0_B2 }, 1, GRF_GPIO0AB_SEL_CON),
-	PINCTRL_GROUP("gpio0b3", { GPIO0_B3 }, 1, GRF_GPIO0AB_SEL_CON),
-
-	PINCTRL_GROUP("gpio1a0", { GPIO1_A0 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1a1", { GPIO1_A1 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1a2", { GPIO1_A2 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1a3", { GPIO1_A3 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1a4", { GPIO1_A4 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1a5", { GPIO1_A5 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1a6", { GPIO1_A6 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1a7", { GPIO1_A7 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1b0", { GPIO1_B0 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1b1", { GPIO1_B1 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1b2", { GPIO1_B2 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1b3", { GPIO1_B3 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1b4", { GPIO1_B4 }, 1, GRF_GPIO1AB_SEL_CON),
-	PINCTRL_GROUP("gpio1b5", { GPIO1_B5 }, 1, GRF_GPIO1AB_SEL_CON),
-
-	PINCTRL_GROUP("gpio2a0", { GPIO2_A0 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2a1", { GPIO2_A1 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2a2", { GPIO2_A2 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2a3", { GPIO2_A3 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2a4", { GPIO2_A4 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2a5", { GPIO2_A5 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2a6", { GPIO2_A6 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2a7", { GPIO2_A7 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2b0", { GPIO2_B0 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2b1", { GPIO2_B1 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2b2", { GPIO2_B2 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2b3", { GPIO2_B3 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2b4", { GPIO2_B4 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2b5", { GPIO2_B5 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2b6", { GPIO2_B6 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2b7", { GPIO2_B7 }, 1, GRF_GPIO2AB_SEL_CON),
-	PINCTRL_GROUP("gpio2c0", { GPIO2_C0 }, 1, GRF_GPIO2C_SEL_CON),
-	PINCTRL_GROUP("gpio2c1", { GPIO2_C1 }, 1, GRF_GPIO2C_SEL_CON),
-	PINCTRL_GROUP("gpio2c2", { GPIO2_C2 }, 1, GRF_GPIO2C_SEL_CON),
-	PINCTRL_GROUP("gpio2c3", { GPIO2_C3 }, 1, GRF_GPIO2C_SEL_CON),
-	PINCTRL_GROUP("gpio2c4", { GPIO2_C4 }, 1, GRF_GPIO2C_SEL_CON),
-	PINCTRL_GROUP("gpio2c5", { GPIO2_C5 }, 1, GRF_GPIO2C_SEL_CON),
-	PINCTRL_GROUP("gpio2c6", { GPIO2_C6 }, 1, GRF_GPIO2C_SEL_CON),
-	PINCTRL_GROUP("gpio2c7", { GPIO2_C7 }, 1, GRF_GPIO2C_SEL_CON),
-
-	PINCTRL_GROUP("gpio3a0", { GPIO3_A0 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3a1", { GPIO3_A1 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3a2", { GPIO3_A2 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3a3", { GPIO3_A3 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3a4", { GPIO3_A4 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3a5", { GPIO3_A5 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3a6", { GPIO3_A6 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3a7", { GPIO3_A7 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3b0", { GPIO3_B0 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3b1", { GPIO3_B1 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3b2", { GPIO3_B2 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3b3", { GPIO3_B3 }, 1, GRF_GPIO3AB_SEL_CON),
-	PINCTRL_GROUP("gpio3b4", { GPIO3_B4 }, 1, GRF_GPIO3AB_SEL_CON),
-
-	PINCTRL_GROUP("i2sm_sck", { I2SM_SCK }, 1, GRF_SYSTEM_CON3),
-	PINCTRL_GROUP("i2sm_d", { I2SM_D }, 1, GRF_SYSTEM_CON3),
-	PINCTRL_GROUP("i2sm_lr", { I2SM_LR }, 1, GRF_SYSTEM_CON3),
-	PINCTRL_GROUP("rxddc_scl", { RXDDC_SCL }, 1, GRF_SYSTEM_CON3),
-	PINCTRL_GROUP("rxddc_sda", { RXDDC_SDA }, 1, GRF_SYSTEM_CON3),
-	PINCTRL_GROUP("hdmirx_cec", { HDMIRX_CE }, 1, GRF_SYSTEM_CON3),
-};
-
-static struct rk628_pin_bank rk628_pin_banks[] = {
-	PINCTRL_BANK("rk628-gpio0", GPIO0_BASE, 12),
-	PINCTRL_BANK("rk628-gpio1", GPIO1_BASE, 14),
-	PINCTRL_BANK("rk628-gpio2", GPIO2_BASE, 24),
-	PINCTRL_BANK("rk628-gpio3", GPIO3_BASE, 13),
-};
-
-/* generic gpio chip */
-static int rk628_gpio_get(struct gpio_chip *chip, unsigned int offset)
-{
-	struct rk628_pin_bank *bank = gpiochip_get_data(chip);
-	struct rk628_pctrl_info *pci = bank->pci;
-	int data_reg, val, ret;
-
-	data_reg = bank->reg_base + GPIO_EXT_PORT;
-
-	clk_enable(bank->clk);
-	ret = regmap_read(pci->regmap, data_reg, &val);
-	if (ret)
-		dev_err(pci->dev, "%s: regmap read failed!\n", __func__);
-	clk_disable(bank->clk);
-
-	val >>= offset;
-	val &= 1;
-	dev_dbg(pci->dev, "%s bank->name=%s dir_reg=0x%x offset=%x value=%x\n",
-		__func__, bank->name, data_reg, offset, val);
-
-	return val;
-}
-
-static void rk628_gpio_set(struct gpio_chip *chip,
-			   unsigned int offset,
-			   int value)
-{
-	struct rk628_pin_bank *bank = gpiochip_get_data(chip);
-	struct rk628_pctrl_info *pci = bank->pci;
-	int data_reg, val, ret;
-
-	if (offset / 16) {
-		data_reg = bank->reg_base + GPIO_SWPORT_DR_H;
-		offset -= 16;
-	} else {
-		data_reg = bank->reg_base + GPIO_SWPORT_DR_L;
-	}
-	if (value)
-		val = BIT(offset + 16) | BIT(offset);
-	else
-		val = BIT(offset + 16) | (0xffff & ~BIT(offset));
-
-	clk_enable(bank->clk);
-	ret = regmap_write(pci->regmap, data_reg, val);
-	if (ret)
-		pr_err("%s: regmap write failed! bank->name=%s data_reg=0x%x offset=%d\n",
-		       __func__, bank->name, data_reg, offset);
-	clk_disable(bank->clk);
-}
-
-static int rk628_gpio_direction_input(struct gpio_chip *chip,
-				      unsigned int offset)
-{
-	return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
-static int rk628_gpio_direction_output(struct gpio_chip *chip,
-				       unsigned int offset,
-				       int value)
-{
-	rk628_gpio_set(chip, offset, value);
-	return pinctrl_gpio_direction_output(chip->base + offset);
-}
-
-static int rk628_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
-{
-	struct rk628_pin_bank *bank = gpiochip_get_data(chip);
-	struct rk628_pctrl_info *pci = bank->pci;
-	int dir_reg, val, ret;
-
-	if (offset / 16) {
-		dir_reg = bank->reg_base + GPIO_SWPORT_DDR_H;
-		offset -= 16;
-	} else {
-		dir_reg = bank->reg_base + GPIO_SWPORT_DDR_L;
-	}
-
-	clk_enable(bank->clk);
-	ret = regmap_read(pci->regmap, dir_reg, &val);
-	if (ret)
-		dev_err(pci->dev, "%s: regmap read failed!\n", __func__);
-	clk_disable(bank->clk);
-
-	val = BIT(offset) & val;
-
-	return !val;
-}
-
-static int rk628_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
-{
-	struct rk628_pin_bank *bank = gpiochip_get_data(gc);
-	int virq;
-
-	if (!bank->domain)
-		return -ENXIO;
-
-	virq = irq_create_mapping(bank->domain, offset);
-	if (!virq)
-		pr_err("map interruptr fail, bank->irq=%d\n", bank->irq);
-
-	return (virq) ? : -ENXIO;
-}
-
-static struct gpio_chip rk628_gpiolib_chip = {
-	.label			= "rk628-gpio",
-	.request		= gpiochip_generic_request,
-	.free			= gpiochip_generic_free,
-	.get_direction		= rk628_gpio_get_direction,
-	.get			= rk628_gpio_get,
-	.set			= rk628_gpio_set,
-	.direction_input	= rk628_gpio_direction_input,
-	.direction_output	= rk628_gpio_direction_output,
-	.to_irq			= rk628_gpio_to_irq,
-	.can_sleep              = true,
-	.base			= -1,
-	.owner			= THIS_MODULE,
-};
-
-/* generic pinctrl */
-static int rk628_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-
-	return pci->num_groups;
-}
-
-static const char *rk628_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
-						unsigned int group)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-
-	return pci->groups[group].name;
-}
-
-static int rk628_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
-					unsigned int group,
-					const unsigned int **pins,
-					unsigned int *num_pins)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-
-	*pins = pci->groups[group].pins;
-	*num_pins = pci->groups[group].npins;
-
-	return 0;
-}
-
-static const struct pinctrl_ops rk628_pinctrl_ops = {
-	.get_groups_count = rk628_pinctrl_get_groups_count,
-	.get_group_name = rk628_pinctrl_get_group_name,
-	.get_group_pins = rk628_pinctrl_get_group_pins,
-	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
-	.dt_free_map = pinctrl_utils_free_map,
-};
-
-static int rk628_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-
-	return pci->num_functions;
-}
-
-static const char *rk628_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
-					       unsigned int function)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-
-	return pci->functions[function].name;
-}
-
-static int rk628_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
-					 unsigned int function,
-					 const char *const **groups,
-					 unsigned int *const num_groups)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-
-	*groups = pci->functions[function].groups;
-	*num_groups = pci->functions[function].ngroups;
-
-	return 0;
-}
-
-static int rk628_calc_mux_offset(struct rk628_pctrl_info *pci, int mux, int reg, int offset)
-{
-	int val = 0, orig;
-
-	switch (reg) {
-	case GRF_SYSTEM_CON3:
-		regmap_read(pci->grf_regmap, reg, &orig);
-		if (mux)
-			val = BIT(offset) | orig;
-		else
-			val = ~BIT(offset) & orig;
-		break;
-	case GRF_GPIO0AB_SEL_CON:
-		if (offset >= 4 && offset < 8) {
-			offset += offset - 4;
-			val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
-		} else if (offset > 7) {
-			offset += 4;
-			val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
-		} else {
-			val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
-		}
-		break;
-	case GRF_GPIO1AB_SEL_CON:
-		if (offset == 13)
-			offset++;
-		if (offset > 11)
-			val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
-		else
-			val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
-		break;
-	case GRF_GPIO2AB_SEL_CON:
-		val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
-		break;
-	case GRF_GPIO2C_SEL_CON:
-		offset -= 16;
-		val = 0x3 << ((offset*2) + 16) | (mux ? BIT(offset*2) : 0);
-		break;
-	case GRF_GPIO3AB_SEL_CON:
-		if (offset > 11)
-			val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0);
-		else
-			val = BIT(offset + 16) | (mux ? BIT(offset) : 0);
-		break;
-	default:
-		break;
-	}
-
-	return val;
-}
-
-static int rk628_pinctrl_set_mux(struct pinctrl_dev *pctldev,
-				 unsigned int func_selector,
-				 unsigned int group_selector)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-	int ret, val;
-	int mux = pci->functions[func_selector].mux_option;
-	int offset = pci->groups[group_selector].pins[0] % BANK_OFFSET;
-	int reg = pci->groups[group_selector].iomux_base;
-
-	dev_dbg(pci->dev, "functions[%d]:%s mux=%s\n",
-		func_selector, pci->functions[func_selector].name,
-		mux ? "func" : "gpio");
-
-	val = rk628_calc_mux_offset(pci, mux, reg, offset);
-
-	dev_dbg(pci->dev, "groups[%d]:%s pin-number=%d reg=0x%x write-val=0x%8x\n",
-		group_selector,
-		pci->groups[group_selector].name,
-		pci->groups[group_selector].pins[0],
-		reg, val);
-
-	ret = regmap_write(pci->grf_regmap, reg, val);
-	if (ret)
-		dev_err(pci->dev, "%s regmap write failed!\n", __func__);
-
-	return ret;
-}
-
-static int rk628_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
-					struct pinctrl_gpio_range *range,
-					unsigned int offset, bool input)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-	struct gpio_chip *chip;
-	struct rk628_pin_bank *bank;
-	int pin_offset, dir_reg, val, ret;
-
-	chip = range->gc;
-	bank = gpiochip_get_data(chip);
-	pin_offset = offset - range->pin_base;
-
-	if (pin_offset / 16) {
-		dir_reg = bank->reg_base + GPIO_SWPORT_DDR_H;
-		pin_offset -= 16;
-	} else {
-		dir_reg = bank->reg_base + GPIO_SWPORT_DDR_L;
-	}
-	if (input)
-		val = BIT(pin_offset + 16) | (0xffff & ~BIT(pin_offset));
-	else
-		val = BIT(pin_offset + 16) | BIT(pin_offset);
-
-	clk_enable(bank->clk);
-	ret = regmap_write(pci->regmap, dir_reg, val);
-	if (ret)
-		dev_err(pci->dev, "regmap update failed!\n");
-	clk_disable(bank->clk);
-
-	return 0;
-}
-
-static const struct pinmux_ops rk628_pinmux_ops = {
-	.get_functions_count	= rk628_pinctrl_get_funcs_count,
-	.get_function_name	= rk628_pinctrl_get_func_name,
-	.get_function_groups	= rk628_pinctrl_get_func_groups,
-	.set_mux		= rk628_pinctrl_set_mux,
-	.gpio_set_direction	= rk628_pmx_gpio_set_direction,
-};
-
-static int rk628_pinconf_get(struct pinctrl_dev *pctldev,
-			     unsigned int pin, unsigned long *config)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-	enum pin_config_param param = pinconf_to_config_param(*config);
-	u32 arg = 0;
-
-	pr_err("no support %s\n", __func__);
-
-	switch (param) {
-	case PIN_CONFIG_OUTPUT:
-		break;
-	default:
-		dev_err(pci->dev, "Properties not supported\n");
-		return -ENOTSUPP;
-	}
-
-	*config = pinconf_to_config_packed(param, (u16)arg);
-
-	return 0;
-}
-
-static int rk628_set_slew_rate(struct rk628_pctrl_info *pci, int pin, int speed)
-{
-	int gpio = pin;
-
-	/* gpio0b_sl(0-3) gpio1b_sl(0-3 -5) gpio3a_sl(4-7)*/
-	char valid_gpio[] = {
-		8,
-		9,
-		10,
-		11,
-		32 + 8,
-		32 + 9,
-		32 + 10,
-		32 + 11,
-		32 + 12,
-		32 + 13,
-		-1, -1,
-		96 + 4,
-		96 + 5,
-		96 + 6,
-		96 + 7
-	};
-
-
-	int val, ret, offset = 0xff;
-	u32 i;
-
-	for (i = 0; i < sizeof(valid_gpio); i++) {
-		if (gpio == valid_gpio[i]) {
-			offset = i;
-			break;
-		}
-	}
-
-	if (offset == 0xff) {
-		dev_err(pci->dev, "pin%u don't support set slew rate\n", pin);
-		return -EINVAL;
-	}
-
-	if (speed)
-		val = BIT(offset + 16) | BIT(offset);
-	else
-		val = BIT(offset + 16);
-
-	dev_dbg(pci->dev, " offset=%d 0x%x\n", offset, val);
-
-	ret = regmap_write(pci->grf_regmap, GRF_GPIO_SR_CON, val);
-	if (ret)
-		dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
-			__func__, pin);
-
-	return ret;
-}
-
-static int rk628_calc_pull_reg_and_value(struct rk628_pctrl_info *pci,
-					 int pin,
-					 int pull,
-					 int *reg,
-					 int *val)
-{
-	struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
-	int gpio2_regs[] = { GRF_GPIO2A_P_CON, GRF_GPIO2B_P_CON, GRF_GPIO2C_P_CON };
-	int gpio3_regs[] = { GRF_GPIO3A_P_CON, GRF_GPIO3B_P_CON };
-	int valid_pinnum[] = { 8, 8, 24, 13 };
-	int offset = pin - range->pin_base;
-
-	switch (range->id) {
-	case 0:
-		if (pull == GPIO_PULL_UP) {
-			dev_err(pci->dev, "pin%u don't support pull up!\n",
-				pin);
-			return -EINVAL;
-		}
-
-		if (offset == 2) {
-			dev_err(pci->dev, "pin%u don't support pull!\n",
-				pin);
-			return -EINVAL;
-		}
-
-		if (offset < valid_pinnum[range->id]) {
-			*val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
-			*reg = GRF_GPIO0A_P_CON;
-			dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
-				pin, *reg, *val);
-			return 0;
-		}
-		break;
-	case 1:
-		if (pull == GPIO_PULL_UP) {
-			dev_err(pci->dev, "pin%u don't support pull up!\n",
-				pin);
-			return -EINVAL;
-		}
-
-		if (offset == 2) {
-			dev_err(pci->dev, "pin%u don't support pull!\n",
-				pin);
-			return -EINVAL;
-		}
-
-		if (offset < valid_pinnum[range->id]) {
-			*val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
-			*reg = GRF_GPIO1A_P_CON;
-			dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
-				pin, *reg, *val);
-			return 0;
-		}
-		break;
-	case 2:
-		if (pull == GPIO_PULL_UP)
-			pull = GPIO_PULL_DOWN;
-		else if (pull == GPIO_PULL_DOWN)
-			pull = GPIO_PULL_UP;
-
-		if (offset < valid_pinnum[range->id]) {
-			*reg = gpio2_regs[offset / 8];
-			offset = offset % 8;
-			*val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
-			dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
-				pin, *reg, *val);
-			return 0;
-		}
-		break;
-	case 3:
-		if (pull == GPIO_PULL_UP && (offset == 2 || offset == 11 || offset == 12)) {
-			dev_err(pci->dev, "pin%u don't support pull up!\n",
-				pin);
-			return -EINVAL;
-		} else if (pull == GPIO_PULL_DOWN && (offset == 9 || offset == 10)) {
-			dev_err(pci->dev, "pin%u don't support pull down!\n",
-				pin);
-			return -EINVAL;
-		}
-
-		if (offset == 0 || offset == 1 || offset == 3 || offset == 8) {
-			if (pull == GPIO_PULL_UP)
-				pull = GPIO_PULL_DOWN;
-			else if (pull == GPIO_PULL_DOWN)
-				pull = GPIO_PULL_UP;
-		}
-
-		if ((offset > 7 && offset < valid_pinnum[range->id]) || offset < 4) {
-			*reg = gpio3_regs[offset / 8];
-			offset = offset % 8;
-			*val = 0x3 << (2 * offset + 16) | pull << (2 * offset);
-			dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
-				pin, *reg, *val);
-			return 0;
-		}
-		break;
-	default:
-		break;
-	}
-
-	return -EINVAL;
-}
-
-static int rk628_calc_strength_reg_and_value(struct rk628_pctrl_info *pci,
-					 int pin,
-					 int strength,
-					 int *reg,
-					 int *val)
-{
-	struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
-	int valid_pinnum[] = { 8, 8, 24, 9 };
-	int gpio_regs[][6] = {
-		{	GRF_GPIO0B_D_CON
-		},
-		{	GRF_GPIO1B_D_CON
-		},
-		{
-			GRF_GPIO2A_D0_CON, GRF_GPIO2A_D1_CON,
-			GRF_GPIO2B_D0_CON, GRF_GPIO2B_D1_CON,
-			GRF_GPIO2C_D0_CON, GRF_GPIO2C_D1_CON
-		},
-		{
-			GRF_GPIO3A_D0_CON, GRF_GPIO3A_D1_CON,
-			GRF_GPIO3B_D_CON
-		}
-	};
-	int offset = pin - range->pin_base;
-
-	switch (range->id) {
-	case 0:
-	case 1:
-		if (offset < valid_pinnum[range->id]) {
-			dev_err(pci->dev, "pin%u don't support driver strength settings!\n",
-				pin);
-			return -EINVAL;
-		}
-
-		offset -= valid_pinnum[range->id];
-
-		*val = 0x3 << (2 * offset + 16) | strength << (2 * offset);
-		*reg = gpio_regs[range->id][0];
-		dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
-				pin, *reg, *val);
-		return 0;
-	case 2:
-	case 3:
-		if (offset < valid_pinnum[range->id]) {
-			*reg = gpio_regs[range->id][offset / 4];
-			offset = offset % 4;
-			*val = 0x7 << (4 * offset + 16) | strength << (4 * offset);
-			dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
-				pin, *reg, *val);
-			return 0;
-		}
-		break;
-	default:
-		break;
-	}
-
-	return -EINVAL;
-}
-
-static int rk628_calc_schmitt_reg_and_value(struct rk628_pctrl_info *pci,
-					 int pin,
-					 int enable,
-					 int *reg,
-					 int *val)
-{
-	struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
-	int gpio2_regs[] = {GRF_GPIO2A_SMT, GRF_GPIO2B_SMT, GRF_GPIO2C_SMT};
-	int gpio3_reg = GRF_GPIO3AB_SMT;
-	int valid_pinnum[] = { 0, 0, 24, 9 };
-	int offset = pin - range->pin_base;
-
-	switch (range->id) {
-	case 0:
-	case 1:
-		break;
-	case 2:
-		if (offset < valid_pinnum[range->id]) {
-			*reg = gpio2_regs[offset / 8];
-			offset = offset % 8;
-			*val = BIT(offset + 16) | enable << (offset);
-			dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
-				pin, *reg, *val);
-			return 0;
-		}
-		break;
-	case 3:
-		if (offset == 0 || offset == 1 || offset == 3 || offset == 8) {
-			*reg = gpio3_reg;
-			*val = BIT(offset + 16) | enable << (offset);
-			dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n",
-				pin, *reg, *val);
-			return 0;
-		}
-		break;
-	default:
-		break;
-	}
-
-	dev_err(pci->dev, "pin%u don't support schmitt settings!\n",
-			pin);
-
-	return -ENOTSUPP;
-}
-
-static int rk628_set_pull(struct rk628_pctrl_info *pci, int pin, int pull)
-{
-	int ret, reg, val;
-
-	ret = rk628_calc_pull_reg_and_value(pci, pin, pull, &reg, &val);
-	if (ret) {
-		dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
-		return ret;
-	}
-
-	ret = regmap_write(pci->grf_regmap, reg, val);
-
-	if (ret)
-		dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
-			__func__, pin);
-
-	return ret;
-}
-
-static int rk628_set_drive_perpin(struct rk628_pctrl_info *pci, int pin, int strength)
-{
-	int ret, reg, val;
-
-	ret = rk628_calc_strength_reg_and_value(pci, pin, strength, &reg, &val);
-	if (ret) {
-		dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
-		return ret;
-	}
-
-	ret = regmap_write(pci->grf_regmap, reg, val);
-
-	if (ret)
-		dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
-			__func__, pin);
-
-	return ret;
-}
-
-static int rk628_set_schmitt(struct rk628_pctrl_info *pci, int pin, int enable)
-{
-	int ret, reg, val;
-
-	ret = rk628_calc_schmitt_reg_and_value(pci, pin, enable, &reg, &val);
-	if (ret) {
-		dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin);
-		return ret;
-	}
-
-	ret = regmap_write(pci->grf_regmap, reg, val);
-
-	if (ret)
-		dev_err(pci->dev, "%s:regmap write failed! pin%u\n",
-			__func__, pin);
-
-	return ret;
-}
-
-static int rk628_pinconf_set(struct pinctrl_dev *pctldev,
-			     unsigned int pin, unsigned long *configs,
-			     unsigned int num_configs)
-{
-	struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
-	enum pin_config_param param;
-	u32 i, arg = 0;
-
-	for (i = 0; i < num_configs; i++) {
-		param = pinconf_to_config_param(configs[i]);
-		arg = pinconf_to_config_argument(configs[i]);
-
-		switch (param) {
-		case PIN_CONFIG_DRIVE_STRENGTH:
-			rk628_set_drive_perpin(pci, pin, arg);
-			break;
-		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-			rk628_set_pull(pci, pin, GPIO_HIGH_Z);
-			break;
-		case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
-			dev_err(pci->dev,
-				"PIN_CONFIG_BIAS_PULL_PIN_DEFAULT not supported\n");
-			break;
-		case PIN_CONFIG_BIAS_PULL_UP:
-			rk628_set_pull(pci, pin, GPIO_PULL_UP);
-			break;
-		case PIN_CONFIG_BIAS_PULL_DOWN:
-			rk628_set_pull(pci, pin, GPIO_PULL_DOWN);
-			break;
-		case PIN_CONFIG_SLEW_RATE:
-			rk628_set_slew_rate(pci, pin, arg);
-			break;
-		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
-			rk628_set_schmitt(pci, pin, arg);
-			break;
-		case PIN_CONFIG_OUTPUT:
-		{
-			struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin);
-
-			rk628_gpio_direction_output(range->gc, pin - range->pin_base, arg);
-			break;
-		}
-		default:
-			dev_err(pci->dev, "Properties not supported param=%d\n", param);
-			break;
-		}
-	}
-
-	return 0;
-}
-
-static const struct pinconf_ops rk628_pinconf_ops = {
-	.pin_config_get = rk628_pinconf_get,
-	.pin_config_set = rk628_pinconf_set,
-};
-
-static struct pinctrl_desc rk628_pinctrl_desc = {
-	.name = "rk628-pinctrl",
-	.pctlops = &rk628_pinctrl_ops,
-	.pmxops = &rk628_pinmux_ops,
-	.confops = &rk628_pinconf_ops,
-	.owner = THIS_MODULE,
-};
-
-static int rk628_pinctrl_create_function(struct device *dev,
-					 struct rk628_pctrl_info *pci,
-					 struct device_node *func_np,
-					 struct rk628_pin_function *func)
-{
-	int npins;
-	int ret;
-	int i;
-	char *func_sel[6] = {
-		"vop_dclk0", "i2sm0_input", "rxdcc_input0", "hdmirx_cec0",
-		"force_jtag_dis", "uart_iomux_dis",
-	};
-
-	if (of_property_read_string(func_np, "function", &func->name))
-		return -1;
-
-	func->mux_option = PINMUX_FUNC1;
-	/* for signals input select */
-	for (i = 0; i < 6; i++) {
-		if (!strcmp(func_sel[i], func->name))
-			func->mux_option = PINMUX_FUNC0;
-	}
-
-	dev_dbg(dev, "%s func->name=%s\n", __func__, func->name);
-	npins = of_property_count_strings(func_np, "pins");
-	if (npins < 1) {
-		dev_err(dev, "invalid pin list in %s node", func_np->name);
-		return -EINVAL;
-	}
-
-	func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL);
-	if (!func->groups)
-		return -ENOMEM;
-
-	for (i = 0; i < npins; ++i) {
-		const char *gname;
-
-		ret = of_property_read_string_index(func_np,
-						    "pins", i, &gname);
-		if (ret) {
-			dev_err(dev,
-				"failed to read pin name %d from %s node\n",
-				i, func_np->name);
-			return ret;
-		}
-		dev_dbg(dev, "%s func->groups[%d]=%s\n", __func__, i, gname);
-
-		func->groups[i] = gname;
-	}
-
-	func->ngroups = npins;
-	return 0;
-}
-
-static int rk628_pinctrl_parse_gpiobank(struct device *dev,
-					struct rk628_pctrl_info *pci)
-{
-	struct device_node *dev_np = dev->of_node;
-	struct device_node *cfg_np;
-	struct rk628_pin_bank *bank;
-	u32 i, count = 0;
-
-	for_each_child_of_node(dev_np, cfg_np) {
-		if (of_get_child_count(cfg_np))
-			continue;
-		if (!of_find_property(cfg_np, "gpio-controller", NULL))
-			continue;
-		bank = pci->pin_banks;
-		for (i = 0; i < pci->nr_banks; ++i, ++bank) {
-			if (strcmp(bank->name, cfg_np->name))
-				continue;
-			bank->of_node = cfg_np;
-			count++;
-			bank->clk = devm_get_clk_from_child(dev,
-							    bank->of_node,
-							    "pclk");
-			if (IS_ERR(bank->clk))
-				return PTR_ERR(bank->clk);
-			clk_prepare(bank->clk);
-			break;
-		}
-		if (count == pci->nr_banks)
-			break;
-	}
-
-	return 0;
-}
-
-static struct rk628_pin_function *
-rk628_pinctrl_create_functions(struct device *dev,
-			       struct rk628_pctrl_info *pci,
-			       unsigned int *cnt)
-{
-	struct rk628_pin_function *functions, *func;
-	struct device_node *dev_np = dev->of_node;
-	struct device_node *cfg_np;
-	unsigned int func_cnt = 0;
-	const char *func_name;
-	int ret;
-
-	/*
-	 * Iterate over all the child nodes of the pin controller node
-	 * and create pin groups and pin function lists.
-	 */
-	for_each_child_of_node(dev_np, cfg_np) {
-		if (!of_get_child_count(cfg_np)) {
-			if (!of_find_property(cfg_np, "function", NULL))
-				continue;
-			if (!of_property_read_string(cfg_np,
-						     "function", &func_name)) {
-				if (!strncmp("gpio", func_name, 4))
-					continue;
-			}
-			dev_dbg(dev, "%s: count=%d %s\n",
-				__func__, func_cnt, func_name);
-			++func_cnt;
-			continue;
-		}
-	}
-
-	++func_cnt;
-	dev_dbg(dev, "total_count=%d, count %d for gpio function.\n",
-		func_cnt, func_cnt - 1);
-	functions = devm_kzalloc(dev, func_cnt * sizeof(*functions),
-				 GFP_KERNEL);
-	if (!functions)
-		return ERR_PTR(-ENOMEM);
-
-	func = functions;
-
-	/*
-	 * Iterate over all the child nodes of the pin controller node
-	 * and create pin groups and pin function lists.
-	 */
-	func_cnt = 0;
-	for_each_child_of_node(dev_np, cfg_np) {
-		if (!of_get_child_count(cfg_np)) {
-			if (!of_property_read_string(cfg_np,
-						     "function", &func_name)) {
-				if (!strncmp("gpio", func_name, 4))
-					continue;
-			}
-			ret = rk628_pinctrl_create_function(dev, pci,
-							    cfg_np, func);
-			if (!ret) {
-				++func;
-				++func_cnt;
-			}
-			continue;
-		}
-	}
-
-	/* init gpio func */
-	*(func) = rk628_functions[MUX_GPIO];
-	func->mux_option = PINMUX_FUNC0;
-
-	dev_dbg(dev, "count %d is for %s function\n", func_cnt, func->name);
-	++func;
-	++func_cnt;
-	*cnt = func_cnt;
-	return functions;
-}
-
-static int rk628_pinctrl_parse_dt(struct platform_device *pdev,
-				  struct rk628_pctrl_info *pci)
-{
-	struct device *dev = &pdev->dev;
-	struct rk628_pin_function *functions;
-	unsigned int func_cnt = 0;
-	int ret;
-
-	ret = rk628_pinctrl_parse_gpiobank(dev, pci);
-	if (ret)
-		return ret;
-
-	functions = rk628_pinctrl_create_functions(dev, pci, &func_cnt);
-	if (IS_ERR(functions)) {
-		dev_err(dev, "failed to parse pin functions\n");
-		return PTR_ERR(functions);
-	}
-
-	pci->functions = functions;
-	pci->num_functions = func_cnt;
-	return 0;
-}
-
-static const struct regmap_range rk628_pinctrl_readable_ranges[] = {
-	regmap_reg_range(GPIO0_BASE, GPIO0_BASE + GPIO_VER_ID),
-	regmap_reg_range(GPIO1_BASE, GPIO1_BASE + GPIO_VER_ID),
-	regmap_reg_range(GPIO2_BASE, GPIO2_BASE + GPIO_VER_ID),
-	regmap_reg_range(GPIO3_BASE, GPIO3_BASE + GPIO_VER_ID),
-};
-
-static const struct regmap_access_table rk628_pinctrl_readable_table = {
-	.yes_ranges     = rk628_pinctrl_readable_ranges,
-	.n_yes_ranges   = ARRAY_SIZE(rk628_pinctrl_readable_ranges),
-};
-
-static const struct regmap_config rk628_pinctrl_regmap_config = {
-	.name = "pinctrl",
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = 4,
-	.max_register = GPIO_MAX_REGISTER,
-	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
-	.val_format_endian = REGMAP_ENDIAN_LITTLE,
-	.rd_table = &rk628_pinctrl_readable_table,
-};
-
-static void rk628_irq_enable(struct irq_data *d)
-{
-	struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned long hwirq = d->hwirq;
-	u32 offset;
-
-	if (hwirq / 16) {
-		hwirq = hwirq - 16;
-		offset = GPIO_REG_HIGH;
-	} else {
-		offset = GPIO_REG_LOW;
-	}
-
-	bank->mask_regs[offset] |= BIT(hwirq);
-}
-
-static void rk628_irq_disable(struct irq_data *d)
-{
-	struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned long hwirq = d->hwirq;
-	u32 offset;
-
-	if (hwirq / 16) {
-		hwirq = hwirq - 16;
-		offset = GPIO_REG_HIGH;
-	} else {
-		offset = GPIO_REG_LOW;
-	}
-
-	bank->mask_regs[offset] &= ~BIT(hwirq);
-}
-
-static int rk628_irq_set_type(struct irq_data *d, unsigned int type)
-{
-	struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
-	struct rk628_pctrl_info *pci = bank->pci;
-	unsigned long hwirq = d->hwirq;
-	u32 offset;
-
-	if (hwirq / 16) {
-		hwirq = hwirq - 16;
-		offset = GPIO_REG_HIGH;
-	} else {
-		offset = GPIO_REG_LOW;
-	}
-
-	switch (type) {
-	case IRQ_TYPE_EDGE_BOTH:
-		bank->bothedge_regs[offset] |= BIT(hwirq);
-		break;
-	case IRQ_TYPE_EDGE_RISING:
-		bank->bothedge_regs[offset] &= ~BIT(hwirq);
-		bank->level_regs[offset] |= BIT(hwirq);
-		bank->polarity_regs[offset] |= BIT(hwirq);
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		bank->bothedge_regs[offset] &= ~BIT(hwirq);
-		bank->level_regs[offset] |= BIT(hwirq);
-		bank->polarity_regs[offset] &= ~BIT(hwirq);
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		bank->bothedge_regs[offset] &= ~BIT(hwirq);
-		bank->level_regs[offset] &= ~BIT(hwirq);
-		bank->polarity_regs[offset] |= BIT(hwirq);
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		bank->bothedge_regs[offset] &= ~BIT(hwirq);
-		bank->level_regs[offset] &= ~BIT(hwirq);
-		bank->polarity_regs[offset] &= ~BIT(hwirq);
-		break;
-	default:
-		dev_err(pci->dev, "irq type invalid!\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static void rk628_irq_lock(struct irq_data *d)
-{
-	struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
-
-	mutex_lock(&bank->lock);
-	clk_enable(bank->clk);
-}
-
-static void rk628_irq_sync_unlock(struct irq_data *d)
-{
-	struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d);
-	struct rk628_pctrl_info *pci = bank->pci;
-	int ret;
-	unsigned long hwirq = d->hwirq;
-	u32 offset, inten, level, polarity, bothedge;
-
-	if (hwirq / 16) {
-		hwirq = hwirq - 16;
-		offset = GPIO_REG_HIGH;
-	} else {
-		offset = GPIO_REG_LOW;
-	}
-
-	inten = (bank->reg_base + GPIO_INTEN_L + ((offset) * 4));
-	level = (bank->reg_base + GPIO_INTTYPE_L + ((offset) * 4));
-	polarity = (bank->reg_base + GPIO_INT_POLARITY_L + ((offset) * 4));
-	bothedge = (bank->reg_base + GPIO_INT_BOTHEDGE_L + ((offset) * 4));
-
-	ret = regmap_write(pci->regmap, level,
-			   bank->level_regs[offset] | BIT(hwirq + 16));
-	if (ret)
-		dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
-			level, d->irq);
-
-	ret = regmap_write(pci->regmap, polarity,
-			   bank->polarity_regs[offset] | BIT(hwirq + 16));
-	if (ret)
-		dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
-			polarity, d->irq);
-
-	ret = regmap_write(pci->regmap, bothedge,
-			   bank->bothedge_regs[offset] | BIT(hwirq + 16));
-	if (ret)
-		dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
-			bothedge, d->irq);
-
-	ret = regmap_write(pci->regmap, inten,
-			   bank->mask_regs[offset] | BIT(hwirq + 16));
-	if (ret)
-		dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n",
-			inten, d->irq);
-
-	clk_disable(bank->clk);
-	mutex_unlock(&bank->lock);
-}
-
-enum rk628_irqchip {
-	IRQCHIP_gpio0,
-	IRQCHIP_gpio1,
-	IRQCHIP_gpio2,
-	IRQCHIP_gpio3,
-};
-
-static const struct irq_chip rk628_irq_chip[] = {
-	IRQ_CHIP(gpio0),
-	IRQ_CHIP(gpio1),
-	IRQ_CHIP(gpio2),
-	IRQ_CHIP(gpio3),
-};
-
-static int rk628_irq_map(struct irq_domain *h, unsigned int virq,
-			 irq_hw_number_t hw)
-{
-	struct rk628_pin_bank *bank = h->host_data;
-
-	irq_set_chip_data(virq, bank);
-	irq_set_chip(virq, &bank->irq_chip);
-	irq_set_nested_thread(virq, 1);
-	irq_set_noprobe(virq);
-
-	return 0;
-}
-
-static const struct irq_domain_ops rk628_domain_ops = {
-	.map	= rk628_irq_map,
-	.xlate	= irq_domain_xlate_twocell,
-};
-
-static irqreturn_t rk628_irq_demux_thread(int irq, void *d)
-{
-	struct rk628_pin_bank *bank = d;
-	struct rk628_pctrl_info *pci = bank->pci;
-	int ret;
-	u32 pend, low_bit, high_bit;
-
-	clk_enable(bank->clk);
-
-	ret = regmap_read(pci->regmap, bank->reg_base + GPIO_INT_STATUS, &pend);
-	if (ret)
-		dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
-
-	low_bit = pend & 0x0000ffff;
-	high_bit = (pend >> 16);
-	ret = regmap_write(pci->regmap, bank->reg_base + GPIO_PORTS_EOI_L,
-			   (low_bit << 16) | low_bit);
-	if (ret)
-		dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
-
-	ret = regmap_write(pci->regmap, bank->reg_base + GPIO_PORTS_EOI_H,
-			   (high_bit << 16) | high_bit);
-	if (ret)
-		dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__);
-
-	while (pend) {
-		unsigned int irq, virq;
-
-		irq = __ffs(pend);
-		pend &= ~BIT(irq);
-		virq = irq_linear_revmap(bank->domain, irq);
-
-		if (!virq) {
-			dev_err(pci->dev, "unmapped irq %d\n", irq);
-			continue;
-		}
-
-		handle_nested_irq(virq);
-	}
-	clk_disable(bank->clk);
-
-	return IRQ_HANDLED;
-}
-
-static int rk628_interrupts_register(struct platform_device *pdev,
-				     struct rk628_pctrl_info *pci)
-{
-	struct rk628_pin_bank *bank = pci->pin_banks;
-	int ret;
-	u32 i;
-
-	for (i = 0; i < pci->nr_banks; ++i, ++bank) {
-		mutex_init(&bank->lock);
-		ret = clk_enable(bank->clk);
-		if (ret) {
-			dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
-				bank->name);
-			continue;
-		}
-
-		bank->irq = platform_get_irq(pdev, i);
-		bank->irq_chip = rk628_irq_chip[i];
-		bank->domain = irq_domain_add_linear(bank->of_node,
-						     bank->nr_pins,
-						     &rk628_domain_ops,
-						     bank);
-		if (!bank->domain) {
-			dev_warn(&pdev->dev,
-				 "could not initialize irq domain for bank %s\n",
-				 bank->name);
-			clk_disable(bank->clk);
-			continue;
-		}
-
-		ret = request_threaded_irq(bank->irq, NULL,
-					   rk628_irq_demux_thread,
-					   IRQF_ONESHOT,
-					   bank->name, bank);
-		if (ret != 0) {
-			dev_err(&pdev->dev,
-				"Failed to request IRQ %d for %s: %d\n",
-				bank->irq, bank->name, ret);
-		}
-
-		clk_disable(bank->clk);
-	}
-
-	return 0;
-}
-
-static int rk628_gpiolib_register(struct platform_device *pdev,
-				  struct rk628_pctrl_info *pci)
-{
-	struct rk628_pin_bank *bank = pci->pin_banks;
-	struct gpio_chip *gc;
-	int ret = 0, i;
-
-	for (i = 0; i < pci->nr_banks; ++i, ++bank) {
-		bank->gpio_chip = rk628_gpiolib_chip;
-		bank->pci = pci;
-		gc = &bank->gpio_chip;
-		gc->base = -1;
-		gc->ngpio = bank->nr_pins;
-		gc->parent = &pdev->dev;
-		gc->of_node = bank->of_node;
-		gc->label = bank->name;
-
-		ret = devm_gpiochip_add_data(&pdev->dev, gc, bank);
-		if (ret) {
-			dev_err(&pdev->dev,
-				"failed to register gpio_chip %s, error code: %d\n",
-				gc->label, ret);
-		}
-	}
-
-	return ret;
-}
-
-static int rk628_pinctrl_probe(struct platform_device *pdev)
-{
-	struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
-	struct device *dev = &pdev->dev;
-	struct rk628_pctrl_info *pci;
-	int ret;
-	u32 bank;
-	struct rk628_pin_bank *pin_bank;
-
-	pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
-	if (!pci)
-		return -ENOMEM;
-
-	pci->dev = &pdev->dev;
-	pci->grf_regmap = rk628->grf;
-
-	pci->pinctrl_desc = rk628_pinctrl_desc;
-	pci->groups = rk628_pin_groups;
-	pci->num_groups = ARRAY_SIZE(rk628_pin_groups);
-	pci->pinctrl_desc.pins = rk628_pins_desc;
-	pci->pinctrl_desc.npins = ARRAY_SIZE(rk628_pins_desc);
-	pci->pin_banks = rk628_pin_banks;
-	pci->nr_banks = ARRAY_SIZE(rk628_pin_banks),
-
-	platform_set_drvdata(pdev, pci);
-
-	ret = rk628_pinctrl_parse_dt(pdev, pci);
-	if (ret < 0)
-		return ret;
-
-	pci->regmap = devm_regmap_init_i2c(rk628->client,
-					   &rk628_pinctrl_regmap_config);
-	if (IS_ERR(pci->regmap)) {
-		ret = PTR_ERR(pci->regmap);
-		dev_err(dev, "failed to allocate register map: %d\n", ret);
-		return ret;
-	}
-
-	/* Add gpiochip */
-	ret = rk628_gpiolib_register(pdev, pci);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Couldn't add gpiochip\n");
-		return ret;
-	}
-
-	/* Add pinctrl */
-	pci->pctl = devm_pinctrl_register(&pdev->dev, &pci->pinctrl_desc, pci);
-	if (IS_ERR(pci->pctl)) {
-		dev_err(&pdev->dev, "Couldn't add pinctrl\n");
-		return PTR_ERR(pci->pctl);
-	}
-
-	for (bank = 0; bank < pci->nr_banks; ++bank) {
-		pin_bank = &pci->pin_banks[bank];
-		pin_bank->grange.name = pin_bank->name;
-		pin_bank->grange.id = bank;
-		pin_bank->grange.pin_base = BANK_OFFSET * bank;
-		pin_bank->grange.base = pin_bank->gpio_chip.base;
-		pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
-		pin_bank->grange.gc = &pin_bank->gpio_chip;
-		pinctrl_add_gpio_range(pci->pctl, &pin_bank->grange);
-	}
-
-	rk628_interrupts_register(pdev, pci);
-
-	return 0;
-}
-
-static const struct of_device_id rk628_pinctrl_dt_match[] = {
-	{ .compatible = "rockchip,rk628-pinctrl" },
-	{},
-};
-
-MODULE_DEVICE_TABLE(of, rk628_pinctrl_dt_match);
-
-static struct platform_driver rk628_pinctrl_driver = {
-	.probe = rk628_pinctrl_probe,
-	.driver = {
-		.name = "rk628-pinctrl",
-		.of_match_table = of_match_ptr(rk628_pinctrl_dt_match),
-	},
-};
-
-module_platform_driver(rk628_pinctrl_driver);
-
-MODULE_DESCRIPTION("RK628 pin control and GPIO driver");
-MODULE_AUTHOR("Weixin Zhou <zwx@rock-chips.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/rk628.h b/include/linux/mfd/rk628.h
deleted file mode 100755
index 52ff63e0c601..000000000000
--- a/include/linux/mfd/rk628.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
- *
- * Author: Wyon Bi <bivvy.bi@rock-chips.com>
- */
-
-#ifndef _RK628_H
-#define _RK628_H
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/regmap.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-
-#include <drm/drm_crtc_helper.h>
-
-#define UPDATE(x, h, l)		(((x) << (l)) & GENMASK((h), (l)))
-#define HIWORD_UPDATE(v, h, l)	(((v) << (l)) | (GENMASK((h), (l)) << 16))
-
-#define GRF_SYSTEM_CON0			0x0000
-#define SW_VSYNC_POL_MASK		BIT(26)
-#define SW_VSYNC_POL(x)			UPDATE(x, 26, 26)
-#define SW_HSYNC_POL_MASK		BIT(25)
-#define SW_HSYNC_POL(x)			UPDATE(x, 25, 25)
-#define SW_ADAPTER_I2CSLADR_MASK	GENMASK(24, 22)
-#define SW_ADAPTER_I2CSLADR(x)		UPDATE(x, 24, 22)
-#define SW_EDID_MODE_MASK		BIT(21)
-#define SW_EDID_MODE(x)			UPDATE(x, 21, 21)
-#define SW_I2S_DATA_OEN_MASK		BIT(10)
-#define SW_I2S_DATA_OEN(x)		UPDATE(x, 10, 10)
-#define SW_BT_DATA_OEN_MASK		BIT(9)
-#define SW_BT_DATA_OEN			BIT(9)
-#define SW_EFUSE_HDCP_EN_MASK		BIT(8)
-#define SW_EFUSE_HDCP_EN(x)		UPDATE(x, 8, 8)
-#define SW_OUTPUT_MODE_MASK		GENMASK(7, 3)
-#define SW_OUTPUT_MODE(x)		UPDATE(x, 7, 3)
-#define SW_INPUT_MODE_MASK		GENMASK(2, 0)
-#define SW_INPUT_MODE(x)		UPDATE(x, 2, 0)
-#define GRF_SYSTEM_CON1			0x0004
-#define GRF_SYSTEM_CON2			0x0008
-#define GRF_SYSTEM_CON3			0x000c
-#define GRF_GPIO_RX_CEC_SEL_MASK	BIT(7)
-#define GRF_GPIO_RX_CEC_SEL(x)		UPDATE(x, 7, 7)
-#define GRF_GPIO_RXDDC_SDA_SEL_MASK	BIT(6)
-#define GRF_GPIO_RXDDC_SDA_SEL(x)	UPDATE(x, 6, 6)
-#define GRF_GPIO_RXDDC_SCL_SEL_MASK	BIT(5)
-#define GRF_GPIO_RXDDC_SCL_SEL(x)	UPDATE(x, 5, 5)
-#define GRF_SCALER_CON0			0x0010
-#define SCL_VER_DOWN_MODE(x)		HIWORD_UPDATE(x, 8, 8)
-#define SCL_HOR_DOWN_MODE(x)		HIWORD_UPDATE(x, 7, 7)
-#define SCL_BIC_COE_SEL(x)		HIWORD_UPDATE(x, 6, 5)
-#define SCL_VER_MODE(x)			HIWORD_UPDATE(x, 4, 3)
-#define SCL_HOR_MODE(x)			HIWORD_UPDATE(x, 2, 1)
-#define SCL_EN(x)			HIWORD_UPDATE(x, 0, 0)
-#define GRF_SCALER_CON1			0x0014
-#define SCL_V_FACTOR(x)			UPDATE(x, 31, 16)
-#define SCL_H_FACTOR(x)			UPDATE(x, 15, 0)
-#define GRF_SCALER_CON2			0x0018
-#define DSP_FRAME_VST(x)		UPDATE(x, 28, 16)
-#define DSP_FRAME_HST(x)		UPDATE(x, 12, 0)
-#define GRF_SCALER_CON3			0x001c
-#define DSP_HS_END(x)			UPDATE(x, 23, 16)
-#define DSP_HTOTAL(x)			UPDATE(x, 12, 0)
-#define GRF_SCALER_CON4			0x0020
-#define DSP_HACT_ST(x)			UPDATE(x, 28, 16)
-#define DSP_HACT_END(x)			UPDATE(x, 12, 0)
-#define GRF_SCALER_CON5			0x0024
-#define DSP_VS_END(x)			UPDATE(x, 23, 16)
-#define DSP_VTOTAL(x)			UPDATE(x, 12, 0)
-#define GRF_SCALER_CON6			0x0028
-#define DSP_VACT_ST(x)			UPDATE(x, 28, 16)
-#define DSP_VACT_END(x)			UPDATE(x, 12, 0)
-#define GRF_SCALER_CON7			0x002c
-#define DSP_HBOR_ST(x)			UPDATE(x, 28, 16)
-#define DSP_HBOR_END(x)			UPDATE(x, 12, 0)
-#define GRF_SCALER_CON8			0x0030
-#define DSP_VBOR_ST(x)			UPDATE(x, 28, 16)
-#define DSP_VBOR_END(x)			UPDATE(x, 12, 0)
-#define GRF_POST_PROC_CON		0x0034
-#define SW_DCLK_OUT_INV_EN		BIT(9)
-#define SW_DCLK_IN_INV_EN		BIT(8)
-#define SW_TXPHY_REFCLK_SEL_MASK	GENMASK(6, 5)
-#define SW_TXPHY_REFCLK_SEL(x)		UPDATE(x, 6, 5)
-#define SW_HDMITX_VCLK_PLLREF_SEL_MASK	BIT(4)
-#define SW_HDMITX_VCLK_PLLREF_SEL(x)	UPDATE(x, 4, 4)
-#define SW_HDMITX_DCLK_INV_EN		BIT(3)
-#define SW_SPLIT_MODE(x)		UPDATE(x, 1, 1)
-#define SW_SPLIT_EN			BIT(0)
-#define GRF_CSC_CTRL_CON		0x0038
-#define SW_YUV2VYU_SWP(x)		HIWORD_UPDATE(x, 8, 8)
-#define SW_R2Y_EN(x)			HIWORD_UPDATE(x, 4, 4)
-#define SW_Y2R_EN(x)			HIWORD_UPDATE(x, 0, 0)
-#define GRF_LVDS_TX_CON			0x003c
-#define SW_LVDS_CON_DUAL_SEL(x)		HIWORD_UPDATE(x, 12, 12)
-#define SW_LVDS_CON_DEN_POLARITY(x)	HIWORD_UPDATE(x, 11, 11)
-#define SW_LVDS_CON_HS_POLARITY(x)	HIWORD_UPDATE(x, 10, 10)
-#define SW_LVDS_CON_CLKINV(x)		HIWORD_UPDATE(x, 9, 9)
-#define SW_LVDS_STARTPHASE(x)		HIWORD_UPDATE(x, 8, 8)
-#define SW_LVDS_CON_STARTSEL(x)		HIWORD_UPDATE(x, 7, 7)
-#define SW_LVDS_CON_CHASEL(x)		HIWORD_UPDATE(x, 6, 6)
-#define SW_LVDS_TIE_VSYNC_VALUE(x)	HIWORD_UPDATE(x, 5, 5)
-#define SW_LVDS_TIE_HSYNC_VALUE(x)	HIWORD_UPDATE(x, 4, 4)
-#define SW_LVDS_TIE_DEN_ONLY(x)		HIWORD_UPDATE(x, 3, 3)
-#define SW_LVDS_CON_MSBSEL(x)		HIWORD_UPDATE(x, 2, 2)
-#define SW_LVDS_CON_SELECT(x)		HIWORD_UPDATE(x, 1, 0)
-#define GRF_RGB_DEC_CON0		0x0040
-#define SW_HRES_MASK			GENMASK(28, 16)
-#define SW_HRES(x)			UPDATE(x, 28, 16)
-#define DUAL_DATA_SWAP			BIT(6)
-#define DEC_DUALEDGE_EN			BIT(5)
-#define SW_PROGRESS_EN			BIT(4)
-#define SW_YC_SWAP			BIT(3)
-#define SW_CAP_EN_ASYNC			BIT(1)
-#define SW_CAP_EN_PSYNC			BIT(0)
-#define GRF_RGB_DEC_CON1		0x0044
-#define SW_SET_X_MASK			GENMASK(28, 16)
-#define SW_SET_X(x)			HIWORD_UPDATE(x, 28, 16)
-#define SW_SET_Y_MASK			GENMASK(28, 16)
-#define SW_SET_Y(x)			HIWORD_UPDATE(x, 28, 16)
-#define GRF_RGB_DEC_CON2		0x0048
-#define GRF_RGB_ENC_CON			0x004c
-#define BT1120_UV_SWAP(x)		HIWORD_UPDATE(x, 5, 5)
-#define ENC_DUALEDGE_EN(x)		HIWORD_UPDATE(x, 3, 3)
-#define GRF_MIPI_LANE_DELAY_CON0	0x0050
-#define GRF_MIPI_LANE_DELAY_CON1	0x0054
-#define GRF_BT1120_DCLK_DELAY_CON0	0x0058
-#define GRF_BT1120_DCLK_DELAY_CON1	0x005c
-#define GRF_MIPI_TX0_CON		0x0060
-#define DPIUPDATECFG			BIT(26)
-#define DPICOLORM			BIT(25)
-#define DPISHUTDN			BIT(24)
-#define CSI_PHYRSTZ			BIT(21)
-#define CSI_PHYSHUTDOWNZ		BIT(20)
-#define FORCETXSTOPMODE_MASK		GENMASK(19, 16)
-#define FORCETXSTOPMODE(x)		UPDATE(x, 19, 16)
-#define FORCERXMODE_MASK		GENMASK(15, 12)
-#define FORCERXMODE(x)			UPDATE(x, 15, 12)
-#define PHY_TESTCLR			BIT(10)
-#define PHY_TESTCLK			BIT(9)
-#define PHY_TESTEN			BIT(8)
-#define PHY_TESTDIN_MASK		GENMASK(7, 0)
-#define PHY_TESTDIN(x)			UPDATE(x, 7, 0)
-#define GRF_DPHY0_STATUS		0x0064
-#define DPHY_PHYLOCK			BIT(24)
-#define PHY_TESTDOUT_SHIFT		8
-#define GRF_MIPI_TX1_CON		0x0068
-#define GRF_DPHY1_STATUS		0x006c
-#define GRF_GPIO0AB_SEL_CON		0x0070
-#define GRF_GPIO1AB_SEL_CON		0x0074
-#define GRF_GPIO2AB_SEL_CON		0x0078
-#define GRF_GPIO2C_SEL_CON		0x007c
-#define GRF_GPIO3AB_SEL_CON		0x0080
-#define GRF_GPIO2A_SMT			0x0090
-#define GRF_GPIO2B_SMT			0x0094
-#define GRF_GPIO2C_SMT			0x0098
-#define GRF_GPIO3AB_SMT			0x009c
-#define GRF_GPIO0A_P_CON		0x00a0
-#define GRF_GPIO1A_P_CON		0x00a4
-#define GRF_GPIO2A_P_CON		0x00a8
-#define GRF_GPIO2B_P_CON		0x00ac
-#define GRF_GPIO2C_P_CON		0x00b0
-#define GRF_GPIO3A_P_CON		0x00b4
-#define GRF_GPIO3B_P_CON		0x00b8
-#define GRF_GPIO0B_D_CON		0x00c0
-#define GRF_GPIO1B_D_CON		0x00c4
-#define GRF_GPIO2A_D0_CON		0x00c8
-#define GRF_GPIO2A_D1_CON		0x00cc
-#define GRF_GPIO2B_D0_CON		0x00d0
-#define GRF_GPIO2B_D1_CON		0x00d4
-#define GRF_GPIO2C_D0_CON		0x00d8
-#define GRF_GPIO2C_D1_CON		0x00dc
-#define GRF_GPIO3A_D0_CON		0x00e0
-#define GRF_GPIO3A_D1_CON		0x00e4
-#define GRF_GPIO3B_D_CON		0x00e8
-#define GRF_GPIO_SR_CON			0x00ec
-#define GRF_INTR0_EN			0x0100
-#define GRF_INTR0_CLR_EN		0x0104
-#define GRF_INTR0_STATUS		0x0108
-#define GRF_INTR0_RAW_STATUS		0x010c
-#define GRF_INTR1_EN			0x0110
-#define GRF_INTR1_CLR_EN		0x0114
-#define GRF_INTR1_STATUS		0x0118
-#define GRF_INTR1_RAW_STATUS		0x011c
-#define GRF_SYSTEM_STATUS0		0x0120
-/* 0: i2c mode and mcu mode; 1: i2c mode only */
-#define I2C_ONLY_FLAG			BIT(6)
-#define GRF_SYSTEM_STATUS3		0x012c
-#define GRF_SYSTEM_STATUS4		0x0130
-#define GRF_OS_REG0			0x0140
-#define GRF_OS_REG1			0x0144
-#define GRF_OS_REG2			0x0148
-#define GRF_OS_REG3			0x014c
-#define GRF_SOC_VERSION			0x0150
-#define GRF_MAX_REGISTER		GRF_SOC_VERSION
-
-enum {
-	COMBTXPHY_MODULEA_EN = BIT(0),
-	COMBTXPHY_MODULEB_EN = BIT(1),
-};
-
-enum {
-	OUTPUT_MODE_GVI = 1,
-	OUTPUT_MODE_LVDS,
-	OUTPUT_MODE_HDMI,
-	OUTPUT_MODE_CSI,
-	OUTPUT_MODE_DSI,
-	OUTPUT_MODE_BT1120 = 8,
-	OUTPUT_MODE_RGB = 16,
-	OUTPUT_MODE_YUV = 24,
-};
-
-enum {
-	INPUT_MODE_HDMI,
-	INPUT_MODE_BT1120 = 2,
-	INPUT_MODE_RGB,
-	INPUT_MODE_YUV,
-};
-
-struct rk628_irq_chip_data {
-	const char *name;
-	unsigned int status_base;
-	unsigned int mask_base;
-	unsigned int ack_base;
-	int num_regs;
-	const struct regmap_irq *irqs;
-	int num_irqs;
-	struct mutex lock;
-	struct irq_chip irq_chip;
-	struct regmap *map;
-	struct irq_domain *domain;
-	int irq;
-	unsigned int *status_buf;
-	unsigned int *mask_buf;
-	unsigned int *mask_buf_def;
-	unsigned int irq_reg_stride;
-	unsigned int reg_stride;
-};
-
-struct rk628 {
-	struct device *dev;
-	struct i2c_client *client;
-	struct regmap *grf;
-	struct gpio_desc *reset_gpio;
-	struct gpio_desc *enable_gpio;
-	struct rk628_irq_chip_data *irq_data;
-	struct drm_display_mode src_mode;
-	struct drm_display_mode dst_mode;
-	bool dst_mode_valid;
-};
-
-/**
- * rk628_scaler_add_src_mode - add source mode for scaler
- * @rk628: parent device
- * @connector: DRM connector
- * If need scale, call the function at last of get_modes.
- */
-int rk628_scaler_add_src_mode(struct rk628 *rk628,
-			      struct drm_connector *connector);
-
-/**
- * rk628_mode_copy - rk628 mode copy
- * @rk628: parent device
- * @dst: dst mode
- * @src: src mode
- * Call the function at mode_set, replace drm_mode_copy.
- */
-void rk628_mode_copy(struct rk628 *rk628, struct drm_display_mode *dst,
-		     const struct drm_display_mode *src);
-
-#endif