From f15ea98e91414e6304cc2a10eccf1563e2cc127f Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Sun, 21 Jan 2024 14:33:57 +0800 Subject: [PATCH 1/8] Revert "nvmem: rk628-efuse: add rk628 efuse driver" This reverts commit a939cdfe9d10015b50fa5ffae5de9ebf41bfefbf. Signed-off-by: Tao Huang Change-Id: I6b44046b6f8999c84d4380710c9751efd0c14daf --- drivers/nvmem/Kconfig | 12 -- drivers/nvmem/Makefile | 2 - drivers/nvmem/rk628-efuse.c | 299 ------------------------------------ 3 files changed, 313 deletions(-) delete mode 100644 drivers/nvmem/rk628-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index d6ec24c82e15..3e300d06d8fe 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -126,18 +126,6 @@ config NVMEM_SPMI_SDAM Qualcomm Technologies, Inc. PMICs. It provides the clients an interface to read/write to the SDAM module's shared memory. -config RK628_EFUSE - tristate "RK628 eFuse Support" - depends on ARCH_ROCKCHIP || COMPILE_TEST - depends on HAS_IOMEM - depends on MFD_RK628 - help - This is a simple drive to dump specified values of Rk628 SoC - from eFuse, such as cpu-leakage. - - This driver can also be built as a module. If so, the module - will be called nvmem_rk628_efuse. - config ROCKCHIP_EFUSE tristate "Rockchip eFuse Support" depends on ARCH_ROCKCHIP || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index fd1267ddaf23..e734808b7e5a 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -29,8 +29,6 @@ obj-$(CONFIG_QCOM_QFPROM) += nvmem_qfprom.o nvmem_qfprom-y := qfprom.o obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o -obj-$(CONFIG_RK628_EFUSE) += nvmem_rk628_efuse.o -nvmem_rk628_efuse-y := rk628-efuse.o obj-$(CONFIG_ROCKCHIP_EFUSE) += nvmem_rockchip_efuse.o nvmem_rockchip_efuse-y := rockchip-efuse.o obj-$(CONFIG_ROCKCHIP_OTP) += nvmem-rockchip-otp.o diff --git a/drivers/nvmem/rk628-efuse.c b/drivers/nvmem/rk628-efuse.c deleted file mode 100644 index 87b5a3c78021..000000000000 --- a/drivers/nvmem/rk628-efuse.c +++ /dev/null @@ -1,299 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * RK628 eFuse Driver - * - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * - * Author: Weixin Zhou - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define EFUSE_SIZE 64 - -#define T_CSB_P_S 0 -#define T_PGENB_P_S (15 + 200) -#define T_LOAD_P_S 0 -#define T_ADDR_P_S (15 + 200 + 5) -#define T_STROBE_P_S ((150 + 2000 + 100) / 9) -#define T_CSB_P_L 0 -#define T_PGENB_P_L (15 + 200 + 10 + 200 + 190 + 10) -#define T_LOAD_P_L (15 + 200 + 200 + 190 + 10 + 100 + 15) -#define T_ADDR_P_L (15 + 200 + 5 + 200 + 5) -#define T_STROBE_P_L ((150 + 2000 + 100 + 2000) / 9) -#define T_CSB_R_S 0 -#define T_PGENB_R_S 0 -#define T_LOAD_R_S 15 -#define T_ADDR_R_S (15 + 9) -#define T_STROBE_R_S ((150 + 100) / 9) -#define T_CSB_R_L 0 -#define T_PGENB_R_L 0 -#define T_LOAD_R_L (15 + 5 + 5 + 10 + 15) -#define T_ADDR_R_L (15 + 10 + 5 + 1) -#define T_STROBE_R_L ((150 + 100 + 50) / 8) - -#define T_CSB_P 0x28 -#define T_PGENB_P 0x2c -#define T_LOAD_P 0x30 -#define T_ADDR_P 0x34 -#define T_STROBE_P 0x38 -#define T_CSB_R 0x3c -#define T_PGENB_R 0x40 -#define T_LOAD_R 0x44 -#define T_ADDR_R 0x48 -#define T_STROBE_R 0x4c -#define EFUSE_REVISION 0x50 - -#define RK628_EFUSE_BASE 0xb0000 -#define RK628_MOD 0x00 -#define RK628_INT_STATUS 0x0018 -#define RK628_DOUT 0x0020 -#define RK628_AUTO_CTRL 0x0024 -#define RK628_USER_MODE BIT(0) -#define RK628_INT_FINISH BIT(0) -#define RK628_AUTO_ENB BIT(0) -#define RK628_AUTO_RD BIT(1) -#define RK628_ADDR_ROW 16 -#define RK628_ADDR_COL 22 -#define RK628_A_SHIFT 16 -#define RK628_A_MASK 0x3ff -#define RK628_NBYTES 1 - -#define REG_EFUSE_CTRL 0x0000 -#define REG_EFUSE_DOUT 0x0004 - -struct rk628_efuse_chip { - struct device *dev; - u32 base; - struct clk *clk; - struct regmap *regmap; - struct gpio_desc *avdd_gpio; -}; - -static int rk628_read(struct regmap *regmap, u32 reg) -{ - int ret; - u32 val; - struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap); - - ret = regmap_read(regmap, reg, &val); - if (ret) { - dev_err(efuse->dev, "rk628-efuse:failed to read reg 0x%x\n", reg); - return ret; - } - - return val; -} - -static int rk628_write(struct regmap *regmap, u32 val, u32 reg) -{ - int ret; - struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap); - - ret = regmap_write(regmap, reg, val); - if (ret) - dev_err(efuse->dev, "rk628-efuse:failed to write reg 0x%x\n", reg); - - return ret; -} - -static void rk628_efuse_timing_init(struct rk628_efuse_chip *efuse) -{ - u32 base = efuse->base; - /* enable auto mode */ - rk628_write(efuse->regmap, - rk628_read(efuse->regmap, base + RK628_MOD) & (~RK628_USER_MODE), - base + RK628_MOD); - - /* setup efuse timing */ - rk628_write(efuse->regmap, (T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P); - rk628_write(efuse->regmap, (T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P); - rk628_write(efuse->regmap, (T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P); - rk628_write(efuse->regmap, (T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P); - rk628_write(efuse->regmap, (T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P); - rk628_write(efuse->regmap, (T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R); - rk628_write(efuse->regmap, (T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R); - rk628_write(efuse->regmap, (T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R); - rk628_write(efuse->regmap, (T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R); - rk628_write(efuse->regmap, (T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R); -} - -static void rk628_efuse_timing_deinit(struct rk628_efuse_chip *efuse) -{ - u32 base = efuse->base; - /* disable auto mode */ - rk628_write(efuse->regmap, - rk628_read(efuse->regmap, base + RK628_MOD) | RK628_USER_MODE, base + RK628_MOD); - - /* clear efuse timing */ - rk628_write(efuse->regmap, 0, base + T_CSB_P); - rk628_write(efuse->regmap, 0, base + T_PGENB_P); - rk628_write(efuse->regmap, 0, base + T_LOAD_P); - rk628_write(efuse->regmap, 0, base + T_ADDR_P); - rk628_write(efuse->regmap, 0, base + T_STROBE_P); - rk628_write(efuse->regmap, 0, base + T_CSB_R); - rk628_write(efuse->regmap, 0, base + T_PGENB_R); - rk628_write(efuse->regmap, 0, base + T_LOAD_R); - rk628_write(efuse->regmap, 0, base + T_ADDR_R); - rk628_write(efuse->regmap, 0, base + T_STROBE_R); -} - -static int rk628_efuse_read(void *context, unsigned int offset, - void *val, size_t bytes) -{ - struct rk628_efuse_chip *efuse = context; - unsigned int addr_start, addr_end, addr_offset, addr_len; - u32 out_value, status; - u8 *buf; - int ret, i = 0; - - ret = clk_prepare_enable(efuse->clk); - if (ret < 0) { - dev_err(efuse->dev, "failed to prepare/enable efuse pclk\n"); - return ret; - } - - addr_start = rounddown(offset, RK628_NBYTES) / RK628_NBYTES; - addr_end = roundup(offset + bytes, RK628_NBYTES) / RK628_NBYTES; - addr_offset = offset % RK628_NBYTES; - addr_len = addr_end - addr_start; - - buf = kzalloc(sizeof(*buf) * addr_len * RK628_NBYTES, GFP_KERNEL); - if (!buf) { - ret = -ENOMEM; - goto nomem; - } - - rk628_efuse_timing_init(efuse); - - while (addr_len--) { - rk628_write(efuse->regmap, RK628_AUTO_RD | RK628_AUTO_ENB | - ((addr_start++ & RK628_A_MASK) << RK628_A_SHIFT), - efuse->base + RK628_AUTO_CTRL); - udelay(2); - status = rk628_read(efuse->regmap, efuse->base + RK628_INT_STATUS); - if (!(status & RK628_INT_FINISH)) { - ret = -EIO; - goto err; - } - out_value = rk628_read(efuse->regmap, efuse->base + RK628_DOUT); - rk628_write(efuse->regmap, RK628_INT_FINISH, efuse->base + RK628_INT_STATUS); - - memcpy(&buf[i], &out_value, RK628_NBYTES); - i += RK628_NBYTES; - } - memcpy(val, buf + addr_offset, bytes); -err: - rk628_efuse_timing_deinit(efuse); - kfree(buf); -nomem: - clk_disable_unprepare(efuse->clk); - - return ret; -} - -static struct nvmem_config econfig = { - .name = "rk628-efuse", - .owner = THIS_MODULE, - .stride = 1, - .word_size = 1, - .read_only = true, -}; - -static const struct regmap_range rk628_efuse_readable_ranges[] = { - regmap_reg_range(RK628_EFUSE_BASE, RK628_EFUSE_BASE + EFUSE_REVISION), -}; - -static const struct regmap_access_table rk628_efuse_readable_table = { - .yes_ranges = rk628_efuse_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(rk628_efuse_readable_ranges), -}; - -static const struct regmap_config rk628_efuse_regmap_config = { - .name = "rk628-efuse", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = RK628_EFUSE_BASE + EFUSE_REVISION, - .reg_format_endian = REGMAP_ENDIAN_LITTLE, - .val_format_endian = REGMAP_ENDIAN_LITTLE, - .rd_table = &rk628_efuse_readable_table, -}; - -static const struct of_device_id rk628_efuse_match[] = { - { - .compatible = "rockchip,rk628-efuse", - }, - { /* sentinel */ }, -}; -MODULE_DEVICE_TABLE(of, rk628_efuse_match); - -static int __init rk628_efuse_probe(struct platform_device *pdev) -{ - struct nvmem_device *nvmem; - struct rk628_efuse_chip *efuse; - struct device *dev = &pdev->dev; - struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent); - int ret; - - efuse = devm_kzalloc(&pdev->dev, sizeof(struct rk628_efuse_chip), - GFP_KERNEL); - if (!efuse) - return -ENOMEM; - - efuse->regmap = devm_regmap_init_i2c(rk628->client, - &rk628_efuse_regmap_config); - if (IS_ERR(efuse->regmap)) { - ret = PTR_ERR(efuse->regmap); - dev_err(dev, "failed to allocate register map: %d\n", - ret); - return ret; - } - - efuse->clk = devm_clk_get(&pdev->dev, "pclk"); - if (IS_ERR(efuse->clk)) { - dev_err(dev, "failed to get pclk: %ld\n", PTR_ERR(efuse->clk)); - return PTR_ERR(efuse->clk); - } - - efuse->avdd_gpio = devm_gpiod_get_optional(dev, "efuse", GPIOD_OUT_LOW); - efuse->base = RK628_EFUSE_BASE; - efuse->dev = &pdev->dev; - econfig.size = EFUSE_SIZE; - econfig.reg_read = (void *)&rk628_efuse_read; - econfig.priv = efuse; - econfig.dev = efuse->dev; - nvmem = devm_nvmem_register(&econfig); - if (IS_ERR(nvmem)) - return PTR_ERR(nvmem); - - platform_set_drvdata(pdev, nvmem); - - return 0; -} - -static struct platform_driver rk628_efuse_driver = { - .probe = rk628_efuse_probe, - .driver = { - .name = "rk628-efuse", - .of_match_table = rk628_efuse_match, - }, -}; - -module_platform_driver(rk628_efuse_driver); - -MODULE_DESCRIPTION("rk628_efuse driver"); -MODULE_LICENSE("GPL v2"); From 404c9aa46eb95b5c58105668ccfbc84bf9a3dee9 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Sun, 21 Jan 2024 14:34:10 +0800 Subject: [PATCH 2/8] Revert "pinctrl: rk628: add rk628 pinctrl driver" This reverts commit 136c56731b7d86fa26163f841211a4b0198678cb. This reverts commit 4a70b2101249504cde3966c19d979e45716d1f4b. Signed-off-by: Tao Huang Change-Id: If2a96546cefa1453af4229d06563235d447fd8e6 --- drivers/pinctrl/Kconfig | 10 - drivers/pinctrl/Makefile | 1 - drivers/pinctrl/pinctrl-rk628.c | 1696 ------------------------------- 3 files changed, 1707 deletions(-) delete mode 100644 drivers/pinctrl/pinctrl-rk628.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index fda4a167684c..52b88d0fcbeb 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -378,16 +378,6 @@ config PINCTRL_INGENIC select GPIOLIB_IRQCHIP select REGMAP_MMIO -config PINCTRL_RK628 - tristate "Pinctrl and GPIO driver for RK628 PMIC" - depends on MFD_RK628 - select GPIOLIB - select PINMUX - select GENERIC_PINCONF - select REGMAP_IRQ - help - This selects the pinctrl driver for RK628. - config PINCTRL_RK805 tristate "Pinctrl and GPIO driver for RK805 PMIC" depends on MFD_RK808 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d8b32105bb4b..15fc7bfa3dd2 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -46,7 +46,6 @@ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o -obj-$(CONFIG_PINCTRL_RK628) += pinctrl-rk628.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_RK806) += pinctrl-rk806.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o diff --git a/drivers/pinctrl/pinctrl-rk628.c b/drivers/pinctrl/pinctrl-rk628.c deleted file mode 100644 index 6e07be50e6e2..000000000000 --- a/drivers/pinctrl/pinctrl-rk628.c +++ /dev/null @@ -1,1696 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Pinctrl driver for Rockchip RK628 - * - * Copyright (c) 2019, Fuzhou Rockchip Electronics Co., Ltd - * - * Author: Weixin Zhou - * - * Based on the pinctrl-rk805/pinctrl-rockchip driver - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" -#include "pinconf.h" -#include "pinctrl-utils.h" - -#define GPIO0_BASE 0xD0000 -#define GPIO1_BASE 0xE0000 -#define GPIO2_BASE 0xF0000 -#define GPIO3_BASE 0x100000 -#define GPIO_MAX_REGISTER (GPIO3_BASE + GPIO_VER_ID) - -/* GPIO control registers */ -#define GPIO_SWPORT_DR_L 0x00 -#define GPIO_SWPORT_DR_H 0x04 -#define GPIO_SWPORT_DDR_L 0x08 -#define GPIO_SWPORT_DDR_H 0x0c -#define GPIO_INTEN_L 0x10 -#define GPIO_INTEN_H 0x14 -#define GPIO_INTMASK_L 0x18 -#define GPIO_INTMASK_H 0x1c -#define GPIO_INTTYPE_L 0x20 -#define GPIO_INTTYPE_H 0x24 -#define GPIO_INT_POLARITY_L 0x28 -#define GPIO_INT_POLARITY_H 0x2c -#define GPIO_INT_BOTHEDGE_L 0x30 -#define GPIO_INT_BOTHEDGE_H 0x34 -#define GPIO_DEBOUNCE_L 0x38 -#define GPIO_DEBOUNCE_H 0x3c -#define GPIO_DBCLK_DIV_EN_L 0x40 -#define GPIO_DBCLK_DIV_EN_H 0x44 -#define GPIO_INT_STATUS 0x50 -#define GPIO_INT_RAWSTATUS 0x58 -#define GPIO_PORTS_EOI_L 0x60 -#define GPIO_PORTS_EOI_H 0x64 -#define GPIO_EXT_PORT 0x70 -#define GPIO_VER_ID 0x78 - -#define GPIO_REG_LOW 0x0 -#define GPIO_REG_HIGH 0x1 - -/* GPIO control registers */ -#define GPIO_INTMASK 0x34 -#define GPIO_PORTS_EOI 0x4c - -#define BANK_OFFSET 32 - -#define IRQ_CHIP(fname) \ - [IRQCHIP_##fname] = { \ - .name = "rk628-"#fname, \ - .irq_bus_lock = rk628_irq_lock, \ - .irq_bus_sync_unlock = rk628_irq_sync_unlock,\ - .irq_disable = rk628_irq_disable, \ - .irq_enable = rk628_irq_enable, \ - .irq_set_type = rk628_irq_set_type, \ - } - -struct rk628_pin_function { - const char *name; - const char **groups; - unsigned int ngroups; - int mux_option; -}; - -struct rk628_pin_group { - const char *name; - const unsigned int pins[1]; - unsigned int npins; - int iomux_base; -}; - -struct rk628_pin_bank { - char *name; - u32 reg_base; - u32 nr_pins; - struct device_node *of_node; - struct pinctrl_gpio_range grange; - struct gpio_chip gpio_chip; - struct clk *clk; - struct rk628_pctrl_info *pci; - - struct irq_chip irq_chip; - struct irq_domain *domain; - int irq; - struct mutex lock; - unsigned int mask_regs[2]; - unsigned int polarity_regs[2]; - unsigned int level_regs[2]; - unsigned int bothedge_regs[2]; -}; - -struct rk628_pctrl_info { - struct device *dev; - struct pinctrl_dev *pctl; - struct pinctrl_desc pinctrl_desc; - const struct rk628_pin_function *functions; - unsigned int num_functions; - const struct rk628_pin_group *groups; - int num_groups; - const struct pinctrl_pin_desc *pins; - unsigned int num_pins; - struct regmap *regmap; - struct regmap *grf_regmap; - struct rk628_pin_bank *pin_banks; - u32 nr_banks; -}; - -enum rk628_pinmux_option { - PINMUX_FUNC0, - PINMUX_FUNC1, -}; - -#define PINCTRL_GROUP(a, b, c, d) { .name = a, .pins = b, .npins = c, .iomux_base = d} -#define PINCTRL_BANK(a, b, c) { .name = a, .reg_base = b, .nr_pins = c} - -enum rk628_functions { - MUX_GPIO, -}; - -static const char *gpio_groups[] = { - "gpio0a0", "gpio0a1", "gpio0a2", "gpio0a3", "gpio0a4", "gpio0a5", - "gpio0a6", "gpio0a7", "gpio0b0", "gpio0b1", "gpio0b2", "gpio0b3", - "gpio1a0", "gpio1a1", "gpio1a2", "gpio1a3", "gpio1a4", "gpio1a5", - "gpio1a6", "gpio1a7", "gpio1b0", "gpio1b1", "gpio1b2", "gpio1b3", - "gpio1b4", "gpio1b5", - "gpio2a0", "gpio2a1", "gpio2a2", "gpio2a3", "gpio2a4", "gpio2a5", - "gpio2a6", "gpio2a7", "gpio2b0", "gpio2b1", "gpio2b2", "gpio2b3", - "gpio2b4", "gpio2b5", "gpio2b6", "gpio2b7", "gpio2c0", "gpio2c1", - "gpio2c3", "gpio2c4", "gpio2c5", "gpio2c6", "gpio2c7", "gpio1a0", - "gpio3a1", "gpio3a2", "gpio3a3", "gpio3a4", "gpio3a5", "gpio3a6", - "gpio3a7", "gpio3b0", "gpio3b1", "gpio3b2", "gpio3b3", "gpio3b4", -}; - -static struct rk628_pin_function rk628_functions[] = { - { - .name = "gpio", - .groups = gpio_groups, - .ngroups = ARRAY_SIZE(gpio_groups), - }, -}; - -enum { - GPIO_HIGH_Z, - GPIO_PULL_UP, - GPIO_PULL_DOWN, -}; - -enum { - GPIO0_A0 = BANK_OFFSET * 0, - GPIO0_A1, - GPIO0_A2, - GPIO0_A3, - GPIO0_A4, - GPIO0_A5, - GPIO0_A6, - GPIO0_A7, - GPIO0_B0, - GPIO0_B1, - GPIO0_B2, - GPIO0_B3, - GPIO1_A0 = BANK_OFFSET * 1, - GPIO1_A1, - GPIO1_A2, - GPIO1_A3, - GPIO1_A4, - GPIO1_A5, - GPIO1_A6, - GPIO1_A7, - GPIO1_B0, - GPIO1_B1, - GPIO1_B2, - GPIO1_B3, - GPIO1_B4, - GPIO1_B5, - GPIO2_A0 = BANK_OFFSET * 2, - GPIO2_A1, - GPIO2_A2, - GPIO2_A3, - GPIO2_A4, - GPIO2_A5, - GPIO2_A6, - GPIO2_A7, - GPIO2_B0, - GPIO2_B1, - GPIO2_B2, - GPIO2_B3, - GPIO2_B4, - GPIO2_B5, - GPIO2_B6, - GPIO2_B7, - GPIO2_C0, - GPIO2_C1, - GPIO2_C2, - GPIO2_C3, - GPIO2_C4, - GPIO2_C5, - GPIO2_C6, - GPIO2_C7, - GPIO3_A0 = BANK_OFFSET * 3, - GPIO3_A1, - GPIO3_A2, - GPIO3_A3, - GPIO3_A4, - GPIO3_A5, - GPIO3_A6, - GPIO3_A7, - GPIO3_B0, - GPIO3_B1, - GPIO3_B2, - GPIO3_B3, - GPIO3_B4, - I2SM_SCK = BANK_OFFSET * 4 + 2, - I2SM_D, - I2SM_LR, - RXDDC_SCL, - RXDDC_SDA, - HDMIRX_CE, -}; - -static struct pinctrl_pin_desc rk628_pins_desc[] = { - PINCTRL_PIN(GPIO0_A0, "gpio0a0"), - PINCTRL_PIN(GPIO0_A1, "gpio0a1"), - PINCTRL_PIN(GPIO0_A2, "gpio0a2"), - PINCTRL_PIN(GPIO0_A3, "gpio0a3"), - PINCTRL_PIN(GPIO0_A4, "gpio0a4"), - PINCTRL_PIN(GPIO0_A5, "gpio0a5"), - PINCTRL_PIN(GPIO0_A6, "gpio0a6"), - PINCTRL_PIN(GPIO0_A7, "gpio0a7"), - PINCTRL_PIN(GPIO0_B0, "gpio0b0"), - PINCTRL_PIN(GPIO0_B1, "gpio0b1"), - PINCTRL_PIN(GPIO0_B2, "gpio0b2"), - PINCTRL_PIN(GPIO0_B3, "gpio0b3"), - - PINCTRL_PIN(GPIO1_A0, "gpio1a0"), - PINCTRL_PIN(GPIO1_A1, "gpio1a1"), - PINCTRL_PIN(GPIO1_A2, "gpio1a2"), - PINCTRL_PIN(GPIO1_A3, "gpio1a3"), - PINCTRL_PIN(GPIO1_A4, "gpio1a4"), - PINCTRL_PIN(GPIO1_A5, "gpio1a5"), - PINCTRL_PIN(GPIO1_A6, "gpio1a6"), - PINCTRL_PIN(GPIO1_A7, "gpio1a7"), - PINCTRL_PIN(GPIO1_B0, "gpio1b0"), - PINCTRL_PIN(GPIO1_B1, "gpio1b1"), - PINCTRL_PIN(GPIO1_B2, "gpio1b2"), - PINCTRL_PIN(GPIO1_B3, "gpio1b3"), - PINCTRL_PIN(GPIO1_B4, "gpio1b4"), - PINCTRL_PIN(GPIO1_B5, "gpio1b5"), - - PINCTRL_PIN(GPIO2_A0, "gpio2a0"), - PINCTRL_PIN(GPIO2_A1, "gpio2a1"), - PINCTRL_PIN(GPIO2_A2, "gpio2a2"), - PINCTRL_PIN(GPIO2_A3, "gpio2a3"), - PINCTRL_PIN(GPIO2_A4, "gpio2a4"), - PINCTRL_PIN(GPIO2_A5, "gpio2a5"), - PINCTRL_PIN(GPIO2_A6, "gpio2a6"), - PINCTRL_PIN(GPIO2_A7, "gpio2a7"), - PINCTRL_PIN(GPIO2_B0, "gpio2b0"), - PINCTRL_PIN(GPIO2_B1, "gpio2b1"), - PINCTRL_PIN(GPIO2_B2, "gpio2b2"), - PINCTRL_PIN(GPIO2_B3, "gpio2b3"), - PINCTRL_PIN(GPIO2_B4, "gpio2b4"), - PINCTRL_PIN(GPIO2_B5, "gpio2b5"), - PINCTRL_PIN(GPIO2_B6, "gpio2b6"), - PINCTRL_PIN(GPIO2_B7, "gpio2b7"), - PINCTRL_PIN(GPIO2_C0, "gpio2c0"), - PINCTRL_PIN(GPIO2_C1, "gpio2c1"), - PINCTRL_PIN(GPIO2_C2, "gpio2c2"), - PINCTRL_PIN(GPIO2_C3, "gpio2c3"), - PINCTRL_PIN(GPIO2_C4, "gpio2c4"), - PINCTRL_PIN(GPIO2_C5, "gpio2c5"), - PINCTRL_PIN(GPIO2_C6, "gpio2c6"), - PINCTRL_PIN(GPIO2_C7, "gpio2c7"), - - PINCTRL_PIN(GPIO3_A0, "gpio3a0"), - PINCTRL_PIN(GPIO3_A1, "gpio3a1"), - PINCTRL_PIN(GPIO3_A2, "gpio3a2"), - PINCTRL_PIN(GPIO3_A3, "gpio3a3"), - PINCTRL_PIN(GPIO3_A4, "gpio3a4"), - PINCTRL_PIN(GPIO3_A5, "gpio3a5"), - PINCTRL_PIN(GPIO3_A6, "gpio3a6"), - PINCTRL_PIN(GPIO3_A7, "gpio3a7"), - PINCTRL_PIN(GPIO3_B0, "gpio3b0"), - PINCTRL_PIN(GPIO3_B1, "gpio3b1"), - PINCTRL_PIN(GPIO3_B2, "gpio3b2"), - PINCTRL_PIN(GPIO3_B3, "gpio3b3"), - PINCTRL_PIN(GPIO3_B4, "gpio3b4"), - - PINCTRL_PIN(I2SM_SCK, "i2sm_sck"), - PINCTRL_PIN(I2SM_D, "i2sm_d"), - PINCTRL_PIN(I2SM_LR, "i2sm_lr"), - PINCTRL_PIN(RXDDC_SCL, "rxddc_scl"), - PINCTRL_PIN(RXDDC_SDA, "rxddc_sda"), - PINCTRL_PIN(HDMIRX_CE, "hdmirx_cec"), -}; - -static const struct rk628_pin_group rk628_pin_groups[] = { - PINCTRL_GROUP("gpio0a0", { GPIO0_A0 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0a1", { GPIO0_A1 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0a2", { GPIO0_A2 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0a3", { GPIO0_A3 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0a4", { GPIO0_A4 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0a5", { GPIO0_A5 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0a6", { GPIO0_A6 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0a7", { GPIO0_A7 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0b0", { GPIO0_B0 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0b1", { GPIO0_B1 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0b2", { GPIO0_B2 }, 1, GRF_GPIO0AB_SEL_CON), - PINCTRL_GROUP("gpio0b3", { GPIO0_B3 }, 1, GRF_GPIO0AB_SEL_CON), - - PINCTRL_GROUP("gpio1a0", { GPIO1_A0 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1a1", { GPIO1_A1 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1a2", { GPIO1_A2 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1a3", { GPIO1_A3 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1a4", { GPIO1_A4 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1a5", { GPIO1_A5 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1a6", { GPIO1_A6 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1a7", { GPIO1_A7 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1b0", { GPIO1_B0 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1b1", { GPIO1_B1 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1b2", { GPIO1_B2 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1b3", { GPIO1_B3 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1b4", { GPIO1_B4 }, 1, GRF_GPIO1AB_SEL_CON), - PINCTRL_GROUP("gpio1b5", { GPIO1_B5 }, 1, GRF_GPIO1AB_SEL_CON), - - PINCTRL_GROUP("gpio2a0", { GPIO2_A0 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2a1", { GPIO2_A1 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2a2", { GPIO2_A2 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2a3", { GPIO2_A3 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2a4", { GPIO2_A4 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2a5", { GPIO2_A5 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2a6", { GPIO2_A6 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2a7", { GPIO2_A7 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2b0", { GPIO2_B0 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2b1", { GPIO2_B1 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2b2", { GPIO2_B2 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2b3", { GPIO2_B3 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2b4", { GPIO2_B4 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2b5", { GPIO2_B5 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2b6", { GPIO2_B6 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2b7", { GPIO2_B7 }, 1, GRF_GPIO2AB_SEL_CON), - PINCTRL_GROUP("gpio2c0", { GPIO2_C0 }, 1, GRF_GPIO2C_SEL_CON), - PINCTRL_GROUP("gpio2c1", { GPIO2_C1 }, 1, GRF_GPIO2C_SEL_CON), - PINCTRL_GROUP("gpio2c2", { GPIO2_C2 }, 1, GRF_GPIO2C_SEL_CON), - PINCTRL_GROUP("gpio2c3", { GPIO2_C3 }, 1, GRF_GPIO2C_SEL_CON), - PINCTRL_GROUP("gpio2c4", { GPIO2_C4 }, 1, GRF_GPIO2C_SEL_CON), - PINCTRL_GROUP("gpio2c5", { GPIO2_C5 }, 1, GRF_GPIO2C_SEL_CON), - PINCTRL_GROUP("gpio2c6", { GPIO2_C6 }, 1, GRF_GPIO2C_SEL_CON), - PINCTRL_GROUP("gpio2c7", { GPIO2_C7 }, 1, GRF_GPIO2C_SEL_CON), - - PINCTRL_GROUP("gpio3a0", { GPIO3_A0 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3a1", { GPIO3_A1 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3a2", { GPIO3_A2 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3a3", { GPIO3_A3 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3a4", { GPIO3_A4 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3a5", { GPIO3_A5 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3a6", { GPIO3_A6 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3a7", { GPIO3_A7 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3b0", { GPIO3_B0 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3b1", { GPIO3_B1 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3b2", { GPIO3_B2 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3b3", { GPIO3_B3 }, 1, GRF_GPIO3AB_SEL_CON), - PINCTRL_GROUP("gpio3b4", { GPIO3_B4 }, 1, GRF_GPIO3AB_SEL_CON), - - PINCTRL_GROUP("i2sm_sck", { I2SM_SCK }, 1, GRF_SYSTEM_CON3), - PINCTRL_GROUP("i2sm_d", { I2SM_D }, 1, GRF_SYSTEM_CON3), - PINCTRL_GROUP("i2sm_lr", { I2SM_LR }, 1, GRF_SYSTEM_CON3), - PINCTRL_GROUP("rxddc_scl", { RXDDC_SCL }, 1, GRF_SYSTEM_CON3), - PINCTRL_GROUP("rxddc_sda", { RXDDC_SDA }, 1, GRF_SYSTEM_CON3), - PINCTRL_GROUP("hdmirx_cec", { HDMIRX_CE }, 1, GRF_SYSTEM_CON3), -}; - -static struct rk628_pin_bank rk628_pin_banks[] = { - PINCTRL_BANK("rk628-gpio0", GPIO0_BASE, 12), - PINCTRL_BANK("rk628-gpio1", GPIO1_BASE, 14), - PINCTRL_BANK("rk628-gpio2", GPIO2_BASE, 24), - PINCTRL_BANK("rk628-gpio3", GPIO3_BASE, 13), -}; - -/* generic gpio chip */ -static int rk628_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct rk628_pin_bank *bank = gpiochip_get_data(chip); - struct rk628_pctrl_info *pci = bank->pci; - int data_reg, val, ret; - - data_reg = bank->reg_base + GPIO_EXT_PORT; - - clk_enable(bank->clk); - ret = regmap_read(pci->regmap, data_reg, &val); - if (ret) - dev_err(pci->dev, "%s: regmap read failed!\n", __func__); - clk_disable(bank->clk); - - val >>= offset; - val &= 1; - dev_dbg(pci->dev, "%s bank->name=%s dir_reg=0x%x offset=%x value=%x\n", - __func__, bank->name, data_reg, offset, val); - - return val; -} - -static void rk628_gpio_set(struct gpio_chip *chip, - unsigned int offset, - int value) -{ - struct rk628_pin_bank *bank = gpiochip_get_data(chip); - struct rk628_pctrl_info *pci = bank->pci; - int data_reg, val, ret; - - if (offset / 16) { - data_reg = bank->reg_base + GPIO_SWPORT_DR_H; - offset -= 16; - } else { - data_reg = bank->reg_base + GPIO_SWPORT_DR_L; - } - if (value) - val = BIT(offset + 16) | BIT(offset); - else - val = BIT(offset + 16) | (0xffff & ~BIT(offset)); - - clk_enable(bank->clk); - ret = regmap_write(pci->regmap, data_reg, val); - if (ret) - pr_err("%s: regmap write failed! bank->name=%s data_reg=0x%x offset=%d\n", - __func__, bank->name, data_reg, offset); - clk_disable(bank->clk); -} - -static int rk628_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - return pinctrl_gpio_direction_input(chip->base + offset); -} - -static int rk628_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, - int value) -{ - rk628_gpio_set(chip, offset, value); - return pinctrl_gpio_direction_output(chip->base + offset); -} - -static int rk628_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) -{ - struct rk628_pin_bank *bank = gpiochip_get_data(chip); - struct rk628_pctrl_info *pci = bank->pci; - int dir_reg, val, ret; - - if (offset / 16) { - dir_reg = bank->reg_base + GPIO_SWPORT_DDR_H; - offset -= 16; - } else { - dir_reg = bank->reg_base + GPIO_SWPORT_DDR_L; - } - - clk_enable(bank->clk); - ret = regmap_read(pci->regmap, dir_reg, &val); - if (ret) - dev_err(pci->dev, "%s: regmap read failed!\n", __func__); - clk_disable(bank->clk); - - val = BIT(offset) & val; - - return !val; -} - -static int rk628_gpio_to_irq(struct gpio_chip *gc, unsigned offset) -{ - struct rk628_pin_bank *bank = gpiochip_get_data(gc); - int virq; - - if (!bank->domain) - return -ENXIO; - - virq = irq_create_mapping(bank->domain, offset); - if (!virq) - pr_err("map interruptr fail, bank->irq=%d\n", bank->irq); - - return (virq) ? : -ENXIO; -} - -static struct gpio_chip rk628_gpiolib_chip = { - .label = "rk628-gpio", - .request = gpiochip_generic_request, - .free = gpiochip_generic_free, - .get_direction = rk628_gpio_get_direction, - .get = rk628_gpio_get, - .set = rk628_gpio_set, - .direction_input = rk628_gpio_direction_input, - .direction_output = rk628_gpio_direction_output, - .to_irq = rk628_gpio_to_irq, - .can_sleep = true, - .base = -1, - .owner = THIS_MODULE, -}; - -/* generic pinctrl */ -static int rk628_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - - return pci->num_groups; -} - -static const char *rk628_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - - return pci->groups[group].name; -} - -static int rk628_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - - *pins = pci->groups[group].pins; - *num_pins = pci->groups[group].npins; - - return 0; -} - -static const struct pinctrl_ops rk628_pinctrl_ops = { - .get_groups_count = rk628_pinctrl_get_groups_count, - .get_group_name = rk628_pinctrl_get_group_name, - .get_group_pins = rk628_pinctrl_get_group_pins, - .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, - .dt_free_map = pinctrl_utils_free_map, -}; - -static int rk628_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - - return pci->num_functions; -} - -static const char *rk628_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - - return pci->functions[function].name; -} - -static int rk628_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char *const **groups, - unsigned int *const num_groups) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - - *groups = pci->functions[function].groups; - *num_groups = pci->functions[function].ngroups; - - return 0; -} - -static int rk628_calc_mux_offset(struct rk628_pctrl_info *pci, int mux, int reg, int offset) -{ - int val = 0, orig; - - switch (reg) { - case GRF_SYSTEM_CON3: - regmap_read(pci->grf_regmap, reg, &orig); - if (mux) - val = BIT(offset) | orig; - else - val = ~BIT(offset) & orig; - break; - case GRF_GPIO0AB_SEL_CON: - if (offset >= 4 && offset < 8) { - offset += offset - 4; - val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0); - } else if (offset > 7) { - offset += 4; - val = BIT(offset + 16) | (mux ? BIT(offset) : 0); - } else { - val = BIT(offset + 16) | (mux ? BIT(offset) : 0); - } - break; - case GRF_GPIO1AB_SEL_CON: - if (offset == 13) - offset++; - if (offset > 11) - val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0); - else - val = BIT(offset + 16) | (mux ? BIT(offset) : 0); - break; - case GRF_GPIO2AB_SEL_CON: - val = BIT(offset + 16) | (mux ? BIT(offset) : 0); - break; - case GRF_GPIO2C_SEL_CON: - offset -= 16; - val = 0x3 << ((offset*2) + 16) | (mux ? BIT(offset*2) : 0); - break; - case GRF_GPIO3AB_SEL_CON: - if (offset > 11) - val = 0x3 << (offset + 16) | (mux ? BIT(offset) : 0); - else - val = BIT(offset + 16) | (mux ? BIT(offset) : 0); - break; - default: - break; - } - - return val; -} - -static int rk628_pinctrl_set_mux(struct pinctrl_dev *pctldev, - unsigned int func_selector, - unsigned int group_selector) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - int ret, val; - int mux = pci->functions[func_selector].mux_option; - int offset = pci->groups[group_selector].pins[0] % BANK_OFFSET; - int reg = pci->groups[group_selector].iomux_base; - - dev_dbg(pci->dev, "functions[%d]:%s mux=%s\n", - func_selector, pci->functions[func_selector].name, - mux ? "func" : "gpio"); - - val = rk628_calc_mux_offset(pci, mux, reg, offset); - - dev_dbg(pci->dev, "groups[%d]:%s pin-number=%d reg=0x%x write-val=0x%8x\n", - group_selector, - pci->groups[group_selector].name, - pci->groups[group_selector].pins[0], - reg, val); - - ret = regmap_write(pci->grf_regmap, reg, val); - if (ret) - dev_err(pci->dev, "%s regmap write failed!\n", __func__); - - return ret; -} - -static int rk628_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset, bool input) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - struct gpio_chip *chip; - struct rk628_pin_bank *bank; - int pin_offset, dir_reg, val, ret; - - chip = range->gc; - bank = gpiochip_get_data(chip); - pin_offset = offset - range->pin_base; - - if (pin_offset / 16) { - dir_reg = bank->reg_base + GPIO_SWPORT_DDR_H; - pin_offset -= 16; - } else { - dir_reg = bank->reg_base + GPIO_SWPORT_DDR_L; - } - if (input) - val = BIT(pin_offset + 16) | (0xffff & ~BIT(pin_offset)); - else - val = BIT(pin_offset + 16) | BIT(pin_offset); - - clk_enable(bank->clk); - ret = regmap_write(pci->regmap, dir_reg, val); - if (ret) - dev_err(pci->dev, "regmap update failed!\n"); - clk_disable(bank->clk); - - return 0; -} - -static const struct pinmux_ops rk628_pinmux_ops = { - .get_functions_count = rk628_pinctrl_get_funcs_count, - .get_function_name = rk628_pinctrl_get_func_name, - .get_function_groups = rk628_pinctrl_get_func_groups, - .set_mux = rk628_pinctrl_set_mux, - .gpio_set_direction = rk628_pmx_gpio_set_direction, -}; - -static int rk628_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - u32 arg = 0; - - pr_err("no support %s\n", __func__); - - switch (param) { - case PIN_CONFIG_OUTPUT: - break; - default: - dev_err(pci->dev, "Properties not supported\n"); - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, (u16)arg); - - return 0; -} - -static int rk628_set_slew_rate(struct rk628_pctrl_info *pci, int pin, int speed) -{ - int gpio = pin; - - /* gpio0b_sl(0-3) gpio1b_sl(0-3 -5) gpio3a_sl(4-7)*/ - char valid_gpio[] = { - 8, - 9, - 10, - 11, - 32 + 8, - 32 + 9, - 32 + 10, - 32 + 11, - 32 + 12, - 32 + 13, - -1, -1, - 96 + 4, - 96 + 5, - 96 + 6, - 96 + 7 - }; - - - int val, ret, offset = 0xff; - u32 i; - - for (i = 0; i < sizeof(valid_gpio); i++) { - if (gpio == valid_gpio[i]) { - offset = i; - break; - } - } - - if (offset == 0xff) { - dev_err(pci->dev, "pin%u don't support set slew rate\n", pin); - return -EINVAL; - } - - if (speed) - val = BIT(offset + 16) | BIT(offset); - else - val = BIT(offset + 16); - - dev_dbg(pci->dev, " offset=%d 0x%x\n", offset, val); - - ret = regmap_write(pci->grf_regmap, GRF_GPIO_SR_CON, val); - if (ret) - dev_err(pci->dev, "%s:regmap write failed! pin%u\n", - __func__, pin); - - return ret; -} - -static int rk628_calc_pull_reg_and_value(struct rk628_pctrl_info *pci, - int pin, - int pull, - int *reg, - int *val) -{ - struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin); - int gpio2_regs[] = { GRF_GPIO2A_P_CON, GRF_GPIO2B_P_CON, GRF_GPIO2C_P_CON }; - int gpio3_regs[] = { GRF_GPIO3A_P_CON, GRF_GPIO3B_P_CON }; - int valid_pinnum[] = { 8, 8, 24, 13 }; - int offset = pin - range->pin_base; - - switch (range->id) { - case 0: - if (pull == GPIO_PULL_UP) { - dev_err(pci->dev, "pin%u don't support pull up!\n", - pin); - return -EINVAL; - } - - if (offset == 2) { - dev_err(pci->dev, "pin%u don't support pull!\n", - pin); - return -EINVAL; - } - - if (offset < valid_pinnum[range->id]) { - *val = 0x3 << (2 * offset + 16) | pull << (2 * offset); - *reg = GRF_GPIO0A_P_CON; - dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n", - pin, *reg, *val); - return 0; - } - break; - case 1: - if (pull == GPIO_PULL_UP) { - dev_err(pci->dev, "pin%u don't support pull up!\n", - pin); - return -EINVAL; - } - - if (offset == 2) { - dev_err(pci->dev, "pin%u don't support pull!\n", - pin); - return -EINVAL; - } - - if (offset < valid_pinnum[range->id]) { - *val = 0x3 << (2 * offset + 16) | pull << (2 * offset); - *reg = GRF_GPIO1A_P_CON; - dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n", - pin, *reg, *val); - return 0; - } - break; - case 2: - if (pull == GPIO_PULL_UP) - pull = GPIO_PULL_DOWN; - else if (pull == GPIO_PULL_DOWN) - pull = GPIO_PULL_UP; - - if (offset < valid_pinnum[range->id]) { - *reg = gpio2_regs[offset / 8]; - offset = offset % 8; - *val = 0x3 << (2 * offset + 16) | pull << (2 * offset); - dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n", - pin, *reg, *val); - return 0; - } - break; - case 3: - if (pull == GPIO_PULL_UP && (offset == 2 || offset == 11 || offset == 12)) { - dev_err(pci->dev, "pin%u don't support pull up!\n", - pin); - return -EINVAL; - } else if (pull == GPIO_PULL_DOWN && (offset == 9 || offset == 10)) { - dev_err(pci->dev, "pin%u don't support pull down!\n", - pin); - return -EINVAL; - } - - if (offset == 0 || offset == 1 || offset == 3 || offset == 8) { - if (pull == GPIO_PULL_UP) - pull = GPIO_PULL_DOWN; - else if (pull == GPIO_PULL_DOWN) - pull = GPIO_PULL_UP; - } - - if ((offset > 7 && offset < valid_pinnum[range->id]) || offset < 4) { - *reg = gpio3_regs[offset / 8]; - offset = offset % 8; - *val = 0x3 << (2 * offset + 16) | pull << (2 * offset); - dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n", - pin, *reg, *val); - return 0; - } - break; - default: - break; - } - - return -EINVAL; -} - -static int rk628_calc_strength_reg_and_value(struct rk628_pctrl_info *pci, - int pin, - int strength, - int *reg, - int *val) -{ - struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin); - int valid_pinnum[] = { 8, 8, 24, 9 }; - int gpio_regs[][6] = { - { GRF_GPIO0B_D_CON - }, - { GRF_GPIO1B_D_CON - }, - { - GRF_GPIO2A_D0_CON, GRF_GPIO2A_D1_CON, - GRF_GPIO2B_D0_CON, GRF_GPIO2B_D1_CON, - GRF_GPIO2C_D0_CON, GRF_GPIO2C_D1_CON - }, - { - GRF_GPIO3A_D0_CON, GRF_GPIO3A_D1_CON, - GRF_GPIO3B_D_CON - } - }; - int offset = pin - range->pin_base; - - switch (range->id) { - case 0: - case 1: - if (offset < valid_pinnum[range->id]) { - dev_err(pci->dev, "pin%u don't support driver strength settings!\n", - pin); - return -EINVAL; - } - - offset -= valid_pinnum[range->id]; - - *val = 0x3 << (2 * offset + 16) | strength << (2 * offset); - *reg = gpio_regs[range->id][0]; - dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n", - pin, *reg, *val); - return 0; - case 2: - case 3: - if (offset < valid_pinnum[range->id]) { - *reg = gpio_regs[range->id][offset / 4]; - offset = offset % 4; - *val = 0x7 << (4 * offset + 16) | strength << (4 * offset); - dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n", - pin, *reg, *val); - return 0; - } - break; - default: - break; - } - - return -EINVAL; -} - -static int rk628_calc_schmitt_reg_and_value(struct rk628_pctrl_info *pci, - int pin, - int enable, - int *reg, - int *val) -{ - struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin); - int gpio2_regs[] = {GRF_GPIO2A_SMT, GRF_GPIO2B_SMT, GRF_GPIO2C_SMT}; - int gpio3_reg = GRF_GPIO3AB_SMT; - int valid_pinnum[] = { 0, 0, 24, 9 }; - int offset = pin - range->pin_base; - - switch (range->id) { - case 0: - case 1: - break; - case 2: - if (offset < valid_pinnum[range->id]) { - *reg = gpio2_regs[offset / 8]; - offset = offset % 8; - *val = BIT(offset + 16) | enable << (offset); - dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n", - pin, *reg, *val); - return 0; - } - break; - case 3: - if (offset == 0 || offset == 1 || offset == 3 || offset == 8) { - *reg = gpio3_reg; - *val = BIT(offset + 16) | enable << (offset); - dev_dbg(pci->dev, "pin%u reg=0x%8x val=0x%8x\n", - pin, *reg, *val); - return 0; - } - break; - default: - break; - } - - dev_err(pci->dev, "pin%u don't support schmitt settings!\n", - pin); - - return -ENOTSUPP; -} - -static int rk628_set_pull(struct rk628_pctrl_info *pci, int pin, int pull) -{ - int ret, reg, val; - - ret = rk628_calc_pull_reg_and_value(pci, pin, pull, ®, &val); - if (ret) { - dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin); - return ret; - } - - ret = regmap_write(pci->grf_regmap, reg, val); - - if (ret) - dev_err(pci->dev, "%s:regmap write failed! pin%u\n", - __func__, pin); - - return ret; -} - -static int rk628_set_drive_perpin(struct rk628_pctrl_info *pci, int pin, int strength) -{ - int ret, reg, val; - - ret = rk628_calc_strength_reg_and_value(pci, pin, strength, ®, &val); - if (ret) { - dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin); - return ret; - } - - ret = regmap_write(pci->grf_regmap, reg, val); - - if (ret) - dev_err(pci->dev, "%s:regmap write failed! pin%u\n", - __func__, pin); - - return ret; -} - -static int rk628_set_schmitt(struct rk628_pctrl_info *pci, int pin, int enable) -{ - int ret, reg, val; - - ret = rk628_calc_schmitt_reg_and_value(pci, pin, enable, ®, &val); - if (ret) { - dev_err(pci->dev, "pin%u can not find reg or not support!\n", pin); - return ret; - } - - ret = regmap_write(pci->grf_regmap, reg, val); - - if (ret) - dev_err(pci->dev, "%s:regmap write failed! pin%u\n", - __func__, pin); - - return ret; -} - -static int rk628_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned int num_configs) -{ - struct rk628_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param; - u32 i, arg = 0; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - switch (param) { - case PIN_CONFIG_DRIVE_STRENGTH: - rk628_set_drive_perpin(pci, pin, arg); - break; - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - rk628_set_pull(pci, pin, GPIO_HIGH_Z); - break; - case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: - dev_err(pci->dev, - "PIN_CONFIG_BIAS_PULL_PIN_DEFAULT not supported\n"); - break; - case PIN_CONFIG_BIAS_PULL_UP: - rk628_set_pull(pci, pin, GPIO_PULL_UP); - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - rk628_set_pull(pci, pin, GPIO_PULL_DOWN); - break; - case PIN_CONFIG_SLEW_RATE: - rk628_set_slew_rate(pci, pin, arg); - break; - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - rk628_set_schmitt(pci, pin, arg); - break; - case PIN_CONFIG_OUTPUT: - { - struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pci->pctl, pin); - - rk628_gpio_direction_output(range->gc, pin - range->pin_base, arg); - break; - } - default: - dev_err(pci->dev, "Properties not supported param=%d\n", param); - break; - } - } - - return 0; -} - -static const struct pinconf_ops rk628_pinconf_ops = { - .pin_config_get = rk628_pinconf_get, - .pin_config_set = rk628_pinconf_set, -}; - -static struct pinctrl_desc rk628_pinctrl_desc = { - .name = "rk628-pinctrl", - .pctlops = &rk628_pinctrl_ops, - .pmxops = &rk628_pinmux_ops, - .confops = &rk628_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int rk628_pinctrl_create_function(struct device *dev, - struct rk628_pctrl_info *pci, - struct device_node *func_np, - struct rk628_pin_function *func) -{ - int npins; - int ret; - int i; - char *func_sel[6] = { - "vop_dclk0", "i2sm0_input", "rxdcc_input0", "hdmirx_cec0", - "force_jtag_dis", "uart_iomux_dis", - }; - - if (of_property_read_string(func_np, "function", &func->name)) - return -1; - - func->mux_option = PINMUX_FUNC1; - /* for signals input select */ - for (i = 0; i < 6; i++) { - if (!strcmp(func_sel[i], func->name)) - func->mux_option = PINMUX_FUNC0; - } - - dev_dbg(dev, "%s func->name=%s\n", __func__, func->name); - npins = of_property_count_strings(func_np, "pins"); - if (npins < 1) { - dev_err(dev, "invalid pin list in %s node", func_np->name); - return -EINVAL; - } - - func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL); - if (!func->groups) - return -ENOMEM; - - for (i = 0; i < npins; ++i) { - const char *gname; - - ret = of_property_read_string_index(func_np, - "pins", i, &gname); - if (ret) { - dev_err(dev, - "failed to read pin name %d from %s node\n", - i, func_np->name); - return ret; - } - dev_dbg(dev, "%s func->groups[%d]=%s\n", __func__, i, gname); - - func->groups[i] = gname; - } - - func->ngroups = npins; - return 0; -} - -static int rk628_pinctrl_parse_gpiobank(struct device *dev, - struct rk628_pctrl_info *pci) -{ - struct device_node *dev_np = dev->of_node; - struct device_node *cfg_np; - struct rk628_pin_bank *bank; - u32 i, count = 0; - - for_each_child_of_node(dev_np, cfg_np) { - if (of_get_child_count(cfg_np)) - continue; - if (!of_find_property(cfg_np, "gpio-controller", NULL)) - continue; - bank = pci->pin_banks; - for (i = 0; i < pci->nr_banks; ++i, ++bank) { - if (strcmp(bank->name, cfg_np->name)) - continue; - bank->of_node = cfg_np; - count++; - bank->clk = devm_get_clk_from_child(dev, - bank->of_node, - "pclk"); - if (IS_ERR(bank->clk)) - return PTR_ERR(bank->clk); - clk_prepare(bank->clk); - break; - } - if (count == pci->nr_banks) - break; - } - - return 0; -} - -static struct rk628_pin_function * -rk628_pinctrl_create_functions(struct device *dev, - struct rk628_pctrl_info *pci, - unsigned int *cnt) -{ - struct rk628_pin_function *functions, *func; - struct device_node *dev_np = dev->of_node; - struct device_node *cfg_np; - unsigned int func_cnt = 0; - const char *func_name; - int ret; - - /* - * Iterate over all the child nodes of the pin controller node - * and create pin groups and pin function lists. - */ - for_each_child_of_node(dev_np, cfg_np) { - if (!of_get_child_count(cfg_np)) { - if (!of_find_property(cfg_np, "function", NULL)) - continue; - if (!of_property_read_string(cfg_np, - "function", &func_name)) { - if (!strncmp("gpio", func_name, 4)) - continue; - } - dev_dbg(dev, "%s: count=%d %s\n", - __func__, func_cnt, func_name); - ++func_cnt; - continue; - } - } - - ++func_cnt; - dev_dbg(dev, "total_count=%d, count %d for gpio function.\n", - func_cnt, func_cnt - 1); - functions = devm_kzalloc(dev, func_cnt * sizeof(*functions), - GFP_KERNEL); - if (!functions) - return ERR_PTR(-ENOMEM); - - func = functions; - - /* - * Iterate over all the child nodes of the pin controller node - * and create pin groups and pin function lists. - */ - func_cnt = 0; - for_each_child_of_node(dev_np, cfg_np) { - if (!of_get_child_count(cfg_np)) { - if (!of_property_read_string(cfg_np, - "function", &func_name)) { - if (!strncmp("gpio", func_name, 4)) - continue; - } - ret = rk628_pinctrl_create_function(dev, pci, - cfg_np, func); - if (!ret) { - ++func; - ++func_cnt; - } - continue; - } - } - - /* init gpio func */ - *(func) = rk628_functions[MUX_GPIO]; - func->mux_option = PINMUX_FUNC0; - - dev_dbg(dev, "count %d is for %s function\n", func_cnt, func->name); - ++func; - ++func_cnt; - *cnt = func_cnt; - return functions; -} - -static int rk628_pinctrl_parse_dt(struct platform_device *pdev, - struct rk628_pctrl_info *pci) -{ - struct device *dev = &pdev->dev; - struct rk628_pin_function *functions; - unsigned int func_cnt = 0; - int ret; - - ret = rk628_pinctrl_parse_gpiobank(dev, pci); - if (ret) - return ret; - - functions = rk628_pinctrl_create_functions(dev, pci, &func_cnt); - if (IS_ERR(functions)) { - dev_err(dev, "failed to parse pin functions\n"); - return PTR_ERR(functions); - } - - pci->functions = functions; - pci->num_functions = func_cnt; - return 0; -} - -static const struct regmap_range rk628_pinctrl_readable_ranges[] = { - regmap_reg_range(GPIO0_BASE, GPIO0_BASE + GPIO_VER_ID), - regmap_reg_range(GPIO1_BASE, GPIO1_BASE + GPIO_VER_ID), - regmap_reg_range(GPIO2_BASE, GPIO2_BASE + GPIO_VER_ID), - regmap_reg_range(GPIO3_BASE, GPIO3_BASE + GPIO_VER_ID), -}; - -static const struct regmap_access_table rk628_pinctrl_readable_table = { - .yes_ranges = rk628_pinctrl_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(rk628_pinctrl_readable_ranges), -}; - -static const struct regmap_config rk628_pinctrl_regmap_config = { - .name = "pinctrl", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = GPIO_MAX_REGISTER, - .reg_format_endian = REGMAP_ENDIAN_LITTLE, - .val_format_endian = REGMAP_ENDIAN_LITTLE, - .rd_table = &rk628_pinctrl_readable_table, -}; - -static void rk628_irq_enable(struct irq_data *d) -{ - struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d); - unsigned long hwirq = d->hwirq; - u32 offset; - - if (hwirq / 16) { - hwirq = hwirq - 16; - offset = GPIO_REG_HIGH; - } else { - offset = GPIO_REG_LOW; - } - - bank->mask_regs[offset] |= BIT(hwirq); -} - -static void rk628_irq_disable(struct irq_data *d) -{ - struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d); - unsigned long hwirq = d->hwirq; - u32 offset; - - if (hwirq / 16) { - hwirq = hwirq - 16; - offset = GPIO_REG_HIGH; - } else { - offset = GPIO_REG_LOW; - } - - bank->mask_regs[offset] &= ~BIT(hwirq); -} - -static int rk628_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d); - struct rk628_pctrl_info *pci = bank->pci; - unsigned long hwirq = d->hwirq; - u32 offset; - - if (hwirq / 16) { - hwirq = hwirq - 16; - offset = GPIO_REG_HIGH; - } else { - offset = GPIO_REG_LOW; - } - - switch (type) { - case IRQ_TYPE_EDGE_BOTH: - bank->bothedge_regs[offset] |= BIT(hwirq); - break; - case IRQ_TYPE_EDGE_RISING: - bank->bothedge_regs[offset] &= ~BIT(hwirq); - bank->level_regs[offset] |= BIT(hwirq); - bank->polarity_regs[offset] |= BIT(hwirq); - break; - case IRQ_TYPE_EDGE_FALLING: - bank->bothedge_regs[offset] &= ~BIT(hwirq); - bank->level_regs[offset] |= BIT(hwirq); - bank->polarity_regs[offset] &= ~BIT(hwirq); - break; - case IRQ_TYPE_LEVEL_HIGH: - bank->bothedge_regs[offset] &= ~BIT(hwirq); - bank->level_regs[offset] &= ~BIT(hwirq); - bank->polarity_regs[offset] |= BIT(hwirq); - break; - case IRQ_TYPE_LEVEL_LOW: - bank->bothedge_regs[offset] &= ~BIT(hwirq); - bank->level_regs[offset] &= ~BIT(hwirq); - bank->polarity_regs[offset] &= ~BIT(hwirq); - break; - default: - dev_err(pci->dev, "irq type invalid!\n"); - return -EINVAL; - } - - return 0; -} - -static void rk628_irq_lock(struct irq_data *d) -{ - struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d); - - mutex_lock(&bank->lock); - clk_enable(bank->clk); -} - -static void rk628_irq_sync_unlock(struct irq_data *d) -{ - struct rk628_pin_bank *bank = irq_data_get_irq_chip_data(d); - struct rk628_pctrl_info *pci = bank->pci; - int ret; - unsigned long hwirq = d->hwirq; - u32 offset, inten, level, polarity, bothedge; - - if (hwirq / 16) { - hwirq = hwirq - 16; - offset = GPIO_REG_HIGH; - } else { - offset = GPIO_REG_LOW; - } - - inten = (bank->reg_base + GPIO_INTEN_L + ((offset) * 4)); - level = (bank->reg_base + GPIO_INTTYPE_L + ((offset) * 4)); - polarity = (bank->reg_base + GPIO_INT_POLARITY_L + ((offset) * 4)); - bothedge = (bank->reg_base + GPIO_INT_BOTHEDGE_L + ((offset) * 4)); - - ret = regmap_write(pci->regmap, level, - bank->level_regs[offset] | BIT(hwirq + 16)); - if (ret) - dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n", - level, d->irq); - - ret = regmap_write(pci->regmap, polarity, - bank->polarity_regs[offset] | BIT(hwirq + 16)); - if (ret) - dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n", - polarity, d->irq); - - ret = regmap_write(pci->regmap, bothedge, - bank->bothedge_regs[offset] | BIT(hwirq + 16)); - if (ret) - dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n", - bothedge, d->irq); - - ret = regmap_write(pci->regmap, inten, - bank->mask_regs[offset] | BIT(hwirq + 16)); - if (ret) - dev_err(pci->dev, "regmap read failed! reg=0x%x irq=%d\n", - inten, d->irq); - - clk_disable(bank->clk); - mutex_unlock(&bank->lock); -} - -enum rk628_irqchip { - IRQCHIP_gpio0, - IRQCHIP_gpio1, - IRQCHIP_gpio2, - IRQCHIP_gpio3, -}; - -static const struct irq_chip rk628_irq_chip[] = { - IRQ_CHIP(gpio0), - IRQ_CHIP(gpio1), - IRQ_CHIP(gpio2), - IRQ_CHIP(gpio3), -}; - -static int rk628_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct rk628_pin_bank *bank = h->host_data; - - irq_set_chip_data(virq, bank); - irq_set_chip(virq, &bank->irq_chip); - irq_set_nested_thread(virq, 1); - irq_set_noprobe(virq); - - return 0; -} - -static const struct irq_domain_ops rk628_domain_ops = { - .map = rk628_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static irqreturn_t rk628_irq_demux_thread(int irq, void *d) -{ - struct rk628_pin_bank *bank = d; - struct rk628_pctrl_info *pci = bank->pci; - int ret; - u32 pend, low_bit, high_bit; - - clk_enable(bank->clk); - - ret = regmap_read(pci->regmap, bank->reg_base + GPIO_INT_STATUS, &pend); - if (ret) - dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__); - - low_bit = pend & 0x0000ffff; - high_bit = (pend >> 16); - ret = regmap_write(pci->regmap, bank->reg_base + GPIO_PORTS_EOI_L, - (low_bit << 16) | low_bit); - if (ret) - dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__); - - ret = regmap_write(pci->regmap, bank->reg_base + GPIO_PORTS_EOI_H, - (high_bit << 16) | high_bit); - if (ret) - dev_err(pci->dev, "regmap read failed! line=%d\n", __LINE__); - - while (pend) { - unsigned int irq, virq; - - irq = __ffs(pend); - pend &= ~BIT(irq); - virq = irq_linear_revmap(bank->domain, irq); - - if (!virq) { - dev_err(pci->dev, "unmapped irq %d\n", irq); - continue; - } - - handle_nested_irq(virq); - } - clk_disable(bank->clk); - - return IRQ_HANDLED; -} - -static int rk628_interrupts_register(struct platform_device *pdev, - struct rk628_pctrl_info *pci) -{ - struct rk628_pin_bank *bank = pci->pin_banks; - int ret; - u32 i; - - for (i = 0; i < pci->nr_banks; ++i, ++bank) { - mutex_init(&bank->lock); - ret = clk_enable(bank->clk); - if (ret) { - dev_err(&pdev->dev, "failed to enable clock for bank %s\n", - bank->name); - continue; - } - - bank->irq = platform_get_irq(pdev, i); - bank->irq_chip = rk628_irq_chip[i]; - bank->domain = irq_domain_add_linear(bank->of_node, - bank->nr_pins, - &rk628_domain_ops, - bank); - if (!bank->domain) { - dev_warn(&pdev->dev, - "could not initialize irq domain for bank %s\n", - bank->name); - clk_disable(bank->clk); - continue; - } - - ret = request_threaded_irq(bank->irq, NULL, - rk628_irq_demux_thread, - IRQF_ONESHOT, - bank->name, bank); - if (ret != 0) { - dev_err(&pdev->dev, - "Failed to request IRQ %d for %s: %d\n", - bank->irq, bank->name, ret); - } - - clk_disable(bank->clk); - } - - return 0; -} - -static int rk628_gpiolib_register(struct platform_device *pdev, - struct rk628_pctrl_info *pci) -{ - struct rk628_pin_bank *bank = pci->pin_banks; - struct gpio_chip *gc; - int ret = 0, i; - - for (i = 0; i < pci->nr_banks; ++i, ++bank) { - bank->gpio_chip = rk628_gpiolib_chip; - bank->pci = pci; - gc = &bank->gpio_chip; - gc->base = -1; - gc->ngpio = bank->nr_pins; - gc->parent = &pdev->dev; - gc->of_node = bank->of_node; - gc->label = bank->name; - - ret = devm_gpiochip_add_data(&pdev->dev, gc, bank); - if (ret) { - dev_err(&pdev->dev, - "failed to register gpio_chip %s, error code: %d\n", - gc->label, ret); - } - } - - return ret; -} - -static int rk628_pinctrl_probe(struct platform_device *pdev) -{ - struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent); - struct device *dev = &pdev->dev; - struct rk628_pctrl_info *pci; - int ret; - u32 bank; - struct rk628_pin_bank *pin_bank; - - pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL); - if (!pci) - return -ENOMEM; - - pci->dev = &pdev->dev; - pci->grf_regmap = rk628->grf; - - pci->pinctrl_desc = rk628_pinctrl_desc; - pci->groups = rk628_pin_groups; - pci->num_groups = ARRAY_SIZE(rk628_pin_groups); - pci->pinctrl_desc.pins = rk628_pins_desc; - pci->pinctrl_desc.npins = ARRAY_SIZE(rk628_pins_desc); - pci->pin_banks = rk628_pin_banks; - pci->nr_banks = ARRAY_SIZE(rk628_pin_banks), - - platform_set_drvdata(pdev, pci); - - ret = rk628_pinctrl_parse_dt(pdev, pci); - if (ret < 0) - return ret; - - pci->regmap = devm_regmap_init_i2c(rk628->client, - &rk628_pinctrl_regmap_config); - if (IS_ERR(pci->regmap)) { - ret = PTR_ERR(pci->regmap); - dev_err(dev, "failed to allocate register map: %d\n", ret); - return ret; - } - - /* Add gpiochip */ - ret = rk628_gpiolib_register(pdev, pci); - if (ret < 0) { - dev_err(&pdev->dev, "Couldn't add gpiochip\n"); - return ret; - } - - /* Add pinctrl */ - pci->pctl = devm_pinctrl_register(&pdev->dev, &pci->pinctrl_desc, pci); - if (IS_ERR(pci->pctl)) { - dev_err(&pdev->dev, "Couldn't add pinctrl\n"); - return PTR_ERR(pci->pctl); - } - - for (bank = 0; bank < pci->nr_banks; ++bank) { - pin_bank = &pci->pin_banks[bank]; - pin_bank->grange.name = pin_bank->name; - pin_bank->grange.id = bank; - pin_bank->grange.pin_base = BANK_OFFSET * bank; - pin_bank->grange.base = pin_bank->gpio_chip.base; - pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; - pin_bank->grange.gc = &pin_bank->gpio_chip; - pinctrl_add_gpio_range(pci->pctl, &pin_bank->grange); - } - - rk628_interrupts_register(pdev, pci); - - return 0; -} - -static const struct of_device_id rk628_pinctrl_dt_match[] = { - { .compatible = "rockchip,rk628-pinctrl" }, - {}, -}; - -MODULE_DEVICE_TABLE(of, rk628_pinctrl_dt_match); - -static struct platform_driver rk628_pinctrl_driver = { - .probe = rk628_pinctrl_probe, - .driver = { - .name = "rk628-pinctrl", - .of_match_table = of_match_ptr(rk628_pinctrl_dt_match), - }, -}; - -module_platform_driver(rk628_pinctrl_driver); - -MODULE_DESCRIPTION("RK628 pin control and GPIO driver"); -MODULE_AUTHOR("Weixin Zhou "); -MODULE_LICENSE("GPL v2"); From 79ea8d176f989e48c11f7f573055425a2462d6d8 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Sun, 21 Jan 2024 14:36:03 +0800 Subject: [PATCH 3/8] Revert "drm: rockchip: rk628: Add rk628 hdmirx driver" This reverts commit c0a543e874195bde7b1d40c1e4ef0a330a7d8b6f. Signed-off-by: Tao Huang Change-Id: I93343d1b4d9110b30c9b9e7010e41bedad6a597a --- drivers/gpu/drm/rockchip/rk628/Makefile | 3 +- drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c | 980 ------------------ include/linux/mfd/rk628.h | 6 - 3 files changed, 1 insertion(+), 988 deletions(-) delete mode 100755 drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c diff --git a/drivers/gpu/drm/rockchip/rk628/Makefile b/drivers/gpu/drm/rockchip/rk628/Makefile index 76d768d29776..ed2749412113 100644 --- a/drivers/gpu/drm/rockchip/rk628/Makefile +++ b/drivers/gpu/drm/rockchip/rk628/Makefile @@ -10,5 +10,4 @@ obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combrxphy.o \ rk628_lvds.o \ rk628_post_process.o \ rk628_rgb.o \ - rk628_hdmi.o \ - rk628_hdmirx.o + rk628_hdmi.o diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c b/drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c deleted file mode 100755 index 7ff3cc0087a1..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c +++ /dev/null @@ -1,980 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * - * Author: Algea Cao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define REG(x) ((x) + 0x30000) -#define HDMI_RX_HDMI_SETUP_CTRL REG(0x0000) -#define HOT_PLUG_DETECT_MASK BIT(0) -#define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0) -#define HDMI_RX_HDMI_OVR_CTRL REG(0x0004) -#define HDMI_RX_HDMI_TIMER_CTRL REG(0x0008) -#define HDMI_RX_HDMI_RES_OVR REG(0x0010) -#define HDMI_RX_HDMI_RES_STS REG(0x0014) -#define HDMI_RX_HDMI_PLL_CTRL REG(0x0018) -#define HDMI_RX_HDMI_PLL_FRQSET1 REG(0x001c) -#define HDMI_RX_HDMI_PLL_FRQSET2 REG(0x0020) -#define HDMI_RX_HDMI_PLL_PAR1 REG(0x0024) -#define HDMI_RX_HDMI_PLL_PAR2 REG(0x0028) -#define HDMI_RX_HDMI_PLL_PAR3 REG(0x002c) -#define HDMI_RX_HDMI_PLL_LCK_STS REG(0x0030) -#define HDMI_RX_HDMI_CLK_CTRL REG(0x0034) -#define HDMI_RX_HDMI_PCB_CTRL REG(0x0038) -#define SEL_PIXCLKSRC_MASK GENMASK(19, 18) -#define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18) -#define HDMI_RX_HDMI_PHS_CTR REG(0x0040) -#define HDMI_RX_HDMI_PHS_USED REG(0x0044) -#define HDMI_RX_HDMI_MISC_CTRL REG(0x0048) -#define HDMI_RX_HDMI_EQOFF_CTRL REG(0x004c) -#define HDMI_RX_HDMI_EQGAIN_CTRL REG(0x0050) -#define HDMI_RX_HDMI_EQCAL_STS REG(0x0054) -#define HDMI_RX_HDMI_EQRESULT REG(0x0058) -#define HDMI_RX_HDMI_EQ_MEAS_CTRL REG(0x005c) -#define HDMI_RX_HDMI_WR_CFG REG(0x0060) -#define HDMI_RX_HDMI_CTRL REG(0x0064) -#define HDMI_RX_HDMI_MODE_RECOVER REG(0x0080) -#define PREAMBLE_CNT_LIMIT_MASK GENMASK(31, 27) -#define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27) -#define OESSCTL3_THR_MASK GENMASK(20, 19) -#define OESSCTL3_THR(x) UPDATE(x, 20, 19) -#define SPIKE_FILTER_EN_MASK BIT(18) -#define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18) -#define DVI_MODE_HYST_MASK GENMASK(17, 13) -#define DVI_MODE_HYST(x) UPDATE(x, 17, 13) -#define HDMI_MODE_HYST_MASK GENMASK(12, 8) -#define HDMI_MODE_HYST(x) UPDATE(x, 12, 8) -#define HDMI_MODE_MASK GENMASK(7, 6) -#define HDMI_MODE(x) UPDATE(x, 7, 6) -#define GB_DET_MASK GENMASK(5, 4) -#define GB_DET(x) UPDATE(x, 5, 4) -#define EESS_OESS_MASK GENMASK(3, 2) -#define EESS_OESS(x) UPDATE(x, 3, 2) -#define SEL_CTL01_MASK GENMASK(1, 0) -#define SEL_CTL01(x) UPDATE(x, 1, 0) -#define HDMI_RX_HDMI_ERROR_PROTECT REG(0x0084) -#define RG_BLOCK_OFF_MASK BIT(20) -#define RG_BLOCK_OFF(x) UPDATE(x, 20, 20) -#define BLOCK_OFF_MASK BIT(19) -#define BLOCK_OFF(x) UPDATE(x, 19, 19) -#define VALID_MODE_MASK GENMASK(18, 16) -#define VALID_MODE(x) UPDATE(x, 18, 16) -#define CTRL_FILT_SEN_MASK GENMASK(13, 12) -#define CTRL_FILT_SEN(x) UPDATE(x, 13, 12) -#define VS_FILT_SENS_MASK GENMASK(11, 10) -#define VS_FILT_SENS(x) UPDATE(x, 11, 10) -#define HS_FILT_SENS_MASK GENMASK(9, 8) -#define HS_FILT_SENS(x) UPDATE(x, 9, 8) -#define DE_MEASURE_MODE_MASK GENMASK(7, 6) -#define DE_MEASURE_MODE(x) UPDATE(x, 7, 6) -#define DE_REGEN_MASK BIT(5) -#define DE_REGEN(x) UPDATE(x, 5, 5) -#define DE_FILTER_SENS_MASK GENMASK(4, 3) -#define DE_FILTER_SENS(x) UPDATE(x, 4, 3) -#define HDMI_RX_HDMI_ERD_STS REG(0x0088) -#define HDMI_RX_HDMI_SYNC_CTRL REG(0x0090) -#define VS_POL_ADJ_MODE_MASK GENMASK(4, 3) -#define VS_POL_ADJ_MODE(x) UPDATE(x, 4, 3) -#define HS_POL_ADJ_MODE_MASK GENMASK(2, 1) -#define HS_POL_ADJ_MODE(x) UPDATE(x, 2, 1) -#define HDMI_RX_HDMI_CKM_EVLTM REG(0x0094) -#define LOCK_HYST_MASK GENMASK(21, 20) -#define LOCK_HYST(x) UPDATE(x, 21, 20) -#define CLK_HYST_MASK GENMASK(18, 16) -#define CLK_HYST(x) UPDATE(x, 18, 16) -#define EVAL_TIME_MASK GENMASK(15, 4) -#define EVAL_TIME(x) UPDATE(x, 15, 4) -#define HDMI_RX_HDMI_CKM_F REG(0x0098) -#define HDMIRX_MAXFREQ_MASK GENMASK(31, 16) -#define HDMIRX_MAXFREQ(x) UPDATE(x, 31, 16) -#define MINFREQ_MASK GENMASK(15, 0) -#define MINFREQ(x) UPDATE(x, 15, 0) -#define HDMI_RX_HDMI_CKM_RESULT REG(0x009c) -#define HDMI_RX_HDMI_PVO_CONFIG REG(0x00a0) -#define HDMI_RX_HDMI_RESMPL_CTRL REG(0x00a4) -#define MAN_VID_DEREPEAT_MASK GENMASK(4, 1) -#define MAN_VID_DEREPEAT(x) UPDATE(x, 4, 1) -#define AUTO_DEREPEAT_MASK BIT(0) -#define AUTO_DEREPEAT(x) UPDATE(x, 0, 0) -#define HDMI_RX_HDMI_DCM_CTRL REG(0x00a8) -#define DCM_DEFAULT_PHASE_MASK BIT(18) -#define DCM_DEFAULT_PHASE(x) UPDATE(x, 18, 18) -#define DCM_COLOUR_DEPTH_SEL_MASK BIT(12) -#define DCM_COLOUR_DEPTH_SEL(x) UPDATE(x, 12, 12) -#define DCM_COLOUR_DEPTH_MASK GENMASK(11, 8) -#define DCM_COLOUR_DEPTH(x) UPDATE(x, 11, 8) -#define DCM_GCP_ZERO_FIELDS_MASK GENMASK(5, 2) -#define DCM_GCP_ZERO_FIELDS(x) UPDATE(x, 5, 2) -#define HDMI_RX_HDMI_VM_CFG_CH_0_1 REG(0x00b0) -#define HDMI_RX_HDMI_VM_CFG_CH2 REG(0x00b4) -#define HDMI_RX_HDMI_SPARE REG(0x00b8) -#define HDMI_RX_HDMI_STS REG(0x00bc) -#define HDMI_RX_HDCP_CTRL REG(0x00c0) -#define HDCP_ENABLE_MASK BIT(24) -#define HDCP_ENABLE(x) UPDATE(x, 24, 24) -#define FREEZE_HDCP_FSM_MASK BIT(21) -#define FREEZE_HDCP_FSM(x) UPDATE(x, 21, 21) -#define FREEZE_HDCP_STATE_MASK GENMASK(20, 15) -#define FREEZE_HDCP_STATE(x) UPDATE(x, 20, 15) -#define HDCP_CTL_MASK GENMASK(9, 8) -#define HDCP_CTL(x) UPDATE(x, 9, 8) -#define HDCP_RI_RATE_MASK GENMASK(7, 6) -#define HDCP_RI_RATE(x) UPDATE(x, 7, 6) -#define KEY_DECRYPT_ENABLE_MASK BIT(1) -#define KEY_DECRYPT_ENABLE(x) UPDATE(x, 1, 1) -#define HDCP_ENC_EN_MASK BIT(0) -#define HDCP_ENC_EN(x) UPDATE(x, 0, 0) -#define HDMI_RX_HDCP_SETTINGS REG(0x00c4) -#define HDMI_RX_HDCP_SEED REG(0x00c8) -#define HDMI_RX_HDCP_BKSV1 REG(0x00cc) -#define HDMI_RX_HDCP_BKSV0 REG(0x00d0) -#define HDMI_RX_HDCP_KIDX REG(0x00d4) -#define HDMI_RX_HDCP_KEY1 REG(0x00d8) -#define HDMI_RX_HDCP_KEY0 REG(0x00dc) -#define HDMI_RX_HDCP_DBG REG(0x00e0) -#define HDMI_RX_HDCP_AKSV1 REG(0x00e4) -#define HDMI_RX_HDCP_AKSV0 REG(0x00e8) -#define HDMI_RX_HDCP_AN1 REG(0x00ec) -#define HDMI_RX_HDCP_AN0 REG(0x00f0) -#define HDMI_RX_HDCP_EESS_WOO REG(0x00f4) -#define HDMI_RX_HDCP_I2C_TIMEOUT REG(0x00f8) -#define HDMI_RX_HDCP_STS REG(0x00fc) -#define HDMI_RX_MD_HCTRL1 REG(0x0140) -#define HACT_PIX_ITH_MASK GENMASK(10, 8) -#define HACT_PIX_ITH(x) UPDATE(x, 10, 8) -#define HACT_PIX_SRC_MASK BIT(5) -#define HACT_PIX_SRC(x) UPDATE(x, 5, 5) -#define HTOT_PIX_SRC_MASK BIT(4) -#define HTOT_PIX_SRC(x) UPDATE(x, 4, 4) -#define HDMI_RX_MD_HCTRL2 REG(0x0144) -#define HS_CLK_ITH_MASK GENMASK(14, 12) -#define HS_CLK_ITH(x) UPDATE(x, 14, 12) -#define HTOT32_CLK_ITH_MASK GENMASK(9, 8) -#define HTOT32_CLK_ITH(x) UPDATE(x, 9, 8) -#define VS_ACT_TIME_MASK BIT(5) -#define VS_ACT_TIME(x) UPDATE(x, 5, 5) -#define HS_ACT_TIME_MASK GENMASK(4, 3) -#define HS_ACT_TIME(x) UPDATE(x, 4, 3) -#define H_START_POS_MASK GENMASK(1, 0) -#define H_START_POS(x) UPDATE(x, 1, 0) -#define HDMI_RX_MD_HT0 REG(0x0148) -#define HDMI_RX_MD_HT1 REG(0x014c) -#define HDMI_RX_MD_HACT_PX REG(0x0150) -#define HDMI_RX_MD_HACT_RSV REG(0x0154) -#define HDMI_RX_MD_VCTRL REG(0x0158) -#define V_OFFS_LIN_MODE_MASK BIT(4) -#define V_OFFS_LIN_MODE(x) UPDATE(x, 4, 4) -#define V_EDGE_MASK BIT(1) -#define V_EDGE(x) UPDATE(x, 1, 1) -#define V_MODE_MASK BIT(0) -#define V_MODE(x) UPDATE(x, 0, 0) -#define HDMI_RX_MD_VSC REG(0x015c) -#define HDMI_RX_MD_VTC REG(0x0160) -#define HDMI_RX_MD_VOL REG(0x0164) -#define HDMI_RX_MD_VAL REG(0x0168) -#define HDMI_RX_MD_VTH REG(0x016c) -#define VOFS_LIN_ITH_MASK GENMASK(11, 10) -#define VOFS_LIN_ITH(x) UPDATE(x, 11, 10) -#define VACT_LIN_ITH_MASK GENMASK(9, 8) -#define VACT_LIN_ITH(x) UPDATE(x, 9, 8) -#define VTOT_LIN_ITH_MASK GENMASK(7, 6) -#define VTOT_LIN_ITH(x) UPDATE(x, 7, 6) -#define VS_CLK_ITH_MASK GENMASK(5, 3) -#define VS_CLK_ITH(x) UPDATE(x, 5, 3) -#define VTOT_CLK_ITH_MASK GENMASK(2, 0) -#define VTOT_CLK_ITH(x) UPDATE(x, 2, 0) -#define HDMI_RX_MD_VTL REG(0x0170) -#define HDMI_RX_MD_IL_CTRL REG(0x0174) -#define HDMI_RX_MD_IL_SKEW REG(0x0178) -#define HDMI_RX_MD_IL_POL REG(0x017c) -#define FAFIELDDET_EN_MASK BIT(2) -#define FAFIELDDET_EN(x) UPDATE(x, 2, 2) -#define FIELD_POL_MODE_MASK GENMASK(1, 0) -#define FIELD_POL_MODE(x) UPDATE(x, 1, 0) -#define HDMI_RX_MD_STS REG(0x0180) -#define HDMI_RX_AUD_CTRL REG(0x0200) -#define HDMI_RX_AUD_PLL_CTRL REG(0x0208) -#define PLL_LOCK_TOGGLE_DIV_MASK GENMASK(27, 24) -#define PLL_LOCK_TOGGLE_DIV(x) UPDATE(x, 27, 24) -#define HDMI_RX_AUD_CLK_CTRL REG(0x0214) -#define CTS_N_REF_MASK BIT(4) -#define CTS_N_REF(x) UPDATE(x, 4, 4) -#define HDMI_RX_AUD_CLK_STS REG(0x023c) -#define HDMI_RX_AUD_FIFO_CTRL REG(0x0240) -#define AFIF_SUBPACKET_DESEL_MASK GENMASK(27, 24) -#define AFIF_SUBPACKET_DESEL(x) UPDATE(x, 27, 24) -#define AFIF_SUBPACKETS_MASK BIT(16) -#define AFIF_SUBPACKETS(x) UPDATE(x, 16, 16) -#define MSA_CHANNEL_DESELECT BIT(24) -#define HDMI_RX_AUD_FIFO_TH REG(0x0244) -#define AFIF_TH_START_MASK GENMASK(26, 18) -#define AFIF_TH_START(x) UPDATE(x, 26, 18) -#define AFIF_TH_MAX_MASK GENMASK(17, 9) -#define AFIF_TH_MAX(x) UPDATE(x, 17, 9) -#define AFIF_TH_MIN_MASK GENMASK(8, 0) -#define AFIF_TH_MIN(x) UPDATE(x, 8, 0) -#define HDMI_RX_AUD_FIFO_FILL_S REG(0x0248) -#define HDMI_RX_AUD_FIFO_CLR_MM REG(0x024c) -#define HDMI_RX_AUD_FIFO_FILLSTS REG(0x0250) -#define HDMI_RX_AUD_CHEXTR_CTRL REG(0x0254) -#define AUD_LAYOUT_CTRL(x) UPDATE(x, 1, 0) -#define HDMI_RX_AUD_MUTE_CTRL REG(0x0258) -#define APPLY_INT_MUTE_MASK BIT(31) -#define APPLY_INT_MUTE(x) UPDATE(x, 31, 31) -#define APORT_SHDW_CTRL_MASK GENMASK(22, 21) -#define APORT_SHDW_CTRL(x) UPDATE(x, 22, 21) -#define AUTO_ACLK_MUTE_MASK GENMASK(20, 19) -#define AUTO_ACLK_MUTE(x) UPDATE(x, 20, 19) -#define AUD_MUTE_SPEED_MASK GENMASK(16, 10) -#define AUD_MUTE_SPEED(x) UPDATE(x, 16, 10) -#define AUD_AVMUTE_EN_MASK BIT(7) -#define AUD_AVMUTE_EN(x) UPDATE(x, 7, 7) -#define AUD_MUTE_SEL_MASK GENMASK(6, 5) -#define AUD_MUTE_SEL(x) UPDATE(x, 6, 5) -#define AUD_MUTE_MODE_MASK GENMASK(4, 3) -#define AUD_MUTE_MODE(x) UPDATE(x, 4, 3) -#define HDMI_RX_AUD_FIFO_FILLSTS1 REG(0x025c) -#define HDMI_RX_AUD_SAO_CTRL REG(0x0260) -#define I2S_LPCM_BPCUV_MASK BIT(11) -#define I2S_LPCM_BPCUV(x) UPDATE(x, 11, 11) -#define I2S_32_16_MASK BIT(0) -#define I2S_32_16(x) UPDATE(x, 0, 0) -#define HDMI_RX_AUD_PAO_CTRL REG(0x0264) -#define PAO_RATE_MASK GENMASK(17, 16) -#define PAO_RATE(x) UPDATE(x, 17, 16) -#define HDMI_RX_AUD_SPARE REG(0x0268) -#define HDMI_RX_AUD_FIFO_STS REG(0x027c) -#define HDMI_RX_AUDPLL_GEN_CTS REG(0x0280) -#define AUDPLL_CTS_MANUAL(x) UPDATE(x, 19, 0) -#define HDMI_RX_AUDPLL_GEN_N REG(0x0284) -#define AUDPLL_N_MANUAL(x) UPDATE(x, 19, 0) -#define HDMI_RX_AUDPLL_GEN_CTRL_RW1 REG(0x0288) -#define HDMI_RX_AUDPLL_GEN_CTRL_RW2 REG(0x028c) -#define HDMI_RX_AUDPLL_GEN_CTRL_W1 REG(0x0298) -#define HDMI_RX_AUDPLL_GEN_STS_RO1 REG(0x02a0) -#define HDMI_RX_AUDPLL_GEN_STS_RO2 REG(0x02a4) -#define HDMI_RX_AUDPLL_SC_NDIVCTSTH REG(0x02a8) -#define HDMI_RX_AUDPLL_SC_CTS REG(0x02ac) -#define HDMI_RX_AUDPLL_SC_N REG(0x02b0) -#define HDMI_RX_AUDPLL_SC_CTRL REG(0x02b4) -#define HDMI_RX_AUDPLL_SC_STS1 REG(0x02b8) -#define HDMI_RX_AUDPLL_SC_STS2 REG(0x02bc) -#define HDMI_RX_SNPS_PHYG3_CTRL REG(0x02c0) -#define PORTSELECT_MASK GENMASK(3, 2) -#define PORTSELECT(x) UPDATE(x, 3, 2) -#define HDMI_RX_I2CM_PHYG3_SLAVE REG(0x02c4) -#define HDMI_RX_I2CM_PHYG3_ADDRESS REG(0x02c8) -#define HDMI_RX_I2CM_PHYG3_DATAO REG(0x02cc) -#define HDMI_RX_I2CM_PHYG3_DATAI REG(0x02d0) -#define HDMI_RX_I2CM_PHYG3_OPERATION REG(0x02d4) -#define HDMI_RX_I2CM_PHYG3_MODE REG(0x02d8) -#define HDMI_RX_I2CM_PHYG3_SOFTRST REG(0x02dc) -#define HDMI_RX_I2CM_PHYG3_SS_CNTS REG(0x02e0) -#define HDMI_RX_I2CM_PHYG3_FS_HCNT REG(0x02e4) -#define HDMI_RX_JTAG_CONF REG(0x02ec) -#define HDMI_RX_JTAG_TAP_TCLK REG(0x02f0) -#define HDMI_RX_JTAG_TAP_IN REG(0x02f4) -#define HDMI_RX_JTAG_TAP_OUT REG(0x02f8) -#define HDMI_RX_JTAG_ADDR REG(0x02fc) -#define HDMI_RX_PDEC_CTRL REG(0x0300) -#define PFIFO_SCORE_FILTER_EN BIT(31) -#define PFIFO_SCORE_HDP_IF BIT(29) -#define PFIFO_SCORE_AMP_IF BIT(28) -#define PFIFO_SCORE_NTSCVBI_IF BIT(27) -#define PFIFO_SCORE_MPEGS_IF BIT(26) -#define PFIFO_SCORE_AUD_IF BIT(25) -#define PFIFO_SCORE_SPD_IF BIT(24) -#define PFIFO_SCORE_AVI_IF BIT(23) -#define PFIFO_SCORE_VS_IF BIT(22) -#define PFIFO_SCORE_GMTP BIT(21) -#define PFIFO_SCORE_ISRC2 BIT(20) -#define PFIFO_SCORE_ISRC1 BIT(19) -#define PFIFO_SCORE_ACP BIT(18) -#define PFIFO_SCORE_GCP BIT(17) -#define PFIFO_SCORE_ACR BIT(16) -#define GCP_GLOBAVMUTE BIT(15) -#define PD_FIFO_WE BIT(4) -#define PDEC_BCH_EN BIT(0) -#define HDMI_RX_PDEC_FIFO_CFG REG(0x0304) -#define PD_FIFO_TH_START_MASK GENMASK(29, 20) -#define PD_FIFO_TH_START(x) UPDATE(x, 29, 20) -#define PD_FIFO_TH_MAX_MASK GENMASK(19, 10) -#define PD_FIFO_TH_MAX(x) UPDATE(x, 19, 10) -#define PD_FIFO_TH_MIN_MASK GENMASK(9, 0) -#define PD_FIFO_TH_MIN(x) UPDATE(x, 9, 0) -#define HDMI_RX_PDEC_FIFO_STS REG(0x0308) -#define HDMI_RX_PDEC_FIFO_DATA REG(0x030c) -#define HDMI_RX_PDEC_AUDIODET_CTRL REG(0x0310) -#define AUDIODET_THRESHOLD_MASK GENMASK(13, 9) -#define AUDIODET_THRESHOLD(x) UPDATE(x, 13, 9) -#define HDMI_RX_PDEC_DBG_ACP REG(0x031c) -#define HDMI_RX_PDEC_DBG_ERR_CORR REG(0x0320) -#define HDMI_RX_PDEC_FIFO_STS1 REG(0x0324) -#define HDMI_RX_PDEC_ACRM_CTRL REG(0x0330) -#define DELTACTS_IRQTRIG_MASK GENMASK(4, 2) -#define DELTACTS_IRQTRIG(x) UPDATE(x, 4, 2) -#define HDMI_RX_PDEC_ACRM_MAX REG(0x0334) -#define HDMI_RX_PDEC_ACRM_MIN REG(0x0338) -#define HDMI_RX_PDEC_ERR_FILTER REG(0x033c) -#define HDMI_RX_PDEC_ASP_CTRL REG(0x0340) -#define HDMI_RX_PDEC_ASP_ERR REG(0x0344) -#define HDMI_RX_PDEC_STS REG(0x0360) -#define HDMI_RX_PDEC_AUD_STS REG(0x0364) -#define HDMI_RX_PDEC_VSI_PAYLOAD0 REG(0x0368) -#define HDMI_RX_PDEC_VSI_PAYLOAD1 REG(0x036c) -#define HDMI_RX_PDEC_VSI_PAYLOAD2 REG(0x0370) -#define HDMI_RX_PDEC_VSI_PAYLOAD3 REG(0x0374) -#define HDMI_RX_PDEC_VSI_PAYLOAD4 REG(0x0378) -#define HDMI_RX_PDEC_VSI_PAYLOAD5 REG(0x037c) -#define HDMI_RX_PDEC_GCP_AVMUTE REG(0x0380) -#define PKTDEC_GCP_CD_MASK GENMASK(7, 4) -#define HDMI_RX_PDEC_ACR_CTS REG(0x0390) -#define HDMI_RX_PDEC_ACR_N REG(0x0394) -#define HDMI_RX_PDEC_AVI_HB REG(0x03a0) -#define HDMI_RX_PDEC_AVI_PB REG(0x03a4) -#define VID_IDENT_CODE_VIC7 BIT(31) -#define VID_IDENT_CODE GENMASK(30, 24) -#define VIDEO_FORMAT GENMASK(6, 5) -#define HDMI_RX_PDEC_AVI_TBB REG(0x03a8) -#define HDMI_RX_PDEC_AVI_LRB REG(0x03ac) -#define HDMI_RX_PDEC_AIF_CTRL REG(0x03c0) -#define FC_LFE_EXCHG BIT(18) -#define HDMI_RX_PDEC_AIF_HB REG(0x03c4) -#define HDMI_RX_PDEC_AIF_PB0 REG(0x03c8) -#define HDMI_RX_PDEC_AIF_PB1 REG(0x03cc) -#define HDMI_RX_PDEC_GMD_HB REG(0x03d0) -#define HDMI_RX_PDEC_GMD_PB REG(0x03d4) -#define HDMI_RX_PDEC_VSI_ST0 REG(0x03e0) -#define HDMI_RX_PDEC_VSI_ST1 REG(0x03e4) -#define HDMI_RX_PDEC_VSI_PB0 REG(0x03e8) -#define HDMI_RX_PDEC_VSI_PB1 REG(0x03ec) -#define HDMI_RX_PDEC_VSI_PB2 REG(0x03f0) -#define HDMI_RX_PDEC_VSI_PB3 REG(0x03f4) -#define HDMI_RX_PDEC_VSI_PB4 REG(0x03f8) -#define HDMI_RX_PDEC_VSI_PB5 REG(0x03fc) -#define HDMI_RX_CEAVID_CONFIG REG(0x0400) -#define HDMI_RX_CEAVID_3DCONFIG REG(0x0404) -#define HDMI_RX_CEAVID_HCONFIG_LO REG(0x0408) -#define HDMI_RX_CEAVID_HCONFIG_HI REG(0x040c) -#define HDMI_RX_CEAVID_VCONFIG_LO REG(0x0410) -#define HDMI_RX_CEAVID_VCONFIG_HI REG(0x0414) -#define HDMI_RX_CEAVID_STATUS REG(0x0418) -#define HDMI_RX_PDEC_AMP_HB REG(0x0480) -#define HDMI_RX_PDEC_AMP_PAYLOAD0 REG(0x0484) -#define HDMI_RX_PDEC_AMP_PAYLOAD1 REG(0x0488) -#define HDMI_RX_PDEC_AMP_PAYLOAD2 REG(0x048c) -#define HDMI_RX_PDEC_AMP_PAYLOAD3 REG(0x0490) -#define HDMI_RX_PDEC_AMP_PAYLOAD4 REG(0x0494) -#define HDMI_RX_PDEC_AMP_PAYLOAD5 REG(0x0498) -#define HDMI_RX_PDEC_AMP_PAYLOAD6 REG(0x049c) -#define HDMI_RX_PDEC_NTSCVBI_HB REG(0x04a0) -#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD0 REG(0x04a4) -#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD1 REG(0x04a8) -#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD2 REG(0x04ac) -#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD3 REG(0x04b0) -#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD4 REG(0x04b4) -#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD5 REG(0x04b8) -#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD6 REG(0x04bc) -#define HDMI_RX_PDEC_DRM_HB REG(0x04c0) -#define HDMI_RX_PDEC_DRM_PAYLOAD0 REG(0x04c4) -#define HDMI_RX_PDEC_DRM_PAYLOAD1 REG(0x04c8) -#define HDMI_RX_PDEC_DRM_PAYLOAD2 REG(0x04cc) -#define HDMI_RX_PDEC_DRM_PAYLOAD3 REG(0x04d0) -#define HDMI_RX_PDEC_DRM_PAYLOAD4 REG(0x04d4) -#define HDMI_RX_PDEC_DRM_PAYLOAD5 REG(0x04d8) -#define HDMI_RX_PDEC_DRM_PAYLOAD6 REG(0x04dc) -#define HDMI_RX_MHLMODE_CTRL REG(0x0500) -#define HDMI_RX_CDSENSE_STATUS REG(0x0504) -#define HDMI_RX_DESERFIFO_CTRL REG(0x0508) -#define HDMI_RX_DESER_INTTRSHCTRL REG(0x050c) -#define HDMI_RX_DESER_INTCNTCTRL REG(0x0510) -#define HDMI_RX_DESER_INTCNT REG(0x0514) -#define HDMI_RX_HDCP_RPT_CTRL REG(0x0600) -#define HDMI_RX_HDCP_RPT_BSTATUS REG(0x0604) -#define HDMI_RX_HDCP_RPT_KSVFIFO_CTRL REG(0x0608) -#define HDMI_RX_HDCP_RPT_KSVFIFO1 REG(0x060c) -#define HDMI_RX_HDCP_RPT_KSVFIFO0 REG(0x0610) -#define HDMI_RX_HDMI20_CONTROL REG(0x0800) -#define HDMI_RX_SCDC_I2CCONFIG REG(0x0804) -#define I2CSPIKESUPPR_MASK GENMASK(25, 24) -#define I2CSPIKESUPPR(x) UPDATE(x, 25, 24) -#define HDMI_RX_SCDC_CONFIG REG(0x0808) -#define HDMI_RX_CHLOCK_CONFIG REG(0x080c) -#define CHLOCKMAXER_MASK GENMASK(29, 20) -#define CHLOCKMAXER(x) UPDATE(x, 29, 20) -#define MILISECTIMERLIMIT_MASK GENMASK(15, 0) -#define MILISECTIMERLIMIT(x) UPDATE(x, 15, 0) -#define HDMI_RX_HDCP22_CONTROL REG(0x081c) -#define HDMI_RX_SCDC_REGS0 REG(0x0820) -#define HDMI_RX_SCDC_REGS1 REG(0x0824) -#define HDMI_RX_SCDC_REGS2 REG(0x0828) -#define HDMI_RX_SCDC_REGS3 REG(0x082c) -#define HDMI_RX_SCDC_MANSPEC0 REG(0x0840) -#define HDMI_RX_SCDC_MANSPEC1 REG(0x0844) -#define HDMI_RX_SCDC_MANSPEC2 REG(0x0848) -#define HDMI_RX_SCDC_MANSPEC3 REG(0x084c) -#define HDMI_RX_SCDC_MANSPEC4 REG(0x0850) -#define HDMI_RX_SCDC_WRDATA0 REG(0x0860) -#define MANUFACTUREROUI_MASK GENMASK(31, 8) -#define MANUFACTUREROUI(x) UPDATE(x, 31, 8) -#define SINKVERSION_MASK GENMASK(7, 0) -#define SINKVERSION(x) UPDATE(x, 7, 0) -#define HDMI_RX_SCDC_WRDATA1 REG(0x0864) -#define HDMI_RX_SCDC_WRDATA2 REG(0x0868) -#define HDMI_RX_SCDC_WRDATA3 REG(0x086c) -#define HDMI_RX_SCDC_WRDATA4 REG(0x0870) -#define HDMI_RX_SCDC_WRDATA5 REG(0x0874) -#define HDMI_RX_SCDC_WRDATA6 REG(0x0878) -#define HDMI_RX_SCDC_WRDATA7 REG(0x087c) -#define HDMI_RX_HDMI20_STATUS REG(0x08e0) -#define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_IN REG(0x08e8) -#define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_OUT REG(0x08ec) -#define HDMI_RX_HDCP2_ESM_P0_GPIO_IN REG(0x08f0) -#define HDMI_RX_HDCP2_ESM_P0_GPIO_OUT REG(0x08f4) -#define HDMI_RX_HDCP22_STATUS REG(0x08fc) -#define HDMI_RX_HDMI2_IEN_CLR REG(0x0f60) -#define HDMI_RX_HDMI2_IEN_SET REG(0x0f64) -#define HDMI_RX_HDMI2_ISTS REG(0x0f68) -#define HDMI_RX_HDMI2_IEN REG(0x0f6c) -#define HDMI_RX_HDMI2_ICLR REG(0x0f70) -#define HDMI_RX_HDMI2_ISET REG(0x0f74) -#define HDMI_RX_PDEC_IEN_CLR REG(0x0f78) -#define HDMI_RX_PDEC_IEN_SET REG(0x0f7c) -#define HDMI_RX_PDEC_ISTS REG(0x0f80) -#define HDMI_RX_PDEC_IEN REG(0x0f84) -#define HDMI_RX_PDEC_ICLR REG(0x0f88) -#define HDMI_RX_PDEC_ISET REG(0x0f8c) -#define HDMI_RX_AUD_CEC_IEN_CLR REG(0x0f90) -#define HDMI_RX_AUD_CEC_IEN_SET REG(0x0f94) -#define HDMI_RX_AUD_CEC_ISTS REG(0x0f98) -#define HDMI_RX_AUD_CEC_IEN REG(0x0f9c) -#define HDMI_RX_AUD_CEC_ICLR REG(0x0fa0) -#define HDMI_RX_AUD_CEC_ISET REG(0x0fa4) -#define HDMI_RX_AUD_FIFO_IEN_CLR REG(0x0fa8) -#define HDMI_RX_AUD_FIFO_IEN_SET REG(0x0fac) -#define HDMI_RX_AUD_FIFO_ISTS REG(0x0fb0) -#define HDMI_RX_AUD_FIFO_IEN REG(0x0fb4) -#define HDMI_RX_AUD_FIFO_ICLR REG(0x0fb8) -#define HDMI_RX_AUD_FIFO_ISET REG(0x0fbc) -#define HDMI_RX_MD_IEN_CLR REG(0x0fc0) -#define HDMI_RX_MD_IEN_SET REG(0x0fc4) -#define HDMI_RX_MD_ISTS REG(0x0fc8) -#define HDMI_RX_MD_IEN REG(0x0fcc) -#define HDMI_RX_MD_ICLR REG(0x0fd0) -#define HDMI_RX_MD_ISET REG(0x0fd4) -#define HDMI_RX_HDMI_IEN_CLR REG(0x0fd8) -#define HDMI_RX_HDMI_IEN_SET REG(0x0fdc) -#define HDCP_DKSET_DONE_ENCLR_MASK BIT(31) -#define HDCP_DKSET_DONE_ENCLR(x) UPDATE(x, 31, 31) -#define HDMI_RX_HDMI_ISTS REG(0x0fe0) -#define HDMI_RX_HDMI_IEN REG(0x0fe4) -#define HDMI_RX_HDMI_ICLR REG(0x0fe8) -#define HDMI_RX_HDMI_ISET REG(0x0fec) -#define HDMI_RX_DMI_SW_RST REG(0x0ff0) -#define HDMI_RX_DMI_DISABLE_IF REG(0x0ff4) -#define MAIN_ENABLE BIT(0) -#define MODET_ENABLE BIT(1) -#define HDMI_ENABLE BIT(2) -#define BUS_ENABLE BIT(3) -#define AUD_ENABLE BIT(4) -#define CEC_ENABLE BIT(5) -#define PIXEL_ENABLE BIT(6) -#define VID_ENABLE BIT(7) -#define TMDS_ENABLE_MASK BIT(16) -#define TMDS_ENABLE(x) UPDATE(x, 16, 16) -#define HDMI_RX_DMI_MODULE_ID_EXT REG(0x0ff8) -#define HDMI_RX_DMI_MODULE_ID REG(0x0ffc) -#define HDMI_RX_CEC_CTRL REG(0x1f00) -#define HDMI_RX_CEC_MASK REG(0x1f08) -#define HDMI_RX_CEC_ADDR_L REG(0x1f14) -#define HDMI_RX_CEC_ADDR_H REG(0x1f18) -#define HDMI_RX_CEC_TX_CNT REG(0x1f1c) -#define HDMI_RX_CEC_RX_CNT REG(0x1f20) -#define HDMI_RX_CEC_TX_DATA_0 REG(0x1f40) -#define HDMI_RX_CEC_TX_DATA_1 REG(0x1f44) -#define HDMI_RX_CEC_TX_DATA_2 REG(0x1f48) -#define HDMI_RX_CEC_TX_DATA_3 REG(0x1f4c) -#define HDMI_RX_CEC_TX_DATA_4 REG(0x1f50) -#define HDMI_RX_CEC_TX_DATA_5 REG(0x1f54) -#define HDMI_RX_CEC_TX_DATA_6 REG(0x1f58) -#define HDMI_RX_CEC_TX_DATA_7 REG(0x1f5c) -#define HDMI_RX_CEC_TX_DATA_8 REG(0x1f60) -#define HDMI_RX_CEC_TX_DATA_9 REG(0x1f64) -#define HDMI_RX_CEC_TX_DATA_10 REG(0x1f68) -#define HDMI_RX_CEC_TX_DATA_11 REG(0x1f6c) -#define HDMI_RX_CEC_TX_DATA_12 REG(0x1f70) -#define HDMI_RX_CEC_TX_DATA_13 REG(0x1f74) -#define HDMI_RX_CEC_TX_DATA_14 REG(0x1f78) -#define HDMI_RX_CEC_TX_DATA_15 REG(0x1f7c) -#define HDMI_RX_CEC_RX_DATA_0 REG(0x1f80) -#define HDMI_RX_CEC_RX_DATA_1 REG(0x1f84) -#define HDMI_RX_CEC_RX_DATA_2 REG(0x1f88) -#define HDMI_RX_CEC_RX_DATA_3 REG(0x1f8c) -#define HDMI_RX_CEC_RX_DATA_4 REG(0x1f90) -#define HDMI_RX_CEC_RX_DATA_5 REG(0x1f94) -#define HDMI_RX_CEC_RX_DATA_6 REG(0x1f98) -#define HDMI_RX_CEC_RX_DATA_7 REG(0x1f9c) -#define HDMI_RX_CEC_RX_DATA_8 REG(0x1fa0) -#define HDMI_RX_CEC_RX_DATA_9 REG(0x1fa4) -#define HDMI_RX_CEC_RX_DATA_10 REG(0x1fa8) -#define HDMI_RX_CEC_RX_DATA_11 REG(0x1fac) -#define HDMI_RX_CEC_RX_DATA_12 REG(0x1fb0) -#define HDMI_RX_CEC_RX_DATA_13 REG(0x1fb4) -#define HDMI_RX_CEC_RX_DATA_14 REG(0x1fb8) -#define HDMI_RX_CEC_RX_DATA_15 REG(0x1fbc) -#define HDMI_RX_CEC_LOCK REG(0x1fc0) -#define HDMI_RX_CEC_WAKEUPCTRL REG(0x1fc4) -#define HDMI_RX_CBUSSWRESETREQ REG(0x3000) -#define HDMI_RX_CBUSENABLEIF REG(0x3004) -#define HDMI_RX_CB_LOCKONCLOCK_STS REG(0x3010) -#define HDMI_RX_CB_LOCKONCLOCKCLR REG(0x3014) -#define HDMI_RX_CBUSIOCTRL REG(0x3020) -#define HDMI_RX_DD_CTRL REG(0x3040) -#define HDMI_RX_DD_OP_CTRL REG(0x3044) -#define HDMI_RX_DD_STS REG(0x3048) -#define HDMI_RX_DD_BYPASS_EN REG(0x304c) -#define HDMI_RX_DD_BYPASS_CTRL REG(0x3050) -#define HDMI_RX_DD_BYPASS_CBUS REG(0x3054) -#define HDMI_RX_LL_TXPCKFIFO REG(0x3080) -#define HDMI_RX_LL_RXPCKFIFO_RD_CLR REG(0x3084) -#define HDMI_RX_LL_RXPCKFIFO_A REG(0x3088) -#define HDMI_RX_LL_RXPCKFIFO_B REG(0x308c) -#define HDMI_RX_LL_TXPCKCTRL_0 REG(0x3090) -#define HDMI_RX_LL_TXPCKCTRL_1 REG(0x3094) -#define HDMI_RX_LL_PCKFIFO_STS REG(0x309c) -#define HDMI_RX_LL_RXPCKCTRL_0 REG(0x30a0) -#define HDMI_RX_LL_RXPCKCTRL_1 REG(0x30a4) -#define HDMI_RX_LL_INTTRSHLDCTRL REG(0x30b0) -#define HDMI_RX_LL_INTCNTCTRL REG(0x30b4) -#define HDMI_RX_LL_INTCNT_0 REG(0x30b8) -#define HDMI_RX_LL_INTCNT_1 REG(0x30bc) -#define HDMI_RX_CBHDCP_OPCTRL REG(0x3100) -#define HDMI_RX_CBHDCP_WDATA_0 REG(0x3104) -#define HDMI_RX_CBHDCP_WDATA_1 REG(0x3108) -#define HDMI_RX_CBHDCP_RDATA_0 REG(0x310c) -#define HDMI_RX_CBHDCP_RDATA_1 REG(0x3110) -#define HDMI_RX_CBHDCP_STATUS REG(0x3114) -#define HDMI_RX_CBHDCP_DDC_REPORT REG(0x3118) -#define HDMI_RX_ISTAT_CB_DD REG(0x3200) -#define HDMI_RX_IMASK_CB_DD REG(0x3204) -#define HDMI_RX_IFORCE_CB_DD REG(0x3208) -#define HDMI_RX_ICLEAR_CB_DD REG(0x320c) -#define HDMI_RX_IMUTE_CB_DD REG(0x3210) -#define HDMI_RX_ISTAT_CB_LL REG(0x3220) -#define HDMI_RX_IMASK_CB_LL REG(0x3224) -#define HDMI_RX_IFORCE_CB_LL REG(0x3228) -#define HDMI_RX_ICLEAR_CB_LL REG(0x322c) -#define HDMI_RX_IMUTE_CB_LL REG(0x3230) -#define HDMI_RX_ISTAT_CB_HDCP REG(0x3240) -#define HDMI_RX_IMASK_CB_HDCP REG(0x3244) -#define HDMI_RX_IFORCE_CB_HDCP REG(0x3248) -#define HDMI_RX_ICLEAR_CB_HDCP REG(0x324c) -#define HDMI_RX_IMUTE_CB_HDCP REG(0x3250) -#define HDMI_RX_ISTAT_CB_MCTRL REG(0x3260) -#define HDMI_RX_IMASK_CB_MCTRL REG(0x3264) -#define HDMI_RX_IFORCE_CB_MCTRL REG(0x3268) -#define HDMI_RX_ICLEAR_CB_MCTRL REG(0x326c) -#define HDMI_RX_IMUTE_CB_MCTRL REG(0x3270) -#define HDMI_RX_IMASTER_MUTE_CB REG(0x32e0) -#define HDMI_RX_IVECTOR_INDEX_CB REG(0x32e4) -#define HDMI_RX_MAX_REGISTER HDMI_RX_IVECTOR_INDEX_CB - -struct rk628_hdmirx { - struct drm_bridge base; - struct drm_bridge *bridge; - struct device *dev; - struct regmap *regmap; - struct regmap *grf; - struct phy *phy; - struct clk *pclk; - struct clk *cec_clk; - struct clk *aud_clk; - struct clk *imodet_clk; - struct reset_control *hdmirx; - struct reset_control *hdmirx_pon; - struct rk628 *parent; - struct drm_display_mode mode; -}; - -static const struct regmap_range rk628_hdmirx_readable_ranges[] = { - regmap_reg_range(HDMI_RX_HDMI_SETUP_CTRL, HDMI_RX_HDMI_TIMER_CTRL), - regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERD_STS), - regmap_reg_range(HDMI_RX_MD_HCTRL1, HDMI_RX_MD_STS), - regmap_reg_range(HDMI_RX_PDEC_ACRM_CTRL, HDMI_RX_PDEC_ASP_ERR), - regmap_reg_range(HDMI_RX_PDEC_AVI_HB, HDMI_RX_PDEC_AVI_LRB), - regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_GMD_PB), - regmap_reg_range(HDMI_RX_HDMI20_CONTROL, HDMI_RX_CHLOCK_CONFIG), - regmap_reg_range(HDMI_RX_SCDC_REGS1, HDMI_RX_SCDC_REGS3), - regmap_reg_range(HDMI_RX_SCDC_WRDATA0, HDMI_RX_SCDC_WRDATA7), - regmap_reg_range(HDMI_RX_DMI_DISABLE_IF, HDMI_RX_DMI_DISABLE_IF), -}; - -static const struct regmap_access_table rk628_hdmirx_readable_table = { - .yes_ranges = rk628_hdmirx_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(rk628_hdmirx_readable_ranges), -}; - -static const struct regmap_config rk628_hdmirx_regmap_config = { - .name = "hdmirx", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = HDMI_RX_MAX_REGISTER, - .reg_format_endian = REGMAP_ENDIAN_LITTLE, - .val_format_endian = REGMAP_ENDIAN_LITTLE, - .rd_table = &rk628_hdmirx_readable_table, -}; - -static inline struct rk628_hdmirx *bridge_to_hdmirx(struct drm_bridge *bridge) -{ - return container_of(bridge, struct rk628_hdmirx, base); -} - -static void rk628_hdmirx_ctrl_enable(struct rk628_hdmirx *hdmirx) -{ - clk_prepare_enable(hdmirx->pclk); - clk_prepare_enable(hdmirx->aud_clk); - clk_prepare_enable(hdmirx->imodet_clk); - - reset_control_deassert(hdmirx->hdmirx); - reset_control_deassert(hdmirx->hdmirx_pon); - - regmap_update_bits(hdmirx->grf, GRF_SYSTEM_CON0, - SW_INPUT_MODE_MASK, - SW_INPUT_MODE(INPUT_MODE_HDMI)); - - regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000101ff); - - regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x00000000); - regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0000017f); - regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0001017f); - - regmap_write(hdmirx->regmap, HDMI_RX_HDMI20_CONTROL, 0x10001f10); - - regmap_update_bits(hdmirx->regmap, HDMI_RX_CHLOCK_CONFIG, - CHLOCKMAXER_MASK | MILISECTIMERLIMIT_MASK, - CHLOCKMAXER(0x1) | MILISECTIMERLIMIT(49500)); - - regmap_write(hdmirx->regmap, HDMI_RX_SCDC_CONFIG, 0x00000001); - regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000001fe); - regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_EVLTM, 0x0016fff0); - regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_F, 0xf98a0190); - - regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_MODE_RECOVER, - SPIKE_FILTER_EN_MASK | DVI_MODE_HYST_MASK | - HDMI_MODE_HYST_MASK | HDMI_MODE_MASK | - GB_DET_MASK | EESS_OESS_MASK | SEL_CTL01_MASK, - SPIKE_FILTER_EN(0) | - DVI_MODE_HYST(0) | - HDMI_MODE_HYST(0) | - HDMI_MODE(3) | - GB_DET(2) | - EESS_OESS(0) | - SEL_CTL01(1)); - - regmap_write(hdmirx->regmap, HDMI_RX_PDEC_CTRL, 0xbfff8011); - regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ASP_CTRL, 0x00000040); - - regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_RESMPL_CTRL, - MAN_VID_DEREPEAT_MASK, MAN_VID_DEREPEAT(1)); - - regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_SYNC_CTRL, - VS_POL_ADJ_MODE_MASK | HS_POL_ADJ_MODE_MASK, - VS_POL_ADJ_MODE(2) | HS_POL_ADJ_MODE(2)); - - regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ERR_FILTER, 0x00000008); - - regmap_update_bits(hdmirx->regmap, HDMI_RX_SCDC_I2CCONFIG, - I2CSPIKESUPPR_MASK, I2CSPIKESUPPR(1)); - - regmap_write(hdmirx->regmap, HDMI_RX_SCDC_CONFIG, 0x00000001); - regmap_write(hdmirx->regmap, HDMI_RX_SCDC_WRDATA0, 0xabcdef01); - - regmap_update_bits(hdmirx->regmap, HDMI_RX_CHLOCK_CONFIG, - CHLOCKMAXER_MASK | MILISECTIMERLIMIT_MASK, - CHLOCKMAXER(0x1) | MILISECTIMERLIMIT(49500)); - - regmap_write(hdmirx->regmap, HDMI_RX_HDMI_ERROR_PROTECT, 0x000d0c98); - regmap_write(hdmirx->regmap, HDMI_RX_MD_HCTRL1, 0x00000010); - regmap_write(hdmirx->regmap, HDMI_RX_MD_HCTRL2, 0x00001738); - regmap_write(hdmirx->regmap, HDMI_RX_MD_VCTRL, 0x00000012); - regmap_write(hdmirx->regmap, HDMI_RX_MD_VTH, 0x0000073a); - regmap_write(hdmirx->regmap, HDMI_RX_MD_IL_POL, 0x00000004); - regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ACRM_CTRL, 0x00000000); - regmap_write(hdmirx->regmap, HDMI_RX_HDMI_DCM_CTRL, 0x00040414); - regmap_write(hdmirx->regmap, HDMI_RX_HDMI_PCB_CTRL, 0x00100000); - regmap_write(hdmirx->regmap, HDMI_RX_HDMI_SETUP_CTRL, 0x0f000fff); - regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_EVLTM, 0x00104260); - regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_F, 0x0f2d0eed); - regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x00000001); - udelay(400); - regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0001017f); - regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_RESMPL_CTRL, - MAN_VID_DEREPEAT_MASK, MAN_VID_DEREPEAT(1)); - regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000001fe); -} - -static void rk628_hdmirx_ctrl_disable(struct rk628_hdmirx *hdmirx) -{ - reset_control_assert(hdmirx->hdmirx); - reset_control_assert(hdmirx->hdmirx_pon); - clk_disable_unprepare(hdmirx->pclk); - clk_disable_unprepare(hdmirx->aud_clk); - clk_disable_unprepare(hdmirx->imodet_clk); -} - -static void rk628_hdmirx_bridge_enable(struct drm_bridge *bridge) -{ - bool locked; - u32 value, i, hact, vact, bus_width, hdisplay, vdisplay; - struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge); - - /* force 594m mode to yuv420 format */ - if (hdmirx->mode.clock == 594000) { - /* - * bit30 is used to indicate whether it is - * yuv420 format - */ - bus_width = hdmirx->mode.clock | BIT(30); - hdisplay = hdmirx->mode.hdisplay / 2; - } else { - bus_width = hdmirx->mode.clock; - hdisplay = hdmirx->mode.hdisplay; - } - - vdisplay = hdmirx->mode.vdisplay; - - phy_set_bus_width(hdmirx->phy, bus_width); - phy_power_on(hdmirx->phy); - usleep_range(10*1000, 11*1000); - rk628_hdmirx_ctrl_enable(hdmirx); - - /* if hdmirx ctrl unlock or get incorrect timing, reset ctrl and phy */ - for (i = 0; i < 5; i++) { - usleep_range(100*1000, 110*1000); - regmap_read(hdmirx->regmap, HDMI_RX_SCDC_REGS1, &value); - dev_dbg(hdmirx->dev, "HDMI_RX_SCDC_REGS1:0x%x\n", value); - value = (value >> 8) & 0xf; - - regmap_read(hdmirx->regmap, HDMI_RX_MD_HACT_PX, &hact); - regmap_read(hdmirx->regmap, HDMI_RX_MD_VAL, &vact); - - hact = hact & 0xffff; - vact = vact & 0xffff; - dev_dbg(hdmirx->dev, "hact:%d,vact:%d\n", hact, vact); - - if (value == 0xf && hact == hdisplay && vact == vdisplay) - locked = true; - else - locked = false; - - if (!locked) { - rk628_hdmirx_ctrl_disable(hdmirx); - usleep_range(10*1000, 11*1000); - phy_power_off(hdmirx->phy); - usleep_range(10*1000, 11*1000); - phy_power_on(hdmirx->phy); - usleep_range(10*1000, 11*1000); - rk628_hdmirx_ctrl_enable(hdmirx); - } else { - /* hdmirx ctrl get correct timing, enable output */ - regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, - 0x000001ff); - return; - } - } - - dev_err(hdmirx->dev, "hdmirx channel can't lock!\n"); - -} - -static void rk628_hdmirx_bridge_disable(struct drm_bridge *bridge) -{ - struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge); - - rk628_hdmirx_ctrl_disable(hdmirx); - phy_power_off(hdmirx->phy); -} - -static int rk628_hdmirx_bridge_attach(struct drm_bridge *bridge, - enum drm_bridge_attach_flags flags) -{ - struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge); - struct device *dev = hdmirx->dev; - int ret; - - ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, - NULL, &hdmirx->bridge); - if (ret) { - dev_err(dev, "failed to find next bridge\n"); - return ret; - } - - ret = drm_bridge_attach(bridge->encoder, hdmirx->bridge, bridge, flags); - if (ret) { - dev_err(dev, "failed to attach bridge\n"); - return ret; - } - - return 0; -} - -static void rk628_hdmirx_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adj) -{ - struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge); - - memcpy(&hdmirx->mode, adj, sizeof(hdmirx->mode)); -} - -static const struct drm_bridge_funcs rk628_hdmirx_bridge_funcs = { - .attach = rk628_hdmirx_bridge_attach, - .enable = rk628_hdmirx_bridge_enable, - .disable = rk628_hdmirx_bridge_disable, - .mode_set = rk628_hdmirx_bridge_mode_set, -}; - -static int rk628_hdmirx_probe(struct platform_device *pdev) -{ - struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent); - struct device *dev = &pdev->dev; - struct platform_device_info pdevinfo; - struct rk628_hdmirx *hdmirx; - int ret, irq; - - if (!of_device_is_available(dev->of_node)) - return -ENODEV; - - hdmirx = devm_kzalloc(dev, sizeof(*hdmirx), GFP_KERNEL); - if (!hdmirx) - return -ENOMEM; - - hdmirx->dev = dev; - hdmirx->parent = rk628; - platform_set_drvdata(pdev, hdmirx); - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - hdmirx->grf = rk628->grf; - if (!hdmirx->grf) - return -ENODEV; - - hdmirx->pclk = devm_clk_get(dev, "pclk"); - if (IS_ERR(hdmirx->pclk)) { - ret = PTR_ERR(hdmirx->pclk); - dev_err(dev, "failed to get pclk: %d\n", ret); - return ret; - } - - hdmirx->cec_clk = devm_clk_get(dev, "cec"); - if (IS_ERR(hdmirx->cec_clk)) { - ret = PTR_ERR(hdmirx->cec_clk); - dev_err(dev, "failed to get cec clk: %d\n", ret); - return ret; - } - - hdmirx->aud_clk = devm_clk_get(dev, "audio"); - if (IS_ERR(hdmirx->aud_clk)) { - ret = PTR_ERR(hdmirx->aud_clk); - dev_err(dev, "failed to get audio clk: %d\n", ret); - return ret; - } - - hdmirx->imodet_clk = devm_clk_get(dev, "imodet"); - if (IS_ERR(hdmirx->imodet_clk)) { - ret = PTR_ERR(hdmirx->imodet_clk); - dev_err(dev, "failed to get imodet clk: %d\n", ret); - return ret; - } - - hdmirx->hdmirx = of_reset_control_get(dev->of_node, "hdmirx"); - if (IS_ERR(hdmirx->hdmirx)) { - ret = PTR_ERR(hdmirx->hdmirx); - DRM_DEV_ERROR(dev, "failed to get hdmirx control: %d\n", ret); - return ret; - } - - hdmirx->hdmirx_pon = of_reset_control_get(dev->of_node, "hdmirx_pon"); - if (IS_ERR(hdmirx->hdmirx_pon)) { - ret = PTR_ERR(hdmirx->hdmirx_pon); - DRM_DEV_ERROR(dev, "failed to get hdmirx_pon control: %d\n", ret); - return ret; - } - - hdmirx->phy = devm_of_phy_get(dev, dev->of_node, NULL); - if (IS_ERR(hdmirx->phy)) { - ret = PTR_ERR(hdmirx->phy); - dev_err(dev, "failed to get phy: %d\n", ret); - return ret; - } - - hdmirx->regmap = devm_regmap_init_i2c(rk628->client, - &rk628_hdmirx_regmap_config); - if (IS_ERR(hdmirx->regmap)) { - ret = PTR_ERR(hdmirx->regmap); - dev_err(dev, "failed to allocate register map: %d\n", ret); - return ret; - } - - hdmirx->base.funcs = &rk628_hdmirx_bridge_funcs; - hdmirx->base.of_node = dev->of_node; - drm_bridge_add(&hdmirx->base); - - memset(&pdevinfo, 0, sizeof(pdevinfo)); - pdevinfo.parent = dev; - pdevinfo.id = PLATFORM_DEVID_AUTO; - - return 0; -} - -static int rk628_hdmirx_remove(struct platform_device *pdev) -{ - struct rk628_hdmirx *hdmirx = platform_get_drvdata(pdev); - - drm_bridge_remove(&hdmirx->base); - - return 0; -} - -static const struct of_device_id rk628_hdmirx_of_match[] = { - { .compatible = "rockchip,rk628-hdmirx", }, - {}, -}; -MODULE_DEVICE_TABLE(of, rk628_hdmirx_of_match); - -static struct platform_driver rk628_hdmirx_driver = { - .driver = { - .name = "rk628-hdmirx", - .of_match_table = of_match_ptr(rk628_hdmirx_of_match), - }, - .probe = rk628_hdmirx_probe, - .remove = rk628_hdmirx_remove, -}; -module_platform_driver(rk628_hdmirx_driver); - -MODULE_AUTHOR("Algea Cao "); -MODULE_DESCRIPTION("Rockchip RK628 HDMI RX driver"); -MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/rk628.h b/include/linux/mfd/rk628.h index 52ff63e0c601..7463f7036149 100755 --- a/include/linux/mfd/rk628.h +++ b/include/linux/mfd/rk628.h @@ -41,12 +41,6 @@ #define GRF_SYSTEM_CON1 0x0004 #define GRF_SYSTEM_CON2 0x0008 #define GRF_SYSTEM_CON3 0x000c -#define GRF_GPIO_RX_CEC_SEL_MASK BIT(7) -#define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7) -#define GRF_GPIO_RXDDC_SDA_SEL_MASK BIT(6) -#define GRF_GPIO_RXDDC_SDA_SEL(x) UPDATE(x, 6, 6) -#define GRF_GPIO_RXDDC_SCL_SEL_MASK BIT(5) -#define GRF_GPIO_RXDDC_SCL_SEL(x) UPDATE(x, 5, 5) #define GRF_SCALER_CON0 0x0010 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8) #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7) From 3506b5e5dd001c2bbc3c39a59a52765f84d55441 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Sun, 21 Jan 2024 14:36:22 +0800 Subject: [PATCH 4/8] Revert "drm: rockchip: rk628: Add rk628 combrx-phy driver" This reverts commit 92ae0beb2be2a7529721dbec8374f9db3fb16e30. Signed-off-by: Tao Huang Change-Id: I3ac211f4b6359a6e875fb97626938e8d6a0876ad --- drivers/gpu/drm/rockchip/rk628/Makefile | 3 +- .../gpu/drm/rockchip/rk628/rk628_combrxphy.c | 1030 ----------------- 2 files changed, 1 insertion(+), 1032 deletions(-) delete mode 100644 drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c diff --git a/drivers/gpu/drm/rockchip/rk628/Makefile b/drivers/gpu/drm/rockchip/rk628/Makefile index ed2749412113..cbdc259151d5 100644 --- a/drivers/gpu/drm/rockchip/rk628/Makefile +++ b/drivers/gpu/drm/rockchip/rk628/Makefile @@ -3,8 +3,7 @@ # Makefile for the Rockchip RK628 display bridge driver. # -obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combrxphy.o \ - rk628_combtxphy.o \ +obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combtxphy.o \ rk628_dsi.o \ rk628_gvi.o \ rk628_lvds.o \ diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c b/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c deleted file mode 100644 index a83eeeaf935f..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c +++ /dev/null @@ -1,1030 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * - * Author: Algea Cao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct rk628_combrxphy { - struct device *dev; - struct rk628 *parent; - struct regmap *regmap; - struct clk *pclk; - struct reset_control *rstc; - bool is_cable_mode; -}; - -#define REG(x) ((x) + 0x10000) -#define COMBRXPHY_MAX_REGISTER REG(0x6790) - -#define MAX_ROUND 6 -#define MAX_DATA_NUM 16 -#define MAX_CHANNEL 3 -#define CLK_DET_TRY_TIMES 10 -#define CLK_STABLE_LOOP_CNT 10 -#define CLK_STABLE_THRESHOLD 6 - -static int debug; -module_param(debug, int, 0644); -MODULE_PARM_DESC(debug, "debug level (0-1)"); - -static void rk628_combrxphy_set_data_of_round(u32 *data, u32 *data_in) -{ - if ((data != NULL) && (data_in != NULL)) { - data_in[0] = data[0]; - data_in[1] = data[7]; - data_in[2] = data[13]; - data_in[3] = data[14]; - data_in[4] = data[15]; - data_in[5] = data[1]; - data_in[6] = data[2]; - data_in[7] = data[3]; - data_in[8] = data[4]; - data_in[9] = data[5]; - data_in[10] = data[6]; - data_in[11] = data[8]; - data_in[12] = data[9]; - data_in[13] = data[10]; - data_in[14] = data[11]; - data_in[15] = data[12]; - } -} - -static void -rk628_combrxphy_max_zero_of_round(struct rk628_combrxphy *combrxphy, - u32 *data_in, u32 *max_zero, u32 *max_val, - int n, int ch) -{ - u32 i; - u32 cnt = 0; - u32 max_cnt = 0; - u32 max_v = 0; - - if (debug > 0) { - dev_info(combrxphy->dev, - "%s channel:%d, round:%d ====\n", __func__, ch, n); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4, - data_in, MAX_DATA_NUM * sizeof(u32), false); - } - - for (i = 0; i < MAX_DATA_NUM; i++) { - if (max_v < data_in[i]) - max_v = data_in[i]; - } - - for (i = 0; i < MAX_DATA_NUM; i++) { - if (data_in[i] == 0) - cnt = cnt + 200; - else if ((data_in[i] > 0) && (data_in[i] < 100)) - cnt = cnt + 100 - data_in[i]; - } - max_cnt = (cnt >= 3200) ? 0 : cnt; - - max_zero[n] = max_cnt; - max_val[n] = max_v; - dev_dbg(combrxphy->dev, - "channel:%d, round:%d, max_zero_cnt:%d, max_val:%#x", - ch, n, max_zero[n], max_val[n]); -} - -static int -rk628_combrxphy_chose_round_for_ch(struct rk628_combrxphy *combrxphy, - u32 *rd_max_zero, - u32 *rd_max_val, int ch) -{ - int i, rd = 0; - u32 max = 0; - u32 max_v = 0; - - if (debug > 0) { - dev_info(combrxphy->dev, - "%s max cnt of channel:%d ====\n", __func__, ch); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4, - rd_max_zero, MAX_ROUND * sizeof(u32), false); - - dev_info(combrxphy->dev, - "%s max value of channel:%d ====\n", __func__, ch); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_NONE, 32, 4, - rd_max_val, MAX_ROUND * sizeof(u32), false); - } - - for (i = 0; i < MAX_ROUND; i++) { - if (rd_max_zero[i] > max) { - max = rd_max_zero[i]; - max_v = rd_max_val[i]; - rd = i; - } else if (rd_max_zero[i] == max && rd_max_val[i] > max_v) { - max = rd_max_zero[i]; - max_v = rd_max_val[i]; - rd = i; - } - } - - dev_dbg(combrxphy->dev, "%s channel:%d, rd:%d\n", __func__, ch, rd); - return rd; -} - -static void rk628_combrxphy_get_data_of_round(struct rk628_combrxphy - *combrxphy, u32 *data) -{ - u32 i; - - for (i = 0; i < MAX_DATA_NUM; i++) - regmap_read(combrxphy->regmap, REG(0x6740 + i * 4), &data[i]); -} - -static void -rk628_combrxphy_set_dc_gain(struct rk628_combrxphy *combrxphy, - u32 x, u32 y, u32 z) -{ - u32 val; - u32 dc_gain_ch0, dc_gain_ch1, dc_gain_ch2; - - dev_dbg(combrxphy->dev, "channel dc gain ch0:%d, ch1:%d, ch2:%d\n", - x, y, z); - - dc_gain_ch0 = x & 0xf; - dc_gain_ch1 = y & 0xf; - dc_gain_ch2 = z & 0xf; - regmap_read(combrxphy->regmap, REG(0x661c), &val); - - val = (val & 0xff0f0f0f) | (dc_gain_ch0 << 20) | (dc_gain_ch1 << 12) | - (dc_gain_ch2 << 4); - regmap_write(combrxphy->regmap, REG(0x661c), val); -} - -static void rk628_combrxphy_set_sample_edge_round(struct rk628_combrxphy - *combrxphy, u32 x, u32 y, u32 z) -{ - u32 val; - u32 equ_gain_ch0, equ_gain_ch1, equ_gain_ch2; - - dev_dbg(combrxphy->dev, "channel equ gain ch0:%d, ch1:%d, ch2:%d\n", - x, y, z); - - equ_gain_ch0 = (x & 0xf); - equ_gain_ch1 = (y & 0xf); - equ_gain_ch2 = (z & 0xf); - regmap_read(combrxphy->regmap, REG(0x6618), &val); - val = (val & 0xff00f0ff) | (equ_gain_ch1 << 20) | - (equ_gain_ch0 << 16) | (equ_gain_ch2 << 8); - regmap_write(combrxphy->regmap, REG(0x6618), val); -} - -static void rk628_combrxphy_start_sample_edge(struct rk628_combrxphy *combrxphy) -{ - u32 val; - - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - val &= 0xfffff1ff; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - val = (val & 0xfffff1ff) | (0x7 << 9); - regmap_write(combrxphy->regmap, REG(0x66f0), val); -} - -static void -rk628_combrxphy_set_sample_edge_mode(struct rk628_combrxphy *combrxphy, - int ch) -{ - u32 val; - - regmap_read(combrxphy->regmap, REG(0x6634), &val); - val = val & (~(0xf << ((ch + 1) * 4))); - regmap_write(combrxphy->regmap, REG(0x6634), val); -} - -static void rk628_combrxphy_select_channel(struct rk628_combrxphy *combrxphy, - int ch) -{ - u32 val; - - regmap_read(combrxphy->regmap, REG(0x6700), &val); - val = (val & 0xfffffffc) | (ch & 0x3); - regmap_write(combrxphy->regmap, REG(0x6700), val); -} - -static void rk628_combrxphy_cfg_6730(struct rk628_combrxphy *combrxphy) -{ - u32 val; - - regmap_read(combrxphy->regmap, REG(0x6730), &val); - val = (val & 0xffff0000) | 0x1; - regmap_write(combrxphy->regmap, REG(0x6730), val); -} - -static void rk628_combrxphy_sample_edge_procedure_for_cable( - struct rk628_combrxphy *combrxphy, u32 cdr_mode) -{ - u32 n, ch; - u32 data[MAX_DATA_NUM]; - u32 data_in[MAX_DATA_NUM]; - u32 round_max_zero[MAX_CHANNEL][MAX_ROUND]; - u32 round_max_value[MAX_CHANNEL][MAX_ROUND]; - u32 ch_round[MAX_CHANNEL]; - u32 edge, dc_gain; - u32 rd_offset; - - /* Step1: set sample edge mode for channel 0~2 */ - for (ch = 0; ch < MAX_CHANNEL; ch++) - rk628_combrxphy_set_sample_edge_mode(combrxphy, ch); - - /* step2: once per round */ - for (ch = 0; ch < MAX_CHANNEL; ch++) { - rk628_combrxphy_select_channel(combrxphy, ch); - rk628_combrxphy_cfg_6730(combrxphy); - } - - /* step3: config sample edge until the end of one frame - * (for example 1080p:2200*1125=32’h25c3f8) - */ - if (cdr_mode < 16) { - dc_gain = 0; - rd_offset = 0; - } else if (cdr_mode < 18) { - dc_gain = 1; - rd_offset = 0; - } else { - dc_gain = 3; - rd_offset = 2; - } - - /* When the pix clk is the same, the low frame rate resolution is used - * to calculate the sampling window (the frame rate is not less than - * 30). The sampling delay time is configured as 40ms. - */ - if (cdr_mode <= 1) { /* 27M vic17 720x576P50 */ - edge = 864 * 625; - } else if (cdr_mode <= 4) { /* 59.4M vic81 1680x720P30 */ - edge = 2640 * 750; - } else if (cdr_mode <= 7) { /* 74.25M vic34 1920x1080P30 */ - edge = 2200 * 1125; - } else if (cdr_mode <= 14) { /* 119M vic88 2560x1180P30 */ - edge = 3520 * 1125; - } else if (cdr_mode <= 16) { /* 148.5M vic31 1920x1080P50 */ - edge = 2640 * 1125; - } else if (cdr_mode <= 17) { /* 162M vic89 2560x1080P50 */ - edge = 3300 * 1125; - } else if (cdr_mode <= 18) { /* 297M vic95 3840x2160P30 */ - edge = 4400 * 2250; - } else { /* unkonw vic16 1920x1080P60 */ - edge = 2200 * 1125; - } - - dev_info(combrxphy->dev, - "cdr_mode:%d, dc_gain:%d, rd_offset:%d, edge:%#x\n", - cdr_mode, dc_gain, rd_offset, edge); - for (ch = 0; ch < MAX_CHANNEL; ch++) { - rk628_combrxphy_select_channel(combrxphy, ch); - regmap_write(combrxphy->regmap, REG(0x6708), edge); - } - - rk628_combrxphy_set_dc_gain(combrxphy, dc_gain, dc_gain, dc_gain); - for (n = rd_offset; n < (rd_offset + MAX_ROUND); n++) { - /* step4:set sample edge round value n,n=0(n=0~31) */ - rk628_combrxphy_set_sample_edge_round(combrxphy, n, n, n); - /* step5:start sample edge */ - rk628_combrxphy_start_sample_edge(combrxphy); - /* step6:waiting more than one frame time */ - usleep_range(40*1000, 41*1000); - for (ch = 0; ch < MAX_CHANNEL; ch++) { - /* step7: get data of round n */ - rk628_combrxphy_select_channel(combrxphy, ch); - rk628_combrxphy_get_data_of_round(combrxphy, data); - rk628_combrxphy_set_data_of_round(data, data_in); - /* step8: get the max constant value of round n */ - rk628_combrxphy_max_zero_of_round(combrxphy, data_in, - round_max_zero[ch], round_max_value[ch], - n - rd_offset, ch); - } - } - - /* step9: after finish round, get the max constant value and - * corresponding value n. - */ - for (ch = 0; ch < MAX_CHANNEL; ch++) { - ch_round[ch] = rk628_combrxphy_chose_round_for_ch(combrxphy, - round_max_zero[ch], round_max_value[ch], ch) - + rd_offset; - } - dev_info(combrxphy->dev, "last equ gain ch0:%d, ch1:%d, ch2:%d\n", - ch_round[0], ch_round[1], ch_round[2]); - - /* step10: write result to sample edge round value */ - rk628_combrxphy_set_sample_edge_round(combrxphy, ch_round[0], - ch_round[1], ch_round[2]); - - /* do step5, step6 again */ - /* step5:start sample edge */ - rk628_combrxphy_start_sample_edge(combrxphy); - /* step6:waiting more than one frame time */ - usleep_range(40*1000, 41*1000); -} - -static void -rk628_combrxphy_sample_edge_procedure(struct rk628_combrxphy *combrxphy, - int f, u32 rd_offset) -{ - u32 n, ch; - u32 data[MAX_DATA_NUM]; - u32 data_in[MAX_DATA_NUM]; - u32 round_max_zero[MAX_CHANNEL][MAX_ROUND]; - u32 round_max_value[MAX_CHANNEL][MAX_ROUND]; - u32 ch_round[MAX_CHANNEL]; - u32 edge, dc_gain; - - dev_dbg(combrxphy->dev, "%s in!", __func__); - /* Step1: set sample edge mode for channel 0~2 */ - for (ch = 0; ch < MAX_CHANNEL; ch++) - rk628_combrxphy_set_sample_edge_mode(combrxphy, ch); - - dev_dbg(combrxphy->dev, "step1 set sample edge mode ok!"); - - /* step2: once per round */ - for (ch = 0; ch < MAX_CHANNEL; ch++) { - rk628_combrxphy_select_channel(combrxphy, ch); - rk628_combrxphy_cfg_6730(combrxphy); - } - dev_dbg(combrxphy->dev, "step2 once per round ok!"); - - /* - * step3:config sample edge until the end of one frame - * (for example 1080p:2200*1125=32’h25c3f8) - */ - switch (f) { - case 27000: - edge = 858 * 525; - dc_gain = 0; - break; - case 64000: - edge = 1317 * 810; - dc_gain = 0; - break; - case 74250: - edge = 1650 * 750; - dc_gain = 0; - break; - case 148500: - edge = 2200 * 1125; - dc_gain = 1; - break; - case 297000: - dc_gain = 3; - edge = 4400 * 2250; - break; - case 594000: - dc_gain = 0xf; - edge = 4400 * 2250; - break; - default: - edge = 2200 * 1125; - dc_gain = 1; - break; - } - dev_dbg(combrxphy->dev, "===>>> f:%d, edge:%#x", f, edge); - for (ch = 0; ch < MAX_CHANNEL; ch++) { - rk628_combrxphy_select_channel(combrxphy, ch); - regmap_write(combrxphy->regmap, REG(0x6708), edge); - } - dev_dbg(combrxphy->dev, "step3 cfg sample edge ok!"); - - rk628_combrxphy_set_dc_gain(combrxphy, dc_gain, dc_gain, dc_gain); - - for (n = rd_offset; n < (rd_offset + MAX_ROUND); n++) { - /* step4:set sample edge round value n,n=0(n=0~31) */ - rk628_combrxphy_set_sample_edge_round(combrxphy, n, n, n); - dev_dbg(combrxphy->dev, "step4 ok!"); - /* step5:start sample edge */ - rk628_combrxphy_start_sample_edge(combrxphy); - dev_dbg(combrxphy->dev, "step5 ok!"); - /* step6:waiting more than one frame time */ - usleep_range(40*1000, 41*1000); - for (ch = 0; ch < MAX_CHANNEL; ch++) { - /* step7:get data of round n */ - rk628_combrxphy_select_channel(combrxphy, ch); - dev_dbg(combrxphy->dev, "step7 set ch ok!"); - rk628_combrxphy_get_data_of_round(combrxphy, data); - dev_dbg(combrxphy->dev, "step7 get data ok!"); - rk628_combrxphy_set_data_of_round(data, data_in); - dev_dbg(combrxphy->dev, "step7 set data ok!"); - rk628_combrxphy_max_zero_of_round(combrxphy, data_in, - round_max_zero[ch], - round_max_value[ch], - n - rd_offset, ch); - } - } - for (ch = 0; ch < MAX_CHANNEL; ch++) - ch_round[ch] = - rk628_combrxphy_chose_round_for_ch(combrxphy, - round_max_zero[ch], - round_max_value[ch], - ch) + rd_offset; - - /* - * step8:after finish round 31, get the max constant value and - * corresponding value n. - * write result to sample edge round value. - */ - rk628_combrxphy_set_sample_edge_round(combrxphy, ch_round[0], - ch_round[1], ch_round[2]); - - /* do step5, step6 again */ - dev_dbg(combrxphy->dev, "do step5 step6 again!"); - rk628_combrxphy_start_sample_edge(combrxphy); - usleep_range(40*1000, 41*1000); -} - -static int rk628_combrxphy_try_clk_detect(struct rk628_combrxphy *combrxphy) -{ - u32 val, i; - int ret; - - ret = -1; - reset_control_assert(combrxphy->rstc); - usleep_range(10, 20); - reset_control_deassert(combrxphy->rstc); - usleep_range(10, 20); - - /* step1: set pin_rst_n to 1’b0.wait 1 period(1us).release reset */ - /* step2: select pll clock src and enable auto check */ - regmap_read(combrxphy->regmap, REG(0x6630), &val); - /* clear bit0 and bit3 */ - val = val & 0xfffffff6; - regmap_write(combrxphy->regmap, REG(0x6630), val); - /* step3: select hdmi mode and enable chip, read reg6654, - * make sure auto setup done. - */ - /* auto fsm reset related */ - regmap_read(combrxphy->regmap, REG(0x6630), &val); - val = val | BIT(24); - regmap_write(combrxphy->regmap, REG(0x6630), val); - /* pull down ana rstn */ - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - val = val & 0xfffffeff; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - /* pull down dig rstn */ - regmap_read(combrxphy->regmap, REG(0x66f4), &val); - val = val & 0xfffffffe; - regmap_write(combrxphy->regmap, REG(0x66f4), val); - /* pull up ana rstn */ - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - val = val | 0x100; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - /* pull up dig rstn */ - regmap_read(combrxphy->regmap, REG(0x66f4), &val); - val = val | 0x1; - regmap_write(combrxphy->regmap, REG(0x66f4), val); - - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - /* set bit0 and bit2 to 1*/ - val = (val & 0xfffffff8) | 0x5; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - - /* auto fsm en = 0 */ - regmap_read(combrxphy->regmap, REG(0x66f0), &val); - /* set bit0 and bit2 to 1*/ - val = (val & 0xfffffff8) | 0x4; - regmap_write(combrxphy->regmap, REG(0x66f0), val); - - for (i = 0; i < 10; i++) { - usleep_range(500, 510); - regmap_read(combrxphy->regmap, REG(0x6654), &val); - if ((val & 0xf0000000) == 0x80000000) { - ret = 0; - dev_info(combrxphy->dev, "clock detected!"); - break; - } - } - - return ret; -} - -static int -rk628_combrxphy_set_hdmi_mode_for_cable(struct rk628_combrxphy *combrxphy, - int f) -{ - u32 val, val_a, val_b, data_a, data_b; - u32 i, j, count, ret; - u32 cdr_mode, cdr_data, pll_man; - u32 tmds_bitrate_per_lane; - u32 cdr_data_min, cdr_data_max; - - /* - * use the mode of automatic clock detection, only supports fixed TMDS - * frequency.Refer to register 0x6654[21:16]: - * 5'd31:Error mode - * 5'd30:manual mode detected - * 5'd18:rx3p clock = 297MHz - * 5'd17:rx3p clock = 162MHz - * 5'd16:rx3p clock = 148.5MHz - * 5'd15:rx3p clock = 135MHz - * 5'd14:rx3p clock = 119MHz - * 5'd13:rx3p clock = 108MHz - * 5'd12:rx3p clock = 101MHz - * 5'd11:rx3p clock = 92.8125MHz - * 5'd10:rx3p clock = 88.75MHz - * 5'd9:rx3p clock = 85.5MHz - * 5'd8:rx3p clock = 83.5MHz - * 5'd7:rx3p clock = 74.25MHz - * 5'd6:rx3p clock = 68.25MHz - * 5'd5:rx3p clock = 65MHz - * 5'd4:rx3p clock = 59.4MHz - * 5'd3:rx3p clock = 40MHz - * 5'd2:rx3p clock = 33.75MHz - * 5'd1:rx3p clock = 27MHz - * 5'd0:rx3p clock = 25.17MHz - */ - - const u32 cdr_mode_to_khz[] = { - 25170, 27000, 33750, 40000, 59400, 65000, 68250, - 74250, 83500, 85500, 88750, 92812, 101000, 108000, - 119000, 135000, 148500, 162000, 297000, - }; - - for (i = 0; i < CLK_DET_TRY_TIMES; i++) { - if (rk628_combrxphy_try_clk_detect(combrxphy) >= 0) - break; - usleep_range(100*1000, 100*1000); - } - regmap_read(combrxphy->regmap, REG(0x6654), &val); - dev_info(combrxphy->dev, "clk det over cnt:%d, reg_0x6654:%#x", i, val); - - regmap_read(combrxphy->regmap, REG(0x6620), &val); - if ((i == CLK_DET_TRY_TIMES) || - ((val & 0x7f000000) == 0) || - ((val & 0x007f0000) == 0) || - ((val & 0x00007f00) == 0) || - ((val & 0x0000007f) == 0)) { - dev_info(combrxphy->dev, - "clock detected failed, cfg resistance manual!"); - regmap_write(combrxphy->regmap, REG(0x6620), 0x66666666); - regmap_update_bits(combrxphy->regmap, REG(0x6604), BIT(31), - BIT(31)); - usleep_range(1000, 1100); - } - - /* step4: get cdr_mode and cdr_data */ - for (j = 0; j < CLK_STABLE_LOOP_CNT ; j++) { - cdr_data_min = 0xffffffff; - cdr_data_max = 0; - - for (i = 0; i < CLK_DET_TRY_TIMES; i++) { - regmap_read(combrxphy->regmap, REG(0x6654), &val); - cdr_data = val & 0xffff; - if (cdr_data <= cdr_data_min) - cdr_data_min = cdr_data; - if (cdr_data >= cdr_data_max) - cdr_data_max = cdr_data; - udelay(50); - } - - if (((cdr_data_max - cdr_data_min) <= CLK_STABLE_THRESHOLD) && - (cdr_data_min >= 60)) { - dev_info(combrxphy->dev, "clock stable!"); - break; - } - } - - if (j == CLK_STABLE_LOOP_CNT) { - regmap_read(combrxphy->regmap, REG(0x6630), &val_a); - regmap_read(combrxphy->regmap, REG(0x6608), &val_b); - dev_err(combrxphy->dev, - "err, clk not stable, reg_0x6630:%#x, reg_0x6608:%#x", - val_a, val_b); - - return -EINVAL; - } - - regmap_read(combrxphy->regmap, REG(0x6654), &val); - if ((val & 0x1f0000) == 0x1f0000) { - regmap_read(combrxphy->regmap, REG(0x6630), &val_a); - regmap_read(combrxphy->regmap, REG(0x6608), &val_b); - dev_err(combrxphy->dev, - "clock error: 0x1f, reg_0x6630:%#x, reg_0x6608:%#x", - val_a, val_b); - - return -EINVAL; - } - - cdr_mode = (val >> 16) & 0x1f; - cdr_data = val & 0xffff; - dev_info(combrxphy->dev, "cdr_mode:%d, cdr_data:%d\n", cdr_mode, - cdr_data); - - /* step5: manually configure PLL - * cfg reg 66a8 tmds clock div2 for rgb/yuv444 as default - * reg 662c[16:8] pll_pre_div - */ - if (f <= 340000) { - regmap_write(combrxphy->regmap, REG(0x662c), 0x01000500); - regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600); - } else { - regmap_write(combrxphy->regmap, REG(0x662c), 0x01001400); - regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600); - } - - /* when tmds bitrate/lane <= 340M, bitrate/lane = pix_clk * 10 */ - tmds_bitrate_per_lane = cdr_mode_to_khz[cdr_mode] * 10; - if (tmds_bitrate_per_lane < 400000) - pll_man = 0x7960c; - else if (tmds_bitrate_per_lane < 600000) - pll_man = 0x7750c; - else if (tmds_bitrate_per_lane < 800000) - pll_man = 0x7964c; - else if (tmds_bitrate_per_lane < 1000000) - pll_man = 0x7754c; - else if (tmds_bitrate_per_lane < 1600000) - pll_man = 0x7a108; - else if (tmds_bitrate_per_lane < 2400000) - pll_man = 0x73588; - else if (tmds_bitrate_per_lane < 3400000) - pll_man = 0x7a108; - else - pll_man = 0x7f0c8; - - dev_info(combrxphy->dev, "cdr_mode:%d, pll_man:%#x\n", cdr_mode, - pll_man); - regmap_write(combrxphy->regmap, REG(0x6630), pll_man); - - /* step6: EQ and SAMPLE cfg */ - rk628_combrxphy_sample_edge_procedure_for_cable(combrxphy, cdr_mode); - - /* step7: Deassert fifo reset,enable fifo write and read */ - /* reset rx_infifo */ - regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000003); - /* rx_infofo wr/rd disable */ - regmap_write(combrxphy->regmap, REG(0x66b0), 0x00080060); - /* deassert rx_infifo reset */ - regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000083); - /* enable rx_infofo wr/rd en */ - regmap_write(combrxphy->regmap, REG(0x66b0), 0x00380060); - /* cfg 0x2260 high_8b to 0x66ac high_8b, low_8b to 0x66b0 low_8b */ - regmap_update_bits(combrxphy->regmap, REG(0x66ac), GENMASK(31, 24), - UPDATE(0x22, 31, 24)); - usleep_range(5*1000, 6*1000); - - /* step8: check all 3 data channels alignment */ - count = 0; - for (i = 0; i < 100; i++) { - usleep_range(100, 110); - regmap_read(combrxphy->regmap, REG(0x66b4), &data_a); - regmap_read(combrxphy->regmap, REG(0x66b8), &data_b); - /* ch0 ch1 ch2 lock */ - if (((data_a & 0x00ff00ff) == 0x00ff00ff) && - ((data_b & 0xff) == 0xff)) { - count++; - } - } - - if (count >= 100) { - dev_info(combrxphy->dev, "channel alignment done"); - dev_info(combrxphy->dev, "rx initial done"); - ret = 0; - } else if (count > 0) { - dev_err(combrxphy->dev, "link not stable, count:%d of 100", - count); - ret = 0; - } else { - dev_err(combrxphy->dev, "channel alignment failed!"); - ret = -EINVAL; - } - - return ret; -} - -static int rk628_combrxphy_set_hdmi_mode(struct rk628_combrxphy *combrxphy, - int bus_width) -{ - u32 val, data_a, data_b, f, val2 = 0; - int i, ret, count; - u32 pll_man, rd_offset; - bool is_yuv420; - - is_yuv420 = bus_width & BIT(30); - - if (is_yuv420) - f = (bus_width & 0xffffff) / 2; - else - f = bus_width & 0xffffff; - - dev_dbg(combrxphy->dev, "f:%d\n", f); - - regmap_read(combrxphy->regmap, REG(0x6630), &val); - val &= ~BIT(23); - val |= 0x18; - regmap_write(combrxphy->regmap, REG(0x6630), val); - - /* enable cal */ - regmap_read(combrxphy->regmap, REG(0x6610), &val); - val |= 0x18000000; - regmap_write(combrxphy->regmap, REG(0x6610), val); - - usleep_range(10*1000, 11*1000); - /* disable cal */ - val &= ~BIT(28); - val |= BIT(27); - regmap_write(combrxphy->regmap, REG(0x6610), val); - - /* save cal val */ - regmap_read(combrxphy->regmap, REG(0x6614), &val); - if (!(val & 0x3f00)) { - dev_err(combrxphy->dev, "resistor error\n"); - return -EINVAL; - } - - val &= 0x3f00; - val = val >> 8; - val2 |= 0x40404040; - val2 |= val << 24 | val << 16 | val << 8 | val; - - /* rtm inc */ - regmap_read(combrxphy->regmap, REG(0x6604), &val); - val |= BIT(31); - regmap_write(combrxphy->regmap, REG(0x6604), val); - - regmap_write(combrxphy->regmap, REG(0x6620), val2); - - /* rtm en bypass */ - regmap_read(combrxphy->regmap, REG(0x6600), &val); - val |= BIT(7); - regmap_write(combrxphy->regmap, REG(0x6600), val); - - /* rtm prot en bypass */ - regmap_read(combrxphy->regmap, REG(0x6610), &val); - val |= 0x80f000; - regmap_write(combrxphy->regmap, REG(0x6610), val); - - regmap_read(combrxphy->regmap, REG(0x661c), &val); - val |= 0x81000000; - regmap_write(combrxphy->regmap, REG(0x661c), val); - - /* enable pll */ - regmap_read(combrxphy->regmap, REG(0x6630), &val); - val &= ~BIT(4); - val |= BIT(3); - regmap_write(combrxphy->regmap, REG(0x6630), val); - - /* equ en */ - regmap_read(combrxphy->regmap, REG(0x6618), &val); - val |= BIT(4); - regmap_write(combrxphy->regmap, REG(0x6618), val); - - regmap_read(combrxphy->regmap, REG(0x6614), &val); - val |= 0x10900000; - regmap_write(combrxphy->regmap, REG(0x6614), val); - - regmap_read(combrxphy->regmap, REG(0x6610), &val); - val |= 0xf00; - regmap_write(combrxphy->regmap, REG(0x6610), val); - - regmap_read(combrxphy->regmap, REG(0x6630), &val); - val |= 0x870000; - regmap_write(combrxphy->regmap, REG(0x6630), val); - - udelay(10); - - /* get cdr_mode,make sure cdr_mode != 5’h1f */ - regmap_read(combrxphy->regmap, REG(0x6654), &val); - if ((val & 0x1f0000) == 0x1f0000) - dev_err(combrxphy->dev, "error,clock error!"); - - /* manually configure PLL */ - if (f <= 340000) { - regmap_write(combrxphy->regmap, REG(0x662c), 0x01000500); - if (is_yuv420) - regmap_write(combrxphy->regmap, REG(0x66a8), - 0x0000c000); - else - regmap_write(combrxphy->regmap, REG(0x66a8), - 0x0000c600); - } else { - regmap_write(combrxphy->regmap, REG(0x662c), 0x01001400); - regmap_write(combrxphy->regmap, REG(0x66a8), 0x0000c600); - } - - switch (f) { - case 27000: - case 64000: - case 74250: - rd_offset = 0; - pll_man = 0x7964c; - break; - case 148500: - pll_man = 0x7a1c8; - rd_offset = 0; - break; - case 297000: - pll_man = 0x7a108; - rd_offset = 2; - break; - case 594000: - pll_man = 0x7f0c8; - rd_offset = 4; - break; - default: - pll_man = 0x7964c; - rd_offset = 1; - break; - } - - pll_man |= BIT(23); - regmap_write(combrxphy->regmap, REG(0x6630), pll_man); - - /* EQ and SAMPLE cfg */ - rk628_combrxphy_sample_edge_procedure(combrxphy, f, rd_offset); - - /* Deassert fifo reset,enable fifo write and read */ - regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000003); - regmap_write(combrxphy->regmap, REG(0x66b0), 0x00080060); - regmap_write(combrxphy->regmap, REG(0x66a0), 0x00000083); - regmap_write(combrxphy->regmap, REG(0x66b0), 0x00380060); - regmap_update_bits(combrxphy->regmap, REG(0x66ac), GENMASK(31, 24), - UPDATE(0x22, 31, 24)); - usleep_range(10*1000, 11*1000); - - /* check all 3 data channels alignment */ - count = 0; - for (i = 0; i < 100; i++) { - udelay(100); - regmap_read(combrxphy->regmap, REG(0x66b4), &data_a); - regmap_read(combrxphy->regmap, REG(0x66b8), &data_b); - /* ch0 ch1 ch2 lock */ - if (((data_a & 0x00ff00ff) == 0x00ff00ff) && - ((data_b & 0xff) == 0xff)) - count++; - } - - if (count >= 100) { - dev_info(combrxphy->dev, "channel alignment done"); - ret = 0; - } else if (count > 0) { - dev_err(combrxphy->dev, "not stable, count:%d of 100", count); - ret = -EINVAL; - } else { - dev_err(combrxphy->dev, "channel alignment failed!"); - ret = -EINVAL; - } - - return ret; -} - -static int rk628_combrxphy_power_on(struct phy *phy) -{ - struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy); - int f = phy_get_bus_width(phy); - int ret; - - /* Bit31 is used to distinguish HDMI cable mode and direct - * connection mode. - * Bit31: 0 -direct connection mode; - * 1 -cable mode; - */ - combrxphy->is_cable_mode = (f & BIT(31)) ? true : false; - dev_dbg(combrxphy->dev, "%s\n", __func__); - clk_prepare_enable(combrxphy->pclk); - reset_control_assert(combrxphy->rstc); - udelay(10); - reset_control_deassert(combrxphy->rstc); - udelay(10); - - if (combrxphy->is_cable_mode) { - f = f & 0x7fffffff; - ret = rk628_combrxphy_set_hdmi_mode_for_cable(combrxphy, f); - } else { - ret = rk628_combrxphy_set_hdmi_mode(combrxphy, f); - } - - return ret; -} - -static int rk628_combrxphy_power_off(struct phy *phy) -{ - struct rk628_combrxphy *combrxphy = phy_get_drvdata(phy); - - dev_dbg(combrxphy->dev, "%s\n", __func__); - reset_control_assert(combrxphy->rstc); - udelay(10); - clk_disable_unprepare(combrxphy->pclk); - - return 0; -} - -static const struct phy_ops rk628_combrxphy_ops = { - .power_on = rk628_combrxphy_power_on, - .power_off = rk628_combrxphy_power_off, - .owner = THIS_MODULE, -}; - -static const struct regmap_range rk628_combrxphy_readable_ranges[] = { - regmap_reg_range(REG(0x6600), REG(0x665b)), - regmap_reg_range(REG(0x66a0), REG(0x66db)), - regmap_reg_range(REG(0x66f0), REG(0x66ff)), - regmap_reg_range(REG(0x6700), REG(0x6790)), -}; - -static const struct regmap_access_table rk628_combrxphy_readable_table = { - .yes_ranges = rk628_combrxphy_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(rk628_combrxphy_readable_ranges), -}; - -static const struct regmap_config rk628_combrxphy_regmap_cfg = { - .name = "combrxphy", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = COMBRXPHY_MAX_REGISTER, - .reg_format_endian = REGMAP_ENDIAN_LITTLE, - .val_format_endian = REGMAP_ENDIAN_LITTLE, - .rd_table = &rk628_combrxphy_readable_table, -}; - -static int rk628_combrxphy_probe(struct platform_device *pdev) -{ - struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent); - struct device *dev = &pdev->dev; - struct rk628_combrxphy *combrxphy; - struct phy_provider *phy_provider; - struct phy *phy; - int ret; - - if (!of_device_is_available(dev->of_node)) - return -ENODEV; - - combrxphy = devm_kzalloc(dev, sizeof(*combrxphy), GFP_KERNEL); - if (!combrxphy) - return -ENOMEM; - - combrxphy->dev = dev; - combrxphy->parent = rk628; - platform_set_drvdata(pdev, combrxphy); - - combrxphy->pclk = devm_clk_get(dev, "pclk"); - if (IS_ERR(combrxphy->pclk)) { - ret = PTR_ERR(combrxphy->pclk); - dev_err(dev, "failed to get pclk: %d\n", ret); - return ret; - } - - combrxphy->rstc = of_reset_control_get(dev->of_node, NULL); - if (IS_ERR(combrxphy->rstc)) { - ret = PTR_ERR(combrxphy->rstc); - dev_err(dev, "failed to get reset control: %d\n", ret); - return ret; - } - - combrxphy->regmap = devm_regmap_init_i2c(rk628->client, - &rk628_combrxphy_regmap_cfg); - if (IS_ERR(combrxphy->regmap)) { - ret = PTR_ERR(combrxphy->regmap); - dev_err(dev, "failed to allocate host register map: %d\n", ret); - return ret; - } - - phy = devm_phy_create(dev, NULL, &rk628_combrxphy_ops); - if (IS_ERR(phy)) { - ret = PTR_ERR(phy); - dev_err(dev, "failed to create phy: %d\n", ret); - return ret; - } - - phy_set_drvdata(phy, combrxphy); - - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (IS_ERR(phy_provider)) { - ret = PTR_ERR(phy_provider); - dev_err(dev, "failed to register phy provider: %d\n", ret); - return ret; - } - - return 0; -} - -static const struct of_device_id rk628_combrxphy_of_match[] = { - { .compatible = "rockchip,rk628-combrxphy", }, - {} -}; -MODULE_DEVICE_TABLE(of, rk628_combrxphy_of_match); - -static struct platform_driver rk628_combrxphy_driver = { - .driver = { - .name = "rk628-combrxphy", - .of_match_table = of_match_ptr(rk628_combrxphy_of_match), - }, - .probe = rk628_combrxphy_probe, -}; -module_platform_driver(rk628_combrxphy_driver); - -MODULE_AUTHOR("Algea Cao "); -MODULE_DESCRIPTION("Rockchip RK628 HDMI Combo RX PHY driver"); -MODULE_LICENSE("GPL v2"); From 88f9a01d8d26d73592154a277e5844ccf1439219 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Sun, 21 Jan 2024 14:36:39 +0800 Subject: [PATCH 5/8] Revert "drm/rockchip/rk628: Add GVI driver" This reverts commit fe736116babcb88c6f556a1d9882df8a49ab72f5. Signed-off-by: Tao Huang Change-Id: I3381fffc5992c55e20c7d9dd7db999ca7b234f44 --- drivers/gpu/drm/rockchip/rk628/Makefile | 1 - drivers/gpu/drm/rockchip/rk628/rk628_gvi.c | 664 --------------------- 2 files changed, 665 deletions(-) delete mode 100644 drivers/gpu/drm/rockchip/rk628/rk628_gvi.c diff --git a/drivers/gpu/drm/rockchip/rk628/Makefile b/drivers/gpu/drm/rockchip/rk628/Makefile index cbdc259151d5..08b038789a57 100644 --- a/drivers/gpu/drm/rockchip/rk628/Makefile +++ b/drivers/gpu/drm/rockchip/rk628/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combtxphy.o \ rk628_dsi.o \ - rk628_gvi.o \ rk628_lvds.o \ rk628_post_process.o \ rk628_rgb.o \ diff --git a/drivers/gpu/drm/rockchip/rk628/rk628_gvi.c b/drivers/gpu/drm/rockchip/rk628/rk628_gvi.c deleted file mode 100644 index a3c92195e2dd..000000000000 --- a/drivers/gpu/drm/rockchip/rk628/rk628_gvi.c +++ /dev/null @@ -1,664 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * - * Author: Sandy Huang - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include