From 004e0a6e1f8db37ebfd5fbacfe9db006195f19e6 Mon Sep 17 00:00:00 2001 From: Li Huang Date: Thu, 23 Dec 2021 19:43:43 +0800 Subject: [PATCH] video: rockchip: rga3: Fixup the problem that dst offset not taking effect Signed-off-by: Li Huang Change-Id: I5ae13bdbda7d9f8f22505518f1d9f64ac11d9fa0 --- drivers/video/rockchip/rga3/rga3_reg_info.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/video/rockchip/rga3/rga3_reg_info.c b/drivers/video/rockchip/rga3/rga3_reg_info.c index fd02b7569aa0..4ed8dc33bdd9 100644 --- a/drivers/video/rockchip/rga3/rga3_reg_info.c +++ b/drivers/video/rockchip/rga3/rga3_reg_info.c @@ -1191,12 +1191,9 @@ static void RGA3_set_reg_overlap_info(u8 *base, struct rga3_req *msg) } /* 1: ABB mode, 0: ABC modeļ¼Œ ABB cannot support fbc in&out */ - if ((msg->win0.rd_mode != 1) && (msg->win1.rd_mode != 1) - && msg->wr.rd_mode != 1) { - if (msg->win0.yrgb_addr == msg->wr.yrgb_addr) - reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_OVLP_MODE)) | - (s_RGA3_OVLP_CTRL_SW_OVLP_MODE(1))); - } + if (msg->win0.yrgb_addr == msg->wr.yrgb_addr) + reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_OVLP_MODE)) | + (s_RGA3_OVLP_CTRL_SW_OVLP_MODE(1))); /* 1: yuv field, 0: rgb field */ if (msg->wr.format >= RGA2_FORMAT_BGR_565) @@ -1222,12 +1219,7 @@ int rga3_gen_reg_info(u8 *base, struct rga3_req *msg) case BITBLT_MODE: RGA3_set_reg_win0_info(base, msg); RGA3_set_reg_win1_info(base, msg); - - if (msg->alpha_mode_0 != 0 || msg->alpha_mode_1 != 0 || - msg->win0_a_global_val != 0 || - msg->win1_a_global_val != 0) - RGA3_set_reg_overlap_info(base, msg); - + RGA3_set_reg_overlap_info(base, msg); RGA3_set_reg_wr_info(base, msg); break; default: