From 0142cfb4ec1bef3901ab78c8d0ea7abd3984e1db Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 17 Oct 2022 16:10:15 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3568: Add trim configure for tsadc Signed-off-by: Finley Xiao Change-Id: If1b4bf98b3be24c8a3f97fbb0adf7279ca9a2ed2 Signed-off-by: Elaine Zhang --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 3eaa19904f16..406edf40e114 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -2711,6 +2711,27 @@ core_pvtm:core-pvtm@2a { reg = <0x2a 0x2>; }; + cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e { + reg = <0x2e 0x1>; + }; + cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f { + reg = <0x2f 0x1>; + bits = <0 4>; + }; + gpu_tsadc_trim_l: npu-tsadc-trim-l@30 { + reg = <0x30 0x1>; + }; + gpu_tsadc_trim_h: npu-tsadc-trim-h@31 { + reg = <0x31 0x1>; + bits = <0 4>; + }; + tsadc_trim_base_frac: tsadc-trim-base-frac@31 { + reg = <0x31 0x1>; + bits = <4 4>; + }; + tsadc_trim_base: tsadc-trim-base@32 { + reg = <0x32 0x1>; + }; }; i2s0_8ch: i2s@fe400000 { @@ -3374,13 +3395,28 @@ <&cru SRST_TSADCPHY>; reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; #thermal-sensor-cells = <1>; + nvmem-cells = <&tsadc_trim_base>, <&tsadc_trim_base_frac>; + nvmem-cell-names = "trim_base", "trim_base_frac"; rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ pinctrl-names = "gpio", "otpout"; pinctrl-0 = <&tsadc_gpio_func>; pinctrl-1 = <&tsadc_shutorg>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; + + tsadc@0 { + reg = <0>; + nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; + tsadc@1 { + reg = <1>; + nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; }; saradc: saradc@fe720000 {