vdin: horizontal floral stripe 4k afbc mode [1/1]

PD#SWPL-7391

Problem:
4k afbc mode, horizontal floral stripe in the lower half of
the screen when HDMI connect to PS4.

Solution:
when game mode and panel is reverse, vdin must delay
one frame, can't read/write the same buffer

Verify:
tl1

Change-Id: I42bb3271b8dd5972799b3dfda021b5c120710bdd
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2019-06-17 20:07:26 +08:00
committed by Tao Zeng
parent b8d9145a06
commit 01526afe34
5 changed files with 73 additions and 46 deletions

View File

@@ -1780,6 +1780,13 @@ void vlock_phaselock_check(struct stvlock_sig_sts *pvlock,
vlock_reset(1);
vlock_reset(0);
}
vlock.vdinsts.lcnt_sts =
READ_VPP_REG(0x1204/*VDIN_LCNT_STATUS*/);
vlock.vdinsts.com_sts0 =
READ_VPP_REG(0x1205/*VDIN_COM_STATUS0*/);
vlock.vdinsts.com_sts1 =
READ_VPP_REG(0x1206/*VDIN_COM_STATUS1*/);
}
}
}
@@ -2410,6 +2417,9 @@ void vlock_status(void)
pr_info("vinfo vtotal:%d\n", vinfo->vtotal);
pr_info("vframe input_hz:%d\n", vlock.input_hz);
pr_info("vframe output_hz:%d\n", vlock.output_hz);
pr_info("lcnt_sts :0x%0x\n", vlock.vdinsts.lcnt_sts);
pr_info("com_sts0 :0x%0x\n", vlock.vdinsts.com_sts0);
pr_info("com_sts1 :0x%0x\n", vlock.vdinsts.com_sts1);
}
void vlock_reg_dump(void)
@@ -2616,7 +2626,7 @@ static int __init phlock_phase_config(char *str)
pr_info("%s: bootargs is %s.\n", __func__, str);
if (strstr(ptr, "1"))
vlock.phlock_percent = 99;
vlock.phlock_percent = 15;
else
vlock.phlock_percent = 40;

View File

@@ -27,6 +27,12 @@
#define VLOCK_REG_NUM 33
struct vdin_sts {
unsigned int lcnt_sts;
unsigned int com_sts0;
unsigned int com_sts1;
};
struct vlock_log_s {
unsigned int pll_m;
unsigned int pll_frac;
@@ -81,6 +87,7 @@ struct stvlock_sig_sts {
struct vecm_match_data_s *dtdata;
u32 val_frac;
u32 val_m;
struct vdin_sts vdinsts;
};
extern void amve_vlock_process(struct vframe_s *vf);
extern void amve_vlock_resume(void);

View File

@@ -809,7 +809,8 @@ static void vdin_dump_state(struct vdin_dev_s *devp)
devp->vdin_irq_flag, devp->vdin_reset_flag,
devp->irq_cnt, devp->rdma_irq_cnt);
pr_info("vdin_drop_cnt: %d\n", vdin_drop_cnt);
pr_info("game_mode : %d\n", devp->game_mode);
pr_info("game_mode cfg : 0x%x\n", game_mode);
pr_info("game_mode cur: 0x%x\n", devp->game_mode);
pr_info("dolby_input : %d\n", devp->dv.dolby_input);
if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x100))
pr_info("dolby_mem_start = %ld, dolby_mem_size = %d\n",

View File

@@ -153,6 +153,9 @@ unsigned int vdin_drop_cnt;
module_param(vdin_drop_cnt, uint, 0664);
MODULE_PARM_DESC(vdin_drop_cnt, "vdin_drop_cnt");
static unsigned int panel_reverse;
struct vdin_hist_s vdin1_hist;
struct vdin_v4l2_param_s vdin_v4l2_param;
@@ -164,6 +167,17 @@ static void vdin_backup_histgram(struct vframe_s *vf, struct vdin_dev_s *devp);
char *vf_get_receiver_name(const char *provider_name);
static int __init vdin_get_video_reverse(char *str)
{
unsigned char *ptr = str;
pr_info("%s: bootargs is %s.\n", __func__, str);
if (strstr(ptr, "1"))
panel_reverse = 1;
return 0;
}
__setup("video_reverse=", vdin_get_video_reverse);
static void vdin_timer_func(unsigned long arg)
{
struct vdin_dev_s *devp = (struct vdin_dev_s *)arg;
@@ -279,7 +293,8 @@ static void vdin_game_mode_check(struct vdin_dev_s *devp)
(devp->parm.port != TVIN_PORT_CVBS3)) {
if (devp->h_active > 720 && ((devp->parm.info.fps == 50) ||
(devp->parm.info.fps == 60)))
if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) &&
(panel_reverse == 0)) {
devp->game_mode = (VDIN_GAME_MODE_0 |
VDIN_GAME_MODE_1 |
VDIN_GAME_MODE_SWITCH_EN);
@@ -304,6 +319,39 @@ static void vdin_game_mode_check(struct vdin_dev_s *devp)
pr_info("%s: game_mode flag=%d, game_mode=%d\n",
__func__, game_mode, devp->game_mode);
}
static void vdin_game_mode_transfer(struct vdin_dev_s *devp)
{
/*switch to game mode 2 from game mode 1,otherwise may appear blink*/
if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
if (devp->game_mode & VDIN_GAME_MODE_SWITCH_EN) {
/* make sure phase lock for next few frames */
if (vlock_get_phlock_flag())
phase_lock_flag++;
else
phase_lock_flag = 0;
if (phase_lock_flag >= game_mode_phlock_switch_frames) {
if (vdin_dbg_en) {
pr_info("switch game mode (%d-->5), frame_cnt=%d\n",
devp->game_mode,
devp->frame_cnt);
}
devp->game_mode = (VDIN_GAME_MODE_0 |
VDIN_GAME_MODE_2);
}
}
} else {
if ((devp->frame_cnt >= game_mode_switch_frames) &&
(devp->game_mode & VDIN_GAME_MODE_SWITCH_EN)) {
if (vdin_dbg_en) {
pr_info("switch game mode (%d-->5), frame_cnt=%d\n",
devp->game_mode, devp->frame_cnt);
}
devp->game_mode = (VDIN_GAME_MODE_0 | VDIN_GAME_MODE_2);
}
}
}
/*
*based on the bellow parameters:
* a.h_active (vf->width = devp->h_active)
@@ -1836,47 +1884,8 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
if (devp->vfp->skip_vf_num > 0)
vdin_vf_disp_mode_update(curr_wr_vfe, devp->vfp);
}
/*switch to game mode 2 from game mode 1,otherwise may appear blink*/
if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
if (devp->game_mode & VDIN_GAME_MODE_SWITCH_EN) {
/* make sure phase lock for next few frames */
if (vlock_get_phlock_flag())
phase_lock_flag++;
else
phase_lock_flag = 0;
if (phase_lock_flag >= game_mode_phlock_switch_frames) {
if (vdin_dbg_en) {
pr_info("switch game mode (%d-->5), frame_cnt=%d\n",
devp->game_mode,
devp->frame_cnt);
}
devp->game_mode = (VDIN_GAME_MODE_0 |
VDIN_GAME_MODE_2);
}
}
#if 0
if (phase_lock_flag >= game_mode_phlock_switch_frames) {
if (!vlock_get_phlock_flag())
phase_lock_flag = 0;
if (vdin_dbg_en) {
pr_info(
"switch game mode to %d, frame_cnt=%d\n",
devp->game_mode, devp->frame_cnt);
}
devp->game_mode = (VDIN_GAME_MODE_0 | VDIN_GAME_MODE_1 |
VDIN_GAME_MODE_SWITCH_EN);
}
#endif
} else {
if ((devp->frame_cnt >= game_mode_switch_frames) &&
(devp->game_mode & VDIN_GAME_MODE_SWITCH_EN)) {
if (vdin_dbg_en) {
pr_info("switch game mode (%d-->5), frame_cnt=%d\n",
devp->game_mode, devp->frame_cnt);
}
devp->game_mode = (VDIN_GAME_MODE_0 | VDIN_GAME_MODE_2);
}
}
vdin_game_mode_transfer(devp);
/* prepare for next input data */
next_wr_vfe = provider_vf_get(devp->vfp);

View File

@@ -91,9 +91,9 @@
/*values of vdin game mode process flag */
/*enable*/
#define VDIN_GAME_MODE_0 (1 << 0)
/*delay 1 frame*/
/*delay 1 frame, vdin have one frame buffer delay*/
#define VDIN_GAME_MODE_1 (1 << 1)
/*delay 2 frame*/
/*delay 2 frame write, read at same buffer*/
#define VDIN_GAME_MODE_2 (1 << 2)
/*when phase lock, will switch 2 to 1*/
#define VDIN_GAME_MODE_SWITCH_EN (1 << 3)