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vdin: horizontal floral stripe 4k afbc mode [1/1]
PD#SWPL-7391 Problem: 4k afbc mode, horizontal floral stripe in the lower half of the screen when HDMI connect to PS4. Solution: when game mode and panel is reverse, vdin must delay one frame, can't read/write the same buffer Verify: tl1 Change-Id: I42bb3271b8dd5972799b3dfda021b5c120710bdd Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
@@ -1780,6 +1780,13 @@ void vlock_phaselock_check(struct stvlock_sig_sts *pvlock,
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vlock_reset(1);
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vlock_reset(0);
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}
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vlock.vdinsts.lcnt_sts =
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READ_VPP_REG(0x1204/*VDIN_LCNT_STATUS*/);
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vlock.vdinsts.com_sts0 =
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READ_VPP_REG(0x1205/*VDIN_COM_STATUS0*/);
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vlock.vdinsts.com_sts1 =
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READ_VPP_REG(0x1206/*VDIN_COM_STATUS1*/);
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}
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}
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}
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@@ -2410,6 +2417,9 @@ void vlock_status(void)
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pr_info("vinfo vtotal:%d\n", vinfo->vtotal);
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pr_info("vframe input_hz:%d\n", vlock.input_hz);
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pr_info("vframe output_hz:%d\n", vlock.output_hz);
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pr_info("lcnt_sts :0x%0x\n", vlock.vdinsts.lcnt_sts);
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pr_info("com_sts0 :0x%0x\n", vlock.vdinsts.com_sts0);
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pr_info("com_sts1 :0x%0x\n", vlock.vdinsts.com_sts1);
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}
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void vlock_reg_dump(void)
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@@ -2616,7 +2626,7 @@ static int __init phlock_phase_config(char *str)
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pr_info("%s: bootargs is %s.\n", __func__, str);
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if (strstr(ptr, "1"))
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vlock.phlock_percent = 99;
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vlock.phlock_percent = 15;
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else
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vlock.phlock_percent = 40;
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@@ -27,6 +27,12 @@
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#define VLOCK_REG_NUM 33
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struct vdin_sts {
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unsigned int lcnt_sts;
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unsigned int com_sts0;
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unsigned int com_sts1;
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};
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struct vlock_log_s {
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unsigned int pll_m;
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unsigned int pll_frac;
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@@ -81,6 +87,7 @@ struct stvlock_sig_sts {
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struct vecm_match_data_s *dtdata;
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u32 val_frac;
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u32 val_m;
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struct vdin_sts vdinsts;
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};
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extern void amve_vlock_process(struct vframe_s *vf);
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extern void amve_vlock_resume(void);
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@@ -809,7 +809,8 @@ static void vdin_dump_state(struct vdin_dev_s *devp)
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devp->vdin_irq_flag, devp->vdin_reset_flag,
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devp->irq_cnt, devp->rdma_irq_cnt);
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pr_info("vdin_drop_cnt: %d\n", vdin_drop_cnt);
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pr_info("game_mode : %d\n", devp->game_mode);
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pr_info("game_mode cfg : 0x%x\n", game_mode);
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pr_info("game_mode cur: 0x%x\n", devp->game_mode);
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pr_info("dolby_input : %d\n", devp->dv.dolby_input);
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if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x100))
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pr_info("dolby_mem_start = %ld, dolby_mem_size = %d\n",
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@@ -153,6 +153,9 @@ unsigned int vdin_drop_cnt;
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module_param(vdin_drop_cnt, uint, 0664);
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MODULE_PARM_DESC(vdin_drop_cnt, "vdin_drop_cnt");
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static unsigned int panel_reverse;
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struct vdin_hist_s vdin1_hist;
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struct vdin_v4l2_param_s vdin_v4l2_param;
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@@ -164,6 +167,17 @@ static void vdin_backup_histgram(struct vframe_s *vf, struct vdin_dev_s *devp);
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char *vf_get_receiver_name(const char *provider_name);
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static int __init vdin_get_video_reverse(char *str)
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{
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unsigned char *ptr = str;
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pr_info("%s: bootargs is %s.\n", __func__, str);
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if (strstr(ptr, "1"))
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panel_reverse = 1;
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return 0;
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}
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__setup("video_reverse=", vdin_get_video_reverse);
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static void vdin_timer_func(unsigned long arg)
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{
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struct vdin_dev_s *devp = (struct vdin_dev_s *)arg;
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@@ -279,7 +293,8 @@ static void vdin_game_mode_check(struct vdin_dev_s *devp)
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(devp->parm.port != TVIN_PORT_CVBS3)) {
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if (devp->h_active > 720 && ((devp->parm.info.fps == 50) ||
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(devp->parm.info.fps == 60)))
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if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
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if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) &&
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(panel_reverse == 0)) {
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devp->game_mode = (VDIN_GAME_MODE_0 |
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VDIN_GAME_MODE_1 |
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VDIN_GAME_MODE_SWITCH_EN);
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@@ -304,6 +319,39 @@ static void vdin_game_mode_check(struct vdin_dev_s *devp)
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pr_info("%s: game_mode flag=%d, game_mode=%d\n",
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__func__, game_mode, devp->game_mode);
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}
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static void vdin_game_mode_transfer(struct vdin_dev_s *devp)
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{
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/*switch to game mode 2 from game mode 1,otherwise may appear blink*/
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if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
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if (devp->game_mode & VDIN_GAME_MODE_SWITCH_EN) {
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/* make sure phase lock for next few frames */
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if (vlock_get_phlock_flag())
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phase_lock_flag++;
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else
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phase_lock_flag = 0;
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if (phase_lock_flag >= game_mode_phlock_switch_frames) {
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if (vdin_dbg_en) {
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pr_info("switch game mode (%d-->5), frame_cnt=%d\n",
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devp->game_mode,
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devp->frame_cnt);
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}
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devp->game_mode = (VDIN_GAME_MODE_0 |
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VDIN_GAME_MODE_2);
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}
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}
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} else {
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if ((devp->frame_cnt >= game_mode_switch_frames) &&
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(devp->game_mode & VDIN_GAME_MODE_SWITCH_EN)) {
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if (vdin_dbg_en) {
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pr_info("switch game mode (%d-->5), frame_cnt=%d\n",
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devp->game_mode, devp->frame_cnt);
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}
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devp->game_mode = (VDIN_GAME_MODE_0 | VDIN_GAME_MODE_2);
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}
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}
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}
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/*
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*based on the bellow parameters:
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* a.h_active (vf->width = devp->h_active)
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@@ -1836,47 +1884,8 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
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if (devp->vfp->skip_vf_num > 0)
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vdin_vf_disp_mode_update(curr_wr_vfe, devp->vfp);
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}
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/*switch to game mode 2 from game mode 1,otherwise may appear blink*/
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if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
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if (devp->game_mode & VDIN_GAME_MODE_SWITCH_EN) {
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/* make sure phase lock for next few frames */
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if (vlock_get_phlock_flag())
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phase_lock_flag++;
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else
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phase_lock_flag = 0;
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if (phase_lock_flag >= game_mode_phlock_switch_frames) {
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if (vdin_dbg_en) {
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pr_info("switch game mode (%d-->5), frame_cnt=%d\n",
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devp->game_mode,
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devp->frame_cnt);
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}
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devp->game_mode = (VDIN_GAME_MODE_0 |
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VDIN_GAME_MODE_2);
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}
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}
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#if 0
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if (phase_lock_flag >= game_mode_phlock_switch_frames) {
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if (!vlock_get_phlock_flag())
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phase_lock_flag = 0;
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if (vdin_dbg_en) {
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pr_info(
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"switch game mode to %d, frame_cnt=%d\n",
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devp->game_mode, devp->frame_cnt);
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}
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devp->game_mode = (VDIN_GAME_MODE_0 | VDIN_GAME_MODE_1 |
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VDIN_GAME_MODE_SWITCH_EN);
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}
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#endif
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} else {
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if ((devp->frame_cnt >= game_mode_switch_frames) &&
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(devp->game_mode & VDIN_GAME_MODE_SWITCH_EN)) {
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if (vdin_dbg_en) {
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pr_info("switch game mode (%d-->5), frame_cnt=%d\n",
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devp->game_mode, devp->frame_cnt);
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}
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devp->game_mode = (VDIN_GAME_MODE_0 | VDIN_GAME_MODE_2);
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}
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}
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vdin_game_mode_transfer(devp);
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/* prepare for next input data */
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next_wr_vfe = provider_vf_get(devp->vfp);
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@@ -91,9 +91,9 @@
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/*values of vdin game mode process flag */
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/*enable*/
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#define VDIN_GAME_MODE_0 (1 << 0)
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/*delay 1 frame*/
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/*delay 1 frame, vdin have one frame buffer delay*/
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#define VDIN_GAME_MODE_1 (1 << 1)
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/*delay 2 frame*/
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/*delay 2 frame write, read at same buffer*/
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#define VDIN_GAME_MODE_2 (1 << 2)
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/*when phase lock, will switch 2 to 1*/
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#define VDIN_GAME_MODE_SWITCH_EN (1 << 3)
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