From 015580a0086ac402b878906dbf89adfc463b83fd Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Fri, 29 Dec 2017 09:56:49 +0800 Subject: [PATCH] clk: rockchip: clk-ddr: fix section mismatch problem In rockchip_clk_register_ddrclk, ifdef CONFIG_ARM if (!psci_smp_available()) return NULL; endif Add "__init" for rockchip_clk_register_ddrclk() to match with psci_smp_available(). Change-Id: Ib6849e359921c3a937bf8dc4f6547aed353f1071 Signed-off-by: Jianqun Xu --- drivers/clk/rockchip/clk-ddr.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 23719546f21c..3e3b65732e7a 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -306,12 +306,13 @@ static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = { .get_parent = rockchip_ddrclk_get_parent, }; -struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, - const char *const *parent_names, - u8 num_parents, int mux_offset, - int mux_shift, int mux_width, - int div_shift, int div_width, - int ddr_flag, void __iomem *reg_base) +struct clk * __init +rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, + u8 num_parents, int mux_offset, + int mux_shift, int mux_width, + int div_shift, int div_width, + int ddr_flag, void __iomem *reg_base) { struct rockchip_ddrclk *ddrclk; struct clk_init_data init;