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Merge ad8f71d64a ("tools/bootconfig: Fix the wrong format specifier") into android14-6.1-lts

Browse Source 
Steps on the way to 6.1.129

Change-Id: I30bcf71d285ba65a092b9a4899532cde31208c48
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2025-03-06 19:13:57 +00:00
parent 3e716b1ee2 ad8f71d64a
commit 015c802557
74 changed files with 394 additions and 335 deletions
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2
arch/arm/boot/dts/mt7623.dtsi
View File

@@ -309,7 +309,7 @@
clock-names = "spi", "wrap";
};
cir: cir@10013000 {
cir: ir-receiver@10013000 {
compatible = "mediatek,mt7623-cir";
reg = <0 0x10013000 0 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;

31
arch/arm/mach-at91/pm.c
View File

@@ -590,7 +590,21 @@ static int at91_suspend_finish(unsigned long val)
return 0;
}
static void at91_pm_switch_ba_to_vbat(void)
/**
* at91_pm_switch_ba_to_auto() - Configure Backup Unit Power Switch
* to automatic/hardware mode.
*
* The Backup Unit Power Switch can be managed either by software or hardware.
* Enabling hardware mode allows the automatic transition of power between
* VDDANA (or VDDIN33) and VDDBU (or VBAT, respectively), based on the
* availability of these power sources.
*
* If the Backup Unit Power Switch is already in automatic mode, no action is
* required. If it is in software-controlled mode, it is switched to automatic
* mode to enhance safety and eliminate the need for toggling between power
* sources.
*/
static void at91_pm_switch_ba_to_auto(void)
{
unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
unsigned int val;
@@ -601,24 +615,19 @@ static void at91_pm_switch_ba_to_vbat(void)
val = readl(soc_pm.data.sfrbu + offset);
/* Already on VBAT. */
if (!(val & soc_pm.sfrbu_regs.pswbu.state))
/* Already on auto/hardware. */
if (!(val & soc_pm.sfrbu_regs.pswbu.ctrl))
return;
val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
val &= ~soc_pm.sfrbu_regs.pswbu.ctrl;
val |= soc_pm.sfrbu_regs.pswbu.key;
writel(val, soc_pm.data.sfrbu + offset);
/* Wait for update. */
val = readl(soc_pm.data.sfrbu + offset);
while (val & soc_pm.sfrbu_regs.pswbu.state)
val = readl(soc_pm.data.sfrbu + offset);
}
static void at91_pm_suspend(suspend_state_t state)
{
if (soc_pm.data.mode == AT91_PM_BACKUP) {
at91_pm_switch_ba_to_vbat();
at91_pm_switch_ba_to_auto();
cpu_suspend(0, at91_suspend_finish);

29
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
View File

@@ -922,7 +922,7 @@
interrupt-controller;
#interrupt-cells = <2>;
clock: mt6397clock {
clock: clocks {
compatible = "mediatek,mt6397-clk";
#clock-cells = <1>;
};
@@ -934,11 +934,10 @@
#gpio-cells = <2>;
};
regulator: mt6397regulator {
regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -948,7 +947,6 @@
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-compatible = "buck_vpca7";
regulator-name = "vpca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -958,7 +956,6 @@
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-compatible = "buck_vsramca15";
regulator-name = "vsramca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -967,7 +964,6 @@
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-compatible = "buck_vsramca7";
regulator-name = "vsramca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -976,7 +972,6 @@
};
mt6397_vcore_reg: buck_vcore {
regulator-compatible = "buck_vcore";
regulator-name = "vcore";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -985,7 +980,6 @@
};
mt6397_vgpu_reg: buck_vgpu {
regulator-compatible = "buck_vgpu";
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -994,7 +988,6 @@
};
mt6397_vdrm_reg: buck_vdrm {
regulator-compatible = "buck_vdrm";
regulator-name = "vdrm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
@@ -1003,7 +996,6 @@
};
mt6397_vio18_reg: buck_vio18 {
regulator-compatible = "buck_vio18";
regulator-name = "vio18";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
@@ -1012,18 +1004,15 @@
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-compatible = "ldo_vtcxo";
regulator-name = "vtcxo";
regulator-always-on;
};
mt6397_va28_reg: ldo_va28 {
regulator-compatible = "ldo_va28";
regulator-name = "va28";
};
mt6397_vcama_reg: ldo_vcama {
regulator-compatible = "ldo_vcama";
regulator-name = "vcama";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -1031,18 +1020,15 @@
};
mt6397_vio28_reg: ldo_vio28 {
regulator-compatible = "ldo_vio28";
regulator-name = "vio28";
regulator-always-on;
};
mt6397_vusb_reg: ldo_vusb {
regulator-compatible = "ldo_vusb";
regulator-name = "vusb";
};
mt6397_vmc_reg: ldo_vmc {
regulator-compatible = "ldo_vmc";
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@@ -1050,7 +1036,6 @@
};
mt6397_vmch_reg: ldo_vmch {
regulator-compatible = "ldo_vmch";
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@@ -1058,7 +1043,6 @@
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-compatible = "ldo_vemc3v3";
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@@ -1066,7 +1050,6 @@
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-compatible = "ldo_vgp1";
regulator-name = "vcamd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -1074,7 +1057,6 @@
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-compatible = "ldo_vgp2";
regulator-name = "vcamio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -1082,7 +1064,6 @@
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-compatible = "ldo_vgp3";
regulator-name = "vcamaf";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -1090,7 +1071,6 @@
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -1098,7 +1078,6 @@
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-compatible = "ldo_vgp5";
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
@@ -1106,7 +1085,6 @@
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-compatible = "ldo_vgp6";
regulator-name = "vgp6";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -1115,7 +1093,6 @@
};
mt6397_vibr_reg: ldo_vibr {
regulator-compatible = "ldo_vibr";
regulator-name = "vibr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <3300000>;
@@ -1123,7 +1100,7 @@
};
};
rtc: mt6397rtc {
rtc: rtc {
compatible = "mediatek,mt6397-rtc";
};

25
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View File

@@ -307,11 +307,10 @@
interrupt-controller;
#interrupt-cells = <2>;
mt6397regulator: mt6397regulator {
regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -320,7 +319,6 @@
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-compatible = "buck_vpca7";
regulator-name = "vpca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -329,7 +327,6 @@
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-compatible = "buck_vsramca15";
regulator-name = "vsramca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -338,7 +335,6 @@
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-compatible = "buck_vsramca7";
regulator-name = "vsramca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -347,7 +343,6 @@
};
mt6397_vcore_reg: buck_vcore {
regulator-compatible = "buck_vcore";
regulator-name = "vcore";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -356,7 +351,6 @@
};
mt6397_vgpu_reg: buck_vgpu {
regulator-compatible = "buck_vgpu";
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -365,7 +359,6 @@
};
mt6397_vdrm_reg: buck_vdrm {
regulator-compatible = "buck_vdrm";
regulator-name = "vdrm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
@@ -374,7 +367,6 @@
};
mt6397_vio18_reg: buck_vio18 {
regulator-compatible = "buck_vio18";
regulator-name = "vio18";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
@@ -383,19 +375,16 @@
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-compatible = "ldo_vtcxo";
regulator-name = "vtcxo";
regulator-always-on;
};
mt6397_va28_reg: ldo_va28 {
regulator-compatible = "ldo_va28";
regulator-name = "va28";
regulator-always-on;
};
mt6397_vcama_reg: ldo_vcama {
regulator-compatible = "ldo_vcama";
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
@@ -403,18 +392,15 @@
};
mt6397_vio28_reg: ldo_vio28 {
regulator-compatible = "ldo_vio28";
regulator-name = "vio28";
regulator-always-on;
};
mt6397_vusb_reg: ldo_vusb {
regulator-compatible = "ldo_vusb";
regulator-name = "vusb";
};
mt6397_vmc_reg: ldo_vmc {
regulator-compatible = "ldo_vmc";
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@@ -422,7 +408,6 @@
};
mt6397_vmch_reg: ldo_vmch {
regulator-compatible = "ldo_vmch";
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@@ -430,7 +415,6 @@
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-compatible = "ldo_vemc3v3";
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@@ -438,7 +422,6 @@
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-compatible = "ldo_vgp1";
regulator-name = "vcamd";
regulator-min-microvolt = <1220000>;
regulator-max-microvolt = <3300000>;
@@ -446,7 +429,6 @@
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-compatible = "ldo_vgp2";
regulator-name = "vcamio";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
@@ -454,7 +436,6 @@
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-compatible = "ldo_vgp3";
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -462,7 +443,6 @@
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -470,7 +450,6 @@
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-compatible = "ldo_vgp5";
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
@@ -478,7 +457,6 @@
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-compatible = "ldo_vgp6";
regulator-name = "vgp6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -486,7 +464,6 @@
};
mt6397_vibr_reg: ldo_vibr {
regulator-compatible = "ldo_vibr";
regulator-name = "vibr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <3300000>;

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
View File

@@ -26,6 +26,10 @@
hid-descr-addr = <0x0001>;
};
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_DAMU";
};

15
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
View File

@@ -11,3 +11,18 @@
model = "Google kenzo sku17 board";
compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
};
&i2c0 {
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <70>;
hid-descr-addr = <0x0001>;
};
};

15
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
View File

@@ -6,6 +6,21 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
&i2c0 {
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <70>;
hid-descr-addr = <0x0001>;
};
};
&i2c2 {
trackpad@2c {
compatible = "hid-over-i2c";

2
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@@ -39,8 +39,6 @@
pp3300_panel: pp3300-panel {
compatible = "regulator-fixed";
regulator-name = "pp3300_panel";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pp3300_panel_pins>;

3
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View File

@@ -901,7 +901,6 @@
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@@ -911,7 +910,6 @@
};
mt6315_6_vbuck3: vbuck3 {
regulator-compatible = "vbuck3";
regulator-name = "Vlcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@@ -928,7 +926,6 @@
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <800000>;

2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@@ -843,7 +843,6 @@
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@@ -861,7 +860,6 @@
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;

9
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
View File

@@ -120,7 +120,6 @@
richtek,vinovp-microvolt = <14500000>;
otg_vbus_regulator: usb-otg-vbus-regulator {
regulator-compatible = "usb-otg-vbus";
regulator-name = "usb-otg-vbus";
regulator-min-microvolt = <4425000>;
regulator-max-microvolt = <5825000>;
@@ -132,7 +131,6 @@
LDO_VIN3-supply = <&mt6360_buck2>;
mt6360_buck1: buck1 {
regulator-compatible = "BUCK1";
regulator-name = "mt6360,buck1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
@@ -143,7 +141,6 @@
};
mt6360_buck2: buck2 {
regulator-compatible = "BUCK2";
regulator-name = "mt6360,buck2";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
@@ -154,7 +151,6 @@
};
mt6360_ldo1: ldo1 {
regulator-compatible = "LDO1";
regulator-name = "mt6360,ldo1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@@ -163,7 +159,6 @@
};
mt6360_ldo2: ldo2 {
regulator-compatible = "LDO2";
regulator-name = "mt6360,ldo2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@@ -172,7 +167,6 @@
};
mt6360_ldo3: ldo3 {
regulator-compatible = "LDO3";
regulator-name = "mt6360,ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@@ -181,7 +175,6 @@
};
mt6360_ldo5: ldo5 {
regulator-compatible = "LDO5";
regulator-name = "mt6360,ldo5";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3600000>;
@@ -190,7 +183,6 @@
};
mt6360_ldo6: ldo6 {
regulator-compatible = "LDO6";
regulator-name = "mt6360,ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
@@ -199,7 +191,6 @@
};
mt6360_ldo7: ldo7 {
regulator-compatible = "LDO7";
regulator-name = "mt6360,ldo7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;

2
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@@ -2000,7 +2000,7 @@
};
ovl0: ovl@1c000000 {
compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
compatible = "mediatek,mt8195-disp-ovl";
reg = <0 0x1c000000 0 0x1000>;
interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

11
arch/arm64/boot/dts/mediatek/mt8516.dtsi
View File

@@ -144,10 +144,10 @@
#size-cells = <2>;
ranges;
/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@43000000 {
no-map;
reg = <0 0x43000000 0 0x20000>;
reg = <0 0x43000000 0 0x30000>;
};
};
@@ -206,7 +206,7 @@
compatible = "mediatek,mt8516-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x1000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
#reset-cells = <1>;
};
@@ -269,7 +269,7 @@
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10310000 0 0x1000>,
<0 0x10320000 0 0x1000>,
<0 0x1032f000 0 0x2000>,
<0 0x10340000 0 0x2000>,
<0 0x10360000 0 0x2000>;
interrupts = <GIC_PPI 9
@@ -345,6 +345,7 @@
reg = <0 0x11009000 0 0x90>,
<0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C0>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";
@@ -359,6 +360,7 @@
reg = <0 0x1100a000 0 0x90>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C1>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";
@@ -373,6 +375,7 @@
reg = <0 0x1100b000 0 0x90>,
<0 0x11000280 0 0x80>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C2>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";

2
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
View File

@@ -47,7 +47,6 @@
};
&i2c0 {
clock-div = <2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
@@ -156,7 +155,6 @@
};
&i2c2 {
clock-div = <2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";

2
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@@ -109,7 +109,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
};
};

11
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@@ -33,7 +33,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
@@ -434,6 +434,15 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,

2
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@@ -65,7 +65,7 @@
};
led@1 {
reg = <0>;
reg = <1>;
chan-name = "button-backlight1";
led-cur = /bits/ 8 <0x32>;
max-cur = /bits/ 8 <0xC8>;

9
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@@ -2968,9 +2968,14 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,

2
arch/arm64/boot/dts/qcom/pm6150.dtsi
View File

@@ -11,7 +11,7 @@
thermal-zones {
pm6150_thermal: pm6150-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm6150_temp>;
trips {

35
arch/arm64/boot/dts/qcom/pm6150l.dtsi
View File

@@ -5,6 +5,34 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm6150l-thermal {
thermal-sensors = <&pm6150l_temp>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pm6150l_lsid4: pmic@4 {
compatible = "qcom,pm6150l", "qcom,spmi-pmic";
@@ -12,6 +40,13 @@
#address-cells = <1>;
#size-cells = <0>;
pm6150l_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm6150l_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;

15
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View File

@@ -306,14 +306,9 @@
reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
@@ -333,10 +328,6 @@
vdds-supply = <&vreg_l4a_0p8>;
};
&mdp {
status = "okay";
};
&mdss {
status = "okay";
};

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
View File

@@ -26,7 +26,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <965>;

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View File

@@ -43,7 +43,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <965>;

7
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
View File

@@ -12,14 +12,11 @@
/ {
thermal-zones {
5v-choke-thermal {
polling-delay-passive = <0>;
polling-delay = <250>;
choke-5v-thermal {
thermal-sensors = <&pm6150_adc_tm 1>;
trips {
5v-choke-crit {
choke-5v-crit {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";

12
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
View File

@@ -60,19 +60,15 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_rst>;
avdd-supply = <&ppvar_lcd>;
avee-supply = <&ppvar_lcd>;
pp1800-supply = <&v1p8_disp>;
pp3300-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
rotation = <270>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};

12
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
View File

@@ -50,7 +50,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <574>;
@@ -124,14 +123,9 @@
backlight = <&backlight>;
rotation = <270>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};

9
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@@ -20,9 +20,6 @@
/ {
thermal-zones {
charger_thermal: charger-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 0>;
trips {
@@ -777,6 +774,10 @@ hp_i2c: &i2c9 {
};
};
&lpasscc {
status = "okay";
};
&lpass_cpu {
status = "okay";
@@ -802,7 +803,7 @@ hp_i2c: &i2c9 {
};
};
&mdp {
&lpass_hm {
status = "okay";
};

34
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@@ -2937,8 +2937,6 @@
interrupt-parent = <&mdss>;
interrupts = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2985,7 +2983,8 @@
};
dsi0: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
compatible = "qcom,sc7180-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
@@ -3576,6 +3575,8 @@
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
#clock-cells = <1>;
#power-domain-cells = <1>;
status = "reserved"; /* Controlled by ADSP */
};
lpass_cpu: lpass@62d87000 {
@@ -3621,13 +3622,14 @@
clock-names = "iface", "bi_tcxo";
#clock-cells = <1>;
#power-domain-cells = <1>;
status = "reserved"; /* Controlled by ADSP */
};
};
thermal-zones {
cpu0_thermal: cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
sustainable-power = <1052>;
@@ -3676,7 +3678,6 @@
cpu1_thermal: cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
sustainable-power = <1052>;
@@ -3725,7 +3726,6 @@
cpu2_thermal: cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
sustainable-power = <1052>;
@@ -3774,7 +3774,6 @@
cpu3_thermal: cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
sustainable-power = <1052>;
@@ -3823,7 +3822,6 @@
cpu4_thermal: cpu4-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
sustainable-power = <1052>;
@@ -3872,7 +3870,6 @@
cpu5_thermal: cpu5-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
sustainable-power = <1052>;
@@ -3921,7 +3918,6 @@
cpu6_thermal: cpu6-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
sustainable-power = <1425>;
@@ -3962,7 +3958,6 @@
cpu7_thermal: cpu7-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
sustainable-power = <1425>;
@@ -4003,7 +3998,6 @@
cpu8_thermal: cpu8-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
sustainable-power = <1425>;
@@ -4044,7 +4038,6 @@
cpu9_thermal: cpu9-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
sustainable-power = <1425>;
@@ -4085,7 +4078,6 @@
aoss0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
@@ -4106,7 +4098,6 @@
cpuss0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
@@ -4126,7 +4117,6 @@
cpuss1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
@@ -4146,7 +4136,6 @@
gpuss0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
@@ -4174,7 +4163,6 @@
gpuss1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
@@ -4202,7 +4190,6 @@
aoss1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
@@ -4223,7 +4210,6 @@
cwlan-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
@@ -4244,7 +4230,6 @@
audio-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
@@ -4265,7 +4250,6 @@
ddr-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
@@ -4286,7 +4270,6 @@
q6-hvx-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
@@ -4307,7 +4290,6 @@
camera-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
@@ -4328,7 +4310,6 @@
mdm-core-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 6>;
@@ -4349,7 +4330,6 @@
mdm-dsp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 7>;
@@ -4370,7 +4350,6 @@
npu-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 8>;
@@ -4391,7 +4370,6 @@
video-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 9>;

2
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@@ -79,7 +79,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};

6
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@@ -1119,7 +1119,7 @@
remoteproc_adsp: remoteproc@3000000 {
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x100>;
reg = <0 0x03000000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1806,7 +1806,7 @@
remoteproc_nsp0: remoteproc@1b300000 {
compatible = "qcom,sc8280xp-nsp0-pas";
reg = <0 0x1b300000 0 0x100>;
reg = <0 0x1b300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1937,7 +1937,7 @@
remoteproc_nsp1: remoteproc@21300000 {
compatible = "qcom,sc8280xp-nsp1-pas";
reg = <0 0x21300000 0 0x100>;
reg = <0 0x21300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,

20
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@@ -4234,16 +4234,16 @@
"vfe1",
"vfe_lite";
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid0",
"csid1",
"csid2",

2
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@@ -27,7 +27,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};

2
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
View File

@@ -20,7 +20,7 @@
chassis-type = "handset";
/* required for bootloader to select correct board */
qcom,msm-id = <434 0x10000>, <459 0x10000>;
qcom,msm-id = <459 0x10000>;
qcom,board-id = <8 32>;
aliases {

4
arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
View File

@@ -376,8 +376,8 @@
pinctrl-0 = <&da7280_intr_default>;
dlg,actuator-type = "LRA";
dlg,dlg,const-op-mode = <1>;
dlg,dlg,periodic-op-mode = <1>;
dlg,const-op-mode = <1>;
dlg,periodic-op-mode = <1>;
dlg,nom-microvolt = <2000000>;
dlg,abs-max-microvolt = <2000000>;
dlg,imax-microamp = <129000>;

30
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@@ -84,7 +84,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
@@ -3291,20 +3291,20 @@
"vfe_lite0",
"vfe_lite1";
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",

2
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@@ -34,7 +34,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};

2
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@@ -33,7 +33,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-frequency = <32764>;
};
};

1
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
View File

@@ -23,7 +23,6 @@
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */

1
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
View File

@@ -18,7 +18,6 @@
compatible = "arm,gic-v3";
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */

2
drivers/firmware/efi/sysfb_efi.c
View File

@@ -91,6 +91,7 @@ void efifb_setup_from_dmi(struct screen_info *si, const char *opt)
_ret_; \
})
#ifdef CONFIG_EFI
static int __init efifb_set_system(const struct dmi_system_id *id)
{
struct efifb_dmi_info *info = id->driver_data;
@@ -346,7 +347,6 @@ static const struct fwnode_operations efifb_fwnode_ops = {
.add_links = efifb_add_links,
};
#ifdef CONFIG_EFI
static struct fwnode_handle efifb_fwnode;
__init void sysfb_apply_efi_quirks(void)

6
drivers/infiniband/hw/cxgb4/device.c
View File

@@ -1114,8 +1114,10 @@ static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
* The math here assumes sizeof cpl_pass_accept_req >= sizeof
* cpl_rx_pkt.
*/
skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
skb = alloc_skb(size_add(gl->tot_len,
sizeof(struct cpl_pass_accept_req) +
sizeof(struct rss_header)) - pktshift,
GFP_ATOMIC);
if (unlikely(!skb))
return NULL;

6
drivers/infiniband/hw/mlx4/main.c
View File

@@ -384,10 +384,10 @@ static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context)
}
spin_unlock_bh(&iboe->lock);
if (!ret && hw_update) {
if (gids)
ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
kfree(gids);
}
kfree(gids);
return ret;
}

32
drivers/infiniband/hw/mlx5/odp.c
View File

@@ -808,8 +808,7 @@ static bool mkey_is_eq(struct mlx5_ib_mkey *mmkey, u32 key)
/*
* Handle a single data segment in a page-fault WQE or RDMA region.
*
* Returns number of OS pages retrieved on success. The caller may continue to
* the next data segment.
* Returns zero on success. The caller may continue to the next data segment.
* Can return the following error codes:
* -EAGAIN to designate a temporary error. The caller will abort handling the
* page fault and resolve it.
@@ -822,7 +821,7 @@ static int pagefault_single_data_segment(struct mlx5_ib_dev *dev,
u32 *bytes_committed,
u32 *bytes_mapped)
{
int npages = 0, ret, i, outlen, cur_outlen = 0, depth = 0;
int ret, i, outlen, cur_outlen = 0, depth = 0, pages_in_range;
struct pf_frame *head = NULL, *frame;
struct mlx5_ib_mkey *mmkey;
struct mlx5_ib_mr *mr;
@@ -865,13 +864,20 @@ next_mr:
case MLX5_MKEY_MR:
mr = container_of(mmkey, struct mlx5_ib_mr, mmkey);
pages_in_range = (ALIGN(io_virt + bcnt, PAGE_SIZE) -
(io_virt & PAGE_MASK)) >>
PAGE_SHIFT;
ret = pagefault_mr(mr, io_virt, bcnt, bytes_mapped, 0, false);
if (ret < 0)
goto end;
mlx5_update_odp_stats(mr, faults, ret);
npages += ret;
if (ret < pages_in_range) {
ret = -EFAULT;
goto end;
}
ret = 0;
break;
@@ -962,7 +968,7 @@ end:
kfree(out);
*bytes_committed = 0;
return ret ? ret : npages;
return ret;
}
/*
@@ -981,8 +987,7 @@ end:
* the committed bytes).
* @receive_queue: receive WQE end of sg list
*
* Returns the number of pages loaded if positive, zero for an empty WQE, or a
* negative error code.
* Returns zero for success or a negative error code.
*/
static int pagefault_data_segments(struct mlx5_ib_dev *dev,
struct mlx5_pagefault *pfault,
@@ -990,7 +995,7 @@ static int pagefault_data_segments(struct mlx5_ib_dev *dev,
void *wqe_end, u32 *bytes_mapped,
u32 *total_wqe_bytes, bool receive_queue)
{
int ret = 0, npages = 0;
int ret = 0;
u64 io_virt;
u32 key;
u32 byte_count;
@@ -1046,10 +1051,9 @@ static int pagefault_data_segments(struct mlx5_ib_dev *dev,
bytes_mapped);
if (ret < 0)
break;
npages += ret;
}
return ret < 0 ? ret : npages;
return ret;
}
/*
@@ -1285,12 +1289,6 @@ resolve_page_fault:
free_page((unsigned long)wqe_start);
}
static int pages_in_range(u64 address, u32 length)
{
return (ALIGN(address + length, PAGE_SIZE) -
(address & PAGE_MASK)) >> PAGE_SHIFT;
}
static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev,
struct mlx5_pagefault *pfault)
{
@@ -1329,7 +1327,7 @@ static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev,
if (ret == -EAGAIN) {
/* We're racing with an invalidation, don't prefetch */
prefetch_activated = 0;
} else if (ret < 0 || pages_in_range(address, length) > ret) {
} else if (ret < 0) {
mlx5_ib_page_fault_resume(dev, pfault, 1);
if (ret != -ENOENT)
mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%x, type: 0x%x\n",

11
drivers/infiniband/sw/rxe/rxe_pool.c
View File

@@ -221,7 +221,6 @@ int __rxe_cleanup(struct rxe_pool_elem *elem, bool sleepable)
{
struct rxe_pool *pool = elem->pool;
struct xarray *xa = &pool->xa;
static int timeout = RXE_POOL_TIMEOUT;
int ret, err = 0;
void *xa_ret;
@@ -245,19 +244,19 @@ int __rxe_cleanup(struct rxe_pool_elem *elem, bool sleepable)
* return to rdma-core
*/
if (sleepable) {
if (!completion_done(&elem->complete) && timeout) {
if (!completion_done(&elem->complete)) {
ret = wait_for_completion_timeout(&elem->complete,
timeout);
msecs_to_jiffies(50000));
/* Shouldn't happen. There are still references to
* the object but, rather than deadlock, free the
* object or pass back to rdma-core.
*/
if (WARN_ON(!ret))
err = -EINVAL;
err = -ETIMEDOUT;
}
} else {
unsigned long until = jiffies + timeout;
unsigned long until = jiffies + RXE_POOL_TIMEOUT;
/* AH objects are unique in that the destroy_ah verb
* can be called in atomic context. This delay
@@ -269,7 +268,7 @@ int __rxe_cleanup(struct rxe_pool_elem *elem, bool sleepable)
mdelay(1);
if (WARN_ON(!completion_done(&elem->complete)))
err = -EINVAL;
err = -ETIMEDOUT;
}
if (pool->cleanup)

1
drivers/infiniband/ulp/srp/ib_srp.c
View File

@@ -3983,7 +3983,6 @@ static struct srp_host *srp_add_port(struct srp_device *device, u32 port)
return host;
put_host:
device_del(&host->dev);
put_device(&host->dev);
return NULL;
}

42
drivers/media/i2c/imx412.c
View File

@@ -549,7 +549,7 @@ static int imx412_update_exp_gain(struct imx412 *imx412, u32 exposure, u32 gain)
lpfr = imx412->vblank + imx412->cur_mode->height;
dev_dbg(imx412->dev, "Set exp %u, analog gain %u, lpfr %u",
dev_dbg(imx412->dev, "Set exp %u, analog gain %u, lpfr %u\n",
exposure, gain, lpfr);
ret = imx412_write_reg(imx412, IMX412_REG_HOLD, 1, 1);
@@ -596,7 +596,7 @@ static int imx412_set_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_VBLANK:
imx412->vblank = imx412->vblank_ctrl->val;
dev_dbg(imx412->dev, "Received vblank %u, new lpfr %u",
dev_dbg(imx412->dev, "Received vblank %u, new lpfr %u\n",
imx412->vblank,
imx412->vblank + imx412->cur_mode->height);
@@ -615,7 +615,7 @@ static int imx412_set_ctrl(struct v4l2_ctrl *ctrl)
exposure = ctrl->val;
analog_gain = imx412->again_ctrl->val;
dev_dbg(imx412->dev, "Received exp %u, analog gain %u",
dev_dbg(imx412->dev, "Received exp %u, analog gain %u\n",
exposure, analog_gain);
ret = imx412_update_exp_gain(imx412, exposure, analog_gain);
@@ -624,7 +624,7 @@ static int imx412_set_ctrl(struct v4l2_ctrl *ctrl)
break;
default:
dev_err(imx412->dev, "Invalid control %d", ctrl->id);
dev_err(imx412->dev, "Invalid control %d\n", ctrl->id);
ret = -EINVAL;
}
@@ -805,14 +805,14 @@ static int imx412_start_streaming(struct imx412 *imx412)
ret = imx412_write_regs(imx412, reg_list->regs,
reg_list->num_of_regs);
if (ret) {
dev_err(imx412->dev, "fail to write initial registers");
dev_err(imx412->dev, "fail to write initial registers\n");
return ret;
}
/* Setup handler will write actual exposure and gain */
ret = __v4l2_ctrl_handler_setup(imx412->sd.ctrl_handler);
if (ret) {
dev_err(imx412->dev, "fail to setup handler");
dev_err(imx412->dev, "fail to setup handler\n");
return ret;
}
@@ -823,7 +823,7 @@ static int imx412_start_streaming(struct imx412 *imx412)
ret = imx412_write_reg(imx412, IMX412_REG_MODE_SELECT,
1, IMX412_MODE_STREAMING);
if (ret) {
dev_err(imx412->dev, "fail to start streaming");
dev_err(imx412->dev, "fail to start streaming\n");
return ret;
}
@@ -904,7 +904,7 @@ static int imx412_detect(struct imx412 *imx412)
return ret;
if (val != IMX412_ID) {
dev_err(imx412->dev, "chip id mismatch: %x!=%x",
dev_err(imx412->dev, "chip id mismatch: %x!=%x\n",
IMX412_ID, val);
return -ENXIO;
}
@@ -936,7 +936,7 @@ static int imx412_parse_hw_config(struct imx412 *imx412)
imx412->reset_gpio = devm_gpiod_get_optional(imx412->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(imx412->reset_gpio)) {
dev_err(imx412->dev, "failed to get reset gpio %ld",
dev_err(imx412->dev, "failed to get reset gpio %ld\n",
PTR_ERR(imx412->reset_gpio));
return PTR_ERR(imx412->reset_gpio);
}
@@ -944,13 +944,13 @@ static int imx412_parse_hw_config(struct imx412 *imx412)
/* Get sensor input clock */
imx412->inclk = devm_clk_get(imx412->dev, NULL);
if (IS_ERR(imx412->inclk)) {
dev_err(imx412->dev, "could not get inclk");
dev_err(imx412->dev, "could not get inclk\n");
return PTR_ERR(imx412->inclk);
}
rate = clk_get_rate(imx412->inclk);
if (rate != IMX412_INCLK_RATE) {
dev_err(imx412->dev, "inclk frequency mismatch");
dev_err(imx412->dev, "inclk frequency mismatch\n");
return -EINVAL;
}
@@ -975,14 +975,14 @@ static int imx412_parse_hw_config(struct imx412 *imx412)
if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX412_NUM_DATA_LANES) {
dev_err(imx412->dev,
"number of CSI2 data lanes %d is not supported",
"number of CSI2 data lanes %d is not supported\n",
bus_cfg.bus.mipi_csi2.num_data_lanes);
ret = -EINVAL;
goto done_endpoint_free;
}
if (!bus_cfg.nr_of_link_frequencies) {
dev_err(imx412->dev, "no link frequencies defined");
dev_err(imx412->dev, "no link frequencies defined\n");
ret = -EINVAL;
goto done_endpoint_free;
}
@@ -1040,7 +1040,7 @@ static int imx412_power_on(struct device *dev)
ret = clk_prepare_enable(imx412->inclk);
if (ret) {
dev_err(imx412->dev, "fail to enable inclk");
dev_err(imx412->dev, "fail to enable inclk\n");
goto error_reset;
}
@@ -1151,7 +1151,7 @@ static int imx412_init_controls(struct imx412 *imx412)
imx412->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
if (ctrl_hdlr->error) {
dev_err(imx412->dev, "control init failed: %d",
dev_err(imx412->dev, "control init failed: %d\n",
ctrl_hdlr->error);
v4l2_ctrl_handler_free(ctrl_hdlr);
return ctrl_hdlr->error;
@@ -1184,7 +1184,7 @@ static int imx412_probe(struct i2c_client *client)
ret = imx412_parse_hw_config(imx412);
if (ret) {
dev_err(imx412->dev, "HW configuration is not supported");
dev_err(imx412->dev, "HW configuration is not supported\n");
return ret;
}
@@ -1192,14 +1192,14 @@ static int imx412_probe(struct i2c_client *client)
ret = imx412_power_on(imx412->dev);
if (ret) {
dev_err(imx412->dev, "failed to power-on the sensor");
dev_err(imx412->dev, "failed to power-on the sensor\n");
goto error_mutex_destroy;
}
/* Check module identity */
ret = imx412_detect(imx412);
if (ret) {
dev_err(imx412->dev, "failed to find sensor: %d", ret);
dev_err(imx412->dev, "failed to find sensor: %d\n", ret);
goto error_power_off;
}
@@ -1209,7 +1209,7 @@ static int imx412_probe(struct i2c_client *client)
ret = imx412_init_controls(imx412);
if (ret) {
dev_err(imx412->dev, "failed to init controls: %d", ret);
dev_err(imx412->dev, "failed to init controls: %d\n", ret);
goto error_power_off;
}
@@ -1221,14 +1221,14 @@ static int imx412_probe(struct i2c_client *client)
imx412->pad.flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&imx412->sd.entity, 1, &imx412->pad);
if (ret) {
dev_err(imx412->dev, "failed to init entity pads: %d", ret);
dev_err(imx412->dev, "failed to init entity pads: %d\n", ret);
goto error_handler_free;
}
ret = v4l2_async_register_subdev_sensor(&imx412->sd);
if (ret < 0) {
dev_err(imx412->dev,
"failed to register async subdev: %d", ret);
"failed to register async subdev: %d\n", ret);
goto error_media_entity;
}

2
drivers/media/i2c/ov9282.c
View File

@@ -31,7 +31,7 @@
/* Exposure control */
#define OV9282_REG_EXPOSURE 0x3500
#define OV9282_EXPOSURE_MIN 1
#define OV9282_EXPOSURE_OFFSET 12
#define OV9282_EXPOSURE_OFFSET 25
#define OV9282_EXPOSURE_STEP 1
#define OV9282_EXPOSURE_DEFAULT 0x0282

7
drivers/media/platform/marvell/mcam-core.c
View File

@@ -935,7 +935,12 @@ static int mclk_enable(struct clk_hw *hw)
ret = pm_runtime_resume_and_get(cam->dev);
if (ret < 0)
return ret;
clk_enable(cam->clk[0]);
ret = clk_enable(cam->clk[0]);
if (ret) {
pm_runtime_put(cam->dev);
return ret;
}
mcam_reg_write(cam, REG_CLKCTRL, (mclk_src << 29) | mclk_div);
mcam_ctlr_power_up(cam);

10
drivers/media/platform/samsung/exynos4-is/mipi-csis.c
View File

@@ -940,13 +940,19 @@ static int s5pcsis_pm_resume(struct device *dev, bool runtime)
state->supplies);
goto unlock;
}
clk_enable(state->clock[CSIS_CLK_GATE]);
ret = clk_enable(state->clock[CSIS_CLK_GATE]);
if (ret) {
phy_power_off(state->phy);
regulator_bulk_disable(CSIS_NUM_SUPPLIES,
state->supplies);
goto unlock;
}
}
if (state->flags & ST_STREAMING)
s5pcsis_start_stream(state);
state->flags &= ~ST_SUSPENDED;
unlock:
unlock:
mutex_unlock(&state->lock);
return ret ? -EAGAIN : 0;
}

13
drivers/media/platform/samsung/s3c-camif/camif-core.c
View File

@@ -528,10 +528,19 @@ static int s3c_camif_remove(struct platform_device *pdev)
static int s3c_camif_runtime_resume(struct device *dev)
{
struct camif_dev *camif = dev_get_drvdata(dev);
int ret;
ret = clk_enable(camif->clock[CLK_GATE]);
if (ret)
return ret;
clk_enable(camif->clock[CLK_GATE]);
/* null op on s3c244x */
clk_enable(camif->clock[CLK_CAM]);
ret = clk_enable(camif->clock[CLK_CAM]);
if (ret) {
clk_disable(camif->clock[CLK_GATE]);
return ret;
}
return 0;
}

4
drivers/media/rc/iguanair.c
View File

@@ -194,8 +194,10 @@ static int iguanair_send(struct iguanair *ir, unsigned size)
if (rc)
return rc;
if (wait_for_completion_timeout(&ir->completion, TIMEOUT) == 0)
if (wait_for_completion_timeout(&ir->completion, TIMEOUT) == 0) {
usb_kill_urb(ir->urb_out);
return -ETIMEDOUT;
}
return rc;
}

12
drivers/media/usb/dvb-usb-v2/lmedm04.c
View File

@@ -373,6 +373,7 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap)
struct dvb_usb_device *d = adap_to_d(adap);
struct lme2510_state *lme_int = adap_to_priv(adap);
struct usb_host_endpoint *ep;
int ret;
lme_int->lme_urb = usb_alloc_urb(0, GFP_KERNEL);
@@ -390,11 +391,20 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap)
/* Quirk of pipe reporting PIPE_BULK but behaves as interrupt */
ep = usb_pipe_endpoint(d->udev, lme_int->lme_urb->pipe);
if (!ep) {
usb_free_urb(lme_int->lme_urb);
return -ENODEV;
}
if (usb_endpoint_type(&ep->desc) == USB_ENDPOINT_XFER_BULK)
lme_int->lme_urb->pipe = usb_rcvbulkpipe(d->udev, 0xa);
usb_submit_urb(lme_int->lme_urb, GFP_KERNEL);
ret = usb_submit_urb(lme_int->lme_urb, GFP_KERNEL);
if (ret) {
usb_free_urb(lme_int->lme_urb);
return ret;
}
info("INT Interrupt Service Started");
return 0;

3
drivers/media/usb/uvc/uvc_queue.c
View File

@@ -483,7 +483,8 @@ static void uvc_queue_buffer_complete(struct kref *ref)
buf->state = buf->error ? UVC_BUF_STATE_ERROR : UVC_BUF_STATE_DONE;
vb2_set_plane_payload(&buf->buf.vb2_buf, 0, buf->bytesused);
vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_DONE);
vb2_buffer_done(&buf->buf.vb2_buf, buf->error ? VB2_BUF_STATE_ERROR :
VB2_BUF_STATE_DONE);
}
/*

8
drivers/memory/tegra/tegra20-emc.c
View File

@@ -477,14 +477,15 @@ tegra_emc_find_node_by_ram_code(struct tegra_emc *emc)
ram_code = tegra_read_ram_code();
for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
np = of_find_node_by_name(np, "emc-tables")) {
for_each_child_of_node(dev->of_node, np) {
if (!of_node_name_eq(np, "emc-tables"))
continue;
err = of_property_read_u32(np, "nvidia,ram-code", &value);
if (err || value != ram_code) {
struct device_node *lpddr2_np;
bool cfg_mismatches = false;
lpddr2_np = of_find_node_by_name(np, "lpddr2");
lpddr2_np = of_get_child_by_name(np, "lpddr2");
if (lpddr2_np) {
const struct lpddr2_info *info;
@@ -521,7 +522,6 @@ tegra_emc_find_node_by_ram_code(struct tegra_emc *emc)
}
if (cfg_mismatches) {
of_node_put(np);
continue;
}
}

25
drivers/mtd/hyperbus/hbmc-am654.c
View File

@@ -174,26 +174,30 @@ static int am654_hbmc_probe(struct platform_device *pdev)
priv->hbdev.np = of_get_next_child(np, NULL);
ret = of_address_to_resource(priv->hbdev.np, 0, &res);
if (ret)
return ret;
goto put_node;
if (of_property_read_bool(dev->of_node, "mux-controls")) {
struct mux_control *control = devm_mux_control_get(dev, NULL);
if (IS_ERR(control))
return PTR_ERR(control);
if (IS_ERR(control)) {
ret = PTR_ERR(control);
goto put_node;
}
ret = mux_control_select(control, 1);
if (ret) {
dev_err(dev, "Failed to select HBMC mux\n");
return ret;
goto put_node;
}
priv->mux_ctrl = control;
}
priv->hbdev.map.size = resource_size(&res);
priv->hbdev.map.virt = devm_ioremap_resource(dev, &res);
if (IS_ERR(priv->hbdev.map.virt))
return PTR_ERR(priv->hbdev.map.virt);
if (IS_ERR(priv->hbdev.map.virt)) {
ret = PTR_ERR(priv->hbdev.map.virt);
goto disable_mux;
}
priv->ctlr.dev = dev;
priv->ctlr.ops = &am654_hbmc_ops;
@@ -226,10 +230,12 @@ release_dma:
disable_mux:
if (priv->mux_ctrl)
mux_control_deselect(priv->mux_ctrl);
put_node:
of_node_put(priv->hbdev.np);
return ret;
}
static int am654_hbmc_remove(struct platform_device *pdev)
static void am654_hbmc_remove(struct platform_device *pdev)
{
struct am654_hbmc_priv *priv = platform_get_drvdata(pdev);
struct am654_hbmc_device_priv *dev_priv = priv->hbdev.priv;
@@ -241,8 +247,7 @@ static int am654_hbmc_remove(struct platform_device *pdev)
if (dev_priv->rx_chan)
dma_release_channel(dev_priv->rx_chan);
return 0;
of_node_put(priv->hbdev.np);
}
static const struct of_device_id am654_hbmc_dt_ids[] = {
@@ -256,7 +261,7 @@ MODULE_DEVICE_TABLE(of, am654_hbmc_dt_ids);
static struct platform_driver am654_hbmc_platform_driver = {
.probe = am654_hbmc_probe,
.remove = am654_hbmc_remove,
.remove_new = am654_hbmc_remove,
.driver = {
.name = "hbmc-am654",
.of_match_table = am654_hbmc_dt_ids,

3
drivers/of/of_reserved_mem.c
View File

@@ -50,7 +50,8 @@ static int __init early_init_dt_alloc_reserved_memory_arch(phys_addr_t size,
memblock_phys_free(base, size);
}
kmemleak_ignore_phys(base);
if (!err)
kmemleak_ignore_phys(base);
return err;
}

2
drivers/pci/controller/pcie-rcar-ep.c
View File

@@ -107,7 +107,7 @@ static int rcar_pcie_parse_outbound_ranges(struct rcar_pcie_endpoint *ep,
}
if (!devm_request_mem_region(&pdev->dev, res->start,
resource_size(res),
outbound_name)) {
res->name)) {
dev_err(pcie->dev, "Cannot request memory region %s.\n",
outbound_name);
return -EIO;

51
drivers/pci/endpoint/functions/pci-epf-test.c
View File

@@ -251,7 +251,7 @@ static int pci_epf_test_init_dma_chan(struct pci_epf_test *epf_test)
fail_back_rx:
dma_release_channel(epf_test->dma_chan_rx);
epf_test->dma_chan_tx = NULL;
epf_test->dma_chan_rx = NULL;
fail_back_tx:
dma_cap_zero(mask);
@@ -328,7 +328,6 @@ static void pci_epf_test_print_rate(const char *ops, u64 size,
static int pci_epf_test_copy(struct pci_epf_test *epf_test)
{
int ret;
bool use_dma;
void __iomem *src_addr;
void __iomem *dst_addr;
phys_addr_t src_phys_addr;
@@ -373,16 +372,9 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
}
ktime_get_ts64(&start);
use_dma = !!(reg->flags & FLAG_USE_DMA);
if (use_dma) {
if (!epf_test->dma_supported) {
dev_err(dev, "Cannot transfer data using DMA\n");
ret = -EINVAL;
goto err_map_addr;
}
if (epf_test->dma_private) {
dev_err(dev, "Cannot transfer data using DMA\n");
if (reg->flags & FLAG_USE_DMA) {
if (!dma_has_cap(DMA_MEMCPY, epf_test->dma_chan_tx->device->cap_mask)) {
dev_err(dev, "DMA controller doesn't support MEMCPY\n");
ret = -EINVAL;
goto err_map_addr;
}
@@ -406,7 +398,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
kfree(buf);
}
ktime_get_ts64(&end);
pci_epf_test_print_rate("COPY", reg->size, &start, &end, use_dma);
pci_epf_test_print_rate("COPY", reg->size, &start, &end,
reg->flags & FLAG_USE_DMA);
err_map_addr:
pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr);
@@ -430,7 +423,6 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
void __iomem *src_addr;
void *buf;
u32 crc32;
bool use_dma;
phys_addr_t phys_addr;
phys_addr_t dst_phys_addr;
struct timespec64 start, end;
@@ -463,14 +455,7 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
goto err_map_addr;
}
use_dma = !!(reg->flags & FLAG_USE_DMA);
if (use_dma) {
if (!epf_test->dma_supported) {
dev_err(dev, "Cannot transfer data using DMA\n");
ret = -EINVAL;
goto err_dma_map;
}
if (reg->flags & FLAG_USE_DMA) {
dst_phys_addr = dma_map_single(dma_dev, buf, reg->size,
DMA_FROM_DEVICE);
if (dma_mapping_error(dma_dev, dst_phys_addr)) {
@@ -495,7 +480,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
ktime_get_ts64(&end);
}
pci_epf_test_print_rate("READ", reg->size, &start, &end, use_dma);
pci_epf_test_print_rate("READ", reg->size, &start, &end,
reg->flags & FLAG_USE_DMA);
crc32 = crc32_le(~0, buf, reg->size);
if (crc32 != reg->checksum)
@@ -519,7 +505,6 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
int ret;
void __iomem *dst_addr;
void *buf;
bool use_dma;
phys_addr_t phys_addr;
phys_addr_t src_phys_addr;
struct timespec64 start, end;
@@ -555,14 +540,7 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
get_random_bytes(buf, reg->size);
reg->checksum = crc32_le(~0, buf, reg->size);
use_dma = !!(reg->flags & FLAG_USE_DMA);
if (use_dma) {
if (!epf_test->dma_supported) {
dev_err(dev, "Cannot transfer data using DMA\n");
ret = -EINVAL;
goto err_dma_map;
}
if (reg->flags & FLAG_USE_DMA) {
src_phys_addr = dma_map_single(dma_dev, buf, reg->size,
DMA_TO_DEVICE);
if (dma_mapping_error(dma_dev, src_phys_addr)) {
@@ -589,7 +567,8 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
ktime_get_ts64(&end);
}
pci_epf_test_print_rate("WRITE", reg->size, &start, &end, use_dma);
pci_epf_test_print_rate("WRITE", reg->size, &start, &end,
reg->flags & FLAG_USE_DMA);
/*
* wait 1ms inorder for the write to complete. Without this delay L3
@@ -660,6 +639,12 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
reg->command = 0;
reg->status = 0;
if ((READ_ONCE(reg->flags) & FLAG_USE_DMA) &&
!epf_test->dma_supported) {
dev_err(dev, "Cannot transfer data using DMA\n");
goto reset_handler;
}
if (reg->irq_type > IRQ_TYPE_MSIX) {
dev_err(dev, "Failed to detect IRQ type\n");
goto reset_handler;

2
drivers/pci/endpoint/pci-epc-core.c
View File

@@ -740,7 +740,7 @@ void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc)
{
int r;
r = devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match,
r = devres_release(dev, devm_pci_epc_release, devm_pci_epc_match,
epc);
dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n");
}

3
drivers/scsi/mpt3sas/mpt3sas_base.c
View File

@@ -5649,8 +5649,7 @@ _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) {
pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
ioc->name);
ioc->manu_pg11.EEDPTagMode &= ~0x3;
ioc->manu_pg11.EEDPTagMode |= 0x1;
ioc->manu_pg11.EEDPTagMode = 0x1;
mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
&ioc->manu_pg11);
}

2
drivers/soc/atmel/soc.c
View File

@@ -367,7 +367,7 @@ static const struct of_device_id at91_soc_allowed_list[] __initconst = {
static int __init atmel_soc_device_init(void)
{
struct device_node *np = of_find_node_by_path("/");
struct device_node *np __free(device_node) = of_find_node_by_path("/");
if (!of_match_node(at91_soc_allowed_list, np))
return 0;

8
drivers/staging/media/imx/imx-media-of.c
View File

@@ -55,22 +55,18 @@ int imx_media_add_of_subdevs(struct imx_media_dev *imxmd,
break;
ret = imx_media_of_add_csi(imxmd, csi_np);
of_node_put(csi_np);
if (ret) {
/* unavailable or already added is not an error */
if (ret == -ENODEV || ret == -EEXIST) {
of_node_put(csi_np);
continue;
}
/* other error, can't continue */
goto err_out;
return ret;
}
}
return 0;
err_out:
of_node_put(csi_np);
return ret;
}
EXPORT_SYMBOL_GPL(imx_media_add_of_subdevs);

32
drivers/tty/serial/8250/8250_port.c
View File

@@ -2099,7 +2099,8 @@ static void serial8250_break_ctl(struct uart_port *port, int break_state)
serial8250_rpm_put(up);
}
static void wait_for_lsr(struct uart_8250_port *up, int bits)
/* Returns true if @bits were set, false on timeout */
static bool wait_for_lsr(struct uart_8250_port *up, int bits)
{
unsigned int status, tmout = 10000;
@@ -2114,11 +2115,11 @@ static void wait_for_lsr(struct uart_8250_port *up, int bits)
udelay(1);
touch_nmi_watchdog();
}
return (tmout != 0);
}
/*
* Wait for transmitter & holding register to empty
*/
/* Wait for transmitter and holding register to empty with timeout */
static void wait_for_xmitr(struct uart_8250_port *up, int bits)
{
unsigned int tmout;
@@ -3362,6 +3363,16 @@ static void serial8250_console_restore(struct uart_8250_port *up)
serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
}
static void fifo_wait_for_lsr(struct uart_8250_port *up, unsigned int count)
{
unsigned int i;
for (i = 0; i < count; i++) {
if (wait_for_lsr(up, UART_LSR_THRE))
return;
}
}
/*
* Print a string to the serial port using the device FIFO
*
@@ -3371,13 +3382,15 @@ static void serial8250_console_restore(struct uart_8250_port *up)
static void serial8250_console_fifo_write(struct uart_8250_port *up,
const char *s, unsigned int count)
{
int i;
const char *end = s + count;
unsigned int fifosize = up->tx_loadsz;
unsigned int tx_count = 0;
bool cr_sent = false;
unsigned int i;
while (s != end) {
wait_for_lsr(up, UART_LSR_THRE);
/* Allow timeout for each byte of a possibly full FIFO */
fifo_wait_for_lsr(up, fifosize);
for (i = 0; i < fifosize && s != end; ++i) {
if (*s == '\n' && !cr_sent) {
@@ -3388,7 +3401,14 @@ static void serial8250_console_fifo_write(struct uart_8250_port *up,
cr_sent = false;
}
}
tx_count = i;
}
/*
* Allow timeout for each byte written since the caller will only wait
* for UART_LSR_BOTH_EMPTY using the timeout of a single character
*/
fifo_wait_for_lsr(up, tx_count);
}
/*

1
drivers/ufs/core/ufs_bsg.c
View File

@@ -254,6 +254,7 @@ int ufs_bsg_probe(struct ufs_hba *hba)
q = bsg_setup_queue(bsg_dev, dev_name(bsg_dev), ufs_bsg_request, NULL, 0);
if (IS_ERR(q)) {
ret = PTR_ERR(q);
device_del(bsg_dev);
goto out;
}

2
drivers/vfio/iova_bitmap.c
View File

@@ -126,7 +126,7 @@ struct iova_bitmap {
static unsigned long iova_bitmap_offset_to_index(struct iova_bitmap *bitmap,
unsigned long iova)
{
unsigned long pgsize = 1 << bitmap->mapped.pgshift;
unsigned long pgsize = 1UL << bitmap->mapped.pgshift;
return iova / (BITS_PER_TYPE(*bitmap->bitmap) * pgsize);
}

1
drivers/video/fbdev/omap2/omapfb/dss/dss-of.c
View File

@@ -102,6 +102,7 @@ struct device_node *dss_of_port_get_parent_device(struct device_node *port)
np = of_get_next_parent(np);
}
of_node_put(np);
return NULL;
}

2
fs/nfs/nfs42proc.c
View File

@@ -551,7 +551,7 @@ static int nfs42_do_offload_cancel_async(struct file *dst,
.rpc_message = &msg,
.callback_ops = &nfs42_offload_cancel_ops,
.workqueue = nfsiod_workqueue,
.flags = RPC_TASK_ASYNC,
.flags = RPC_TASK_ASYNC | RPC_TASK_MOVEABLE,
};
int status;

2
fs/nfs/nfs42xdr.c
View File

@@ -129,9 +129,11 @@
decode_putfh_maxsz + \
decode_offload_cancel_maxsz)
#define NFS4_enc_copy_notify_sz (compound_encode_hdr_maxsz + \
encode_sequence_maxsz + \
encode_putfh_maxsz + \
encode_copy_notify_maxsz)
#define NFS4_dec_copy_notify_sz (compound_decode_hdr_maxsz + \
decode_sequence_maxsz + \
decode_putfh_maxsz + \
decode_copy_notify_maxsz)
#define NFS4_enc_deallocate_sz (compound_encode_hdr_maxsz + \

5
fs/ocfs2/quota_global.c
View File

@@ -749,6 +749,11 @@ static int ocfs2_release_dquot(struct dquot *dquot)
handle = ocfs2_start_trans(osb,
ocfs2_calc_qdel_credits(dquot->dq_sb, dquot->dq_id.type));
if (IS_ERR(handle)) {
/*
* Mark dquot as inactive to avoid endless cycle in
* quota_release_workfn().
*/
clear_bit(DQ_ACTIVE_B, &dquot->dq_flags);
status = PTR_ERR(handle);
mlog_errno(status);
goto out_ilock;

3
fs/smb/client/smb2ops.c
View File

@@ -615,7 +615,8 @@ parse_server_interfaces(struct network_interface_info_ioctl_rsp *buf,
while (bytes_left >= (ssize_t)sizeof(*p)) {
memset(&tmp_iface, 0, sizeof(tmp_iface));
tmp_iface.speed = le64_to_cpu(p->LinkSpeed);
/* default to 1Gbps when link speed is unset */
tmp_iface.speed = le64_to_cpu(p->LinkSpeed) ?: 1000000000;
tmp_iface.rdma_capable = le32_to_cpu(p->Capability & RDMA_CAPABLE) ? 1 : 0;
tmp_iface.rss_capable = le32_to_cpu(p->Capability & RSS_CAPABLE) ? 1 : 0;

2
include/linux/kallsyms.h
View File

@@ -57,10 +57,10 @@ static inline void *dereference_symbol_descriptor(void *ptr)
preempt_disable();
mod = __module_address((unsigned long)ptr);
preempt_enable();
if (mod)
ptr = dereference_module_function_descriptor(mod, ptr);
preempt_enable();
#endif
return ptr;
}

43
kernel/padata.c
View File

@@ -47,6 +47,22 @@ struct padata_mt_job_state {
static void padata_free_pd(struct parallel_data *pd);
static void __init padata_mt_helper(struct work_struct *work);
static inline void padata_get_pd(struct parallel_data *pd)
{
refcount_inc(&pd->refcnt);
}
static inline void padata_put_pd_cnt(struct parallel_data *pd, int cnt)
{
if (refcount_sub_and_test(cnt, &pd->refcnt))
padata_free_pd(pd);
}
static inline void padata_put_pd(struct parallel_data *pd)
{
padata_put_pd_cnt(pd, 1);
}
static int padata_index_to_cpu(struct parallel_data *pd, int cpu_index)
{
int cpu, target_cpu;
@@ -198,7 +214,7 @@ int padata_do_parallel(struct padata_shell *ps,
if ((pinst->flags & PADATA_RESET))
goto out;
refcount_inc(&pd->refcnt);
padata_get_pd(pd);
padata->pd = pd;
padata->cb_cpu = *cb_cpu;
@@ -328,8 +344,14 @@ static void padata_reorder(struct parallel_data *pd)
smp_mb();
reorder = per_cpu_ptr(pd->reorder_list, pd->cpu);
if (!list_empty(&reorder->list) && padata_find_next(pd, false))
if (!list_empty(&reorder->list) && padata_find_next(pd, false)) {
/*
* Other context(eg. the padata_serial_worker) can finish the request.
* To avoid UAF issue, add pd ref here, and put pd ref after reorder_work finish.
*/
padata_get_pd(pd);
queue_work(pinst->serial_wq, &pd->reorder_work);
}
}
static void invoke_padata_reorder(struct work_struct *work)
@@ -340,6 +362,8 @@ static void invoke_padata_reorder(struct work_struct *work)
pd = container_of(work, struct parallel_data, reorder_work);
padata_reorder(pd);
local_bh_enable();
/* Pairs with putting the reorder_work in the serial_wq */
padata_put_pd(pd);
}
static void padata_serial_worker(struct work_struct *serial_work)
@@ -372,8 +396,7 @@ static void padata_serial_worker(struct work_struct *serial_work)
}
local_bh_enable();
if (refcount_sub_and_test(cnt, &pd->refcnt))
padata_free_pd(pd);
padata_put_pd_cnt(pd, cnt);
}
/**
@@ -670,8 +693,7 @@ static int padata_replace(struct padata_instance *pinst)
synchronize_rcu();
list_for_each_entry_continue_reverse(ps, &pinst->pslist, list)
if (refcount_dec_and_test(&ps->opd->refcnt))
padata_free_pd(ps->opd);
padata_put_pd(ps->opd);
pinst->flags &= ~PADATA_RESET;
@@ -1110,11 +1132,16 @@ void padata_free_shell(struct padata_shell *ps)
if (!ps)
return;
/*
* Wait for all _do_serial calls to finish to avoid touching
* freed pd's and ps's.
*/
synchronize_rcu();
mutex_lock(&ps->pinst->lock);
list_del(&ps->list);
pd = rcu_dereference_protected(ps->pd, 1);
if (refcount_dec_and_test(&pd->refcnt))
padata_free_pd(pd);
padata_put_pd(pd);
mutex_unlock(&ps->pinst->lock);
kfree(ps);

1
sound/pci/hda/patch_realtek.c
View File

@@ -9583,6 +9583,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
SND_PCI_QUIRK(0x1025, 0x1308, "Acer Aspire Z24-890", ALC286_FIXUP_ACER_AIO_HEADSET_MIC),
SND_PCI_QUIRK(0x1025, 0x132a, "Acer TravelMate B114-21", ALC233_FIXUP_ACER_HEADSET_MIC),
SND_PCI_QUIRK(0x1025, 0x1330, "Acer TravelMate X514-51T", ALC255_FIXUP_ACER_HEADSET_MIC),
SND_PCI_QUIRK(0x1025, 0x1360, "Acer Aspire A115", ALC255_FIXUP_ACER_MIC_NO_PRESENCE),
SND_PCI_QUIRK(0x1025, 0x141f, "Acer Spin SP513-54N", ALC255_FIXUP_ACER_MIC_NO_PRESENCE),
SND_PCI_QUIRK(0x1025, 0x142b, "Acer Swift SF314-42", ALC255_FIXUP_ACER_MIC_NO_PRESENCE),
SND_PCI_QUIRK(0x1025, 0x1430, "Acer TravelMate B311R-31", ALC256_FIXUP_ACER_MIC_NO_PRESENCE),

4
tools/bootconfig/main.c
View File

@@ -226,7 +226,7 @@ static int load_xbc_from_initrd(int fd, char **buf)
/* Wrong Checksum */
rcsum = xbc_calc_checksum(*buf, size);
if (csum != rcsum) {
pr_err("checksum error: %d != %d\n", csum, rcsum);
pr_err("checksum error: %u != %u\n", csum, rcsum);
return -EINVAL;
}
@@ -395,7 +395,7 @@ static int apply_xbc(const char *path, const char *xbc_path)
xbc_get_info(&ret, NULL);
printf("\tNumber of nodes: %d\n", ret);
printf("\tSize: %u bytes\n", (unsigned int)size);
printf("\tChecksum: %d\n", (unsigned int)csum);
printf("\tChecksum: %u\n", (unsigned int)csum);
/* TODO: Check the options by schema */
xbc_exit();