From 0263166d73f212144aef9617eb6b465ee564f65b Mon Sep 17 00:00:00 2001
From: Lin Huang <hl@rock-chips.com>
Date: Fri, 22 Jul 2016 15:37:17 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3399: add dmc and dfi node

To support ddr frequency scaling function, we need
enable dmc and dfi node.

Change-Id: I84ea6bff679365d86937ff10bcdf466ea31901fb
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 393e8ae75cd5..46fbf497b101 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -13,6 +13,8 @@
 #include <dt-bindings/soc/rockchip-system-status.h>
 #include <dt-bindings/thermal/thermal.h>
 
+#include "rk3399-dram-default-timing.dtsi"
+
 / {
 	compatible = "rockchip,rk3399";
 
@@ -1261,6 +1263,25 @@
 		status = "disabled";
 	};
 
+	dfi: dfi@ff630000 {
+		reg = <0x00 0xff630000 0x00 0x4000>;
+		compatible = "rockchip,rk3399-dfi";
+		rockchip,pmu = <&pmugrf>;
+		clocks = <&cru PCLK_DDR_MON>;
+		clock-names = "pclk_ddr_mon";
+		status = "disabled";
+	};
+
+	dmc: dmc {
+		compatible = "rockchip,rk3399-dmc";
+		devfreq-events = <&dfi>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru SCLK_DDRC>;
+		clock-names = "dmc_clk";
+		ddr_timing = <&ddr_timing>;
+		status = "disabled";
+	};
+
 	vpu: video-codec@ff650000 {
 		compatible = "rockchip,rk3399-vpu";
 		reg = <0x0 0xff650000 0x0 0x800>;