From 0276e9624bad57ee2e010ac88f78e27bfabcb40a Mon Sep 17 00:00:00 2001
From: shengfei Xu <xsf@rock-chips.com>
Date: Tue, 28 Nov 2017 14:36:24 +0800
Subject: [PATCH] clk: rockchip: rk3218: add rkclk_cpuclk_div_setting

fix up the RK816 setting voltage drop make the system crash.
Before adjusting voltage, increase clk_cpu div and reduce CPU frequency
Only support for RK312x chips.

Change-Id: Id327da9590f7d9d383450e79acd1b309e05cd024
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
---
 drivers/clk/rockchip/clk-rk3128.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index 0cc478d74d17..23ddfc9a2b2a 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -8,6 +8,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/rockchip/cpu.h>
 #include <linux/syscore_ops.h>
 #include <dt-bindings/clock/rk3128-cru.h>
 #include "clk.h"
@@ -577,6 +578,15 @@ static const char *const rk3128_critical_clocks[] __initconst = {
 	"sclk_timer5",
 };
 
+static void __iomem *rk312x_reg_base;
+
+void rkclk_cpuclk_div_setting(int div)
+{
+	if (cpu_is_rk312x())
+		writel_relaxed((0x001f0000 | (div - 1)),
+			       rk312x_reg_base +  RK2928_CLKSEL_CON(0));
+}
+
 static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
 {
 	struct rockchip_clk_provider *ctx;
@@ -588,6 +598,7 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
 		return ERR_PTR(-ENOMEM);
 	}
 
+	rk312x_reg_base = reg_base;
 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 	if (IS_ERR(ctx)) {
 		pr_err("%s: rockchip clk init failed\n", __func__);