From 02e11db2937b660099cd311bacfcde2b4768ff25 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 12 Apr 2023 17:52:50 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3562: Fix PCIe node Signed-off-by: Shawn Lin Change-Id: I6deb77ddd8ce5593cd6daf636ac85d2274214fb9 --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 57cefcbcba8e..eb5e06d0150e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -1854,13 +1854,13 @@ phys = <&combphy_pu PHY_TYPE_PCIE>; phy-names = "pcie-phy"; power-domains = <&power RK3562_PD_PHP>; - ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 - 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + ranges = <0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; reg = <0x0 0xfe000000 0x0 0x400000>, - <0x0 0xff500000 0x0 0x10000>; - reg-names = "pcie-dbi", "pcie-apb"; + <0x0 0xff500000 0x0 0x10000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names = "pcie-dbi", "pcie-apb", "config"; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; status = "disabled";