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PCIe: dw: rockchip: rework compliance test settings

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There are three types of compliance mode test requirement right
now, consolidate them together:
[1] SMA tool: rockchip,compliance-mode = <0 ANY_VALUE_FROM_0_TO_10>;
[2] Soldered board: rockchip,compliance-mode = <mode preset>;
    mode: 1->Gen1  2->Gen2  3->Gen3
    preset: 0->p0 1->p1 2->p2 .... etc.
[3] lookback: same as SMA tool case

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I180b4881d827e3c2f0fc22f0bab4ca165be44c19
This commit is contained in:
Shawn Lin
2023-08-09 16:57:47 +08:00
committed by Tao Huang
parent 7d42e40890
commit 02ee7a133e
1 changed files with 20 additions and 5 deletions
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25
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -192,6 +192,7 @@ struct rk_pcie {
u32 msi_vector_num; u32 msi_vector_num;
struct workqueue_struct *hot_rst_wq; struct workqueue_struct *hot_rst_wq;
struct work_struct hot_rst_work; struct work_struct hot_rst_work;
u32 comp_prst[2];
}; };
struct rk_pcie_of_data { struct rk_pcie_of_data {
@@ -2081,11 +2082,25 @@ retry_regulator:
rk_pcie->is_signal_test = true; rk_pcie->is_signal_test = true;
} }
/* Force into compliance mode */ /*
if (device_property_read_bool(dev, "rockchip,compliance-mode")) { * Force into compliance mode
val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS); * comp_prst is a two dimensional array of which the first element
val |= BIT(4); * stands for speed mode, and the second one is preset value encoding:
dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); * [0] 0->SMA tool control the signal switch, 1/2/3 is for manual Gen setting
* [1] transmitter setting for manual Gen setting, valid only if [0] isn't zero.
*/
if (device_property_read_u32_array(dev, "rockchip,compliance-mode",
rk_pcie->comp_prst, 2)) {
BUG_ON(rk_pcie->comp_prst[0] > 3 || rk_pcie->comp_prst[1] > 10);
if (!rk_pcie->comp_prst[0]) {
dev_info(dev, "Auto compliance mode for SMA tool.\n");
} else {
dev_info(dev, "compliance mode for soldered board Gen%d, P%d.\n",
rk_pcie->comp_prst[0], rk_pcie->comp_prst[1]);
val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS);
val |= BIT(4) | rk_pcie->comp_prst[0] | (rk_pcie->comp_prst[1] << 12);
dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val);
}
rk_pcie->is_signal_test = true; rk_pcie->is_signal_test = true;
} }