From 031e91e83d6284b1a48e92c001213e2ec7e72d65 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Tue, 31 May 2022 17:07:24 +0530 Subject: [PATCH] FROMLIST: arm64: perf: Make exporting of pmu events configurable The PMU export bit (PMCR_EL0.X) is getting reset during pmu reset, Make is configurable using sysctls to enable/disable at runtime. It can also be enabled at early bootup with kernel arguments. Bug: 230559577 Change-Id: I35dcfeed23e64ec9493f9a15dbb43e9966108664 Link: https://lore.kernel.org/lkml/1653306574-20946-1-git-send-email-quic_c_spathi@quicinc.com/ Signed-off-by: Srinivasarao Pathipati --- .../admin-guide/kernel-parameters.txt | 4 ++++ Documentation/admin-guide/sysctl/kernel.rst | 11 +++++++++ arch/arm64/kernel/perf_event.c | 24 +++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 2e96d2196775..1a84f97b8bd4 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1400,6 +1400,10 @@ Format: { "fix" } Permit 'security.evm' to be updated regardless of current integrity status. + export_pmu_events + [KNL,ARM64] Sets the PMU export bit (PMCR_EL0.X), which enables + the exporting of events over an IMPLEMENTATION DEFINED PMU event + export bus to another device. failslab= fail_usercopy= diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst index 264735c5d0bd..bd63945cf02a 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -267,6 +267,17 @@ domain names are in general different. For a detailed discussion see the ``hostname(1)`` man page. +export_pmu_events (arm64 only) +============================== + +Controls the PMU export bit (PMCR_EL0.X), which enables the exporting of +events over an IMPLEMENTATION DEFINED PMU event export bus to another device. + +0: disables exporting of events (default). + +1: enables exporting of events. + + firmware_config =============== diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index ed7bcffb5b1a..7ce97208adfe 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -287,6 +287,7 @@ PMU_FORMAT_ATTR(event, "config:0-15"); PMU_FORMAT_ATTR(long, "config1:0"); static int sysctl_perf_user_access __read_mostly; +static int sysctl_export_pmu_events __read_mostly; static inline bool armv8pmu_event_is_64bit(struct perf_event *event) { @@ -955,6 +956,17 @@ static int armv8pmu_filter_match(struct perf_event *event) return evtype != ARMV8_PMUV3_PERFCTR_CHAIN; } +static int __init export_pmu_events(char *str) +{ + /* Enable exporting of pmu events at early bootup with kernel + * arguments. + */ + sysctl_export_pmu_events = 1; + return 0; +} + +early_param("export_pmu_events", export_pmu_events); + static void armv8pmu_reset(void *info) { struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; @@ -977,6 +989,9 @@ static void armv8pmu_reset(void *info) if (armv8pmu_has_long_event(cpu_pmu)) pmcr |= ARMV8_PMU_PMCR_LP; + if (sysctl_export_pmu_events) + pmcr |= ARMV8_PMU_PMCR_X; + armv8pmu_pmcr_write(pmcr); } @@ -1116,6 +1131,15 @@ static struct ctl_table armv8_pmu_sysctl_table[] = { .extra1 = SYSCTL_ZERO, .extra2 = SYSCTL_ONE, }, + { + .procname = "export_pmu_events", + .data = &sysctl_export_pmu_events, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, + }, { } };