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MALI: rockchip: upgrade bifrost DDK to g15p0-01eac0, from g13p0-01eac0

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Note, the corresponding mali_csffw.bin for DDK g15 MUST be used.

Change-Id: Ic30634fa6247d62bf96f506c64d13b89e16b02e6
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
This commit is contained in:
Zhen Chen
2022-10-13 08:42:04 +08:00
committed by Tao Huang
parent 96e93dba44
commit 034aad5dd8
192 changed files with 10415 additions and 8170 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/uapi/gpu/arm/bifrost/csf/mali_base_csf_kernel.h
View File

@@ -573,6 +573,7 @@ struct base_csf_notification {
* is a bitpattern where a set bit indicates that the format is supported.
* Before using a texture format, it is recommended that the corresponding
* bit be checked.
* @paddings: Padding bytes.
* @gpu_available_memory_size: Theoretical maximum memory available to the GPU.
* It is unlikely that a client will be able to allocate all of this memory
* for their own purposes, but this at least provides an upper bound on the
@@ -590,6 +591,7 @@ struct mali_base_gpu_core_props {
__u32 gpu_freq_khz_max;
__u32 log2_program_counter_size;
__u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
__u8 paddings[4];
__u64 gpu_available_memory_size;
};

81
include/uapi/gpu/arm/bifrost/csf/mali_kbase_csf_errors_dumpfault.h Normal file
View File

@@ -0,0 +1,81 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
#ifndef _UAPI_KBASE_CSF_ERRORS_DUMPFAULT_H_
#define _UAPI_KBASE_CSF_ERRORS_DUMPFAULT_H_
/**
* enum dumpfault_error_type - Enumeration to define errors to be dumped
*
* @DF_NO_ERROR: No pending error
* @DF_CSG_SUSPEND_TIMEOUT: CSG suspension timeout
* @DF_CSG_TERMINATE_TIMEOUT: CSG group termination timeout
* @DF_CSG_START_TIMEOUT: CSG start timeout
* @DF_CSG_RESUME_TIMEOUT: CSG resume timeout
* @DF_CSG_EP_CFG_TIMEOUT: CSG end point configuration timeout
* @DF_CSG_STATUS_UPDATE_TIMEOUT: CSG status update timeout
* @DF_PROGRESS_TIMER_TIMEOUT: Progress timer timeout
* @DF_FW_INTERNAL_ERROR: Firmware internal error
* @DF_CS_FATAL: CS fatal error
* @DF_CS_FAULT: CS fault error
* @DF_FENCE_WAIT_TIMEOUT: Fence wait timeout
* @DF_PROTECTED_MODE_EXIT_TIMEOUT: P.mode exit timeout
* @DF_PROTECTED_MODE_ENTRY_FAILURE: P.mode entrance failure
* @DF_PING_REQUEST_TIMEOUT: Ping request timeout
* @DF_CORE_DOWNSCALE_REQUEST_TIMEOUT: DCS downscale request timeout
* @DF_TILER_OOM: Tiler Out-of-memory error
* @DF_GPU_PAGE_FAULT: GPU page fault
* @DF_BUS_FAULT: MMU BUS Fault
* @DF_GPU_PROTECTED_FAULT: GPU P.mode fault
* @DF_AS_ACTIVE_STUCK: AS active stuck
* @DF_GPU_SOFT_RESET_FAILURE: GPU soft reset falure
*
* This is used for kbase to notify error type of an event whereby
* user space client will dump relevant debugging information via debugfs.
* @DF_NO_ERROR is used to indicate no pending fault, thus the client will
* be blocked on reading debugfs file till a fault happens.
*/
enum dumpfault_error_type {
DF_NO_ERROR = 0,
DF_CSG_SUSPEND_TIMEOUT,
DF_CSG_TERMINATE_TIMEOUT,
DF_CSG_START_TIMEOUT,
DF_CSG_RESUME_TIMEOUT,
DF_CSG_EP_CFG_TIMEOUT,
DF_CSG_STATUS_UPDATE_TIMEOUT,
DF_PROGRESS_TIMER_TIMEOUT,
DF_FW_INTERNAL_ERROR,
DF_CS_FATAL,
DF_CS_FAULT,
DF_FENCE_WAIT_TIMEOUT,
DF_PROTECTED_MODE_EXIT_TIMEOUT,
DF_PROTECTED_MODE_ENTRY_FAILURE,
DF_PING_REQUEST_TIMEOUT,
DF_CORE_DOWNSCALE_REQUEST_TIMEOUT,
DF_TILER_OOM,
DF_GPU_PAGE_FAULT,
DF_BUS_FAULT,
DF_GPU_PROTECTED_FAULT,
DF_AS_ACTIVE_STUCK,
DF_GPU_SOFT_RESET_FAILURE,
};
#endif /* _UAPI_KBASE_CSF_ERRORS_DUMPFAULT_H_ */

80
include/uapi/gpu/arm/bifrost/csf/mali_kbase_csf_ioctl.h
View File

@@ -60,10 +60,22 @@
* - Dummy model (no mali) backend will now clear HWC values after each sample
* 1.12:
* - Added support for incremental rendering flag in CSG create call
* 1.13:
* - Added ioctl to query a register of USER page.
* 1.14:
* - Added support for passing down the buffer descriptor VA in tiler heap init
* 1.15:
* - Enable new sync_wait GE condition
* 1.16:
* - Remove legacy definitions:
* - base_jit_alloc_info_10_2
* - base_jit_alloc_info_11_5
* - kbase_ioctl_mem_jit_init_10_2
* - kbase_ioctl_mem_jit_init_11_5
*/
#define BASE_UK_VERSION_MAJOR 1
#define BASE_UK_VERSION_MINOR 12
#define BASE_UK_VERSION_MINOR 16
/**
* struct kbase_ioctl_version_check - Check version compatibility between
@@ -271,9 +283,9 @@ union kbase_ioctl_cs_queue_group_create {
__u8 csi_handlers;
__u8 padding[2];
/**
* @in.reserved: Reserved
* @in.dvs_buf: buffer for deferred vertex shader
*/
__u64 reserved;
__u64 dvs_buf;
} in;
struct {
__u8 group_handle;
@@ -361,6 +373,7 @@ struct kbase_ioctl_kcpu_queue_enqueue {
* allowed.
* @in.group_id: Group ID to be used for physical allocations.
* @in.padding: Padding
* @in.buf_desc_va: Buffer descriptor GPU VA for tiler heap reclaims.
* @out: Output parameters
* @out.gpu_heap_va: GPU VA (virtual address) of Heap context that was set up
* for the heap.
@@ -376,6 +389,7 @@ union kbase_ioctl_cs_tiler_heap_init {
__u16 target_in_flight;
__u8 group_id;
__u8 padding;
__u64 buf_desc_va;
} in;
struct {
__u64 gpu_heap_va;
@@ -386,6 +400,43 @@ union kbase_ioctl_cs_tiler_heap_init {
#define KBASE_IOCTL_CS_TILER_HEAP_INIT \
_IOWR(KBASE_IOCTL_TYPE, 48, union kbase_ioctl_cs_tiler_heap_init)
/**
* union kbase_ioctl_cs_tiler_heap_init_1_13 - Initialize chunked tiler memory heap,
* earlier version upto 1.13
* @in: Input parameters
* @in.chunk_size: Size of each chunk.
* @in.initial_chunks: Initial number of chunks that heap will be created with.
* @in.max_chunks: Maximum number of chunks that the heap is allowed to use.
* @in.target_in_flight: Number of render-passes that the driver should attempt to
* keep in flight for which allocation of new chunks is
* allowed.
* @in.group_id: Group ID to be used for physical allocations.
* @in.padding: Padding
* @out: Output parameters
* @out.gpu_heap_va: GPU VA (virtual address) of Heap context that was set up
* for the heap.
* @out.first_chunk_va: GPU VA of the first chunk allocated for the heap,
* actually points to the header of heap chunk and not to
* the low address of free memory in the chunk.
*/
union kbase_ioctl_cs_tiler_heap_init_1_13 {
struct {
__u32 chunk_size;
__u32 initial_chunks;
__u32 max_chunks;
__u16 target_in_flight;
__u8 group_id;
__u8 padding;
} in;
struct {
__u64 gpu_heap_va;
__u64 first_chunk_va;
} out;
};
#define KBASE_IOCTL_CS_TILER_HEAP_INIT_1_13 \
_IOWR(KBASE_IOCTL_TYPE, 48, union kbase_ioctl_cs_tiler_heap_init_1_13)
/**
* struct kbase_ioctl_cs_tiler_heap_term - Terminate a chunked tiler heap
* instance
@@ -487,6 +538,29 @@ union kbase_ioctl_mem_alloc_ex {
#define KBASE_IOCTL_MEM_ALLOC_EX _IOWR(KBASE_IOCTL_TYPE, 59, union kbase_ioctl_mem_alloc_ex)
/**
* union kbase_ioctl_read_user_page - Read a register of USER page
*
* @in: Input parameters.
* @in.offset: Register offset in USER page.
* @in.padding: Padding to round up to a multiple of 8 bytes, must be zero.
* @out: Output parameters.
* @out.val_lo: Value of 32bit register or the 1st half of 64bit register to be read.
* @out.val_hi: Value of the 2nd half of 64bit register to be read.
*/
union kbase_ioctl_read_user_page {
struct {
__u32 offset;
__u32 padding;
} in;
struct {
__u32 val_lo;
__u32 val_hi;
} out;
};
#define KBASE_IOCTL_READ_USER_PAGE _IOWR(KBASE_IOCTL_TYPE, 60, union kbase_ioctl_read_user_page)
/***************
* test ioctls *
***************/

30
include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_csf.h Normal file
View File

@@ -0,0 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
#ifndef _UAPI_KBASE_GPU_REGMAP_CSF_H_
#define _UAPI_KBASE_GPU_REGMAP_CSF_H_
/* IPA control registers */
#define IPA_CONTROL_BASE 0x40000
#define IPA_CONTROL_REG(r) (IPA_CONTROL_BASE + (r))
#define STATUS 0x004 /* (RO) Status register */
#endif /* _UAPI_KBASE_GPU_REGMAP_CSF_H_ */

24
include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_jm.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -23,8 +23,24 @@
#define _UAPI_KBASE_GPU_REGMAP_JM_H_
/* GPU control registers */
#define LATEST_FLUSH 0x038 /* (RO) Flush ID of latest
* clean-and-invalidate operation
*/
#define LATEST_FLUSH 0x038 /* (RO) Flush ID of latest clean-and-invalidate operation */
/* Job control registers */
#define JS_HEAD_LO 0x00 /* (RO) Job queue head pointer for job slot n, low word */
#define JS_HEAD_HI 0x04 /* (RO) Job queue head pointer for job slot n, high word */
#define JS_TAIL_LO 0x08 /* (RO) Job queue tail pointer for job slot n, low word */
#define JS_TAIL_HI 0x0C /* (RO) Job queue tail pointer for job slot n, high word */
#define JS_AFFINITY_LO 0x10 /* (RO) Core affinity mask for job slot n, low word */
#define JS_AFFINITY_HI 0x14 /* (RO) Core affinity mask for job slot n, high word */
#define JS_CONFIG 0x18 /* (RO) Configuration settings for job slot n */
#define JS_HEAD_NEXT_LO 0x40 /* (RW) Next job queue head pointer for job slot n, low word */
#define JS_HEAD_NEXT_HI 0x44 /* (RW) Next job queue head pointer for job slot n, high word */
#define JS_AFFINITY_NEXT_LO 0x50 /* (RW) Next core affinity mask for job slot n, low word */
#define JS_AFFINITY_NEXT_HI 0x54 /* (RW) Next core affinity mask for job slot n, high word */
#define JS_CONFIG_NEXT 0x58 /* (RW) Next configuration settings for job slot n */
#define JS_COMMAND_NEXT 0x60 /* (RW) Next command register for job slot n */
#endif /* _UAPI_KBASE_GPU_REGMAP_JM_H_ */

2
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_id.h
View File

@@ -126,6 +126,8 @@
#define GPU_ID2_PRODUCT_LODX GPU_ID2_MODEL_MAKE(10, 7)
#define GPU_ID2_PRODUCT_TTUX GPU_ID2_MODEL_MAKE(11, 2)
#define GPU_ID2_PRODUCT_LTUX GPU_ID2_MODEL_MAKE(11, 3)
#define GPU_ID2_PRODUCT_TTIX GPU_ID2_MODEL_MAKE(12, 0)
#define GPU_ID2_PRODUCT_LTIX GPU_ID2_MODEL_MAKE(12, 1)
/**
* GPU_ID_MAKE - Helper macro to generate GPU_ID using id, major, minor, status

61
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_regmap.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -22,13 +22,70 @@
#ifndef _UAPI_KBASE_GPU_REGMAP_H_
#define _UAPI_KBASE_GPU_REGMAP_H_
#if !MALI_USE_CSF
#if MALI_USE_CSF
#include "backend/mali_kbase_gpu_regmap_csf.h"
#else
#include "backend/mali_kbase_gpu_regmap_jm.h"
#endif /* !MALI_USE_CSF */
/* Begin Register Offsets */
/* GPU control registers */
#define GPU_CONTROL_BASE 0x0000
#define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r))
#define GPU_ID 0x000 /* (RO) GPU and revision identifier */
#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
#define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
#define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
#define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
#define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
#define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
#define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
#define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
#define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
#define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
#define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
/* Job control registers */
#define JOB_CONTROL_BASE 0x1000
#define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r))
#define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */
#define JOB_IRQ_MASK 0x008 /* Interrupt mask register */
/* MMU control registers */
#define MEMORY_MANAGEMENT_BASE 0x2000
#define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r))
#define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */
#define MMU_AS0 0x400 /* Configuration registers for address space 0 */
/* MMU address space control registers */
#define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
#define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */
#define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */
#define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */
#define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */
#define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */
/* (RW) Translation table configuration for address space n, low word */
#define AS_TRANSCFG_LO 0x30
/* (RW) Translation table configuration for address space n, high word */
#define AS_TRANSCFG_HI 0x34
#endif /* _UAPI_KBASE_GPU_REGMAP_H_ */

4
include/uapi/gpu/arm/bifrost/jm/mali_base_jm_kernel.h
View File

@@ -1024,6 +1024,7 @@ struct base_dump_cpu_gpu_counters {
* is a bitpattern where a set bit indicates that the format is supported.
* Before using a texture format, it is recommended that the corresponding
* bit be checked.
* @paddings_1: Padding bytes.
* @gpu_available_memory_size: Theoretical maximum memory available to the GPU.
* It is unlikely that a client will be able to allocate all of this memory
* for their own purposes, but this at least provides an upper bound on the
@@ -1034,6 +1035,7 @@ struct base_dump_cpu_gpu_counters {
* @num_exec_engines: The number of execution engines. Only valid for tGOX
* (Bifrost) GPUs, where GPU_HAS_REG_CORE_FEATURES is defined. Otherwise,
* this is always 0.
* @paddings_2: Padding bytes.
*/
struct mali_base_gpu_core_props {
__u32 product_id;
@@ -1044,8 +1046,10 @@ struct mali_base_gpu_core_props {
__u32 gpu_freq_khz_max;
__u32 log2_program_counter_size;
__u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
__u8 paddings_1[4];
__u64 gpu_available_memory_size;
__u8 num_exec_engines;
__u8 paddings_2[7];
};
#endif /* _UAPI_BASE_JM_KERNEL_H_ */

8
include/uapi/gpu/arm/bifrost/jm/mali_kbase_jm_ioctl.h
View File

@@ -127,9 +127,15 @@
* - First release of new HW performance counters interface.
* 11.35:
* - Dummy model (no mali) backend will now clear HWC values after each sample
* 11.36:
* - Remove legacy definitions:
* - base_jit_alloc_info_10_2
* - base_jit_alloc_info_11_5
* - kbase_ioctl_mem_jit_init_10_2
* - kbase_ioctl_mem_jit_init_11_5
*/
#define BASE_UK_VERSION_MAJOR 11
#define BASE_UK_VERSION_MINOR 35
#define BASE_UK_VERSION_MINOR 36
/**
* struct kbase_ioctl_version_check - Check version compatibility between

59
include/uapi/gpu/arm/bifrost/mali_base_kernel.h
View File

@@ -197,55 +197,6 @@ struct base_mem_aliasing_info {
*/
#define BASE_JIT_ALLOC_COUNT (255)
/* base_jit_alloc_info in use for kernel driver versions 10.2 to early 11.5
*
* jit_version is 1
*
* Due to the lack of padding specified, user clients between 32 and 64-bit
* may have assumed a different size of the struct
*
* An array of structures was not supported
*/
struct base_jit_alloc_info_10_2 {
__u64 gpu_alloc_addr;
__u64 va_pages;
__u64 commit_pages;
__u64 extension;
__u8 id;
};
/* base_jit_alloc_info introduced by kernel driver version 11.5, and in use up
* to 11.19
*
* This structure had a number of modifications during and after kernel driver
* version 11.5, but remains size-compatible throughout its version history, and
* with earlier variants compatible with future variants by requiring
* zero-initialization to the unused space in the structure.
*
* jit_version is 2
*
* Kernel driver version history:
* 11.5: Initial introduction with 'usage_id' and padding[5]. All padding bytes
* must be zero. Kbase minor version was not incremented, so some
* versions of 11.5 do not have this change.
* 11.5: Added 'bin_id' and 'max_allocations', replacing 2 padding bytes (Kbase
* minor version not incremented)
* 11.6: Added 'flags', replacing 1 padding byte
* 11.10: Arrays of this structure are supported
*/
struct base_jit_alloc_info_11_5 {
__u64 gpu_alloc_addr;
__u64 va_pages;
__u64 commit_pages;
__u64 extension;
__u8 id;
__u8 bin_id;
__u8 max_allocations;
__u8 flags;
__u8 padding[2];
__u16 usage_id;
};
/**
* struct base_jit_alloc_info - Structure which describes a JIT allocation
* request.
@@ -275,16 +226,6 @@ struct base_jit_alloc_info_11_5 {
* @heap_info_gpu_addr: Pointer to an object in GPU memory describing
* the actual usage of the region.
*
* jit_version is 3.
*
* When modifications are made to this structure, it is still compatible with
* jit_version 3 when: a) the size is unchanged, and b) new members only
* replace the padding bytes.
*
* Previous jit_version history:
* jit_version == 1, refer to &base_jit_alloc_info_10_2
* jit_version == 2, refer to &base_jit_alloc_info_11_5
*
* Kbase version history:
* 11.20: added @heap_info_gpu_addr
*/

6
include/uapi/gpu/arm/bifrost/mali_kbase_hwcnt_reader.h
View File

@@ -221,6 +221,7 @@ struct prfcnt_enum_sample_info {
/**
* struct prfcnt_enum_item - Performance counter enumeration item.
* @padding: Padding bytes.
* @hdr: Header describing the type of item in the list.
* @u: Structure containing discriptor for enumeration item type.
* @u.block_counter: Performance counter block descriptor.
@@ -229,6 +230,7 @@ struct prfcnt_enum_sample_info {
*/
struct prfcnt_enum_item {
struct prfcnt_item_header hdr;
__u8 padding[4];
/** union u - union of block_counter and request */
union {
struct prfcnt_enum_block_counter block_counter;
@@ -305,6 +307,7 @@ struct prfcnt_request_scope {
/**
* struct prfcnt_request_item - Performance counter request item.
* @padding: Padding bytes.
* @hdr: Header describing the type of item in the list.
* @u: Structure containing descriptor for request type.
* @u.req_mode: Mode request descriptor.
@@ -313,6 +316,7 @@ struct prfcnt_request_scope {
*/
struct prfcnt_request_item {
struct prfcnt_item_header hdr;
__u8 padding[4];
/** union u - union on req_mode and req_enable */
union {
struct prfcnt_request_mode req_mode;
@@ -417,6 +421,7 @@ struct prfcnt_block_metadata {
/**
* struct prfcnt_metadata - Performance counter metadata item.
* @padding: Padding bytes.
* @hdr: Header describing the type of item in the list.
* @u: Structure containing descriptor for metadata type.
* @u.sample_md: Counter sample data metadata descriptor.
@@ -425,6 +430,7 @@ struct prfcnt_block_metadata {
*/
struct prfcnt_metadata {
struct prfcnt_item_header hdr;
__u8 padding[4];
union {
struct prfcnt_sample_metadata sample_md;
struct prfcnt_clock_metadata clock_md;

46
include/uapi/gpu/arm/bifrost/mali_kbase_ioctl.h
View File

@@ -218,52 +218,6 @@ struct kbase_ioctl_get_ddk_version {
#define KBASE_IOCTL_GET_DDK_VERSION \
_IOW(KBASE_IOCTL_TYPE, 13, struct kbase_ioctl_get_ddk_version)
/**
* struct kbase_ioctl_mem_jit_init_10_2 - Initialize the just-in-time memory
* allocator (between kernel driver
* version 10.2--11.4)
* @va_pages: Number of VA pages to reserve for JIT
*
* Note that depending on the VA size of the application and GPU, the value
* specified in @va_pages may be ignored.
*
* New code should use KBASE_IOCTL_MEM_JIT_INIT instead, this is kept for
* backwards compatibility.
*/
struct kbase_ioctl_mem_jit_init_10_2 {
__u64 va_pages;
};
#define KBASE_IOCTL_MEM_JIT_INIT_10_2 \
_IOW(KBASE_IOCTL_TYPE, 14, struct kbase_ioctl_mem_jit_init_10_2)
/**
* struct kbase_ioctl_mem_jit_init_11_5 - Initialize the just-in-time memory
* allocator (between kernel driver
* version 11.5--11.19)
* @va_pages: Number of VA pages to reserve for JIT
* @max_allocations: Maximum number of concurrent allocations
* @trim_level: Level of JIT allocation trimming to perform on free (0 - 100%)
* @group_id: Group ID to be used for physical allocations
* @padding: Currently unused, must be zero
*
* Note that depending on the VA size of the application and GPU, the value
* specified in @va_pages may be ignored.
*
* New code should use KBASE_IOCTL_MEM_JIT_INIT instead, this is kept for
* backwards compatibility.
*/
struct kbase_ioctl_mem_jit_init_11_5 {
__u64 va_pages;
__u8 max_allocations;
__u8 trim_level;
__u8 group_id;
__u8 padding[5];
};
#define KBASE_IOCTL_MEM_JIT_INIT_11_5 \
_IOW(KBASE_IOCTL_TYPE, 14, struct kbase_ioctl_mem_jit_init_11_5)
/**
* struct kbase_ioctl_mem_jit_init - Initialize the just-in-time memory
* allocator

35
include/uapi/gpu/arm/bifrost/mali_kbase_mem_profile_debugfs_buf_size.h Normal file
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@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2014, 2017-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
/**
* DOC: Header file for the size of the buffer to accumulate the histogram report text in
*/
#ifndef _UAPI_KBASE_MEM_PROFILE_DEBUGFS_BUF_SIZE_H_
#define _UAPI_KBASE_MEM_PROFILE_DEBUGFS_BUF_SIZE_H_
/**
* KBASE_MEM_PROFILE_MAX_BUF_SIZE - The size of the buffer to accumulate the histogram report text
* in @see @ref CCTXP_HIST_BUF_SIZE_MAX_LENGTH_REPORT
*/
#define KBASE_MEM_PROFILE_MAX_BUF_SIZE ((size_t)(64 + ((80 + (56 * 64)) * 54) + 56))
#endif /*_UAPI_KBASE_MEM_PROFILE_DEBUGFS_BUF_SIZE_H_*/