diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 3f9a8ebd7e83..8d96c0b28053 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -2381,7 +2381,7 @@
 			      "aclk1", "aclk2",
 			      "hclk0", "hclk1",
 			      "hclk2", "pclk";
-		assigned-clocks = <&cru CLK_NPU_DSU0>;
+		assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
 		assigned-clock-rates = <200000000>;
 		resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>,
 			 <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>;
@@ -2399,6 +2399,22 @@
 	npu_opp_table: npu-opp-table {
 		compatible = "operating-points-v2";
 
+		rockchip,pvtm-voltage-sel = <
+			0	840	0
+			841	865	1
+			866	890	2
+			891	915	3
+			916	9999	4
+		>;
+		rockchip,pvtm-pvtpll;
+		rockchip,pvtm-offset = <0x50>;
+		rockchip,pvtm-sample-time = <1100>;
+		rockchip,pvtm-freq = <800000>;
+		rockchip,pvtm-volt = <750000>;
+		rockchip,pvtm-ref-temp = <25>;
+		rockchip,pvtm-temp-prop = <175 81>;
+		rockchip,pvtm-thermal-zone = "npu-thermal";
+
 		clocks = <&cru PCLK_NPU_GRF>;
 		clock-names = "pclk";
 		rockchip,grf = <&npu_grf>;
@@ -2406,23 +2422,24 @@
 			855000	1
 			765000	2
 			675000	3
-			585000	4
+			495000	4
 		>;
+		low-volt-read-margin = <4>;
+		intermediate-threshold-freq = <500000>;	/* KHz*/
+		rockchip,init-freq = <1000000>;		/* KHz */
 
-		rockchip,init-freq = <1000000>; /* KHz */
-
-		opp-198000000 {
-			opp-hz = /bits/ 64 <198000000>;
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
 			opp-microvolt = <675000 675000 850000>,
 					<750000 750000 850000>;
 		};
-		opp-297000000 {
-			opp-hz = /bits/ 64 <297000000>;
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
 			opp-microvolt = <675000 675000 850000>,
 					<750000 750000 850000>;
 		};
-		opp-396000000 {
-			opp-hz = /bits/ 64 <396000000>;
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
 			opp-microvolt = <675000 675000 850000>,
 					<675000 675000 850000>;
 		};
@@ -2440,21 +2457,51 @@
 			opp-hz = /bits/ 64 <700000000>;
 			opp-microvolt = <700000 700000 850000>,
 					<700000 700000 850000>;
+			opp-microvolt-L2 = <687500 687500 850000>,
+					   <687500 687500 850000>;
+			opp-microvolt-L3 = <675000 675000 850000>,
+					   <675000 675000 850000>;
+			opp-microvolt-L4 = <675000 675000 850000>,
+					   <675000 675000 850000>;
 		};
 		opp-800000000 {
 			opp-hz = /bits/ 64 <800000000>;
 			opp-microvolt = <750000 750000 850000>,
 					<750000 750000 850000>;
+			opp-microvolt-L1 = <737500 737500 850000>,
+					   <737500 737500 850000>;
+			opp-microvolt-L2 = <725000 725000 850000>,
+					   <725000 725000 850000>;
+			opp-microvolt-L3 = <712500 712500 850000>,
+					   <712500 712500 850000>;
+			opp-microvolt-L4 = <712500 712500 850000>,
+					   <712500 712500 850000>;
 		};
 		opp-900000000 {
 			opp-hz = /bits/ 64 <900000000>;
 			opp-microvolt = <800000 800000 850000>,
 					<800000 800000 850000>;
+			opp-microvolt-L1 = <787500 787500 850000>,
+					   <787500 787500 850000>;
+			opp-microvolt-L2 = <775000 775000 850000>,
+					   <775000 775000 850000>;
+			opp-microvolt-L3 = <762500 762500 850000>,
+					   <762500 762500 850000>;
+			opp-microvolt-L4 = <750000 750000 850000>,
+					   <750000 750000 850000>;
 		};
 		opp-1000000000 {
 			opp-hz = /bits/ 64 <1000000000>;
 			opp-microvolt = <850000 850000 850000>,
 					<850000 850000 850000>;
+			opp-microvolt-L1 = <837500 837500 850000>,
+					   <837500 837500 850000>;
+			opp-microvolt-L2 = <825000 825000 850000>,
+					   <825000 825000 850000>;
+			opp-microvolt-L3 = <812500 812500 850000>,
+					   <812500 812500 850000>;
+			opp-microvolt-L4 = <800000 800000 850000>,
+					   <800000 800000 850000>;
 		};
 	};