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x86: Add new Intel CPU cache size descriptors

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commit 85160b92fb upstream.

The latest rev of Intel doc AP-485 details new cache descriptors
that we don't yet support. 12MB, 18MB and 24MB 24-way assoc L3
caches.

Signed-off-by: Dave Jones <davej@redhat.com>
LKML-Reference: <20091110184924.GA20337@redhat.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Dave Jones
2009-11-10 13:49:24 -05:00
committed by Greg Kroah-Hartman
parent cf8b14f356
commit 04071db2c1
1 changed files with 3 additions and 0 deletions
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3
arch/x86/kernel/cpu/intel_cacheinfo.c
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@@ -102,6 +102,9 @@ static const struct _cache_table __cpuinitconst cache_table[] =
{ 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */
{ 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
{ 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
{ 0xea, LVL_3, 12288 }, /* 24-way set assoc, 64 byte line size */
{ 0xeb, LVL_3, 18432 }, /* 24-way set assoc, 64 byte line size */
{ 0xec, LVL_3, 24576 }, /* 24-way set assoc, 64 byte line size */
{ 0x00, 0, 0}
};