From 04add2900912cff7a144a7c8e791f3ef4c9387dc Mon Sep 17 00:00:00 2001 From: Zitong Cai Date: Tue, 9 Sep 2025 20:28:25 +0800 Subject: [PATCH] arm64: dts: rockchip: vehicle-evb: Fix the issue of left and right shaking in probability display Change-Id: I759f845221455c2f0f5d227282fe7167fdab75f3 Signed-off-by: Zitong Cai --- ...icle-evb-v20-serdes-mfd-display-maxim.dtsi | 56 +++++-------------- ...ehicle-serdes-mfd-display-maxim-split.dtsi | 33 ++++++----- ...3588-vehicle-serdes-mfd-display-maxim.dtsi | 47 ++++++++-------- 3 files changed, 53 insertions(+), 83 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi index 5c08a3329b03..b66f9186ebf8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi @@ -282,62 +282,34 @@ 0322 0024 //Init Default 0326 00E4 - //HSYNC_WIDTH_L - 0385 0038 - //VSYNC_WIDTH_L - 0386 0008 + //HSYNC_WIDTH_L HSYNC=32 + 0385 0020 + //VSYNC_WIDTH_L VSYNC=2 + 0386 0002 //HSYNC_WIDTH_H/VSYNC_WIDTH_H 0387 0000 - //VFP_L + //VFP_L VFP=200 03A5 00C8 //VBP_H 03A7 0000 - //VFP_H/VBP_L - 03A6 0020 - //VRES_L + //VBP_L/VFP_H VBP=8 + 03A6 0080 + //VRES_L VRES=0X02D0=720 03A8 00D0 //VRES_H 03A9 0002 - //HFP_L + //HFP_L HFP=56 03AA 0038 //HBP_H - 03AC 0002 - //HFP_H/HBP_L - 03AB 0000 - //HRES_L + 03AC 0003 + //HBP_L/HFP_H(4bit) HBP=56 + 03AB 0080 + //HRES_L HRES=0X0780=1920 03AD 0080 //HRES_H 03AE 0007 //Disable FIFO/DESKEW_EN - 03A4 00C0 - //HSYNC_WIDTH_L - 0395 0038 - //VSYNC_WIDTH_L - 0396 0008 - //HSYNC_WIDTH_H/VSYNC_WIDTH_H - 0397 0000 - //VFP_L - 03B1 00C8 - //VBP_H - 03B3 0000 - //VFP_H/VBP_L - 03B2 0020 - //VRES_L - 03B4 00D0 - //VRES_H - 03B5 0002 - //HFP_L - 03B6 0038 - //HBP_H - 03B8 0002 - //HFP_H/HBP_L - 03B7 0000 - //HRES_L - 03B9 0080 - //HRES_H - 03BA 0007 - //Disable FIFO/DESKEW_EN - 03B0 00C0 + 03A4 00C1 //Turn on video pipe 0002 0033 //Enable splitter mode reset one shot diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi index 035c1cfb09d3..bf32c5cd090f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi @@ -499,8 +499,8 @@ 03A5 00C8 //VBP_H 03A7 0000 - //VFP_H/VBP_L VBP=8 - 03A6 0008 + //VBP_L/VFP_H VBP=8 + 03A6 0080 //VRES_L VRES=0X02D0=720 03A8 00D0 //VRES_H @@ -509,14 +509,14 @@ 03AA 0038 //HBP_H 03AC 0003 - //HFP_H/HBP_L(4bit) HBP=56 - 03AB 0008 + //HBP_L/HFP_H(4bit) HBP=56 + 03AB 0080 //HRES_L HRES=0X0780=1920 03AD 0080 //HRES_H 03AE 0007 //Disable FIFO/DESKEW_EN - 03A4 00C0 + 03A4 00C1 //HSYNC_WIDTH_L HSYNC=40 0395 0028 //VSYNC_WIDTH_L VSYNC=20 @@ -527,8 +527,8 @@ 03B1 000F //VBP_H 03B3 0000 - //VFP_H/VBP_L VBP=10 - 03B2 000A + //VBP_L/VFP_H VBP=10 + 03B2 00A0 //VRES_L VRES=0X0438=1080 03B4 0038 //VRES_H @@ -537,14 +537,14 @@ 03B6 008C //HBP_H 03B8 0006 - //HFP_H/HBP_L HBP=100 - 03B7 0004 + //HBP_L/HFP_H HBP=100 + 03B7 0040 //HRES_L HRES=0X0780=1920 03B9 0080 //HRES_H 03BA 0007 //Disable FIFO/DESKEW_EN - 03B0 00C0 + 03B0 00C1 //Turn on video pipe 0002 0033 //Enable splitter mode reset one shot @@ -740,7 +740,7 @@ panel-size= <346 194>; panel-timing { - clock-frequency = <115200000>; + clock-frequency = <115000000>; hactive = <1920>; vactive = <720>; hfront-porch = <56>; @@ -1422,7 +1422,7 @@ panel-size= <346 194>; panel-timing { - clock-frequency = <230400000>; //4128*930@60 + clock-frequency = <230000000>; //3840*720@60 hactive = <3840>; vactive = <720>; hfront-porch = <112>; @@ -1550,7 +1550,7 @@ panel-size= <346 194>; panel-timing { - clock-frequency = <115200000>; + clock-frequency = <115000000>; hactive = <1920>; vactive = <720>; hfront-porch = <56>; @@ -2101,7 +2101,7 @@ panel-size= <346 194>; panel-timing { - clock-frequency = <230400000>; //4128*930@60 + clock-frequency = <230000000>; //3840*720@60 hactive = <3840>; vactive = <720>; hfront-porch = <112>; @@ -2230,7 +2230,7 @@ panel-size= <346 194>; panel-timing { - clock-frequency = <115200000>; + clock-frequency = <115000000>; hactive = <1920>; vactive = <720>; hfront-porch = <56>; @@ -2413,8 +2413,7 @@ }; &vop { - assigned-clocks = <&cru PLL_V0PLL>; - assigned-clock-rates = <2304000000>; + status = "okay"; }; &vp0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim.dtsi index fbe04680f379..3c3b31b37226 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim.dtsi @@ -499,8 +499,8 @@ 03A5 00C8 //VBP_H 03A7 0000 - //VFP_H/VBP_L VBP=8 - 03A6 0008 + //VBP_L/VFP_H VBP=8 + 03A6 0080 //VRES_L VRES=0X02D0=720 03A8 00D0 //VRES_H @@ -509,42 +509,42 @@ 03AA 0038 //HBP_H 03AC 0003 - //HFP_H/HBP_L(4bit) HBP=56 - 03AB 0008 + //HBP_L/HFP_H(4bit) HBP=56 + 03AB 0080 //HRES_L HRES=0X0780=1920 03AD 0080 //HRES_H 03AE 0007 //Disable FIFO/DESKEW_EN - 03A4 00C0 - //HSYNC_WIDTH_L HSYNC=40 - 0395 0028 - //VSYNC_WIDTH_L VSYNC=20 - 0396 0014 + 03A4 00C1 + //HSYNC_WIDTH_L HSYNC=32 + 0395 0020 + //VSYNC_WIDTH_L VSYNC=2 + 0396 0002 //HSYNC_WIDTH_H/VSYNC_WIDTH_H 0397 0000 - //VFP_L VFP=15 - 03B1 000F + //VFP_L VFP=200 + 03B1 00C8 //VBP_H 03B3 0000 - //VFP_H/VBP_L VBP=10 - 03B2 000A - //VRES_L VRES=0X0438=1080 - 03B4 0038 + //VBP_L/VFP_H VBP=8 + 03B2 0080 + //VRES_L VRES=0X02D0=720 + 03B4 00D0 //VRES_H - 03B5 0004 - //HFP_L HFP=140 - 03B6 008C + 03B5 0002 + //HFP_L HFP=56 + 03B6 0038 //HBP_H - 03B8 0006 - //HFP_H/HBP_L HBP=100 - 03B7 0004 + 03B8 0003 + //HBP_L/HFP_H HBP=56 + 03B7 0080 //HRES_L HRES=0X0780=1920 03B9 0080 //HRES_H 03BA 0007 //Disable FIFO/DESKEW_EN - 03B0 00C0 + 03B0 00C1 //Turn on video pipe 0002 0033 //Enable splitter mode reset one shot @@ -2103,8 +2103,7 @@ }; &vop { - assigned-clocks = <&cru PLL_V0PLL>; - assigned-clock-rates = <1150000000>; + status = "okay"; }; //dp &vp0 {