From 04da7662847da195c9f409b5c1796caa2d567f6a Mon Sep 17 00:00:00 2001 From: William Wu Date: Thu, 19 Jul 2018 10:34:28 +0800 Subject: [PATCH] usb: dwc3: Don't reset core in host mode When do core init, only reset the core for device mode. Becasue in host mode, xHCI driver will reset the core and its host block via usbcmd.hcrst. If we do core reset in dwc3_core_init() for host mode, it will reset both the dwc3 core registers and xHCI registers, and cause device to be reenumerated when usb suspend/resume. Change-Id: If723ce8a771975e9757d28cb2c114d6269581677 Signed-off-by: William Wu --- drivers/usb/dwc3/core.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index b4d1d887be31..366738c582bf 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -100,7 +100,10 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) * XHCI driver will reset the host block. If dwc3 was configured for * host-only mode, then we can return early. */ - if (dwc->dr_mode == USB_DR_MODE_HOST) + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + if (dwc->dr_mode == USB_DR_MODE_HOST || + (dwc->dr_mode == USB_DR_MODE_OTG && + DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST)) return 0; reg = dwc3_readl(dwc->regs, DWC3_DCTL); @@ -127,6 +130,17 @@ static int dwc3_soft_reset(struct dwc3 *dwc) unsigned long timeout; u32 reg; + /* + * We're resetting only the device side because, if we're in host mode, + * XHCI driver will reset the host block. If dwc3 was configured for + * host-only mode, then we can return early. + */ + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + if (dwc->dr_mode == USB_DR_MODE_HOST || + (dwc->dr_mode == USB_DR_MODE_OTG && + DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST)) + return 0; + timeout = jiffies + msecs_to_jiffies(500); dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); do {