From 058b229588b79b95bb315a03ef3d875b9d8b42cb Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 17 Dec 2024 22:38:58 +0800 Subject: [PATCH] phy: rockchip-snps-pcie3: Configure registers only when defining phy mode Change-Id: I75ef3313d59708f9238dbb7cac3a7f210fb97c9b Signed-off-by: Jon Lin --- drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index a10e23b68115..5841a41a6703 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -276,17 +276,15 @@ static int rockchip_p3phy_probe(struct platform_device *pdev) dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val); - if (!ret) + if (!ret) { priv->pcie30_phymode = val; - else + if (priv->pcie30_phymode > 4) + priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION; + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, + (0x7<<16) | priv->pcie30_phymode); + } else { priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION; - - /* Select correct pcie30_phymode */ - if (priv->pcie30_phymode > 4) - priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION; - - regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, - (0x7<<16) | priv->pcie30_phymode); + } /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ if (!IS_ERR(priv->pipe_grf)) {