From 05c62decf906cabf8a4e5d30271b14fd8a3ead7c Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 29 Aug 2023 14:51:58 +0800 Subject: [PATCH] soc: rockchip: opp_select: Fix set scmi clk rate error Fixes: c64369f0e48e ("soc: rockchip: opp_select: Implements new opp APIs for kernel 6.1") Change-Id: I1c2e71016bacd846f4146e8036c85f9271a15e93 Signed-off-by: Finley Xiao --- drivers/soc/rockchip/rockchip_opp_select.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c index 0fcda11958a4..236e7ab9dad1 100644 --- a/drivers/soc/rockchip/rockchip_opp_select.c +++ b/drivers/soc/rockchip/rockchip_opp_select.c @@ -2119,6 +2119,12 @@ int rockchip_opp_config_clks(struct device *dev, struct opp_table *opp_table, if (!info->is_runtime_active) return 0; + ret = clk_bulk_prepare_enable(info->nclocks, info->clocks); + if (ret) { + dev_err(dev, "failed to enable opp clks\n"); + return ret; + } + dev_dbg(dev, "%lu -> %lu (Hz)\n", opp_table->rate_clk_single, *target); ret = clk_set_rate(opp_table->clk, *target); if (ret) @@ -2126,6 +2132,8 @@ int rockchip_opp_config_clks(struct device *dev, struct opp_table *opp_table, else opp_table->rate_clk_single = *target; + clk_bulk_disable_unprepare(info->nclocks, info->clocks); + return ret; } EXPORT_SYMBOL(rockchip_opp_config_clks);