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vdin: disable afbce under 4k resolution [1/1]
PD#SWPL-7511 Problem: no need enable vdin afbce under 4k, it is no help for bandwidth with these resolution Solution: only enable vdin afbce for 4k resolution Verify: x301 Change-Id: I283efd872004846d158ef6c9addbd1e666d2f61a Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
@@ -828,6 +828,8 @@ static void vdin_dump_state(struct vdin_dev_s *devp)
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devp->dv.dv_flag, devp->dv.dv_config, devp->prop.dolby_vision);
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pr_info("size of struct vdin_dev_s: %d\n", devp->vdin_dev_ssize);
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pr_info("afbce_flag: %d\n", devp->afbce_flag);
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pr_info("afbce_mode: %d\n", devp->afbce_mode);
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if (devp->afbce_mode == 1) {
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for (i = 0; i < devp->vfmem_max_cnt; i++) {
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pr_info("head(%d) addr:0x%lx, size:0x%x\n",
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@@ -78,8 +78,10 @@ static unsigned int vdin_addr_offset[VDIN_MAX_DEVS] = {0, 0x80};
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static struct vdin_dev_s *vdin_devp[VDIN_MAX_DEVS];
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static unsigned long mem_start, mem_end;
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static unsigned int use_reserved_mem;
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static int afbc_init_flag[VDIN_MAX_DEVS];
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static unsigned int pr_times;
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/* afbce related */
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static int afbc_init_flag[VDIN_MAX_DEVS];
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unsigned int tl1_vdin1_preview_flag;
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static unsigned int tl1_vdin1_data_readied;
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static unsigned int tl1_vdin1_canvas_addr;
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@@ -536,6 +538,17 @@ void vdin_start_dec(struct vdin_dev_s *devp)
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vdin_wr_reverse(devp->addr_offset,
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devp->parm.h_reverse,
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devp->parm.v_reverse);
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/* check if need enable afbce */
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if (devp->afbce_flag == 1) {
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if ((devp->h_active > 1920) && (devp->v_active > 1080))
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devp->afbce_mode = 1;
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else
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devp->afbce_mode = 0;
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pr_info("vdin%d afbce_mode: %d\n",
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devp->index, devp->afbce_mode);
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}
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#ifdef CONFIG_CMA
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vdin_cma_malloc_mode(devp);
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if (devp->afbce_mode == 1) {
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@@ -612,12 +625,10 @@ void vdin_start_dec(struct vdin_dev_s *devp)
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vdin_hw_enable(devp->addr_offset);
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vdin_set_all_regs(devp);
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if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
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if (devp->afbce_mode == 0)
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vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF);
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else if (devp->afbce_mode == 1)
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vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_AFBCE);
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}
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if (devp->afbce_mode == 0)
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vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF);
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else if (devp->afbce_mode == 1)
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vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_AFBCE);
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if (!(devp->parm.flag & TVIN_PARM_FLAG_CAP) &&
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(devp->frontend) &&
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@@ -713,8 +724,7 @@ void vdin_stop_dec(struct vdin_dev_s *devp)
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disable_irq_nosync(devp->irq);
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afbc_init_flag[devp->index] = 0;
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if ((is_meson_tl1_cpu() || is_meson_tm2_cpu())
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&& (devp->afbce_mode == 1)) {
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if (devp->afbce_mode == 1) {
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while (i++ < afbc_write_down_timeout) {
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if (vdin_afbce_read_writedown_flag())
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break;
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@@ -756,8 +766,7 @@ void vdin_stop_dec(struct vdin_dev_s *devp)
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vf_unreg_provider(&devp->vprov);
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devp->dv.dv_config = 0;
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if ((is_meson_tl1_cpu() || is_meson_tm2_cpu())
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&& (devp->afbce_mode == 1)) {
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if (devp->afbce_mode == 1) {
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vdin_afbce_hw_disable();
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vdin_afbce_soft_reset();
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}
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@@ -1445,8 +1454,7 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
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offset = devp->addr_offset;
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if ((is_meson_tl1_cpu() || is_meson_tm2_cpu())
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&& (devp->afbce_mode == 1)) {
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if (devp->afbce_mode == 1) {
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if (afbc_init_flag[devp->index] == 0) {
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afbc_init_flag[devp->index] = 1;
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/*set mem power on*/
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@@ -1467,7 +1475,7 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
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*/
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spin_lock_irqsave(&devp->isr_lock, flags);
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if (is_meson_tl1_cpu() && (devp->afbce_mode == 1)) {
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if (devp->afbce_mode == 1) {
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/* no need reset mif under afbc mode */
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devp->vdin_reset_flag = 0;
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} else {
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@@ -2339,8 +2347,7 @@ static int vdin_open(struct inode *inode, struct file *file)
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return 0;
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}
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if ((devp->afbce_mode == 1) &&
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(is_meson_tl1_cpu() || is_meson_tm2_cpu()))
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if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()))
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switch_vpu_mem_pd_vmod(VPU_AFBCE, VPU_MEM_POWER_ON);
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devp->flags |= VDIN_FLAG_FS_OPENED;
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@@ -2389,8 +2396,7 @@ static int vdin_release(struct inode *inode, struct file *file)
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return 0;
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}
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if ((devp->afbce_mode == 1) &&
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(is_meson_tl1_cpu() || is_meson_tm2_cpu()))
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if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()))
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switch_vpu_mem_pd_vmod(VPU_AFBCE, VPU_MEM_POWER_DOWN);
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devp->flags &= (~VDIN_FLAG_FS_OPENED);
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@@ -3336,22 +3342,21 @@ static int vdin_drv_probe(struct platform_device *pdev)
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ret = of_property_read_u32(pdev->dev.of_node,
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"afbce_bit_mode", &val);
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if (ret) {
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vdevp->afbce_mode = 0;
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pr_info("no afbce mode found, use normal mode\n");
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vdevp->afbce_flag = 0;
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} else {
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vdevp->afbce_mode = val & 0xf;
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vdevp->afbce_flag = val & 0xf;
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vdevp->afbce_lossy_en = (val>>4)&0xf;
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if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) &&
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(vdevp->index == 0)) {
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/* just use afbce at vdin0 */
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pr_info("afbce mode = %d\n", vdevp->afbce_mode);
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pr_info("afbce flag = %d\n", vdevp->afbce_flag);
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pr_info("afbce loosy en = %d\n", vdevp->afbce_lossy_en);
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vdevp->afbce_info = devm_kzalloc(vdevp->dev,
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sizeof(struct vdin_afbce_s), GFP_KERNEL);
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if (!vdevp->afbce_info)
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goto fail_kzalloc_vdev;
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} else {
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vdevp->afbce_mode = 0;
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vdevp->afbce_flag = 0;
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pr_info("get afbce from dts, but chip cannot support\n");
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}
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}
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@@ -329,6 +329,7 @@ struct vdin_dev_s {
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* 1: use afbce non-mmu mode: head/body addr set by code
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* 2: use afbce mmu mode: head set by code, body addr assigning by hw
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*/
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unsigned int afbce_flag;
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unsigned int afbce_mode;
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unsigned int afbce_lossy_en;
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unsigned int canvas_config_mode;
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