vdin: disable afbce under 4k resolution [1/1]

PD#SWPL-7511

Problem:
no need enable vdin afbce under 4k,
it is no help for bandwidth with these resolution

Solution:
only enable vdin afbce for 4k resolution

Verify:
x301

Change-Id: I283efd872004846d158ef6c9addbd1e666d2f61a
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2019-04-20 17:55:10 +08:00
committed by Tao Zeng
parent c912a3d588
commit 05df3113ca
3 changed files with 31 additions and 23 deletions

View File

@@ -828,6 +828,8 @@ static void vdin_dump_state(struct vdin_dev_s *devp)
devp->dv.dv_flag, devp->dv.dv_config, devp->prop.dolby_vision); devp->dv.dv_flag, devp->dv.dv_config, devp->prop.dolby_vision);
pr_info("size of struct vdin_dev_s: %d\n", devp->vdin_dev_ssize); pr_info("size of struct vdin_dev_s: %d\n", devp->vdin_dev_ssize);
pr_info("afbce_flag: %d\n", devp->afbce_flag);
pr_info("afbce_mode: %d\n", devp->afbce_mode);
if (devp->afbce_mode == 1) { if (devp->afbce_mode == 1) {
for (i = 0; i < devp->vfmem_max_cnt; i++) { for (i = 0; i < devp->vfmem_max_cnt; i++) {
pr_info("head(%d) addr:0x%lx, size:0x%x\n", pr_info("head(%d) addr:0x%lx, size:0x%x\n",

View File

@@ -78,8 +78,10 @@ static unsigned int vdin_addr_offset[VDIN_MAX_DEVS] = {0, 0x80};
static struct vdin_dev_s *vdin_devp[VDIN_MAX_DEVS]; static struct vdin_dev_s *vdin_devp[VDIN_MAX_DEVS];
static unsigned long mem_start, mem_end; static unsigned long mem_start, mem_end;
static unsigned int use_reserved_mem; static unsigned int use_reserved_mem;
static int afbc_init_flag[VDIN_MAX_DEVS];
static unsigned int pr_times; static unsigned int pr_times;
/* afbce related */
static int afbc_init_flag[VDIN_MAX_DEVS];
unsigned int tl1_vdin1_preview_flag; unsigned int tl1_vdin1_preview_flag;
static unsigned int tl1_vdin1_data_readied; static unsigned int tl1_vdin1_data_readied;
static unsigned int tl1_vdin1_canvas_addr; static unsigned int tl1_vdin1_canvas_addr;
@@ -536,6 +538,17 @@ void vdin_start_dec(struct vdin_dev_s *devp)
vdin_wr_reverse(devp->addr_offset, vdin_wr_reverse(devp->addr_offset,
devp->parm.h_reverse, devp->parm.h_reverse,
devp->parm.v_reverse); devp->parm.v_reverse);
/* check if need enable afbce */
if (devp->afbce_flag == 1) {
if ((devp->h_active > 1920) && (devp->v_active > 1080))
devp->afbce_mode = 1;
else
devp->afbce_mode = 0;
pr_info("vdin%d afbce_mode: %d\n",
devp->index, devp->afbce_mode);
}
#ifdef CONFIG_CMA #ifdef CONFIG_CMA
vdin_cma_malloc_mode(devp); vdin_cma_malloc_mode(devp);
if (devp->afbce_mode == 1) { if (devp->afbce_mode == 1) {
@@ -612,12 +625,10 @@ void vdin_start_dec(struct vdin_dev_s *devp)
vdin_hw_enable(devp->addr_offset); vdin_hw_enable(devp->addr_offset);
vdin_set_all_regs(devp); vdin_set_all_regs(devp);
if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) { if (devp->afbce_mode == 0)
if (devp->afbce_mode == 0) vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF);
vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF); else if (devp->afbce_mode == 1)
else if (devp->afbce_mode == 1) vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_AFBCE);
vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_AFBCE);
}
if (!(devp->parm.flag & TVIN_PARM_FLAG_CAP) && if (!(devp->parm.flag & TVIN_PARM_FLAG_CAP) &&
(devp->frontend) && (devp->frontend) &&
@@ -713,8 +724,7 @@ void vdin_stop_dec(struct vdin_dev_s *devp)
disable_irq_nosync(devp->irq); disable_irq_nosync(devp->irq);
afbc_init_flag[devp->index] = 0; afbc_init_flag[devp->index] = 0;
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) if (devp->afbce_mode == 1) {
&& (devp->afbce_mode == 1)) {
while (i++ < afbc_write_down_timeout) { while (i++ < afbc_write_down_timeout) {
if (vdin_afbce_read_writedown_flag()) if (vdin_afbce_read_writedown_flag())
break; break;
@@ -756,8 +766,7 @@ void vdin_stop_dec(struct vdin_dev_s *devp)
vf_unreg_provider(&devp->vprov); vf_unreg_provider(&devp->vprov);
devp->dv.dv_config = 0; devp->dv.dv_config = 0;
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) if (devp->afbce_mode == 1) {
&& (devp->afbce_mode == 1)) {
vdin_afbce_hw_disable(); vdin_afbce_hw_disable();
vdin_afbce_soft_reset(); vdin_afbce_soft_reset();
} }
@@ -1445,8 +1454,7 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
offset = devp->addr_offset; offset = devp->addr_offset;
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) if (devp->afbce_mode == 1) {
&& (devp->afbce_mode == 1)) {
if (afbc_init_flag[devp->index] == 0) { if (afbc_init_flag[devp->index] == 0) {
afbc_init_flag[devp->index] = 1; afbc_init_flag[devp->index] = 1;
/*set mem power on*/ /*set mem power on*/
@@ -1467,7 +1475,7 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
*/ */
spin_lock_irqsave(&devp->isr_lock, flags); spin_lock_irqsave(&devp->isr_lock, flags);
if (is_meson_tl1_cpu() && (devp->afbce_mode == 1)) { if (devp->afbce_mode == 1) {
/* no need reset mif under afbc mode */ /* no need reset mif under afbc mode */
devp->vdin_reset_flag = 0; devp->vdin_reset_flag = 0;
} else { } else {
@@ -2339,8 +2347,7 @@ static int vdin_open(struct inode *inode, struct file *file)
return 0; return 0;
} }
if ((devp->afbce_mode == 1) && if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()))
(is_meson_tl1_cpu() || is_meson_tm2_cpu()))
switch_vpu_mem_pd_vmod(VPU_AFBCE, VPU_MEM_POWER_ON); switch_vpu_mem_pd_vmod(VPU_AFBCE, VPU_MEM_POWER_ON);
devp->flags |= VDIN_FLAG_FS_OPENED; devp->flags |= VDIN_FLAG_FS_OPENED;
@@ -2389,8 +2396,7 @@ static int vdin_release(struct inode *inode, struct file *file)
return 0; return 0;
} }
if ((devp->afbce_mode == 1) && if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()))
(is_meson_tl1_cpu() || is_meson_tm2_cpu()))
switch_vpu_mem_pd_vmod(VPU_AFBCE, VPU_MEM_POWER_DOWN); switch_vpu_mem_pd_vmod(VPU_AFBCE, VPU_MEM_POWER_DOWN);
devp->flags &= (~VDIN_FLAG_FS_OPENED); devp->flags &= (~VDIN_FLAG_FS_OPENED);
@@ -3336,22 +3342,21 @@ static int vdin_drv_probe(struct platform_device *pdev)
ret = of_property_read_u32(pdev->dev.of_node, ret = of_property_read_u32(pdev->dev.of_node,
"afbce_bit_mode", &val); "afbce_bit_mode", &val);
if (ret) { if (ret) {
vdevp->afbce_mode = 0; vdevp->afbce_flag = 0;
pr_info("no afbce mode found, use normal mode\n");
} else { } else {
vdevp->afbce_mode = val & 0xf; vdevp->afbce_flag = val & 0xf;
vdevp->afbce_lossy_en = (val>>4)&0xf; vdevp->afbce_lossy_en = (val>>4)&0xf;
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) && if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) &&
(vdevp->index == 0)) { (vdevp->index == 0)) {
/* just use afbce at vdin0 */ /* just use afbce at vdin0 */
pr_info("afbce mode = %d\n", vdevp->afbce_mode); pr_info("afbce flag = %d\n", vdevp->afbce_flag);
pr_info("afbce loosy en = %d\n", vdevp->afbce_lossy_en); pr_info("afbce loosy en = %d\n", vdevp->afbce_lossy_en);
vdevp->afbce_info = devm_kzalloc(vdevp->dev, vdevp->afbce_info = devm_kzalloc(vdevp->dev,
sizeof(struct vdin_afbce_s), GFP_KERNEL); sizeof(struct vdin_afbce_s), GFP_KERNEL);
if (!vdevp->afbce_info) if (!vdevp->afbce_info)
goto fail_kzalloc_vdev; goto fail_kzalloc_vdev;
} else { } else {
vdevp->afbce_mode = 0; vdevp->afbce_flag = 0;
pr_info("get afbce from dts, but chip cannot support\n"); pr_info("get afbce from dts, but chip cannot support\n");
} }
} }

View File

@@ -329,6 +329,7 @@ struct vdin_dev_s {
* 1: use afbce non-mmu mode: head/body addr set by code * 1: use afbce non-mmu mode: head/body addr set by code
* 2: use afbce mmu mode: head set by code, body addr assigning by hw * 2: use afbce mmu mode: head set by code, body addr assigning by hw
*/ */
unsigned int afbce_flag;
unsigned int afbce_mode; unsigned int afbce_mode;
unsigned int afbce_lossy_en; unsigned int afbce_lossy_en;
unsigned int canvas_config_mode; unsigned int canvas_config_mode;