From 0657602584a253d208d11ffb0cf81659f9db1ca2 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 7 Dec 2020 09:18:27 +0800 Subject: [PATCH] clk: rockchip: rk3568: export cpll_xxx clk id for more function Signed-off-by: Elaine Zhang Change-Id: I5f310f9b857623a5a204ab9b5f0a4befde894684 --- drivers/clk/rockchip/clk-rk3568.c | 14 +++++++------- include/dt-bindings/clock/rk3568-cru.h | 8 ++++++++ 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index d5e76faa9e32..a9cfa187b19b 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -483,28 +483,28 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(78), 0, 6, DFLAGS, RK3568_CLKGATE_CON(35), 6, GFLAGS), - COMPOSITE_NOMUX(0, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(78), 8, 5, DFLAGS, RK3568_CLKGATE_CON(35), 7, GFLAGS), COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(79), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 8, GFLAGS), - COMPOSITE_NOMUX(0, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(79), 8, 5, DFLAGS, RK3568_CLKGATE_CON(35), 9, GFLAGS), - COMPOSITE_NOMUX(0, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 10, GFLAGS), - COMPOSITE_NOMUX(0, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, RK3568_CLKGATE_CON(35), 11, GFLAGS), - COMPOSITE_NOMUX(0, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 12, GFLAGS), - COMPOSITE_NOMUX(0, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, RK3568_CLKGATE_CON(35), 13, GFLAGS), - COMPOSITE_NOMUX(0, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, + COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 14, GFLAGS), COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h index 236c7925666b..566a04384892 100644 --- a/include/dt-bindings/clock/rk3568-cru.h +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -471,6 +471,14 @@ #define CLK_I2S2_2CH 408 #define CLK_I2S3_2CH_TX 409 #define CLK_I2S3_2CH_RX 410 +#define CPLL_500M 411 +#define CPLL_250M 412 +#define CPLL_125M 413 +#define CPLL_62P5M 414 +#define CPLL_50M 415 +#define CPLL_25M 416 +#define CPLL_100M 417 + #define PCLK_CORE_PVTM 450 #define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)