From 06a2bad16e5716e3c54e7ba7fa837bd4033c11cd Mon Sep 17 00:00:00 2001 From: Luo Wei Date: Thu, 27 Jun 2024 16:32:25 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588-vehicle-evb: init v23 dts files Signed-off-by: Luo Wei Signed-off-by: Cai Wenzhong Signed-off-by: Xu Xuehui Signed-off-by: Jianqun Xu Signed-off-by: Zheng zhiqi Change-Id: Id704f2ee9a4f1c117cad6ae63f2d71f93c9dcc12 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + ...hicle-evb-maxim-max96712-dphy3-isx021.dtsi | 726 +++++ .../rk3588-vehicle-evb-v23-audio.dtsi | 120 + .../dts/rockchip/rk3588-vehicle-evb-v23.dts | 643 +++++ ...3588-vehicle-serdes-mfd-display-maxim.dtsi | 2380 ++++++++++++----- 5 files changed, 3198 insertions(+), 672 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy3-isx021.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 17dd9a0db37c..1fe167b0b185 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -323,6 +323,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v20.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v21.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v22.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v23.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-s66-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy3-isx021.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy3-isx021.dtsi new file mode 100644 index 000000000000..66a0c81a41ed --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy3-isx021.dtsi @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ +#include + +/ { + max96712_dphy3_osc: max96712-dphy3-oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-dphy3-osc"; + }; + + max96712_dphy3_vcc1v2: max96712-dphy3-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy3_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc5v0_sys>; + }; + + max96712_dphy3_vcc1v8: max96712-dphy3-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy3_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_3v3_s3>; + }; + + max96712_dphy3_pwdn_regulator: max96712-dphy3-pwdn-regulator { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy3_pwdn"; + gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dphy3_pwdn>; + enable-active-high; + startup-delay-us = <10000>; + off-on-delay-us = <5000>; + vin-supply = <&max96712_dphy3_vcc1v8>; + }; + + max96712_dphy3_poc_regulator: max96712-dphy3-poc-regulator { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy3_poc"; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + off-on-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy3_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy3_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + max96712_dphy3: max96712@29 { + compatible = "maxim4c,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_dphy3_osc 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dphy3_errb>, <&max96712_dphy3_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + vcc1v2-supply = <&max96712_dphy3_vcc1v2>; + vcc1v8-supply = <&max96712_dphy3_vcc1v8>; + pwdn-supply = <&max96712_dphy3_pwdn_regulator>; + lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + + port { + max96712_dphy3_out: endpoint { + remote-endpoint = <&mipi_dphy3_in_max96712>; + data-lanes = <1 2 3 4>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1920>; + sensor-height = <1281>; + crop-rect = <0 1 1920 1280>; // [ left, top, width, height ] + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <1>; // 0: GMSL1, 1: GMSL2 + link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS + link-tx-rate = <0>; // 0: default for 187.5MBPS + + link-remote-cam = <&max96712_dphy3_cam0>; // remote camera + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <1>; // 0: GMSL1, 1: GMSL2 + link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS + link-tx-rate = <0>; // 0: default for 187.5MBPS + + link-remote-cam = <&max96712_dphy3_cam1>; // remote camera + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link C: link-id = 2 + gmsl-link-config-2 { + status = "okay"; + link-id = <2>; // Link ID: 0/1/2/3 + + link-type = <1>; // 0: GMSL1, 1: GMSL2 + link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS + link-tx-rate = <0>; // 0: default for 187.5MBPS + + link-remote-cam = <&max96712_dphy3_cam2>; // remote camera + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 16 D1 03 00 00 // VGAHiGain + 16 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link D: link-id = 3 + gmsl-link-config-3 { + status = "okay"; + link-id = <3>; // Link ID: 0/1/2/3 + + link-type = <1>; // 0: GMSL1, 1: GMSL2 + link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS + link-tx-rate = <0>; // 0: default for 187.5MBPS + + link-remote-cam = <&max96712_dphy3_cam3>; // remote camera + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 17 D1 03 00 00 // VGAHiGain + 17 45 00 00 00 // Disable SSC + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + ]; + }; + }; + + // Video Pipe 2 + video-pipe-config-2 { + status = "okay"; + pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <2>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 + 09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit + 09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 90 80 00 00 // DST1 VC = 2, DT = Frame Start + 09 91 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 92 81 00 00 // DST2 VC = 2, DT = Frame End + ]; + }; + }; + + // Video Pipe 3 + video-pipe-config-3 { + status = "okay"; + pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <3>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 + 09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit + 09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start + 09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes + phy-force-clock-out = <1>; // 1: default for force clock out + phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0 + phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3 + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; // 0: DPHY, 1: CPHY + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; // 0: DPHY, 1: CPHY + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "okay"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + 04 A2 00 00 00 // Master link Video 0 for frame sync generation + 04 AA 00 00 00 // Disable Vsync-Fsync overlap window + 04 AB 00 00 00 // Disable Vsync-Fsync overlap window + 04 A8 00 00 00 // FRM_DIFF_ERR_THR_L + 04 A9 00 00 00 // FRM_DIFF_ERR_THR_H + 04 A7 0c 00 00 // FSYNC_PERIOD_H, Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz + 04 A6 bf 00 00 // FSYNC_PERIOD_M + 04 A5 35 00 00 // FSYNC_PERIOD_L + 04 AF c0 00 00 // FSYNC is GMSL2 type, use osc for fsync + 04 B1 40 00 00 // FSYNC_TX_ID: set 8 to match MFP8 on serializer side + 04 A0 04 00 00 // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode + ]; + }; + }; + /* serdes local device end */ + + /* i2c-mux start */ + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + // Note: Serializer node defined before camera node + max96712_dphy3_ser0: max96717@41 { + compatible = "maxim,ser,max96717f"; + reg = <0x41>; + + ser-i2c-addr-def = <0x40>; + + ser-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 03 02 10 00 00 + 14 17 00 00 00 + 14 32 7f 00 00 + ]; + }; + }; + + max96712_dphy3_cam0: isx021@31 { + compatible = "maxim,dummy,sensor"; + reg = <0x31>; + + cam-i2c-addr-def = <0x30>; + + cam-remote-ser = <&max96712_dphy3_ser0>; // remote serializer + + poc-supply = <&max96712_dphy3_poc_regulator>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + + /* port config start */ + port { + max96712_dphy3_cam0_out: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + /* port config end */ + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // Note: Serializer node defined before camera node + max96712_dphy3_ser1: max96717@42 { + compatible = "maxim,ser,max96717f"; + reg = <0x42>; + + ser-i2c-addr-def = <0x40>; + + ser-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 03 02 10 00 00 + 14 17 00 00 00 + 14 32 7f 00 00 + ]; + }; + }; + + max96712_dphy3_cam1: isx021@32 { + compatible = "maxim,dummy,sensor"; + reg = <0x32>; + + cam-i2c-addr-def = <0x30>; + + cam-remote-ser = <&max96712_dphy3_ser1>; // remote serializer + + poc-supply = <&max96712_dphy3_poc_regulator>; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + + /* port config start */ + port { + max96712_dphy3_cam1_out: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + /* port config end */ + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + // Note: Serializer node defined before camera node + max96712_dphy3_ser2: max96717@43 { + compatible = "maxim,ser,max96717f"; + reg = <0x43>; + + ser-i2c-addr-def = <0x40>; + + ser-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 03 02 10 00 00 + 14 17 00 00 00 + 14 32 7f 00 00 + ]; + }; + }; + + max96712_dphy3_cam2: isx021@33 { + compatible = "maxim,dummy,sensor"; + reg = <0x33>; + + cam-i2c-addr-def = <0x30>; + + cam-remote-ser = <&max96712_dphy3_ser2>; // remote serializer + + poc-supply = <&max96712_dphy3_poc_regulator>; + + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + + /* port config start */ + port { + max96712_dphy3_cam2_out: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + /* port config end */ + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + // Note: Serializer node defined before camera node + max96712_dphy3_ser3: max96717@44 { + compatible = "maxim,ser,max96717f"; + reg = <0x44>; + + ser-i2c-addr-def = <0x40>; + + ser-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 03 02 10 00 00 + 14 17 00 00 00 + 14 32 7f 00 00 + ]; + }; + }; + + max96712_dphy3_cam3: isx021@34 { + compatible = "maxim,dummy,sensor"; + reg = <0x34>; + + cam-i2c-addr-def = <0x30>; + + cam-remote-ser = <&max96712_dphy3_ser3>; // remote serializer + + poc-supply = <&max96712_dphy3_poc_regulator>; + + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + + /* port config start */ + port { + max96712_dphy3_cam3_out: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + /* port config end */ + }; + }; + }; + /* i2c-mux end */ + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi4_in: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96712-dphy3 { + max96712_dphy3_pwdn: max96712-dphy3-pwdn { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dphy3_errb: max96712-dphy3-errb { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dphy3_lock: max96712-dphy3-lock { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi new file mode 100644 index 000000000000..a7d9a60fe7ae --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/ { + /delete-node/ car-rk3308-sound; + + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + status = "okay"; + }; + + sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,tdm"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + bt_codec: bt-codec { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; + + sound1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,format = "i2s"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_codec 1>; + }; + }; +}; + +&i2s0_8ch { + status = "disabled"; +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_lrck_rx + &i2s1m0_lrck_tx + &i2s1m0_sclk_rx + &i2s1m0_sclk_tx + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &gpio_fsxn_pins>; + fsxn-rx-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + fsxn-tx-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,tdm-multi-lanes; + rockchip,tdm-tx-lanes = <3>; + rockchip,tdm-rx-lanes = <2>; + /delete-property/ rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + status = "okay"; +}; + +&pinctrl { + i2s1_rx_tx { + i2s1m0_lrck_rx: i2s1m0-lrck-rx { + rockchip,pins = + /* i2s1m0_lrck_rx */ + <4 RK_PA4 3 &pcfg_pull_none>; + }; + + i2s1m0_lrck_tx: i2s1m0-lrck-tx { + rockchip,pins = + /* i2s1m0_lrck_tx */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + + i2s1m0_sclk_rx: i2s1m0-sclk-rx { + rockchip,pins = + /* i2s1m0_sclk_rx */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + + i2s1m0_sclk_tx: i2s1m0-sclk-tx { + rockchip,pins = + /* i2s1m0_sclk_tx */ + <4 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + fsxn { + /omit-if-no-ref/ + gpio_fsxn_pins: gpio-fsxn-pins { + rockchip,pins = + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23.dts new file mode 100644 index 000000000000..f68caf003024 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23.dts @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-vehicle-evb-v21.dtsi" +#include "rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi" +#include "rk3588-vehicle-evb-maxim-max96712-dphy3-isx021.dtsi" +#include "rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi" +#include "rk3588-vehicle-serdes-mfd-display-maxim.dtsi" +#include "rk3588-vehicle-evb-v23-audio.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 VEHICLE EVB V23 Board"; + compatible = "rockchip,rk3588-vehicle-evb-v23", "rockchip,rk3588"; + + vcc5v0_buck: vcc5v0-buck { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_buck"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_buck_en>; + startup-delay-us = <2500>; + off-on-delay-us = <1500>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; +#if 0 + vcc4v0_sys_mode: vcc4v0-sys-mode { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_sys_mode"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + vin-supply = <&vcc12v_dcin>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc4v0_sys_mode_en>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <4000000>; + }; + }; +#endif + lcd1_vcc12v_buck: lcd1_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd1_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd2_vcc12v_buck: lcd2_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd2_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd3_vcc12v_buck: lcd3_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd3_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd4_vcc12v_buck: lcd4_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd4_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd5_vcc12v_buck: lcd5_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd5_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd6_vcc12v_buck: lcd6_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd6_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + dcphy0_vcc12v_buck: dcphy0_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "dcphy0_vcc12v_buck"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + dcphy1_vcc12v_buck: dcphy1_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "dcphy1_vcc12v_buck"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + dphy0_vcc12v_buck: dphy0_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "dphy0_vcc12v_buck"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 8 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + dphy3_vcc12v_buck: dphy3_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "dphy3_vcc12v_buck"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + vcc5v0_host_usb20: vcc5v0-host-usb20 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg_usb20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + //enable-active-high; + gpio = <&nca9539_gpio 10 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_host_usb30: vcc5v0-host-usb30 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host_usb30"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&nca9539_gpio 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc5v0_usb>; + }; + + adsp_vcc12v_buck: adsp_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "adsp_vcc12v_buck"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 12 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + minipcie_power_buck: minipcie_power-buck { + compatible = "regulator-fixed"; + regulator-name = "minipcie_power_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&nca9539_gpio 13 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_buck>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vehicle_dummy: vehicle_dummy { + status = "okay"; + compatible = "rockchip,vehicle-dummy-gpio"; + reverse-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + park-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_pcie_wifi: vcc3v3-pcie-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_wifi"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart7m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart7_gpios>; + BT,reset_gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &phydisb>; + tx_delay = <0x20>; + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + rgmii_vddio = "1v8"; + }; +}; + +&hym8563 { + status = "disabled"; +}; + +&max96712_dphy3_vcc1v2 { + vin-supply = <&vcc5v0_buck>; +}; + +&max96712_dphy3_pwdn_regulator { + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; +}; + +&max96712_dphy3_poc_regulator { + vin-supply = <&dphy3_vcc12v_buck>; + gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; +}; + +&max96712_dphy3 { + lock-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&max96756_dphy0_vcc1v2 { + vin-supply = <&vcc5v0_buck>; +}; + +&avdd1v8_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&i2c2 { + himax@45 { + himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + }; + + himax_split@46 { + himax,irq-gpio = <&gpio3 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +/*dsi0*/ +&i2c2_max96789 { + route-enable; +}; + +&i2c2_max96752 { + use-reg-check-work; + vpower-supply = <&lcd1_vcc12v_buck>; +}; + +&i2c2_max96752_split { + use-reg-check-work; + vpower-supply = <&lcd2_vcc12v_buck>; +}; + +/*dp0*/ +&i2c4 { + himax@45 { + himax,irq-gpio = <&gpio3 RK_PD5 IRQ_TYPE_EDGE_FALLING>; + }; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&s35390a_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c4_max96745 { + //use-delay-work; +}; + +&i2c4_max96752 { + use-reg-check-work; + vpower-supply = <&lcd5_vcc12v_buck>; + + himax@45 { + himax,irq-gpio = <&gpio3 RK_PD5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +/*edp0*/ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + + ilitek@41 { + interrupt-parent = <&gpio1>; + interrupts = ; + }; +}; + +&i2c5_max96745 { + //use-delay-work; +}; + +&i2c5_max96752 { + use-reg-check-work; + vpower-supply = <&lcd3_vcc12v_buck>; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m1_xfer>; +}; + +&i2c7 { + status = "disabled"; +}; + +&pinctrl { + pinctrl-names = "init"; + pinctrl-0 = <&max96712_dphy3_pwdn + &max96712_dphy3_errb + &max96712_dphy3_lock>; + + + gmac0 { + phydisb: phydisb { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + max96712-dphy3 { + max96712_dphy3_pwdn: max96712-dphy3-pwdn { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dphy3_errb: max96712-dphy3-errb { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dphy3_lock: max96712-dphy3-lock { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; + + s35390a { + s35390a_int: s35390a-int { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + //dsi0-i2c2 + touch_gpio_dsi0: touch-gpio-dsi0 { + rockchip,pins = + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //RST->V22 INT + }; + //dsi1-i2c6 + touch_gpio_dsi1: touch-gpio-dsi1 { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //INT + }; + //dp0-i2c4 + touch_gpio_dp0: touch-gpio-dp0 { + rockchip,pins = + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + //edp0-i2c5 + touch_gpio_edp0: touch-gpio-edp0 { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; //INT + }; + }; + + vcc5v0-buck { + vcc5v0_buck_en: vcc5v0-buck-en { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +#if 0 + vcc4v0-mode { + vcc4v0_sys_mode_en: vcc4v0-sys-mode-en { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +#endif + wireless-bluetooth { + uart7_gpios: uart7-gpios { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; +}; + +&spi4 { + status = "disabled"; +}; + +&u2phy0_otg { + //phy-supply = <&vcc5v0_host_usb20>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host_usb30>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_usb30>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host_usb30>; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vdd_1v8_pll_s0 { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; +}; + +&vcc5v0_host { + status = "disabled"; +}; + +&uart9 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim.dtsi index 65b9a77135e3..ac45170d9573 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim.dtsi @@ -1,118 +1,299 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * */ -#include - / { - aliases { - pinctrl0 = &pinctrl; + dsi2lvds_backlight1: dsi2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; }; - backlight { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - i2c2_max96755f_backlight: backlight@0 { - compatible = "pwm-backlight"; - reg = <0>; - pwms = <&pwm0 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c4_max96745_backlight: backlight@1 { - compatible = "pwm-backlight"; - reg = <1>; - pwms = <&pwm10 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c5_max96745_backlight: backlight@2 { - compatible = "pwm-backlight"; - reg = <2>; - pwms = <&pwm7 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c6_max96755f_backlight: backlight@3 { - compatible = "pwm-backlight"; - reg = <3>; - pwms = <&pwm13 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c7_max96745_backlight: backlight@4 { - compatible = "pwm-backlight"; - reg = <4>; - pwms = <&pwm11 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c8_max96745_backlight: backlight@5 { - compatible = "pwm-backlight"; - reg = <5>; - pwms = <&pwm14 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; + dp2lvds_backlight0: dp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; }; + + dp2lvds_backlight1: dp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight0: edp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight1: edp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + +&backlight { + pwms = <&pwm0 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl0_enable_pin>; + //enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi2lvds_backlight1 { + pwms = <&pwm2 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl1_enable_pin>; + //enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; }; &dp0 { //rockchip,split-mode; force-hpd; status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp0_out_i2c4_max96745: endpoint { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c4_max96745_from_dp0>; + }; + }; + }; }; &dp0_in_vp0 { status = "okay"; }; -&dp0_out { - link-frequencies = /bits/ 64 <2700000000>; - remote-endpoint = <&i2c4_max96745_in>; +&dp0_in_vp1 { + status = "disabled"; }; -&usbdp_phy0 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&route_dp0 { - connect = <&vp0_out_dp0>; - status = "okay"; +&dp0_in_vp2 { + status = "disabled"; }; &dp1 { force-hpd; status = "disabled"; +#if 0 + ports { + port@1 { + reg = <1>; + + dp1_out_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_from_dp1>; + }; + }; + }; +#endif }; -&dp1_out { - link-frequencies = /bits/ 64 <2700000000>; - remote-endpoint = <&i2c8_max96745_in>; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <0 1 2 3>; +&dp1_in_vp0 { status = "okay"; }; -&usbdp_phy1_dp { +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dp2lvds_backlight0 { + pwms = <&pwm10 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl2_enable_pin>; + //enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; status = "okay"; }; +&dp2lvds_backlight1 { + pwms = <&pwm1 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl3_enable_pin>; + //enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ &dsi0 { status = "okay"; @@ -123,28 +304,27 @@ port@1 { reg = <1>; - dsi0_out: endpoint { - remote-endpoint = <&i2c2_max96755f_in>; + dsi0_out_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_from_dsi0>; }; }; }; }; -&mipi_dcphy0 { - status = "okay"; -}; - &dsi0_in_vp2 { status = "okay"; }; -&route_dsi0 { - connect = <&vp2_out_dsi0>; +&dsi0_in_vp3 { status = "disabled"; }; +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ &dsi1 { - status = "disabled"; + status = "okay"; ports { #address-cells = <1>; @@ -153,48 +333,47 @@ port@1 { reg = <1>; - dsi1_out: endpoint { - remote-endpoint = <&i2c6_max96755f_in>; + dsi1_out_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_from_dsi1>; }; }; }; }; -&mipi_dcphy1 { - status = "okay"; +&dsi1_in_vp2 { + status = "disabled"; }; &dsi1_in_vp3 { status = "okay"; }; -&route_dsi1 { - connect = <&vp3_out_dsi1>; - status = "disabled"; -}; - &edp0 { //rockchip,split-mode; force-hpd; status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_i2c5_max96745: endpoint { + remote-endpoint = <&i2c5_max96745_from_edp0>; + }; + }; + }; }; -&edp0_out { - link-frequencies = /bits/ 64 <2700000000>; - remote-endpoint = <&i2c5_max96745_in>; -}; - -&hdptxphy0 { - status = "okay"; +&edp0_in_vp0 { + status = "disabled"; }; &edp0_in_vp1 { status = "okay"; }; -&route_edp0 { - connect = <&vp1_out_edp0>; - status = "okay"; +&edp0_in_vp2 { + status = "disabled"; }; &edp1 { @@ -202,12 +381,31 @@ status = "disabled"; }; -&edp1_out { - link-frequencies = /bits/ 64 <2700000000>; - remote-endpoint = <&i2c7_max96745_in>; +&edp1_in_vp0 { + status = "disabled"; }; -&hdptxphy1 { +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&edp2lvds_backlight0 { + pwms = <&pwm7 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl4_enable_pin>; + //enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp2lvds_backlight1 { + pwms = <&pwm11 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl5_enable_pin>; + //enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -219,6 +417,14 @@ status = "disabled"; }; +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + &hdptxphy_hdmi0 { status = "disabled"; }; @@ -228,207 +434,497 @@ }; &i2c2 { + status = "okay"; + pinctrl-names = "default"; pinctrl-0 = <&i2c2m4_xfer>; clock-frequency = <400000>; - status = "okay"; - max96755@40 { - compatible = "maxim,max96755"; - reg = <0x40>; + i2c2_max96789: i2c2-max96789@42 { + compatible = "maxim,max96789"; + reg = <0x42>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_serdes_pins>; - lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; + lock-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; sel-mipi; + id-serdes-bridge-split = <0x01>; status = "okay"; serdes-init-sequence = [ - 0001 0008 - 0002 0053 - 0003 0040 - 0010 0031 - 0013 00ca - 0010 0000 - 02be 001c - 02bf 0040 - 02c0 0020 - 0311 0057 - 0331 0033 - 0332 004e - 03a4 0000 - 0385 0000 - 0386 0000 - 0387 0000 - 005b 0012 + //Independent 11_07_17-56 Using MAX96789/91/F (GMSL-1/2) + //Disable Video pipe + 0002 0003 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 008a + //Address Value of I2C SRC_B + 0044 008c + //Address Value of I2C DST_B + 0045 008c + //Set Stream for DSI Port A && assign pipeX 0053 0010 + //Set Stream for DSI Port B && assign pipeY + 0057 0021 + //Clock Select, X for portA, Y/Z for PortB + 0308 0076 + //Start DSI Port + 0311 0061 + //Set Port A Lane Mapping + 0332 004E + //Set Port B Lane Mapping + 0333 00E4 + //Set GMSL type + 0004 00F2 + //Number of Lanes + 0331 0033 + //Set phy_config + 0330 0006 + //Set soft_dtx_en + 031C 0098 + //Set soft_dtx + 0321 0024 + //Set soft_dty_en + 031D 0098 + //Set soft_dty_ + 0322 0024 + //Init Default + 0326 00E4 + //HSYNC_WIDTH_L HSYNC=32 + 0385 0020 + //VSYNC_WIDTH_L VSYNC=2 + 0386 0002 + //HSYNC_WIDTH_H/VSYNC_WIDTH_H + 0387 0000 + //VFP_L VFP=200 + 03A5 00C8 + //VBP_H + 03A7 0000 + //VFP_H/VBP_L VBP=8 + 03A6 0008 + //VRES_L VRES=0X02D0=720 + 03A8 00D0 + //VRES_H + 03A9 0002 + //HFP_L HFP=56 + 03AA 0038 + //HBP_H + 03AC 0003 + //HFP_H/HBP_L(4bit) HBP=56 + 03AB 0008 + //HRES_L HRES=0X0780=1920 + 03AD 0080 + //HRES_H + 03AE 0007 + //Disable FIFO/DESKEW_EN + 03A4 00C0 + //HSYNC_WIDTH_L HSYNC=40 + 0395 0028 + //VSYNC_WIDTH_L VSYNC=20 + 0396 0014 + //HSYNC_WIDTH_H/VSYNC_WIDTH_H + 0397 0000 + //VFP_L VFP=15 + 03B1 000F + //VBP_H + 03B3 0000 + //VFP_H/VBP_L VBP=10 + 03B2 000A + //VRES_L VRES=0X0438=1080 + 03B4 0038 + //VRES_H + 03B5 0004 + //HFP_L HFP=140 + 03B6 008C + //HBP_H + 03B8 0006 + //HFP_H/HBP_L HBP=100 + 03B7 0004 + //HRES_L HRES=0X0780=1920 + 03B9 0080 + //HRES_H + 03BA 0007 + //Disable FIFO/DESKEW_EN + 03B0 00C0 + //Turn on video pipe + 0002 0033 + //Enable splitter mode reset one shot + 0010 0023 + ffff f000 //0xf000 ms delay ]; - i2c2_max96755f_pinctrl: i2c2-max96755f-pinctrl { - compatible = "maxim,max96755-pinctrl"; + i2c2_max96789_pinctrl: i2c2-max96789-pinctrl { + compatible = "maxim,max96789-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_max96789_pinctrl_pins>; + pinctrl-1 = <&i2c2_max96789_pinctrl_pins>; status = "okay"; - - i2c2_max96755f_pinctrl_hog: hog { + i2c2_max96789_pinctrl_pins: pinctrl-pins { i2c { - groups = "MAX96755_I2C"; - function = "MAX96755_I2C"; + groups = "MAX96789_I2C"; + function = "MAX96789_I2C"; + }; + lcd-bl-pwm { + pins = "MAX96789_MFP7"; + function = "SER_TXID4_TO_DES"; + }; + tp-int { + pins = "MAX96789_MFP8"; + function = "DES_RXID8_TO_SER"; + }; + lcd-bl-pwm-split { + pins = "MAX96789_MFP16"; + function = "SER_TXID4_TO_DES"; + }; + tp-int-split { + pins = "MAX96789_MFP14"; + function = "DES_RXID14_TO_SER"; }; }; - i2c2_max96755f_panel_pins: panel-pins { - bl-pwm { - pins = "MAX96755_MFP0"; - function = "DES_GPIO0_OUTPUT"; - }; - }; - - i2c2_max96755f_gpio: i2c2-max96755f-gpio { - compatible = "maxim,max96755-gpio"; + i2c2_max96789_gpio: i2c2-max96789-gpio { + compatible = "maxim,max96789-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&i2c2_max96755f_pinctrl 0 160 24>; + gpio-ranges = <&i2c2_max96789_pinctrl 0 160 20>; }; }; - i2c2_max96755f_bridge: i2c2-max96755f-bridge { - compatible = "maxim,max96755-bridge"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_max96755f_pinctrl_hog>; + i2c2_max96789_bridge: i2c2-max96789-bridge { + compatible = "maxim,max96789-bridge"; status = "okay"; - }; - ports { + ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; - - i2c2_max96755f_in: endpoint { - remote-endpoint = <&dsi0_out>; + i2c2_max96789_from_dsi0: endpoint { + remote-endpoint = <&dsi0_out_i2c2_max96789>; }; }; port@1 { reg = <1>; - - i2c2_max96755f_out: endpoint { - remote-endpoint = <&i2c2_max96755f_panel_in>; + i2c2_max96789_out_i2c2_max96752: endpoint { + remote-endpoint = <&i2c2_max96752_from_i2c2_max96789>; }; }; }; + }; + + i2c2_max96789_bridge_split: i2c2-max96789-bridge-split { + compatible = "maxim,max96789-bridge-split"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96789_from_dsi1: endpoint { + remote-endpoint = <&dsi1_out_i2c2_max96789>; + }; + }; + + port@1 { + reg = <1>; + i2c2_max96789_out_i2c2_max96752_split: endpoint { + remote-endpoint = <&i2c2_max96752_split_from_i2c2_max96789>; + }; + }; + }; + }; }; - - max96772@48 { - compatible = "maxim,max96772"; - reg = <0x48>; - #address-cells = <1>; - #size-cells = <0>; + i2c2_max96752: i2c2-max96752@4a { + compatible = "maxim,max96752"; + reg = <0x4a>; + //reg-hw = <0x4a>; + id-serdes-panel-split = <0x01>; + link = <0x01>; status = "okay"; serdes-init-sequence = [ - 0001 0002 - 0010 0011 + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0031 + 007b 0031 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 0090 + 0050 0000 - 07f0 0001 - e791 0000 - e793 0000 - e794 0000 - e795 000a - e796 007a - e797 0000 - e798 003c - e799 0000 - e79a 003c - e79b 0000 - e79c 00a0 - e79d 0005 - e79e 0054 - e79f 0001 - e7a0 0002 - e7a1 0000 - e7a2 0014 - e7a3 0000 - e7a4 00fc - e7a5 000e - e7a6 0055 - e7a7 0055 - e7a8 0000 - e7a9 0080 - e7aa 0040 - e7ab 0000 - e7ac 0003 - e7ad 0000 - e7b0 0000 - e7b1 0000 - e7b2 0050 - e7b3 0000 - e7b4 0000 - e7b5 0040 - e7b6 006c - e7b7 0020 - e7b8 0007 - e7b9 0000 - e7ba 0001 - e7bb 0000 - e7bc 0000 - e7bd 0000 - e7be 0052 - e7bf 0000 + 01ce 004e + 01ea 0005 ]; - i2c2_max96772_pinctrl: i2c2-max96772-pinctrl { - compatible = "maxim,max96772-pinctrl"; + i2c2_max96752_pinctrl: i2c2-max96752-pinctrl { + compatible = "maxim,max96752-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c2_max96752_panel_pins>; + pinctrl-1 = <&i2c2_max96752_panel_pins>; + pinctrl-2 = <&i2c2_max96752_panel_sleep_pins>; status = "okay"; - i2c2_max96772_gpio: i2c2-max96772-gpio { - compatible = "maxim,max96772-gpio"; + i2c2_max96752_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + lcd-bias-en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd-vdd-en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID8_TO_SER"; + }; + 40ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_40MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + }; + + i2c2_max96752_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c2_max96752_gpio: i2c2-max96752-gpio { + compatible = "maxim,max96752-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&i2c2_max96772_pinctrl 0 185 24>; + gpio-ranges = <&i2c2_max96752_pinctrl 0 180 15>; }; }; - i2c2_max96772_panel: i2c2-max96772-panel { - compatible = "maxim,max96772-panel"; - backlight = <&i2c2_max96755f_backlight>; + i2c2_max96752_panel: i2c2-max96752-panel { + compatible = "maxim,max96752-panel"; + status = "okay"; + + backlight = <&backlight>; + panel-size= <346 194>; panel-timing { - clock-frequency = <180000000>; - hactive = <2560>; - vactive = <1440>; - hfront-porch = <122>; - hsync-len = <60>; - hback-porch = <60>; - vfront-porch = <340>; + clock-frequency = <115000000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; vsync-len = <2>; - vback-porch = <20>; + vback-porch = <8>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; - port { - i2c2_max96755f_panel_in: endpoint { - remote-endpoint = <&i2c2_max96755f_out>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96752_from_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_out_i2c2_max96752>; + }; + }; + }; + }; + }; + + i2c2_max96752_split: i2c2-max96752-split@4b { + compatible = "maxim,max96752"; + reg = <0x4b>; + reg-hw = <0x4a>; + id-serdes-panel-split = <0x01>; + link = <0x02>; + status = "okay"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0032 + 007b 0032 + 007d 0038 + + //Address Value of I2C SRC_A + 0042 008c + //Address Value of I2C DST_A + 0043 0090 + //0140 0020 + 0050 0001 + 01ce 004e + 01ea 0005 + ]; + + i2c2_max96752_split_pinctrl: i2c2-max96752-split-pinctrl { + compatible = "maxim,max96752-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c2_max96752_split_panel_pins>; + pinctrl-1 = <&i2c2_max96752_split_panel_pins>; + pinctrl-2 = <&i2c2_max96752_split_panel_sleep_pins>; + status = "okay"; + + i2c2_max96752_split_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + lcd-bias-en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd-vdd-en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID14_TO_SER"; + }; + 40ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_40MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; }; }; + i2c2_max96752_split_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c2_max96752_split_gpio: i2c2-max96752-split-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_max96752_split_pinctrl 0 200 15>; + }; }; + i2c2_max96752_split_panel: i2c2-max96752-split-panel { + compatible = "maxim,max96752-panel-split"; + status = "okay"; + + backlight = <&dsi2lvds_backlight1>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <115000000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96752_split_from_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_out_i2c2_max96752_split>; + }; + }; + }; + }; }; - ts@30 { - compatible = "gac,gac_ts"; - reg = <0x30>; - gac,max_x = <2560>; - gac,max_y = <1440>; + himax@45 { + compatible = "himax,hxcommon"; + reg = <0x45>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi0>; + pinctrl-1 = <&touch_gpio_dsi0>; + himax,location = "himax-touch-dsi0"; + himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c2_max96752_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; + + himax_split@46 { + compatible = "himax,hxcommon"; + reg = <0x46>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi1>; //hw change + pinctrl-1 = <&touch_gpio_dsi1>; + himax,location = "himax-touch-dsi1"; + himax,irq-gpio = <&gpio3 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c2_max96752_split_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; }; }; @@ -437,122 +933,488 @@ clock-frequency = <400000>; status = "okay"; - max96745@42 { + i2c4_max96745: i2c4-max96745@42 { compatible = "maxim,max96745"; reg = <0x42>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_serdes_pins>; + lock-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; + id-serdes-bridge-split = <0x02>; + status = "okay"; serdes-init-sequence = [ - 0070 0016 - 0005 00c0 - 0107 0042 - 0027 0022 - 0026 0022 - 002a 0007 - 641a 00f0 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 008a + //Address Value of I2C SRC_B + 0044 008c + //Address Value of I2C DST_B + 0045 008c + //Set TX_STR_SEL_X to 0 + 00A3 0000 + //Set TX_STR_SEL_Y to 1 + 00A7 0001 + //Set TX_STR_SEL_Z to 2 + 00AB 0002 + //Set TX_STR_SEL_U to 3 + 00AF 0003 + + //INFOFR TX_SRC_ID0:1:2 + 00C2 0001 + //CC TX_SRC_ID0:1:2 + 00D2 0002 + //IIC X TX_SRC_ID0:1:2 + 00EA 0001 + //IIC Y TX_SRC_ID0:1:2 + 00F2 0002 + + 00B2 0003 + 00BA 0003 + 00CA 0003 + 00C2 0003 + 00D2 0003 + 00DA 0003 + 00E2 0003 + 00EA 0003 + 00F2 0003 + //Set X_VID_LINK_SEL to 0 + 0100 0061 + //Set Y_VID_LINK_SEL to 1 + 0110 0063 + //Set Z_VID_LINK_SEL to 0 + 0120 0061 + //Set U_VID_LINK_SEL to 1 + 0130 0063 + //ASYM_WR_B_MUX_Y of SER will be written 1 + 05CE 003F + //ASYM_WAIT_LINE_FOR_READ_X of SER will be written 1 + 04D1 00F8 + //ASYM_WAIT_LINE_FOR_READ_Y of SER will be written 1 + 05D1 00F8 + //ASYM_VID_EN_W_VS_X of SER will be written 1 + 04CF 00BF + //ASYM_VID_EN_W_VS_Y of SER will be written 1 + 05CF 00BF + //ASYM_FR2FR_CTRL_EN_X of SER will be written 1 + 04D1 00FC + //ASYM_FR2FR_CTRL_EN_Y of SER will be written 1 + 05D1 00FC + //ALT_VTG_EN_X + 04CE 002F + //AUTO_VTG_CFG_X + 04CE 000F + //ALT_VTG_EN_Y + 05CE 0027 + //AUTO_VTG_CFG_Y + 05CE 0007 + //X_M_l + 04C0 0020 + //X_M_m + 04C1 004A + //X_M_h + 04C2 001D + //X_N_l + 04C3 00C8 + //X_N_m + 04C4 0008 + //X_N_h + 04C5 0007 + //X_X_OFFSET_l + 04C6 0000 + //X_X_OFFSET_h + 04C7 0000 + //X_X_MAX_l + 04C8 0080 + //X_X_MAX_h + 04C9 0007 + //X_Y_MAX_l + 04CA 00D0 + //X_Y_MAX_h + 04CB 0002 + //Y_M + 05C0 0020 + //Y_M_h + 05C1 004A + //Y_M_h + 05C2 001D + //Y_N_l + 05C3 00C8 + //Y_N_m + 05C4 0008 + //Y_N_h + 05C5 0007 + //Y_X_OFFSET_l + 05C6 0080 + //Y_X_OFFSET_h + 05C7 0007 + //Y_X_MAX_l + 05C8 0000 + //Y_X_MAX_h + 05C9 000F + //Y_Y_MAX_l + 05CA 00D0 + //Y_Y_MAX_h + 05CB 0002 + //X_LUT_TEMPLATE_SEL + 04CD 0014 + //X_vs_dly_l + 04D8 0080 + //X_vs_dly_m + 04D9 00F9 + //X_vs_dly_h + 04DA 001C + //X_vs_high_l + 04DB 0080 + //X_vs_high_m + 04DC 0040 + //X_vs_high_h + 04DD 0000 + //X_vs_low_l + 04DE 0020 + //X_vs_low_m + 04DF 0010 + //X_vs_low_h + 04E0 0000 + //X_hs_dly_l + 04E1 0000 + //X_hs_dly_m + 04E2 0000 + //X_hs_dly_h + 04E3 0000 + //X_hs_high_l + 04E4 0038 + //X_hs_high_h + 04E5 0000 + //X_hs_low_l + 04E6 00D8 + //X_hs_low_h + 04E7 0007 + //X_hs_cnt_l + 04E8 00A2 + //X_hs_cnt_h + 04E9 0003 + //X_hs_llow_l + 04EA 0000 + //X_hs_llow_m + 04EB 0000 + //X_hs_llow_h + 04EC 0000 + //X_de_dly_l + 04ED 0058 + //X_de_dly_m + 04EE 0000 + //X_de_dly_h + 04EF 0000 + //X_de_high_l + 04F0 0080 + //X_de_high_h + 04F1 0007 + //X_de_low_l + 04F2 0090 + //X_de_low_h + 04F3 0000 + //X_de_cnt_l + 04F4 00D0 + //X_de_cnt_h + 04F5 0002 + //X_de_llow_l + 04F6 00C8 + //X_de_llow_m + 04F7 009C + //X_de_llow_h + 04F8 0006 + //Y_vs_dly_l + 05D8 0080 + //Y_vs_dly_m + 05D9 00F9 + //Y_vs_dly_h + 05DA 001C + //Y_vs_high_l + 05DB 0080 + //Y_vs_high_m + 05DC 0040 + //Y_vs_high_h + 05DD 0000 + //Y_vs_low_l + 05DE 0020 + //Y_vs_low_m + 05DF 0010 + //Y_vs_low_h + 05E0 0000 + //Y_hs_dly_l + 05E1 0000 + //Y_hs_dly_m + 05E2 0000 + //Y_hs_dly_h + 05E3 0000 + //Y_hs_high_l + 05E4 0038 + //Y_hs_high_h + 05E5 0000 + //Y_hs_low_l + 05E6 00D8 + //Y_hs_low_h + 05E7 0007 + //Y_hs_cnt_l + 05E8 00A2 + //Y_hs_cnt_h + 05E9 0003 + //Y_hs_llow_l + 05EA 0000 + //Y_hs_llow_m + 05EB 0000 + //Y_hs_llow_h + 05EC 0000 + //Y_de_dly_l + 05ED 0058 + //Y_de_dly_m + 05EE 0000 + //Y_de_dly_h + 05EF 0000 + //Y_de_high_l + 05F0 0080 + //Y_de_high_h + 05F1 0007 + //Y_de_low_l + 05F2 0090 + //Y_de_low_h + 05F3 0000 + //Y_de_cnt_l + 05F4 00D0 + //Y_de_cnt_h + 05F5 0002 + //Y_de_llow_l + 05F6 00C8 + //Y_de_llow_m + 05F7 009C + //Y_de_llow_h + 05F8 0006 + //Y_LUT_TEMPLATE_SEL + 05CD 0014 + //Turn off video + 6420 0010 + //Disable MST mode + 7019 0000 + //7019 0001 //Set MST_FUNCTION_ENABLE to 1 + //7904 0001 // Set MST_PAYLOAD_ID_0 to 01 + //7908 0002 // Set MST_PAYLOAD_ID_1 to 01 + //Disable MST_VS0_DTG_ENABLE + 7A14 0000 + //Disable LINK_ENABLE + 7000 0000 + //Reset DPRX core (VIDEO_INPUT_RESET) + 7054 0001 + ffff f000 //delay 0xf000 us + //Set MAX_LINK_RATE to 2.7Gb/s + 7074 000A + //Set MAX_LINK_COUNT to 4 + 7070 0004 + //Set ASYM_CTRL_PROP_GAIN to 000A + 04D0 000A + 05D0 000A + //Set AEQ time to 16ms + 6064 0000 + 6065 0000 + 6164 0000 + 6165 0000 + 6264 0000 + 6265 0000 + 6364 0000 + 6365 0000 + //Enable LINK_ENABLE + 7000 0001 + //delay 1000 + //Disable MSA reset + 7A18 0005 + //Adjust VS0_DMA_HSYNC + 7A28 00FF + 7A2A 00FF + //Adjust VS0_DMA_VSYNC + 7A24 00FF + 7A27 000F + //Enable MST_VS0_DTG_ENABLE + 7A14 0001 + //set EDP Video Control + 6421 0001 + //Turn on video + 6420 0013 + //delay 100 + //Turn off video + 6420 0010 + //delay 100 + //Turn on video + 6420 0013 + 6421 0003 ]; i2c4_max96745_pinctrl: i2c4-max96745-pinctrl { compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_max96745_pinctrl_pins>; status = "okay"; + i2c4_max96745_pinctrl_pins: pinctrl-pins { + i2c { + groups = "MAX96745_I2C"; + function = "MAX96745_I2C"; + }; + lcd-bl-pwm { + pins = "MAX96745_MFP0"; + function = "SER_TXID0_TO_DES_LINKA"; + }; + tp-int { + pins = "MAX96745_MFP1"; + function = "DES_RXID1_TO_SER_LINKA"; + }; + }; + i2c4_max96745_gpio: i2c4-max96745-gpio { compatible = "maxim,max96745-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&i2c4_max96745_pinctrl 0 210 25>; + gpio-ranges = <&i2c4_max96745_pinctrl 0 220 25>; }; }; i2c4_max96745_bridge: i2c4-max96745-bridge { compatible = "maxim,max96745-bridge"; - lock-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; status = "okay"; }; ports { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; - - i2c4_max96745_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c4_max96745_out: endpoint { - remote-endpoint = <&i2c4_max96745_panel_in>; - }; + port@0 { + reg = <0>; + i2c4_max96745_from_dp0: endpoint { + remote-endpoint = <&dp0_out_i2c4_max96745>; }; }; - + port@1 { + reg = <1>; + i2c4_max96745_out_i2c4_max96752: endpoint { + remote-endpoint = <&i2c4_max96752_from_i2c4_max96745>; + }; + }; + }; }; - - max96752@48 { + i2c4_max96752: i2c4-max96752@4a { compatible = "maxim,max96752"; - reg = <0x48>; + reg = <0x4a>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; + id-serdes-panel-split = <0x02>; + link = <0x01>; + status = "okay"; serdes-init-sequence = [ - 0001 0002 + /*max96752 dual oLDI output*/ 0002 0043 - 0140 0020 - 01ce 005e - 0200 0084 - 020e 0040 - 020c 0084 - 0207 00a1 - 0206 0083 - 0215 0090 - 0227 0090 - 020f 0090 - 0221 0090 - 0212 0090 - 0209 0090 + 0073 0031 + 007b 0031 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 0090 + + 0050 0000 + 01ce 004e + 01ea 0005 ]; i2c4_max96752_pinctrl: i2c4-max96752-pinctrl { compatible = "maxim,max96752-pinctrl"; status = "okay"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c4_max96752_panel_pins>; + pinctrl-1 = <&i2c4_max96752_panel_pins>; + pinctrl-2 = <&i2c4_max96752_panel_sleep_pins>; + + i2c4_max96752_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID1_TO_SER"; + }; + 40ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_40MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + lcd_bias_en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd_vdd_en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + }; + + i2c4_max96752_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + i2c4_max96752_gpio: i2c4-max96752-gpio { compatible = "maxim,max96752-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&i2c4_max96752_pinctrl 0 236 25>; + gpio-ranges = <&i2c4_max96752_pinctrl 0 250 15>; }; }; i2c4_max96752_panel: i2c4-max96752-panel { compatible = "maxim,max96752-panel"; - reg = <0x48>; - backlight = <&i2c4_max96745_backlight>; + status = "okay"; + + backlight = <&dp2lvds_backlight0>; + panel-size= <346 194>; panel-timing { - clock-frequency = <148500000>; + clock-frequency = <115000000>; hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; vsync-len = <2>; vback-porch = <8>; hsync-active = <0>; @@ -562,57 +1424,369 @@ }; port { - i2c4_max96745_panel_in: endpoint { - remote-endpoint = <&i2c4_max96745_out>; + i2c4_max96752_from_i2c4_max96745: endpoint { + remote-endpoint = <&i2c4_max96745_out_i2c4_max96752>; }; }; }; }; + + himax@45 { + compatible = "himax,hxcommon"; + reg = <0x45>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dp0>; + pinctrl-1 = <&touch_gpio_dp0>; + himax,location = "himax-touch-dp0"; + himax,irq-gpio = <&gpio3 RK_PD5 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c4_max96752_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; }; &i2c5 { clock-frequency = <400000>; status = "okay"; - max96745@42 { + i2c5_max96745: i2c5-max96745@42 { compatible = "maxim,max96745"; reg = <0x42>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_serdes_pins>; - lock-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; + id-serdes-bridge-split = <0x02>; status = "okay"; serdes-init-sequence = [ - 0070 0016 - 0005 00c0 - 0107 0042 - 0027 0022 - 0026 0022 - 002a 0007 - 641a 00f0 - ]; + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 008a + //Address Value of I2C SRC_B + 0044 008c + //Address Value of I2C DST_B + 0045 008c + //Set TX_STR_SEL_X to 0 + 00A3 0000 + //Set TX_STR_SEL_Y to 1 + 00A7 0001 + //Set TX_STR_SEL_Z to 2 + 00AB 0002 + //Set TX_STR_SEL_U to 3 + 00AF 0003 + //INFOFR TX_SRC_ID0:1:2 + 00C2 0001 + //CC TX_SRC_ID0:1:2 + 00D2 0002 + //IIC X TX_SRC_ID0:1:2 + 00EA 0001 + //IIC Y TX_SRC_ID0:1:2 + 00F2 0002 + + 00B2 0003 + 00BA 0003 + 00CA 0003 + 00C2 0003 + 00D2 0003 + 00DA 0003 + 00E2 0003 + 00EA 0003 + 00F2 0003 + //Set X_VID_LINK_SEL to 0 + 0100 0061 + //Set Y_VID_LINK_SEL to 1 + 0110 0063 + //Set Z_VID_LINK_SEL to 0 + 0120 0061 + //Set U_VID_LINK_SEL to 1 + 0130 0063 + //ASYM_WR_B_MUX_Y + 05CE 0037 + //ASYM_WAIT_LINE_FOR_READ_X + 04D1 00F8 + //ASYM_WAIT_LINE_FOR_READ_Y + 05D1 00F8 + //ASYM_VID_EN_W_VS_X + 04CF 00BF + //ASYM_VID_EN_W_VS_Y + 05CF 00BF + //ASYM_FR2FR_CTRL_EN_X + 04D1 00FC + //ASYM_FR2FR_CTRL_EN_Y + 05D1 00FC + //ALT_VTG_EN_X + 04CE 002F + //AUTO_VTG_CFG_X + 04CE 000F + //ALT_VTG_EN_Y + 05CE 0027 + //AUTO_VTG_CFG_Y + 05CE 0007 + //X_M_l + 04C0 00F8 + //X_M_m + 04C1 00C3 + //X_M_h + 04C2 0025 + //X_N_l + 04C3 00C8 + //X_N_m + 04C4 0008 + //X_N_h + 04C5 0007 + //X_X_OFFSET_l + 04C6 0000 + //X_X_OFFSET_h + 04C7 0000 + //X_X_MAX_l + 04C8 0080 + //X_X_MAX_h + 04C9 0007 + //X_Y_MAX_l + 04CA 0038 + //X_Y_MAX_h + 04CB 0004 + //Y_M + 05C0 00F8 + //Y_M_h + 05C1 00C3 + //Y_M_h + 05C2 0025 + //Y_N_l + 05C3 00C8 + //Y_N_m + 05C4 0008 + //Y_N_h + 05C5 0007 + //Y_X_OFFSET_l + 05C6 0080 + //Y_X_OFFSET_h + 05C7 0007 + //Y_X_MAX_l + 05C8 0000 + //Y_X_MAX_h + 05C9 000F + //Y_Y_MAX_l + 05CA 0038 + //Y_Y_MAX_h + 05CB 0004 + //X_vs_dly_l + 04D8 0028 + //X_vs_dly_m + 04D9 00C2 + //X_vs_dly_h + 04DA 0024 + //X_vs_high_l + 04DB 00E0 + //X_vs_high_m + 04DC 00AB + //X_vs_high_h + 04DD 0000 + //X_vs_low_l + 04DE 00F0 + //X_vs_low_m + 04DF 0055 + //X_vs_low_h + 04E0 0000 + //X_hs_dly_l + 04E1 0000 + //X_hs_dly_m + 04E2 0000 + //X_hs_dly_h + 04E3 0000 + //X_hs_high_l + 04E4 0028 + //X_hs_high_h + 04E5 0000 + //X_hs_low_l + 04E6 0070 + //X_hs_low_h + 04E7 0008 + //X_hs_cnt_l + 04E8 0065 + //X_hs_cnt_h + 04E9 0004 + //X_hs_llow_l + 04EA 0000 + //X_hs_llow_m + 04EB 0000 + //X_hs_llow_h + 04EC 0000 + //X_de_dly_l + 04ED 008C + //X_de_dly_m + 04EE 0000 + //X_de_dly_h + 04EF 0000 + //X_de_high_l + 04F0 0080 + //X_de_high_h + 04F1 0007 + //X_de_low_l + 04F2 0018 + //X_de_low_h + 04F3 0001 + //X_de_cnt_l + 04F4 0038 + //X_de_cnt_h + 04F5 0004 + //X_de_llow_l + 04F6 002C + //X_de_llow_m + 04F7 0082 + //X_de_llow_h + 04F8 0001 + + //Y_vs_dly_l + 05D8 0028 + //Y_vs_dly_m + 05D9 00C2 + //Y_vs_dly_h + 05DA 0024 + //Y_vs_high_l + 05DB 00E0 + //Y_vs_high_m + 05DC 00AB + //Y_vs_high_h + 05DD 0000 + //Y_vs_low_l + 05DE 00F0 + //Y_vs_low_m + 05DF 0055 + //Y_vs_low_h + 05E0 0000 + //Y_hs_dly_l + 05E1 0000 + //Y_hs_dly_m + 05E2 0000 + //Y_hs_dly_h + 05E3 0000 + //Y_hs_high_l + 05E4 0028 + //Y_hs_high_h + 05E5 0000 + //Y_hs_low_l + 05E6 0070 + //Y_hs_low_h + 05E7 0008 + //Y_hs_cnt_l + 05E8 0065 + //Y_hs_cnt_h + 05E9 0004 + //Y_hs_llow_l + 05EA 0000 + //Y_hs_llow_m + 05EB 0000 + //Y_hs_llow_h + 05EC 0000 + //Y_de_dly_l + 05ED 008C + //Y_de_dly_m + 05EE 0000 + //Y_de_dly_h + 05EF 0000 + //Y_de_high_l + 05F0 0080 + //Y_de_high_h + 05F1 0007 + //Y_de_low_l + 05F2 0018 + //Y_de_low_h + 05F3 0001 + //Y_de_cnt_l + 05F4 0038 + //Y_de_cnt_h + 05F5 0004 + //Y_de_llow_l + 05F6 002C + //Y_de_llow_m + 05F7 0082 + //Y_de_llow_h + 05F8 0001 + //X_LUT_TEMPLATE_SEL + 04CD 0014 + //Y_LUT_TEMPLATE_SEL + 05CD 0014 + //Turn off video + 6420 0010 + //Disable MST mode + 7019 0000 + //7019 0001 //Set MST_FUNCTION_ENABLE to 1 + //7904 0001 // Set MST_PAYLOAD_ID_0 to 01 + //7908 0002 // Set MST_PAYLOAD_ID_1 to 01 + //Disable MST_VS0_DTG_ENABLE + 7A14 0000 + //Disable LINK_ENABLE + 7000 0000 + //Reset DPRX core (VIDEO_INPUT_RESET) + 7054 0001 + ffff f000 //delay 0xf000 us + //Set MAX_LINK_RATE to 2.7Gb/s + 7074 000A + //Set MAX_LINK_COUNT to 4 + 7070 0004 + //Set ASYM_CTRL_PROP_GAIN to 000A + 04D0 000A + 05D0 000A + //Set AEQ time to 16ms + 6064 0000 + 6065 0000 + 6164 0000 + 6165 0000 + 6264 0000 + 6265 0000 + 6364 0000 + 6365 0000 + //Enable LINK_ENABLE + 7000 0001 + //delay 1000 + //Disable MSA reset + 7A18 0005 + //Adjust VS0_DMA_HSYNC + 7A28 00FF + 7A2A 00FF + //Adjust VS0_DMA_VSYNC + 7A24 00FF + 7A27 000F + //Enable MST_VS0_DTG_ENABLE + 7A14 0001 + //set EDP Video Control + 6421 0001 + //Turn on video + 6420 0013 + //delay 100 + //Turn off video + 6420 0010 + //delay 100 + //Turn on video + 6420 0013 + 6421 0003 + ]; i2c5_max96745_pinctrl: i2c5-max96745-pinctrl { compatible = "maxim,max96745-pinctrl"; pinctrl-names = "default"; - pinctrl-0 = <&i2c5_max96745_pinctrl_hog>, <&i2c5_max96745_panel_pins>; + pinctrl-0 = <&i2c5_max96745_pinctrl_pins>; status = "okay"; - i2c5_max96745_pinctrl_hog: hog { + i2c5_max96745_pinctrl_pins: pinctrl-pins { i2c { groups = "MAX96745_I2C"; function = "MAX96745_I2C"; }; - }; - - i2c5_max96745_panel_pins: panel-pins { - bl-pwm { + lcd-bl-pwm { pins = "MAX96745_MFP0"; - function = "DES_GPIO0_OUTPUT_A"; + function = "SER_TXID4_TO_DES_LINKA"; + }; + tp-int { + pins = "MAX96745_MFP1"; + function = "DES_RXID1_TO_SER_LINKA"; }; }; @@ -622,7 +1796,7 @@ gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&i2c5_max96745_pinctrl 0 262 25>; + gpio-ranges = <&i2c5_max96745_pinctrl 0 280 25>; }; }; @@ -632,84 +1806,138 @@ }; ports { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; + port@0 { + reg = <0>; - i2c5_max96745_in: endpoint { - remote-endpoint = <&edp0_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c5_max96745_out: endpoint { - remote-endpoint = <&i2c5_max96745_panel_in>; - }; + i2c5_max96745_from_edp0: endpoint { + remote-endpoint = <&edp0_out_i2c5_max96745>; }; }; + port@1 { + reg = <1>; + + i2c5_max96745_out_i2c5_max96752: endpoint { + remote-endpoint = <&i2c5_max96752_from_i2c5_max96745>; + }; + }; + }; }; - - max96752@48 { + i2c5_max96752: i2c5-max96752@4a { compatible = "maxim,max96752"; - reg = <0x48>; + reg = <0x4a>; #address-cells = <1>; #size-cells = <0>; + id-serdes-panel-split = <0x02>; + link = <0x01>; status = "okay"; serdes-init-sequence = [ - 0001 0002 + /*max96752 dual oLDI output*/ 0002 0043 - 0140 0020 - 01ce 005e - 0200 0084 - 020e 0040 - 020c 0084 - 0207 00a1 - 0206 0083 - 0215 0090 - 0227 0090 - 020f 0090 - 0221 0090 - 0212 0090 - 0209 0090 + 0073 0031 + 007b 0031 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 0090 + + 0050 0000 + 01ce 004e + 01ea 0005 ]; i2c5_max96752_pinctrl: i2c5-max96752-pinctrl { compatible = "maxim,max96752-pinctrl"; status = "okay"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c5_max96752_panel_pins>; + pinctrl-1 = <&i2c5_max96752_panel_pins>; + pinctrl-2 = <&i2c5_max96752_panel_sleep_pins>; + + i2c5_max96752_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID1_TO_SER"; + }; + 40ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_40MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + lcd_bias_en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd_vdd_en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + }; + + i2c5_max96752_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + i2c5_max96752_gpio: i2c5-max96752-gpio { compatible = "maxim,max96752-gpio"; status = "okay"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&i2c5_max96752_pinctrl 0 288 25>; + gpio-ranges = <&i2c5_max96752_pinctrl 0 305 15>; }; }; i2c5_max96752_panel: i2c5-max96752-panel { compatible = "maxim,max96752-panel"; - reg = <0x48>; - backlight = <&i2c5_max96745_backlight>; + status = "okay"; + + backlight = <&edp2lvds_backlight0>; panel-size= <346 194>; panel-timing { clock-frequency = <148500000>; hactive = <1920>; vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; @@ -717,376 +1945,184 @@ }; port { - i2c5_max96745_panel_in: endpoint { - remote-endpoint = <&i2c5_max96745_out>; + i2c5_max96752_from_i2c5_max96745: endpoint { + remote-endpoint = <&i2c5_max96745_out_i2c5_max96752>; }; }; - }; }; + + ilitek@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio_edp0>; + //reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; + ilitek,name = "ilitek_i2c"; + status = "okay"; + }; }; -&i2c6 { - pinctrl-0 = <&i2c6m3_xfer>; - clock-frequency = <400000>; +&mipi_dcphy0 { status = "okay"; - - max96755f@40 { - compatible = "maxim,max96755f"; - reg = <0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - - pinctrl { - compatible = "maxim,max96755f-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_max96755f_pinctrl_hog>; - - i2c6_max96755f_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - - i2c6_max96755f_panel_pins: panel-pins { - bl-pwm { - pins = "MFP18"; - function = "GPIO_TX_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96755f-bridge"; - lock-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c6_max96755f_in: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c6_max96755f_out: endpoint { - remote-endpoint = <&i2c6_max96755f_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c6_max96755f_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_max96755f_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c6_max96755f_panel_in: endpoint { - remote-endpoint = <&i2c6_max96755f_out>; - }; - }; - }; - }; - }; }; -&i2c7 { - pinctrl-0 = <&i2c7m3_xfer>; - clock-frequency = <400000>; - status = "disabled"; - - max96745@42 { - compatible = "maxim,max96745"; - reg = <0x42>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - - pinctrl { - compatible = "maxim,max96745-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_max96745_pinctrl_hog>; - - i2c7_max96745_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - i2c7_max96745_panel_pins: panel-pins { - bl-pwm { - pins = "MFP0"; - function = "GPIO_TX_A_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96745-bridge"; - lock-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c7_max96745_in: endpoint { - remote-endpoint = <&edp1_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c7_max96745_out: endpoint { - remote-endpoint = <&i2c7_max96745_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c7_max96745_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_max96745_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c7_max96745_panel_in: endpoint { - remote-endpoint = <&i2c7_max96745_out>; - }; - }; - }; - }; - }; -}; - -&i2c8 { - pinctrl-0 = <&i2c8m2_xfer>; - clock-frequency = <400000>; - status = "disabled"; - - max96745@42 { - compatible = "maxim,max96745"; - reg = <0x42>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - - pinctrl { - compatible = "maxim,max96745-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_max96745_pinctrl_hog>; - - i2c8_max96745_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - i2c8_max96745_panel_pins: panel-pins { - bl-pwm { - pins = "MFP0"; - function = "GPIO_TX_A_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96745-bridge"; - lock-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c8_max96745_in: endpoint { - remote-endpoint = <&dp1_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c8_max96745_out: endpoint { - remote-endpoint = <&i2c8_max96745_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c8_max96745_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_max96745_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c8_max96745_panel_in: endpoint { - remote-endpoint = <&i2c8_max96745_out>; - }; - }; - }; - }; - }; +&mipi_dcphy1 { + status = "okay"; }; &pinctrl { serdes { + /*dsi0*/ i2c2_serdes_pins: i2c2-serdes-pins { rockchip,pins = - <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ }; - + /*dp0*/ i2c4_serdes_pins: i2c4-serdes-pins { rockchip,pins = - <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ }; - + /*edp0*/ i2c5_serdes_pins: i2c5-serdes-pins { rockchip,pins = - <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ }; - + /*dsi1*/ i2c6_serdes_pins: i2c6-serdes-pins { rockchip,pins = - <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ }; - + /*edp1*/ i2c7_serdes_pins: i2c7-serdes-pins { rockchip,pins = - <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ }; - + /*dp1*/ i2c8_serdes_pins: i2c8-serdes-pins { rockchip,pins = - <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ }; }; }; +/* dsi0->serdes->lvds_panel */ &pwm0 { - pinctrl-0 = <&pwm0m2_pins>; status = "okay"; + pinctrl-0 = <&pwm0m2_pins>; }; +/* dp0->serdes->lvds_panel */ &pwm10 { pinctrl-0 = <&pwm10m2_pins>; status = "okay"; }; +/* edp1->serdes->lvds_panel */ &pwm11 { pinctrl-0 = <&pwm11m3_pins>; status = "okay"; }; +/* edp0->serdes->lvds_panel */ &pwm7 { pinctrl-0 = <&pwm7m0_pins>; status = "okay"; }; -&pwm13 { - pinctrl-0 = <&pwm13m1_pins>; +/* dsi1->serdes->lvds_panel */ +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2m1_pins>; //v23 hw change to PWM2_M1(GPIO3_B1) +}; + +/* dp1->serdes->lvds_panel */ +&pwm1 { + pinctrl-0 = <&pwm1m2_pins>; status = "okay"; }; -&pwm14 { - pinctrl-0 = <&pwm14m0_pins>; +&route_dp0 { + status = "disabled"; + connect = <&vp0_out_dp0>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dp1 { + status = "disabled"; + connect = <&vp0_out_dp1>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dsi0 { + status = "disabled"; + connect = <&vp2_out_dsi0>; + logo,uboot = "logo1.bmp"; + logo,kernel = "logo1.bmp"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; + logo,uboot = "logo2.bmp"; + logo,kernel = "logo2.bmp"; +}; + +&route_edp0 { + status = "disabled"; + connect = <&vp1_out_edp0>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&route_edp1 { + status = "disabled"; + connect = <&vp1_out_edp1>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; status = "okay"; }; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru PLL_V0PLL>; + assigned-clock-rates = <1150000000>; +}; +//dp +&vp0 { + assigned-clocks = <&cru DCLK_VOP0_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; +//edp +&vp1 { + assigned-clocks = <&cru DCLK_VOP1_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; +//dsi0 +&vp2 { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; +//dsi1 +&vp3 { + assigned-clocks = <&cru DCLK_VOP3>; + assigned-clock-parents = <&cru PLL_V0PLL>; +};