From 06ba74ca82321fd0f60ff7903f5ec920d98c0d4e Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Thu, 26 Mar 2020 12:52:23 +0800
Subject: [PATCH] ARM: dts: rockchip: rv1126: Add opp table for npu

Change-Id: I9683969e613c9ae60454c57118c11063c7e255c9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 arch/arm/boot/dts/rv1126.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
index 1ad4c1681c11..e5bce5326abe 100644
--- a/arch/arm/boot/dts/rv1126.dtsi
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -1580,11 +1580,25 @@
 		clock-names = "aclk_npu", "hclk_npu", "pclk_pdnpu", "sclk_npu";
 		assigned-clocks = <&cru CLK_CORE_NPU>;
 		assigned-clock-rates = <400000000>;
+		operating-points-v2 = <&npu_opp_table>;
 		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 		power-domains = <&power RV1126_PD_NPU>;
 		status = "disabled";
 	};
 
+	npu_opp_table: npu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <800000 800000 1000000>;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <800000 800000 1000000>;
+		};
+	};
+
 	usbdrd: usb0 {
 		compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3";
 		#address-cells = <1>;