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SDMMC: open the 8bit bus width and IDMA

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This commit is contained in:
xbw
2014-03-21 01:17:21 +08:00
parent 9cf11a6375
commit 06c5156923
3 changed files with 7 additions and 7 deletions
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2
arch/arm/configs/rockchip_defconfig
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@@ -453,6 +453,8 @@ CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_IDMAC=y
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y

2
drivers/mmc/host/dw_mmc-rockchip.c
View File

@@ -160,7 +160,7 @@ static int dw_mci_rockchip_parse_dt(struct dw_mci *host)
/* Common capabilities of RK32XX SoC */
static unsigned long rockchip_dwmmc_caps[4] = {
/*MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | //Temporarily comment out!!!!!!, deleted by xbw, at 2014-03-12*/
MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23|MMC_CAP_UHS_SDR12|MMC_CAP_UHS_SDR25|MMC_CAP_UHS_SDR50,
MMC_CAP_8_BIT_DATA|MMC_CAP_4_BIT_DATA|MMC_CAP_CMD23|MMC_CAP_UHS_SDR12|MMC_CAP_UHS_SDR25|MMC_CAP_UHS_SDR50|MMC_CAP_UHS_SDR104|MMC_CAP_ERASE,
MMC_CAP_CMD23,
MMC_CAP_CMD23,
MMC_CAP_CMD23,

10
drivers/mmc/host/rk_sdmmc.c
View File

@@ -420,8 +420,8 @@ static void dw_mci_idmac_complete_dma(struct dw_mci *host)
struct mmc_data *data = host->data;
dev_vdbg(host->dev, "DMA complete\n");
MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \
host->cmd->opcode,host->cmd->arg,data->blocks,data->blksz,mmc_hostname(host->mmc));
// MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \
// host->mrq->cmd->opcode,host->mrq->cmd->arg,data->blocks,data->blksz,mmc_hostname(host->mmc));
host->dma_ops->cleanup(host);
@@ -1014,12 +1014,10 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
switch (ios->bus_width) {
case MMC_BUS_WIDTH_4:
slot->ctype = SDMMC_CTYPE_4BIT;
break;
slot->ctype = SDMMC_CTYPE_4BIT;
break;
case MMC_BUS_WIDTH_8:
slot->ctype = SDMMC_CTYPE_8BIT;
break;
slot->ctype = SDMMC_CTYPE_8BIT;
break;
default:
/* set default 1 bit mode */