From e0d85e33a3506c2c0db7256736a52528c31b60e9 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Mon, 16 Oct 2023 16:52:13 +0800 Subject: [PATCH 1/2] phy: rockchip: csi2-dphy: Support config MIPI CLK mode Change-Id: Iefaf07543ce78295a031b0c2a18bb3017dee02ac Signed-off-by: Zefa Chen Signed-off-by: Cody Xie --- .../phy/rockchip/phy-rockchip-csi2-dphy-hw.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c index e0a9fd65c16b..7f7617754125 100644 --- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c +++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c @@ -54,6 +54,7 @@ #define CSI2_DPHY_DUAL_CAL_EN (0x80) #define CSI2_DPHY_CLK_INV (0X84) +#define CSI2_DPHY_CLK_CONTINUE_MODE (0x128) #define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160) #define CSI2_DPHY_CLK_CALIB_EN (0x168) #define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0) @@ -64,6 +65,7 @@ #define CSI2_DPHY_LANE2_CALIB_EN (0x2e8) #define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360) #define CSI2_DPHY_LANE3_CALIB_EN (0x368) +#define CSI2_DPHY_CLK1_CONTINUE_MODE (0x3a8) #define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0) #define CSI2_DPHY_CLK1_CALIB_EN (0x3e8) @@ -213,6 +215,8 @@ enum csi2dphy_reg_id { CSI2PHY_PATH1_MODEL, CSI2PHY_PATH1_LVDS_MODEL, CSI2PHY_CLK_INV, + CSI2PHY_CLK_CONTINUE_MODE, + CSI2PHY_CLK1_CONTINUE_MODE, }; #define HIWORD_UPDATE(val, mask, shift) \ @@ -397,6 +401,8 @@ static const struct csi2dphy_reg rk3588_csi2dphy_regs[] = { [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE), [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN), [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN), + [CSI2PHY_CLK_CONTINUE_MODE] = CSI2PHY_REG(CSI2_DPHY_CLK_CONTINUE_MODE), + [CSI2PHY_CLK1_CONTINUE_MODE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CONTINUE_MODE), }; static const struct grf_reg rv1106_grf_dphy_regs[] = { @@ -709,19 +715,30 @@ static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy, val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) | (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); + if (sensor->mbus.flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) + write_csi2_dphy_reg(hw, CSI2PHY_CLK_CONTINUE_MODE, 0x30); } else { if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT))) val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT); - if (dphy->phy_index % 3 == DPHY1) + if (dphy->phy_index % 3 == DPHY1) { val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT); + if (sensor->mbus.flags & + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) + write_csi2_dphy_reg( + hw, CSI2PHY_CLK_CONTINUE_MODE, 0x30); + } if (dphy->phy_index % 3 == DPHY2) { val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT); if (hw->drv_data->chip_id >= CHIP_ID_RK3588) write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6)); + if (sensor->mbus.flags & + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) + write_csi2_dphy_reg( + hw, CSI2PHY_CLK1_CONTINUE_MODE, 0x30); } } val |= pre_val; From 5351f974aa891699f77abcce6270e5751d76455f Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 11 Oct 2023 16:17:41 +0800 Subject: [PATCH 2/2] PCI: rockchip: dw: Add dbi_base2 for both RC and EP mode In order to use dw_pcie_writel_dbi2() and standard macro to disable unused BARs. Signed-off-by: Shawn Lin Change-Id: Ibe26abfb319f3f75899dd2f8c4f7b0a9a733bfa7 --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 67b11fbf9e18..b8d86b5f3039 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -1111,8 +1111,8 @@ static int rk_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); /* Disable BAR0 BAR1 */ - dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_0 * 4, 0); - dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_1 * 4, 0); + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0); + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0); ret = rk_pcie_establish_link(pci); @@ -1185,7 +1185,6 @@ static int rk_pcie_add_ep(struct rk_pcie *rk_pcie) return ret; } - rk_pcie->pci->dbi_base2 = rk_pcie->pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET; rk_pcie->pci->atu_base = rk_pcie->pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; rk_pcie->pci->iatu_unroll_enabled = rk_pcie_iatu_unroll_enabled(rk_pcie->pci); @@ -1245,6 +1244,7 @@ static int rk_pcie_resource_get(struct platform_device *pdev, return PTR_ERR(rk_pcie->dbi_base); rk_pcie->pci->dbi_base = rk_pcie->dbi_base; + rk_pcie->pci->dbi_base2 = rk_pcie->pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET; apb_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-apb");