From 08aea10ffdd07ca3395d71f41a10857c00a55094 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Fri, 3 Aug 2018 17:25:06 +0800 Subject: [PATCH] phy/rockchip: typec: PLL1 settings improvements When I tested DP function on excavator, I found that commit 1bf7191033de ("BACKPORT: FROMLIST: phy: rockchip-typec: support variable phy config value"), which change pll settings, but it does not work as expected on excavator board. With this patch series, DP works well on excavator and roc. Change-Id: I48fe0c51e322369d1aff352f4ebaf1096f264834 Signed-off-by: Wyon Bi --- drivers/phy/rockchip/phy-rockchip-typec.c | 42 +++++++++++------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 82085f2266eb..36f2aa52a324 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -367,7 +367,7 @@ struct phy_reg { u32 addr; }; -struct phy_reg usb3_pll_cfg[] = { +static const struct phy_reg usb3_pll_cfg[] = { { 0xf0, CMN_PLL0_VCOCAL_INIT }, { 0x18, CMN_PLL0_VCOCAL_ITER }, { 0xd0, CMN_PLL0_INTDIV }, @@ -384,15 +384,15 @@ struct phy_reg usb3_pll_cfg[] = { { 0x8, CMN_DIAG_PLL0_LF_PROG }, }; -struct phy_reg dp_pll_rbr_cfg[] = { +static const struct phy_reg dp_pll_rbr_cfg[] = { { 0xf0, CMN_PLL1_VCOCAL_INIT }, { 0x18, CMN_PLL1_VCOCAL_ITER }, { 0x30b9, CMN_PLL1_VCOCAL_START }, - { 0x87, CMN_PLL1_INTDIV }, - { 0, CMN_PLL1_FRACDIV }, - { 0x22, CMN_PLL1_HIGH_THR }, - { 0x8000, CMN_PLL1_SS_CTRL1 }, - { 0, CMN_PLL1_SS_CTRL2 }, + { 0x0086, CMN_PLL1_INTDIV }, + { 0xf915, CMN_PLL1_FRACDIV }, + { 0x0022, CMN_PLL1_HIGH_THR }, + { 0x0140, CMN_PLL1_SS_CTRL1 }, + { 0x7f03, CMN_PLL1_SS_CTRL2 }, { 0x20, CMN_PLL1_DSM_DIAG }, { 0, CMN_PLLSM1_USER_DEF_CTRL }, { 0, CMN_DIAG_PLL1_OVRD }, @@ -406,15 +406,15 @@ struct phy_reg dp_pll_rbr_cfg[] = { { 0x1, CMN_DIAG_PLL1_INCLK_CTRL }, }; -struct phy_reg dp_pll_hbr_cfg[] = { +static const struct phy_reg dp_pll_hbr_cfg[] = { { 0xf0, CMN_PLL1_VCOCAL_INIT }, { 0x18, CMN_PLL1_VCOCAL_ITER }, { 0x30b4, CMN_PLL1_VCOCAL_START }, - { 0xe1, CMN_PLL1_INTDIV }, - { 0, CMN_PLL1_FRACDIV }, - { 0x5, CMN_PLL1_HIGH_THR }, - { 0x8000, CMN_PLL1_SS_CTRL1 }, - { 0, CMN_PLL1_SS_CTRL2 }, + { 0x00e0, CMN_PLL1_INTDIV }, + { 0xf479, CMN_PLL1_FRACDIV }, + { 0x0038, CMN_PLL1_HIGH_THR }, + { 0x0204, CMN_PLL1_SS_CTRL1 }, + { 0x7f03, CMN_PLL1_SS_CTRL2 }, { 0x20, CMN_PLL1_DSM_DIAG }, { 0x1000, CMN_PLLSM1_USER_DEF_CTRL }, { 0, CMN_DIAG_PLL1_OVRD }, @@ -428,15 +428,15 @@ struct phy_reg dp_pll_hbr_cfg[] = { { 0x1, CMN_DIAG_PLL1_INCLK_CTRL }, }; -struct phy_reg dp_pll_hbr2_cfg[] = { +static const struct phy_reg dp_pll_hbr2_cfg[] = { { 0xf0, CMN_PLL1_VCOCAL_INIT }, { 0x18, CMN_PLL1_VCOCAL_ITER }, { 0x30b4, CMN_PLL1_VCOCAL_START }, - { 0xe1, CMN_PLL1_INTDIV }, - { 0, CMN_PLL1_FRACDIV }, - { 0x5, CMN_PLL1_HIGH_THR }, - { 0x8000, CMN_PLL1_SS_CTRL1 }, - { 0, CMN_PLL1_SS_CTRL2 }, + { 0x00e0, CMN_PLL1_INTDIV }, + { 0xf479, CMN_PLL1_FRACDIV }, + { 0x0038, CMN_PLL1_HIGH_THR }, + { 0x0204, CMN_PLL1_SS_CTRL1 }, + { 0x7f03, CMN_PLL1_SS_CTRL2 }, { 0x20, CMN_PLL1_DSM_DIAG }, { 0x1000, CMN_PLLSM1_USER_DEF_CTRL }, { 0, CMN_DIAG_PLL1_OVRD }, @@ -505,7 +505,7 @@ static void tcphy_cfg_usb3_pll(struct rockchip_typec_phy *tcphy) static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy, int link_rate) { - struct phy_reg *phy_cfg; + const struct phy_reg *phy_cfg; u32 clk_ctrl; u32 i, cfg_size, hsclk_sel; @@ -595,7 +595,7 @@ static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, int link_rate, val = val & 0x8fff; switch (link_rate) { case 540000: - val |= (4 << 12); + val |= (5 << 12); break; case 162000: case 270000: