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drm/rockchip: vop: add support for rk3506

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Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I7a22f0cc3a3830d23d009213048c44db57854250
This commit is contained in:
Damon Ding
2023-05-05 17:04:03 +08:00
committed by Tao Huang
parent 3e6bcbb063
commit 08fbbdb571
2 changed files with 134 additions and 0 deletions
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132
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -1991,6 +1991,134 @@ static const struct vop_data rv1106_vop = {
.win_size = ARRAY_SIZE(rv1106_vop_win_data), .win_size = ARRAY_SIZE(rv1106_vop_win_data),
}; };
static const struct vop_ctrl rk3506_ctrl_data = {
.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
.axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
.axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
.yuv_clip = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 4),
.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
.bt1120_uv_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 5),
.bt656_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 6),
.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
.mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
.mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
.mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
.bt1120_yc_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 30),
.bt1120_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 31),
.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
.dsp_interlace_pol = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 1),
.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
.dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
.dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
.dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
.dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
.mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
0xffffffff, 0),
};
static const struct vop_win_phy rk3506_lit_win1_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
.enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0),
.csc_mode = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 2),
.format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4),
.interlace_read = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 8),
.rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12),
.channel = VOP_REG(RK3366_LIT_WIN1_CTRL1, 0xf, 8),
.yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0),
.yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0),
.dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
.dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0),
.color_key = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0xffffff, 0),
.color_key_en = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0x1, 24),
.alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
.alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
.alpha_pre_mul = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 2),
.global_alpha_val = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0xff, 4),
};
static const struct vop_win_data rk3506_vop_win_data[] = {
{ .phy = NULL },
{ .base = 0x00, .phy = &rk3506_lit_win1_data,
.type = DRM_PLANE_TYPE_PRIMARY },
};
static const struct vop_grf_ctrl rk3506_grf_ctrl = {
.grf_dclk_inv = VOP_REG(RK3506_GRF_SOC_CON2, 0x1, 0),
};
static const struct vop_data rk3506_vop = {
.soc_id = 0x3506,
.vop_id = 0,
.version = VOP_VERSION(2, 0xc),
.max_input = {1280, 1280},
.max_output = {1280, 1280},
.ctrl = &rk3506_ctrl_data,
.intr = &rk3366_lit_intr,
.grf = &rk3506_grf_ctrl,
.win = rk3506_vop_win_data,
.win_size = ARRAY_SIZE(rk3506_vop_win_data),
};
static const struct vop_ctrl rk3576_lit_ctrl_data = { static const struct vop_ctrl rk3576_lit_ctrl_data = {
.cfg_done = VOP_REG(EBC_CONFIG_DONE, 0x1, 0), .cfg_done = VOP_REG(EBC_CONFIG_DONE, 0x1, 0),
@@ -2178,6 +2306,10 @@ static const struct of_device_id vop_driver_dt_match[] = {
{ .compatible = "rockchip,rk3328-vop", { .compatible = "rockchip,rk3328-vop",
.data = &rk3328_vop }, .data = &rk3328_vop },
#endif #endif
#if IS_ENABLED(CONFIG_CPU_RK3506)
{ .compatible = "rockchip,rk3506-vop",
.data = &rk3506_vop },
#endif
#if IS_ENABLED(CONFIG_CPU_RK3576) #if IS_ENABLED(CONFIG_CPU_RK3576)
{ .compatible = "rockchip,rk3576-vop-lit", { .compatible = "rockchip,rk3576-vop-lit",
.data = &rk3576_vop_lit }, .data = &rk3576_vop_lit },

2
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1039,6 +1039,8 @@
#define RV1126_GRF_IOFUNC_CON3 0x1026c #define RV1126_GRF_IOFUNC_CON3 0x1026c
#define RK3506_GRF_SOC_CON2 0x0008
#define RK3562_GRF_IOC_VO_IO_CON 0x10500 #define RK3562_GRF_IOC_VO_IO_CON 0x10500
/* rk3568 vop registers definition */ /* rk3568 vop registers definition */