From 099bdfba32ff58bba5143218ef94de5ab187ef1d Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Wed, 23 Mar 2022 16:09:18 +0800 Subject: [PATCH] drm/bridge: analogix_dp: Add source capacity limits in .mode_vaild Signed-off-by: Wyon Bi Change-Id: I2a60ee26534ebda02dabe3c22453ad70b0aebdc3 --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 483efe75dfbb..fae4f9ec05a1 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1635,15 +1635,21 @@ analogix_dp_bridge_mode_valid(struct drm_bridge *bridge, { struct analogix_dp_device *dp = bridge->driver_private; struct drm_display_mode m; + u32 max_link_rate, max_lane_count; drm_mode_copy(&m, mode); if (dp->plat_data->split_mode) dp->plat_data->convert_to_origin_mode(&m); + max_link_rate = min_t(u32, dp->video_info.max_link_rate, + dp->link_train.link_rate); + max_lane_count = min_t(u32, dp->video_info.max_lane_count, + dp->link_train.lane_count); + if (!analogix_dp_bandwidth_ok(dp, &m, - drm_dp_bw_code_to_link_rate(dp->link_train.link_rate), - dp->link_train.lane_count)) + drm_dp_bw_code_to_link_rate(max_link_rate), + max_lane_count)) return MODE_BAD; return MODE_OK;