From 09d4b9bcaafc0fb9fbf9dee27ee613bb40630d09 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Fri, 11 Oct 2019 14:56:46 +0800 Subject: [PATCH] clk: rockchip: rk618: fix compile error Change-Id: I1a185202a062eac73ca5f387487ab3e34dafe664 Signed-off-by: Wyon Bi --- drivers/clk/rockchip/Makefile | 2 ++ drivers/clk/rockchip/rk618/clk-regmap-divider.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 7dc2c435a878..af5c0002ce3e 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -26,3 +26,5 @@ obj-$(CONFIG_CPU_RK3308) += clk-rk3308.o obj-$(CONFIG_CPU_RK3328) += clk-rk3328.o obj-$(CONFIG_CPU_RK3368) += clk-rk3368.o obj-$(CONFIG_CPU_RK3399) += clk-rk3399.o + +obj-$(CONFIG_MFD_RK618) += rk618/ diff --git a/drivers/clk/rockchip/rk618/clk-regmap-divider.c b/drivers/clk/rockchip/rk618/clk-regmap-divider.c index ae38f6b1108f..44d77e19aa47 100644 --- a/drivers/clk/rockchip/rk618/clk-regmap-divider.c +++ b/drivers/clk/rockchip/rk618/clk-regmap-divider.c @@ -34,7 +34,7 @@ clk_regmap_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) div &= div_mask(divider->width); return divider_recalc_rate(hw, parent_rate, div, NULL, - CLK_DIVIDER_ROUND_CLOSEST); + CLK_DIVIDER_ROUND_CLOSEST, divider->width); } static long