From 09f5dd48228d68b2edf6663184985643578e5685 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 18 Nov 2020 09:10:10 +0800 Subject: [PATCH] drm/rockchip: dsi: make timing and lane rate more accurate use actual pixel or dot clock in the hardware to calc the timings and lane rate if dclk can not be applied accurately. Change-Id: I6c0bcaca35cb945a58cc50005b23c6c772c9a082 Signed-off-by: Guochun Huang --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index b246e6016c83..13766910779a 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -981,7 +981,7 @@ static void dw_mipi_dsi_set_vid_mode(struct dw_mipi_dsi *dsi) { struct drm_display_mode *mode = &dsi->mode; unsigned int lanebyteclk = (dsi->lane_mbps * USEC_PER_MSEC) >> 3; - unsigned int dpipclk = mode->clock; + unsigned int dpipclk = mode->crtc_clock; u32 hline, hsa, hbp, hline_time, hsa_time, hbp_time; u32 vactive, vsa, vfp, vbp; u32 val; @@ -1118,7 +1118,7 @@ static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi) bpp = 24; lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes; - tmp = (u64)mode->clock * 1000 * bpp; + tmp = (u64)mode->crtc_clock * 1000 * bpp; do_div(tmp, lanes); /* take 1 / 0.9, since mbps must big than bandwidth of RGB */