diff --git a/drivers/amlogic/media/enhancement/amvecm/amcm.c b/drivers/amlogic/media/enhancement/amvecm/amcm.c index 4b0967e82b8e..9bdaff84aa9f 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amcm.c +++ b/drivers/amlogic/media/enhancement/amvecm/amcm.c @@ -148,6 +148,15 @@ void am_set_regmap(struct am_regs_s *p) __func__, p->am_reg[i].addr); break; } + + if (!cm_en) { + if (p->am_reg[i].addr == 0x208) + p->am_reg[i].val = + p->am_reg[i].val & 0xfffffffd; + pr_amcm_dbg("[amcm]:%s REG_TYPE_INDEX_VPPCHROMA addr:0x%x", + __func__, p->am_reg[i].addr); + } + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr); if (p->am_reg[i].mask == 0xffffffff) @@ -221,6 +230,7 @@ void am_set_regmap(struct am_regs_s *p) break; } } + return; } void amcm_disable(void) @@ -363,6 +373,7 @@ void cm_latch_process(void) } else if ((cm_en == 0) && (cm_level_last != 0xff)) { cm_level_last = 0xff; amcm_disable();/* CM manage disable */ + pr_amcm_dbg("\n[amcm..] set cm disable!!!\n"); } } diff --git a/drivers/amlogic/media/enhancement/amvecm/amcsc.c b/drivers/amlogic/media/enhancement/amvecm/amcsc.c index 996e9c7efef0..e4931a20506b 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amcsc.c +++ b/drivers/amlogic/media/enhancement/amvecm/amcsc.c @@ -65,6 +65,8 @@ struct hdr_osd_reg_s hdr_osd_reg = { 0x08000000, /* VIU_OSD1_EOTF_COEF11_12 0x1ad7 */ 0x00000000, /* VIU_OSD1_EOTF_COEF20_21 0x1ad8 */ 0x08000001, /* VIU_OSD1_EOTF_COEF22_RS 0x1ad9 */ + 0x0, /* VIU_OSD1_EOTF_3X3_OFST_0 0x1aa0 */ + 0x0, /* VIU_OSD1_EOTF_3X3_OFST_1 0x1aa1 */ 0x01c00000, /* VIU_OSD1_OETF_CTL 0x1adc */ { /* eotf table */ @@ -127,13 +129,21 @@ static struct vframe_s *dbg_vf; static struct master_display_info_s dbg_hdr_send; static struct hdr_info receiver_hdr_info; -static bool debug_csc; -module_param(debug_csc, bool, 0664); +static uint debug_csc; +module_param(debug_csc, uint, 0664); MODULE_PARM_DESC(debug_csc, "\n debug_csc\n"); -static bool skip_csc_en; -module_param(skip_csc_en, bool, 0664); -MODULE_PARM_DESC(skip_csc_en, "\n skip_csc_en\n"); +static bool print_lut_mtx; +module_param(print_lut_mtx, bool, 0664); +MODULE_PARM_DESC(print_lut_mtx, "\n print_lut_mtx\n"); + +/* bit 0: enable csc */ +/* bit 1: enable osd csc */ +/* bit 2: enable video csc */ +/* bit 4: csc delay one frame */ +static uint csc_en = 0x7; +module_param(csc_en, uint, 0664); +MODULE_PARM_DESC(csc_en, "\n csc_en\n"); /* white balance adjust */ static bool cur_eye_protect_mode; @@ -159,6 +169,10 @@ static uint cur_csc_type = 0xffff; module_param(cur_csc_type, uint, 0444); MODULE_PARM_DESC(cur_csc_type, "\n current color space convert type\n"); +static uint hdmi_csc_type = 0xffff; +module_param(hdmi_csc_type, uint, 0444); +MODULE_PARM_DESC(hdmi_csc_type, "\n current color space convert type\n"); + static uint hdr_mode = 2; /* 0: hdr->hdr, 1:hdr->sdr, 2:auto */ module_param(hdr_mode, uint, 0664); MODULE_PARM_DESC(hdr_mode, "\n set hdr_mode\n"); @@ -168,7 +182,7 @@ static uint cur_hdr_process_mode = 2; /* 0: hdr->hdr, 1:hdr->sdr */ module_param(hdr_process_mode, uint, 0444); MODULE_PARM_DESC(hdr_process_mode, "\n current hdr_process_mode\n"); -unsigned int sdr_mode; /* 0: sdr->sdr, 1:sdr->hdr, 2:auto */ +uint sdr_mode; /* 0: sdr->sdr, 1:sdr->hdr, 2:auto */ static uint sdr_process_mode = 2; /* 0: sdr->sdr, 1:sdr->hdr */ static uint cur_sdr_process_mode = 2; /* 0: sdr->sdr, 1:sdr->hdr */ static int sdr_saturation_offset = 20; /* 0: sdr->sdr, 1:sdr->hdr */ @@ -200,6 +214,10 @@ module_param(hdr_flag, uint, 0664); MODULE_PARM_DESC(hdr_flag, "\n set hdr_flag\n"); static uint rdma_flag = + (1 << VPP_MATRIX_OSD) | + (1 << VPP_MATRIX_VD1) | + (1 << VPP_MATRIX_VD2) | + (1 << VPP_MATRIX_POST) | (1 << VPP_MATRIX_XVYCC); module_param(rdma_flag, uint, 0664); MODULE_PARM_DESC(rdma_flag, "\n set rdma_flag\n"); @@ -493,7 +511,7 @@ static void load_knee_lut(int on) int value; int final_knee_setting[MAX_KNEE_SETTING]; - if ((cur_knee_factor != knee_factor) && (!lut_289_en)) { + if ((cur_knee_factor != knee_factor) && (!lut_289_en) && (on)) { pr_csc("Knee_factor changed from %d to %d\n", cur_knee_factor, knee_factor); for (i = 0; i < MAX_KNEE_SETTING; i++) { @@ -505,15 +523,16 @@ static void load_knee_lut(int on) else if (final_knee_setting[i] < 0) final_knee_setting[i] = 0; } - WRITE_VPP_REG(XVYCC_LUT_CTL, 0x0); + VSYNC_WR_MPEG_REG(XVYCC_LUT_CTL, 0x0); for (j = 0; j < 3; j++) { for (i = 0; i < 16; i++) { - WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 2 * j, i); + VSYNC_WR_MPEG_REG( + XVYCC_LUT_R_ADDR_PORT + 2 * j, i); value = final_knee_setting[0] + (((final_knee_setting[1] - final_knee_setting[0]) * i) >> 4); value = clip(value, 0, 0x3ff); - WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, value); if (j == 0) pr_csc("xvycc_lut[%1d][%3d] = 0x%03x\n", @@ -521,7 +540,8 @@ static void load_knee_lut(int on) } for (i = 16; i < 272; i++) { k = 1 + ((i - 16) >> 3); - WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 2 * j, i); + VSYNC_WR_MPEG_REG( + XVYCC_LUT_R_ADDR_PORT + 2 * j, i); if (knee_interpolation_mode == 0) value = final_knee_setting[k] + (((final_knee_setting[k+1] @@ -535,7 +555,7 @@ static void load_knee_lut(int on) final_knee_setting[k+2], ((i - 16) & 0x7) << 3); value = clip(value, 0, 0x3ff); - WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, value); if (j == 0) pr_csc("xvycc_lut[%1d][%3d] = 0x%03x\n", @@ -543,13 +563,14 @@ static void load_knee_lut(int on) } for (i = 272; i < 289; i++) { k = MAX_KNEE_SETTING - 2; - WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 2 * j, i); + VSYNC_WR_MPEG_REG( + XVYCC_LUT_R_ADDR_PORT + 2 * j, i); value = final_knee_setting[k] + (((final_knee_setting[k+1] - final_knee_setting[k]) * (i - 272)) >> 4); value = clip(value, 0, 0x3ff); - WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_DATA_PORT + 2 * j, value); if (j == 0) pr_csc("xvycc_lut[%1d][%3d] = 0x%03x\n", @@ -559,28 +580,28 @@ static void load_knee_lut(int on) cur_knee_factor = knee_factor; } - if ((cur_knee_factor != knee_factor) && (lut_289_en)) { - WRITE_VPP_REG(XVYCC_LUT_CTL, 0x0); - WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT, 0); + if ((cur_knee_factor != knee_factor) && (lut_289_en) && (on)) { + VSYNC_WR_MPEG_REG(XVYCC_LUT_CTL, 0x0); + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_ADDR_PORT, 0); for (i = 0; i < LUT_289_SIZE; i++) - WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT, + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_DATA_PORT, lut_289_mapping[i]); - WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 2, 0); + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_ADDR_PORT + 2, 0); for (i = 0; i < LUT_289_SIZE; i++) - WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 2, + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_DATA_PORT + 2, lut_289_mapping[i]); - WRITE_VPP_REG(XVYCC_LUT_R_ADDR_PORT + 4, 0); + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_ADDR_PORT + 4, 0); for (i = 0; i < LUT_289_SIZE; i++) - WRITE_VPP_REG(XVYCC_LUT_R_DATA_PORT + 4, + VSYNC_WR_MPEG_REG(XVYCC_LUT_R_DATA_PORT + 4, lut_289_mapping[i]); cur_knee_factor = knee_factor; } if (on) { - WRITE_VPP_REG(XVYCC_LUT_CTL, 0x7f); + VSYNC_WR_MPEG_REG(XVYCC_LUT_CTL, 0x7f); knee_lut_on = 1; } else { - WRITE_VPP_REG(XVYCC_LUT_CTL, 0x0f); + VSYNC_WR_MPEG_REG(XVYCC_LUT_CTL, 0x0f); knee_lut_on = 0; } } @@ -591,6 +612,10 @@ static void load_knee_lut(int on) #define EOTF_INV_LUT_SIZE 32 #define EOTF_INV_LUT_1024_SIZE 17 +#define INVLUT_SDR2HDR 0x1 +#define INVLUT_HLG 0x2 +static unsigned int int_lut_sel[] = {0}; + static unsigned int num_invlut_neg_mapping = EOTF_INV_LUT_NEG2048_SIZE; static int invlut_y_neg[EOTF_INV_LUT_NEG2048_SIZE] = { -2048, -1920, -1792, -1664, @@ -616,6 +641,14 @@ static unsigned int invlut_y_1024[EOTF_INV_LUT_1024_SIZE] = { 2047 }; +static unsigned int num_invlut_hlg_mapping = EOTF_INV_LUT_SIZE; +static unsigned int invlut_hlg_y[EOTF_INV_LUT_SIZE] = { + 0, 14, 28, 48, 69, 91, 114, 138, + 163, 188, 215, 241, 269, 297, 325, 354, + 383, 415, 450, 490, 535, 579, 622, 663, + 705, 745, 786, 826, 866, 905, 945, 985 +}; + #define EOTF_LUT_SIZE 33 static unsigned int num_osd_eotf_r_mapping = EOTF_LUT_SIZE; static unsigned int osd_eotf_r_mapping[EOTF_LUT_SIZE] = { @@ -985,6 +1018,10 @@ module_param_array(invlut_y_1024, uint, &num_invlut_1024_mapping, 0664); MODULE_PARM_DESC(invlut_y_1024, "\n lut for inv y 1024..2048 eotf\n"); +module_param_array(invlut_hlg_y, int, + &num_invlut_hlg_mapping, 0664); +MODULE_PARM_DESC(invlut_hlg_y, "\n lut for hlg 0..1024 eotf\n"); + module_param_array(video_eotf_coeff, int, &num_video_eotf_coeff, 0664); MODULE_PARM_DESC(video_eotf_coeff, "\n matrix for video eotf\n"); @@ -1045,6 +1082,10 @@ module_param_array(xvycc_matrix_coeff, int, &num_xvycc_matrix_coeff, 0664); MODULE_PARM_DESC(xvycc_matrix_coeff, "\n xvycc matrix\n"); +static unsigned int mtx_en_mux; +module_param(mtx_en_mux, uint, 0664); +MODULE_PARM_DESC(mtx_en_mux, "\n mtx enable mux\n"); + /****************** matrix/lut reload********************/ module_param(reload_mtx, uint, 0664); @@ -1332,6 +1373,96 @@ static unsigned int oetf_sdr_2084_mapping[VIDEO_OETF_LUT_SIZE] = { module_param(display_scale_factor, uint, 0664); MODULE_PARM_DESC(display_scale_factor, "\n display scale factor\n"); +/*HLG eotf and oetf curve*/ +static unsigned int eotf_33_hlg_mapping[EOTF_LUT_SIZE] = { + 0, 5, 21, 48, 85, 133, 192, 261, + 341, 432, 533, 645, 768, 901, 1045, 1200, + 1365, 1552, 1774, 2038, 2353, 2729, 3175, 3707, + 4341, 5096, 5995, 7065, 8340, 9858, 11666, 13819, + 16383 +}; + +static unsigned int oetf_289_2084_mapping[VIDEO_OETF_LUT_SIZE] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 249, 301, 335, 360, 379, 396, 410, + 423, 434, 444, 453, 462, 470, 477, 484, + 491, 497, 502, 508, 513, 518, 523, 528, + 532, 536, 540, 544, 548, 552, 555, 559, + 562, 565, 568, 571, 574, 577, 580, 583, + 586, 588, 591, 593, 596, 598, 601, 603, + 605, 607, 609, 612, 614, 616, 618, 620, + 622, 624, 625, 627, 629, 631, 633, 634, + 636, 638, 640, 641, 643, 644, 646, 647, + 649, 651, 652, 653, 655, 656, 658, 659, + 661, 662, 663, 665, 666, 667, 668, 670, + 671, 672, 673, 675, 676, 677, 678, 679, + 681, 682, 683, 684, 685, 686, 687, 688, + 689, 690, 691, 692, 694, 695, 696, 697, + 698, 699, 699, 700, 701, 702, 703, 704, + 705, 706, 707, 708, 709, 710, 711, 711, + 712, 713, 714, 715, 716, 717, 717, 718, + 719, 720, 721, 721, 722, 723, 724, 725, + 725, 726, 727, 728, 728, 729, 730, 731, + 731, 732, 733, 734, 734, 735, 736, 736, + 737, 738, 738, 739, 740, 741, 741, 742, + 743, 743, 744, 744, 745, 746, 746, 747, + 748, 748, 749, 750, 750, 751, 751, 752, + 753, 753, 754, 754, 755, 756, 756, 757, + 757, 758, 759, 759, 760, 760, 761, 761, + 762, 762, 763, 764, 764, 765, 765, 766, + 766, 767, 767, 768, 768, 769, 769, 770, + 771, 771, 772, 772, 773, 773, 774, 774, + 775, 775, 776, 776, 777, 777, 778, 778, + 778, 779, 779, 780, 780, 781, 781, 782, + 782, 783, 783, 784, 784, 785, 785, 785, + 786, 786, 787, 787, 788, 788, 789, 789, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023, 1023, 1023, 1023, 1023, + 1023 +}; + +/*static unsigned int oetf_289_709_mapping[VIDEO_OETF_LUT_SIZE] = {*/ +/* 0, 0, 0, 0, 0, 0, 0, 0,*/ +/* 0, 0, 0, 0, 0, 0, 0, 0,*/ +/* 0, 17, 35, 52, 70, 84, 100, 114,*/ +/* 127, 140, 151, 163, 173, 183, 193, 202,*/ +/* 211, 220, 228, 236, 244, 252, 259, 266,*/ +/* 274, 280, 287, 294, 300, 307, 313, 319,*/ +/* 325, 331, 337, 343, 349, 354, 360, 365,*/ +/* 371, 376, 381, 386, 391, 396, 401, 406,*/ +/* 411, 416, 421, 425, 430, 435, 439, 444,*/ +/* 448, 453, 457, 461, 466, 470, 474, 478,*/ +/* 482, 486, 491, 495, 499, 503, 506, 510,*/ +/* 514, 518, 522, 526, 530, 533, 537, 541,*/ +/* 544, 548, 552, 555, 559, 562, 566, 569,*/ +/* 573, 576, 580, 583, 586, 590, 593, 597,*/ +/* 600, 603, 606, 610, 613, 616, 619, 623,*/ +/* 626, 629, 632, 635, 638, 641, 644, 647,*/ +/* 651, 654, 657, 660, 663, 666, 668, 671,*/ +/* 674, 677, 680, 683, 686, 689, 692, 695,*/ +/* 697, 700, 703, 706, 709, 711, 714, 717,*/ +/* 720, 722, 725, 728, 730, 733, 736, 738,*/ +/* 741, 744, 746, 749, 752, 754, 757, 759,*/ +/* 762, 765, 767, 770, 772, 775, 777, 780,*/ +/* 782, 785, 787, 790, 792, 795, 797, 800,*/ +/* 802, 804, 807, 809, 812, 814, 817, 819,*/ +/* 821, 824, 826, 828, 831, 833, 835, 838,*/ +/* 840, 842, 845, 847, 849, 852, 854, 856,*/ +/* 858, 861, 863, 865, 867, 870, 872, 874,*/ +/* 876, 878, 881, 883, 885, 887, 889, 892,*/ +/* 894, 896, 898, 900, 902, 905, 907, 909,*/ +/* 911, 913, 915, 917, 919, 922, 924, 926,*/ +/* 928, 930, 932, 934, 936, 938, 940, 942,*/ +/* 944, 946, 948, 950, 952, 954, 956, 958,*/ +/* 960, 962, 964, 966, 968, 970, 972, 974,*/ +/* 976, 978, 980, 982, 984, 986, 988, 990,*/ +/* 992, 994, 996, 998, 1000, 1002, 1004, 1006,*/ +/* 1008, 1010, 1012, 1014, 1016, 1018, 1020, 1022,*/ +/* 1023*/ +/*};*/ +/*end HLG eotf and oetf curve*/ + /* video oetf: linear */ #if 0 static unsigned int oetf_289_linear_mapping[VIDEO_OETF_LUT_SIZE] = { @@ -1432,7 +1563,6 @@ const char matrix_name[7][16] = { static void print_vpp_matrix(int m_select, int *s, int on) { unsigned int size; - if (s == NULL) return; if (m_select == VPP_MATRIX_OSD) @@ -1513,9 +1643,9 @@ void set_vpp_matrix(int m_select, int *s, int on) { int *m = NULL; int size = 0; - int i; + int i, reg_value; - if (debug_csc) + if (debug_csc && print_lut_mtx) print_vpp_matrix(m_select, s, on); if (m_select == VPP_MATRIX_OSD) { m = osd_matrix_coeff; @@ -1548,46 +1678,107 @@ void set_vpp_matrix(int m_select, int *s, int on) else reload_mtx &= ~(1 << m_select); + reg_value = READ_VPP_REG(VPP_MATRIX_CTRL); + if (m_select == VPP_MATRIX_OSD) { /* osd matrix, VPP_MATRIX_0 */ - /* not enable latched */ - hdr_osd_reg.viu_osd1_matrix_pre_offset0_1 = - ((m[0] & 0xfff) << 16) | (m[1] & 0xfff); - hdr_osd_reg.viu_osd1_matrix_pre_offset2 = - m[2] & 0xfff; - hdr_osd_reg.viu_osd1_matrix_coef00_01 = - ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff); - hdr_osd_reg.viu_osd1_matrix_coef02_10 = - ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff); - hdr_osd_reg.viu_osd1_matrix_coef11_12 = - ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff); - hdr_osd_reg.viu_osd1_matrix_coef20_21 = - ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff); - if (m[21]) { - hdr_osd_reg.viu_osd1_matrix_coef22_30 = - ((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff); - hdr_osd_reg.viu_osd1_matrix_coef31_32 = - ((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff); - hdr_osd_reg.viu_osd1_matrix_coef40_41 = - ((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff); - hdr_osd_reg.viu_osd1_matrix_colmod_coef42 = - m[17] & 0x1fff; + if (!is_meson_txlx_cpu()) { + /* not enable latched */ + hdr_osd_reg.viu_osd1_matrix_pre_offset0_1 = + ((m[0] & 0xfff) << 16) | (m[1] & 0xfff); + hdr_osd_reg.viu_osd1_matrix_pre_offset2 = + m[2] & 0xfff; + hdr_osd_reg.viu_osd1_matrix_coef00_01 = + ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef02_10 = + ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef11_12 = + ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef20_21 = + ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff); + if (m[21]) { + hdr_osd_reg.viu_osd1_matrix_coef22_30 = + ((m[11] & 0x1fff) << 16) | + (m[12] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef31_32 = + ((m[13] & 0x1fff) << 16) | + (m[14] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_coef40_41 = + ((m[15] & 0x1fff) << 16) | + (m[16] & 0x1fff); + hdr_osd_reg.viu_osd1_matrix_colmod_coef42 = + m[17] & 0x1fff; + } else { + hdr_osd_reg.viu_osd1_matrix_coef22_30 = + (m[11] & 0x1fff) << 16; + } + hdr_osd_reg.viu_osd1_matrix_offset0_1 = + ((m[18] & 0xfff) << 16) | (m[19] & 0xfff); + hdr_osd_reg.viu_osd1_matrix_offset2 = + m[20] & 0xfff; + + hdr_osd_reg.viu_osd1_matrix_colmod_coef42 &= 0x3ff8ffff; + hdr_osd_reg.viu_osd1_matrix_colmod_coef42 |= + (m[21] << 30) | (m[22] << 16); + + /* 23 reserved for clipping control */ + hdr_osd_reg.viu_osd1_matrix_ctrl &= 0xfffffffc; + hdr_osd_reg.viu_osd1_matrix_ctrl |= on; } else { - hdr_osd_reg.viu_osd1_matrix_coef22_30 = - (m[11] & 0x1fff) << 16; + /* move the matrix from osd to vpp in txlx */ + m = osd_matrix_coeff; + + if (on) { + reg_value = (reg_value & (~(7 << 8))) + | (4 << 8); + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, + reg_value); + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET0_1, + ((m[0] & 0xfff) << 16) + | (m[1] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET2, + m[2] & 0xfff); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, + ((m[3] & 0x1fff) << 16) + | (m[4] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, + ((m[5] & 0x1fff) << 16) + | (m[6] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, + ((m[7] & 0x1fff) << 16) + | (m[8] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, + ((m[9] & 0x1fff) << 16) + | (m[10] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, + m[11] & 0x1fff); + if (m[21]) { + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF13_14, + ((m[12] & 0x1fff) << 16) + | (m[13] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF15_25, + ((m[14] & 0x1fff) << 16) + | (m[17] & 0x1fff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF23_24, + ((m[15] & 0x1fff) << 16) + | (m[16] & 0x1fff)); + } + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, + ((m[18] & 0xfff) << 16) + | (m[19] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, + m[20] & 0xfff); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, + m[21], 3, 2); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, + m[22], 5, 3); + } + /*VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CTRL, on, 7, 1);*/ + if (on) + mtx_en_mux |= OSD1_MTX_EN_MASK; + else + mtx_en_mux &= ~OSD1_MTX_EN_MASK; } - hdr_osd_reg.viu_osd1_matrix_offset0_1 = - ((m[18] & 0xfff) << 16) | (m[19] & 0xfff); - hdr_osd_reg.viu_osd1_matrix_offset2 = - m[20] & 0xfff; - - hdr_osd_reg.viu_osd1_matrix_colmod_coef42 &= 0x3ff8ffff; - hdr_osd_reg.viu_osd1_matrix_colmod_coef42 |= - (m[21] << 30) | (m[22] << 16); - - /* 23 reserved for clipping control */ - hdr_osd_reg.viu_osd1_matrix_ctrl &= 0xfffffffc; - hdr_osd_reg.viu_osd1_matrix_ctrl |= on; } else if (m_select == VPP_MATRIX_EOTF) { /* eotf matrix, VPP_MATRIX_EOTF */ /* enable latched */ @@ -1595,32 +1786,61 @@ void set_vpp_matrix(int m_select, int *s, int on) VSYNC_WR_MPEG_REG(VIU_EOTF_CTL + i + 1, ((m[i * 2] & 0x1fff) << 16) | (m[i * 2 + 1] & 0x1fff)); + if (is_meson_txlx_cpu()) { + VSYNC_WR_MPEG_REG(VIU_EOTF_CTL + 8, 0); + VSYNC_WR_MPEG_REG(VIU_EOTF_CTL + 9, 0); + } WRITE_VPP_REG_BITS(VIU_EOTF_CTL, on, 30, 1); WRITE_VPP_REG_BITS(VIU_EOTF_CTL, on, 31, 1); } else if (m_select == VPP_MATRIX_OSD_EOTF) { /* osd eotf matrix, VPP_MATRIX_OSD_EOTF */ - /* enable latched */ - hdr_osd_reg.viu_osd1_eotf_coef00_01 = - ((m[0 * 2] & 0x1fff) << 16) - | (m[0 * 2 + 1] & 0x1fff); + if (!is_meson_txlx_cpu()) { + /* enable latched */ + hdr_osd_reg.viu_osd1_eotf_coef00_01 = + ((m[0 * 2] & 0x1fff) << 16) + | (m[0 * 2 + 1] & 0x1fff); - hdr_osd_reg.viu_osd1_eotf_coef02_10 = - ((m[1 * 2] & 0x1fff) << 16) - | (m[1 * 2 + 1] & 0x1fff); + hdr_osd_reg.viu_osd1_eotf_coef02_10 = + ((m[1 * 2] & 0x1fff) << 16) + | (m[1 * 2 + 1] & 0x1fff); - hdr_osd_reg.viu_osd1_eotf_coef11_12 = - ((m[2 * 2] & 0x1fff) << 16) - | (m[2 * 2 + 1] & 0x1fff); + hdr_osd_reg.viu_osd1_eotf_coef11_12 = + ((m[2 * 2] & 0x1fff) << 16) + | (m[2 * 2 + 1] & 0x1fff); - hdr_osd_reg.viu_osd1_eotf_coef20_21 = - ((m[3 * 2] & 0x1fff) << 16) - | (m[3 * 2 + 1] & 0x1fff); - hdr_osd_reg.viu_osd1_eotf_coef22_rs = - ((m[4 * 2] & 0x1fff) << 16) - | (m[4 * 2 + 1] & 0x1fff); + hdr_osd_reg.viu_osd1_eotf_coef20_21 = + ((m[3 * 2] & 0x1fff) << 16) + | (m[3 * 2 + 1] & 0x1fff); + hdr_osd_reg.viu_osd1_eotf_coef22_rs = + ((m[4 * 2] & 0x1fff) << 16) + | (m[4 * 2 + 1] & 0x1fff); - hdr_osd_reg.viu_osd1_eotf_ctl &= 0x3fffffff; - hdr_osd_reg.viu_osd1_eotf_ctl |= (on << 30) | (on << 31); + hdr_osd_reg.viu_osd1_eotf_ctl &= 0x3fffffff; + hdr_osd_reg.viu_osd1_eotf_ctl |= + (on << 30) | (on << 31); + } else { + /* latch enable */ + WRITE_VPP_REG_BITS(VIU_OSD1_EOTF_CTL, 1, 26, 1); + if (on) { + VSYNC_WR_MPEG_REG(VIU_OSD1_EOTF_COEF00_01, + ((m[0 * 2] & 0x1fff) << 16) | + (m[0 * 2 + 1] & 0x1fff)); + VSYNC_WR_MPEG_REG(VIU_OSD1_EOTF_COEF02_10, + ((m[1 * 2] & 0x1fff) << 16) | + (m[1 * 2 + 1] & 0x1fff)); + VSYNC_WR_MPEG_REG(VIU_OSD1_EOTF_COEF11_12, + ((m[2 * 2] & 0x1fff) << 16) | + (m[2 * 2 + 1] & 0x1fff)); + VSYNC_WR_MPEG_REG(VIU_OSD1_EOTF_COEF20_21, + ((m[3 * 2] & 0x1fff) << 16) | + (m[3 * 2 + 1] & 0x1fff)); + VSYNC_WR_MPEG_REG(VIU_OSD1_EOTF_COEF22_RS, + ((m[4 * 2] & 0x1fff) << 16) | + (m[4 * 2 + 1] & 0x1fff)); + } + WRITE_VPP_REG_BITS(VIU_OSD1_EOTF_CTL, + (on | (on << 1)), 30, 2); + } } else { /* vd1 matrix, VPP_MATRIX_1 */ /* post matrix, VPP_MATRIX_2 */ @@ -1629,64 +1849,102 @@ void set_vpp_matrix(int m_select, int *s, int on) if (m_select == VPP_MATRIX_POST) { /* post matrix */ m = post_matrix_coeff; - /* set bit for enable latched */ - WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 1, 14, 1); - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 0, 1); - if (on) { - if (rdma_flag & (1 << m_select)) - VSYNC_WR_MPEG_REG_BITS( - VPP_MATRIX_CTRL, 0, 8, 2); + if (rdma_flag & (1 << m_select)) { + /* set bit for disable latched */ + WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 0, 14, 1); + if (on) + mtx_en_mux |= POST_MTX_EN_MASK; else + mtx_en_mux &= ~POST_MTX_EN_MASK; + } else { + WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 1, 14, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 0, 1); + } + + if (on) { + if (rdma_flag & (1 << m_select)) { + /*VSYNC_WR_MPEG_REG_BITS(*/ + /*VPP_MATRIX_CTRL, 0, 8, 3);*/ + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, + (reg_value & (~(7 << 8))) + | (0 << 8)); + } else WRITE_VPP_REG_BITS( - VPP_MATRIX_CTRL, 0, 8, 2); + VPP_MATRIX_CTRL, 0, 8, 3); } } else if (m_select == VPP_MATRIX_VD1) { /* vd1 matrix, latched */ m = vd1_matrix_coeff; - /* set bit for enable latched */ - WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 1, 9, 1); - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 5, 1); - if (on) { - if (rdma_flag & (1 << m_select)) - VSYNC_WR_MPEG_REG_BITS( - VPP_MATRIX_CTRL, 1, 8, 2); + if (rdma_flag & (1 << m_select)) { + /* set bit for disable latched */ + WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 0, 9, 1); + /*WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL,*/ + /*on, 5, 1);*/ + if (on) + mtx_en_mux |= VD1_MTX_EN_MASK; else + mtx_en_mux &= ~VD1_MTX_EN_MASK; + } else { + /* set bit for enable latched */ + WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 1, 9, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 5, 1); + } + if (on) { + if (rdma_flag & (1 << m_select)) { + /*VSYNC_WR_MPEG_REG_BITS(*/ + /*VPP_MATRIX_CTRL, 1, 8, 3);*/ + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, + (reg_value & (~(7 << 8))) + | (1 << 8)); + } else WRITE_VPP_REG_BITS( - VPP_MATRIX_CTRL, 1, 8, 2); + VPP_MATRIX_CTRL, 1, 8, 3); } } else if (m_select == VPP_MATRIX_VD2) { /* vd2 matrix, not latched */ m = vd2_matrix_coeff; - if (rdma_flag & (1 << m_select)) - VSYNC_WR_MPEG_REG_BITS( - VPP_MATRIX_CTRL, on, 4, 1); - else - WRITE_VPP_REG_BITS( - VPP_MATRIX_CTRL, on, 4, 1); - if (on) { - if (rdma_flag & (1 << m_select)) - VSYNC_WR_MPEG_REG_BITS( - VPP_MATRIX_CTRL, 2, 8, 2); + if (rdma_flag & (1 << m_select)) { + if (on) + mtx_en_mux |= VD2_MTX_EN_MASK; else + mtx_en_mux &= ~VD2_MTX_EN_MASK; + } else { + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 4, 1); + } + if (on) { + if (rdma_flag & (1 << m_select)) { + /*VSYNC_WR_MPEG_REG_BITS(*/ + /*VPP_MATRIX_CTRL, 2, 8, 3);*/ + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, + (reg_value & (~(7 << 8))) + | (2 << 8)); + } else WRITE_VPP_REG_BITS( - VPP_MATRIX_CTRL, 2, 8, 2); + VPP_MATRIX_CTRL, 2, 8, 3); } } else if (m_select == VPP_MATRIX_XVYCC) { /* xvycc matrix, not latched */ m = xvycc_matrix_coeff; - if (rdma_flag & (1 << m_select)) - VSYNC_WR_MPEG_REG_BITS( - VPP_MATRIX_CTRL, on, 6, 1); - else - WRITE_VPP_REG_BITS( - VPP_MATRIX_CTRL, on, 6, 1); + if (on) { - if (rdma_flag & (1 << m_select)) - VSYNC_WR_MPEG_REG_BITS( - VPP_MATRIX_CTRL, 3, 8, 2); - else + if (rdma_flag & (1 << m_select)) { + mtx_en_mux |= XVY_MTX_EN_MASK; + reg_value = (reg_value & (~(7 << 8))) + | (3 << 8); + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, + reg_value); + } else { WRITE_VPP_REG_BITS( - VPP_MATRIX_CTRL, 3, 8, 2); + VPP_MATRIX_CTRL, on, 6, 1); + WRITE_VPP_REG_BITS( + VPP_MATRIX_CTRL, 3, 8, 3); + } + } else { + if (rdma_flag & (1 << m_select)) { + mtx_en_mux &= ~XVY_MTX_EN_MASK; + } else + WRITE_VPP_REG_BITS( + VPP_MATRIX_CTRL, on, 6, 1); } } if (on) { @@ -1780,7 +2038,6 @@ void enable_osd_path(int on) static int *osd1_mtx_backup; static uint32_t osd1_eotf_ctl_backup; static uint32_t osd1_oetf_ctl_backup; - if (!on) { osd1_mtx_backup = cur_osd_mtx; osd1_eotf_ctl_backup = hdr_osd_reg.viu_osd1_eotf_ctl; @@ -2041,15 +2298,57 @@ void set_vpp_lut( for (i = 0; i < OSD_OETF_LUT_SIZE; i++) b_map[i] = b[i]; - for (i = 0; i < OSD_OETF_LUT_SIZE; i++) { - hdr_osd_reg.lut_val.or_map[i] = r_map[i]; - hdr_osd_reg.lut_val.og_map[i] = g_map[i]; - hdr_osd_reg.lut_val.ob_map[i] = b_map[i]; + if (!is_meson_txlx_cpu()) { + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) { + hdr_osd_reg.lut_val.or_map[i] = r_map[i]; + hdr_osd_reg.lut_val.og_map[i] = g_map[i]; + hdr_osd_reg.lut_val.ob_map[i] = b_map[i]; + } + hdr_osd_reg.viu_osd1_oetf_ctl &= 0x1fffffff; + hdr_osd_reg.viu_osd1_oetf_ctl |= 7 << 22; + if (on) + hdr_osd_reg.viu_osd1_oetf_ctl |= 7 << 29; + } else { + /* latch enable */ + WRITE_VPP_REG_BITS(VIU_OSD1_OETF_CTL, 1, 28, 1); + if (on) { + /* change to 12bit from txlx */ + for (i = 0; i < OSD_OETF_LUT_SIZE; i++) { + r_map[i] = 4 * r_map[i]; + g_map[i] = 4 * g_map[i]; + b_map[i] = 4 * b_map[i]; + } + for (i = 0; i < 20; i++) { + VSYNC_WR_MPEG_REG(addr_port, i); + VSYNC_WR_MPEG_REG(data_port, + r_map[i * 2] + | (r_map[i * 2 + 1] << 16)); + } + VSYNC_WR_MPEG_REG(addr_port, 20); + VSYNC_WR_MPEG_REG(data_port, + r_map[41 - 1] + | (g_map[0] << 16)); + for (i = 0; i < 20; i++) { + VSYNC_WR_MPEG_REG(addr_port, 21 + i); + VSYNC_WR_MPEG_REG(data_port, + g_map[i * 2 + 1] + | (g_map[i * 2 + 2] << 16)); + } + for (i = 0; i < 20; i++) { + VSYNC_WR_MPEG_REG(addr_port, 41 + i); + VSYNC_WR_MPEG_REG(data_port, + b_map[i * 2] + | (b_map[i * 2 + 1] << 16)); + } + VSYNC_WR_MPEG_REG(addr_port, 61); + VSYNC_WR_MPEG_REG(data_port, + b_map[41 - 1]); + } + + WRITE_VPP_REG_BITS(VIU_OSD1_OETF_CTL, 7, 22, 3); + WRITE_VPP_REG_BITS(VIU_OSD1_OETF_CTL, + (on | (on << 1) | (on << 2)), 29, 3); } - hdr_osd_reg.viu_osd1_oetf_ctl &= 0x1fffffff; - hdr_osd_reg.viu_osd1_oetf_ctl |= 7 << 22; - if (on) - hdr_osd_reg.viu_osd1_oetf_ctl |= 7 << 29; } else if (lut_sel == VPP_LUT_OSD_EOTF) { /* enable latched */ if (r && r_map) @@ -2062,15 +2361,50 @@ void set_vpp_lut( for (i = 0; i < EOTF_LUT_SIZE; i++) b_map[i] = b[i]; - for (i = 0; i < EOTF_LUT_SIZE; i++) { - hdr_osd_reg.lut_val.r_map[i] = r_map[i]; - hdr_osd_reg.lut_val.g_map[i] = g_map[i]; - hdr_osd_reg.lut_val.b_map[i] = b_map[i]; + if (!is_meson_txlx_cpu()) { + for (i = 0; i < EOTF_LUT_SIZE; i++) { + hdr_osd_reg.lut_val.r_map[i] = r_map[i]; + hdr_osd_reg.lut_val.g_map[i] = g_map[i]; + hdr_osd_reg.lut_val.b_map[i] = b_map[i]; + } + hdr_osd_reg.viu_osd1_eotf_ctl &= 0xc7ffffff; + if (on) + hdr_osd_reg.viu_osd1_eotf_ctl |= 7 << 27; + hdr_osd_reg.viu_osd1_eotf_ctl |= 1 << 31; + } else { + /* latch enable */ + WRITE_VPP_REG_BITS(VIU_OSD1_EOTF_CTL, 1, 26, 1); + if (on) { + VSYNC_WR_MPEG_REG( + addr_port, 0); + for (i = 0; i < 16; i++) + VSYNC_WR_MPEG_REG( + data_port, + r_map[i * 2] + | (r_map[i * 2 + 1] << 16)); + VSYNC_WR_MPEG_REG( + data_port, + r_map[EOTF_LUT_SIZE - 1] + | (g_map[0] << 16)); + for (i = 0; i < 16; i++) + VSYNC_WR_MPEG_REG( + data_port, + g_map[i * 2 + 1] + | (b_map[i * 2 + 2] << 16)); + for (i = 0; i < 16; i++) + VSYNC_WR_MPEG_REG( + data_port, + b_map[i * 2] + | (b_map[i * 2 + 1] << 16)); + VSYNC_WR_MPEG_REG( + data_port, b_map[EOTF_LUT_SIZE - 1]); + } + + WRITE_VPP_REG_BITS(VIU_OSD1_EOTF_CTL, + 1, 31, 1); + WRITE_VPP_REG_BITS(VIU_OSD1_EOTF_CTL, + (on | (on << 1) | (on << 2)), 27, 3); } - hdr_osd_reg.viu_osd1_eotf_ctl &= 0xc7ffffff; - if (on) - hdr_osd_reg.viu_osd1_eotf_ctl |= 7 << 27; - hdr_osd_reg.viu_osd1_eotf_ctl |= 1 << 31; } else if (lut_sel == VPP_LUT_EOTF) { /* enable latched */ if (r && r_map) @@ -2082,6 +2416,10 @@ void set_vpp_lut( if (r && r_map) for (i = 0; i < EOTF_LUT_SIZE; i++) b_map[i] = b[i]; + /*txlx add eotf latch ctl bit 26*/ + if (is_meson_txlx_cpu()) + WRITE_VPP_REG_BITS(ctrl_port, 1, 26, 1); + if (on) { for (i = 0; i < 16; i++) { VSYNC_WR_MPEG_REG(addr_port, i); @@ -2148,6 +2486,11 @@ void set_vpp_lut( /* set bit to enable latched */ WRITE_VPP_REG_BITS(VPP_XVYCC_MISC, 0x7, 4, 3); if (on) { + if (r[0] & INVLUT_HLG) { + for (i = 0; i < EOTF_INV_LUT_SIZE; i++) + invlut_y[i] = invlut_hlg_y[i]; + r[0] = 0; + } VSYNC_WR_MPEG_REG(addr_port, 0); for (i = 0; i < EOTF_INV_LUT_NEG2048_SIZE; i++) { VSYNC_WR_MPEG_REG(addr_port, i); @@ -2168,7 +2511,7 @@ void set_vpp_lut( } else WRITE_VPP_REG_BITS(ctrl_port, 0, 12, 3); } - if (debug_csc) + if (debug_csc && print_lut_mtx) print_vpp_lut(lut_sel, on); } @@ -2206,29 +2549,72 @@ void set_vpp_lut( /* 6: customer matrix calculation according to src and dest primary*/ /* vd1 for ycbcr to rgb*/ /* post for rgb to r'g'b' */ +static void vpp_set_mtx_en_write(void) +{ + int reg_val; + + reg_val = READ_VPP_REG(VPP_MATRIX_CTRL); + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, (reg_val & + (~(POST_MTX_EN_MASK | + VD2_MTX_EN_MASK | + VD1_MTX_EN_MASK | + XVY_MTX_EN_MASK | + OSD1_MTX_EN_MASK))) | + mtx_en_mux); +} + +static void vpp_set_mtx_en_read(void) +{ + int reg_value; + + reg_value = READ_VPP_REG(VPP_MATRIX_CTRL); + mtx_en_mux = reg_value & + (POST_MTX_EN_MASK | + VD2_MTX_EN_MASK | + VD1_MTX_EN_MASK | + XVY_MTX_EN_MASK | + OSD1_MTX_EN_MASK); +} + static void vpp_set_matrix( enum vpp_matrix_sel_e vd1_or_vd2_or_post, unsigned int on, enum vpp_matrix_csc_e csc_mode, struct matrix_s *m) { + int reg_value; if (force_csc_type != 0xff) csc_mode = force_csc_type; + reg_value = READ_VPP_REG(VPP_MATRIX_CTRL); + if (vd1_or_vd2_or_post == VPP_MATRIX_VD1) { /* vd1 matrix */ - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 5, 1); - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 1, 8, 2); + reg_value = (reg_value & (~(7 << 8))) | (1 << 8); + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, reg_value); + + if (on) + mtx_en_mux |= VD1_MTX_EN_MASK; + else + mtx_en_mux &= ~VD1_MTX_EN_MASK; } else if (vd1_or_vd2_or_post == VPP_MATRIX_VD2) { /* vd2 matrix */ - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 4, 1); - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 2, 8, 2); + reg_value = (reg_value & (~(7 << 8))) | (2 << 8); + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, reg_value); + + if (on) + mtx_en_mux |= VD2_MTX_EN_MASK; + else + mtx_en_mux &= ~VD2_MTX_EN_MASK; } else { /* post matrix */ - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 0, 1); - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 0, 8, 2); - /* saturation enable for 601 & 709 limited input */ - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 0, 1, 2); + reg_value = (reg_value & (~(7 << 8))) | (0 << 8); + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, reg_value); + + if (on) + mtx_en_mux |= POST_MTX_EN_MASK; + else + mtx_en_mux &= ~POST_MTX_EN_MASK; } if (!on) return; @@ -2238,117 +2624,139 @@ static void vpp_set_matrix( /* -16 1.164 0 1.596 0*/ /* -128 1.164 -0.392 -0.813 0*/ /* -128 1.164 2.017 0 0 */ - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04A80000); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x066204A8); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1e701cbf); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x04A80812); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x00000000); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x00000000); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x00000000); - WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, 0x04A80000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, 0x066204A8); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, 0x1e701cbf); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, 0x04A80812); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x00000000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x00000000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x00000000); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); } else if (csc_mode == VPP_MATRIX_YUV601F_RGB) { /* ycbcr full range, 601F to RGB */ /* 0 1 0 1.402 0*/ /* -128 1 -0.34414 -0.71414 0*/ /* -128 1 1.772 0 0 */ - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, (0x400 << 16) | 0); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, (0x59c << 16) | 0x400); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, (0x1ea0 << 16) | 0x1d24); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, (0x400 << 16) | 0x718); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); - WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, (0x400 << 16) | 0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, (0x59c << 16) | 0x400); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, + (0x1ea0 << 16) | 0x1d24); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, (0x400 << 16) | 0x718); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); } else if (csc_mode == VPP_MATRIX_YUV709_RGB) { /* ycbcr limit range, 709 to RGB */ /* -16 1.164 0 1.793 0 */ /* -128 1.164 -0.213 -0.534 0 */ /* -128 1.164 2.115 0 0 */ - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04A80000); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x072C04A8); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1F261DDD); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x04A80876); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, 0x04A80000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, 0x072C04A8); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, 0x1F261DDD); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, 0x04A80876); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x0); - WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); } else if (csc_mode == VPP_MATRIX_YUV709F_RGB) { /* ycbcr full range, 709F to RGB */ /* 0 1 0 1.575 0*/ /* -128 1 -0.187 -0.468 0*/ /* -128 1 1.856 0 0 */ - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04000000); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x064D0400); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1F411E21); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x0400076D); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); - WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, 0x04000000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, 0x064D0400); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, 0x1F411E21); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, 0x0400076D); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); } else if (csc_mode == VPP_MATRIX_NULL) { /* bypass matrix */ - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04000000); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x04000000); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x00000000); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x00000400); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); - WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, 0x04000000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, 0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, 0x04000000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, 0x00000000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x00000400); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); } else if (csc_mode >= VPP_MATRIX_BT2020YUV_BT2020RGB) { if (vd1_or_vd2_or_post == VPP_MATRIX_VD1) { /* bt2020 limit to bt2020 RGB */ - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x4ad0000); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x6e50492); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1f3f1d63); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x492089a); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); - WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, 0x4ad0000); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, 0x6e50492); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, 0x1f3f1d63); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, 0x492089a); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); } if (vd1_or_vd2_or_post == VPP_MATRIX_POST) { if (csc_mode == VPP_MATRIX_BT2020YUV_BT2020RGB) { /* 2020 RGB to R'G'B */ + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET0_1, + 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, + 0xd491b4d); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, + 0x1f6b1f01); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, + 0x9101fef); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, + 0x1fdb1f32); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x108f3); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, + 1, 5, 3); +#if 0 /* disable this case after calculate mtx on the fly*/ + } else if (csc_mode == VPP_MATRIX_BT2020RGB_709RGB) { + /*to R'G'B' */ WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0xd491b4d); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x1f6b1f01); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x9101fef); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x1fdb1f32); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x108f3); + /* from Jason */ + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x9cd1e33); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x00001faa); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x8560000); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x1fd81f5f); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x108c9); WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 1, 5, 3); +#endif } else if (csc_mode == VPP_MATRIX_BT2020RGB_CUSRGB) { /* customer matrix 2020 RGB to R'G'B' */ - WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET0_1, (m->pre_offset[0] << 16) | (m->pre_offset[1] & 0xffff)); - WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET2, m->pre_offset[2] & 0xffff); - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, (m->matrix[0][0] << 16) | (m->matrix[0][1] & 0xffff)); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, (m->matrix[0][2] << 16) | (m->matrix[1][0] & 0xffff)); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, (m->matrix[1][1] << 16) | (m->matrix[1][2] & 0xffff)); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, (m->matrix[2][0] << 16) | (m->matrix[2][1] & 0xffff)); - WRITE_VPP_REG(VPP_MATRIX_COEF22, + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, (m->right_shift << 16) | (m->matrix[2][2] & 0xffff)); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, (m->offset[0] << 16) | (m->offset[1] & 0xffff)); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, m->offset[2] & 0xffff); - WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, + VSYNC_WR_MPEG_REG_BITS(VPP_MATRIX_CLIP, m->right_shift, 5, 3); } } @@ -2361,40 +2769,52 @@ static void vpp_set_matrix3( unsigned int on, enum vpp_matrix_csc_e csc_mode) { - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, on, 6, 1); + int reg_value; + + reg_value = READ_VPP_REG(VPP_MATRIX_CTRL); + + if (on) + mtx_en_mux |= XVY_MTX_EN_MASK; + else + mtx_en_mux &= ~XVY_MTX_EN_MASK; + if (!on) return; if (cur_csc_mode == csc_mode) return; - WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 3, 8, 2); + reg_value = READ_VPP_REG(VPP_MATRIX_CTRL); + + VSYNC_WR_MPEG_REG(VPP_MATRIX_CTRL, + (reg_value & (~(7 << 8))) | (3 << 8)); + if (csc_mode == VPP_MATRIX_RGB_YUV709F) { /* RGB -> 709F*/ /*WRITE_VPP_REG(VPP_MATRIX_CTRL, 0x7360);*/ - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0xda02dc); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x4a1f8a); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1e760200); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x2001e2f); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x1fd1); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x200); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x200); - WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); - WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, 0xda02dc); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, 0x4a1f8a); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, 0x1e760200); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, 0x2001e2f); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x1fd1); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x200); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x200); + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); } else if (csc_mode == VPP_MATRIX_RGB_YUV709) { /* RGB -> 709 limit */ /*WRITE_VPP_REG(VPP_MATRIX_CTRL, 0x7360);*/ - WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x00bb0275); - WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x003f1f99); - WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1ea601c2); - WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x01c21e67); - WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x00001fd7); - WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x00400200); - WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x00000200); - WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); - WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF00_01, 0x00bb0275); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF02_10, 0x003f1f99); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF11_12, 0x1ea601c2); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF20_21, 0x01c21e67); + VSYNC_WR_MPEG_REG(VPP_MATRIX_COEF22, 0x00001fd7); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET0_1, 0x00400200); + VSYNC_WR_MPEG_REG(VPP_MATRIX_OFFSET2, 0x00000200); + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); } cur_csc_mode = csc_mode; } @@ -2531,6 +2951,24 @@ int signal_type_changed(struct vframe_s *vf, struct vinfo_s *vinfo) p_cur->luminance[i] = p_new->luminance[i]; } + if (p_cur->content_light_level.present_flag != + p_new->content_light_level.present_flag) { + change_flag |= SIG_PRI_INFO; + p_cur->content_light_level.present_flag = + p_new->content_light_level.present_flag; + } + if (p_cur->content_light_level.max_content != + p_new->content_light_level.max_content) { + change_flag |= SIG_PRI_INFO; + p_cur->content_light_level.max_content = + p_new->content_light_level.max_content; + } + if (p_cur->content_light_level.max_pic_average != + p_new->content_light_level.max_pic_average) { + change_flag |= SIG_PRI_INFO; + p_cur->content_light_level.max_pic_average = + p_new->content_light_level.max_pic_average; + } if (!p_cur->present_flag) { p_cur->present_flag = 1; change_flag |= SIG_PRI_INFO; @@ -2561,12 +2999,10 @@ int signal_type_changed(struct vframe_s *vf, struct vinfo_s *vinfo) if (cur_hdr_process_mode != hdr_process_mode) { pr_csc("HDR mode changed.\n"); change_flag |= SIG_HDR_MODE; - cur_hdr_process_mode = hdr_process_mode; } if (cur_sdr_process_mode != sdr_process_mode) { pr_csc("SDR mode changed.\n"); change_flag |= SIG_HDR_MODE; - cur_sdr_process_mode = sdr_process_mode; } if (cur_hdr_support != (vinfo->hdr_info.hdr_support & 0x4)) { pr_csc("Tx HDR support changed.\n"); @@ -2589,13 +3025,14 @@ int signal_type_changed(struct vframe_s *vf, struct vinfo_s *vinfo) enum vpp_matrix_csc_e get_csc_type(void) { enum vpp_matrix_csc_e csc_type = VPP_MATRIX_NULL; - - if (signal_color_primaries == 1) { + if ((signal_color_primaries == 1) && + (signal_transfer_characteristic < 14)) { if (signal_range == 0) csc_type = VPP_MATRIX_YUV709_RGB; else csc_type = VPP_MATRIX_YUV709F_RGB; - } else if (signal_color_primaries == 3) { + } else if ((signal_color_primaries == 3) && + (signal_transfer_characteristic < 14)) { if (signal_range == 0) csc_type = VPP_MATRIX_YUV601_RGB; else @@ -2617,9 +3054,9 @@ enum vpp_matrix_csc_e get_csc_type(void) /* bt2020-10 */ pr_csc("\tWARNING: bt2020-10 HDR!!!\n"); if (signal_range == 0) - csc_type = VPP_MATRIX_YUV709_RGB; + csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; else - csc_type = VPP_MATRIX_YUV709F_RGB; + csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; } else if (signal_transfer_characteristic == 15) { /* bt2020-12 */ pr_csc("\tWARNING: bt2020-12 HDR!!!\n"); @@ -2627,6 +3064,13 @@ enum vpp_matrix_csc_e get_csc_type(void) csc_type = VPP_MATRIX_YUV709_RGB; else csc_type = VPP_MATRIX_YUV709F_RGB; + } else if (signal_transfer_characteristic == 18) { + /* bt2020-12 */ + pr_csc("\tWARNING: HLG!!!\n"); + if (signal_range == 0) + csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; + else + csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; } else { /* unknown transfer characteristic */ pr_csc("\tWARNING: unknown HDR!!!\n"); @@ -2644,7 +3088,41 @@ enum vpp_matrix_csc_e get_csc_type(void) } return csc_type; } +/*hdr10: return 0; hlg: return 1*/ +#define HLG_FLAG 0x1 +static int get_hdr_type(void) +{ + int change_flag = 0; + if ((signal_transfer_characteristic == 18) || + (signal_transfer_characteristic == 14)) + change_flag |= HLG_FLAG; + + return change_flag; +} + +static void cal_out_curve(uint panel_luma) +{ + int index; + + if (panel_luma == 0) + return; + + if (panel_luma <= 500) { + if (panel_luma < 250) + panel_luma = 250; + index = (panel_luma - 250) / 20; + } else { + if (panel_luma > 1000) + panel_luma = 1000; + index = ((500 - 240) / 20) + (panel_luma - 500) / 100; + } + memcpy(eotf_33_2084_mapping, + eotf_33_2084_table[index], sizeof(int) * EOTF_LUT_SIZE); + memcpy(oetf_289_gamma22_mapping, + oetf_289_gamma22_table[index], + sizeof(int) * VIDEO_OETF_LUT_SIZE); +} static void mtx_dot_mul( int64_t (*a)[3], int64_t (*b)[3], int64_t (*out)[3], int32_t norm) @@ -2780,7 +3258,6 @@ static void apply_scale_factor(int64_t (*in)[3], int32_t *rs) static void N2C(int64_t (*in)[3], int32_t ibl, int32_t obl) { int i, j; - for (i = 0; i < 3; i++) for (j = 0; j < 3; j++) { in[i][j] = @@ -2797,7 +3274,6 @@ static void cal_mtx_seting( { int i, j; int32_t right_shift; - if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { apply_scale_factor(in, &right_shift); m->right_shift = right_shift; @@ -2923,6 +3399,8 @@ static int check_primaries( if ((*di)[3][i] != bt709_white_point[i]) need_calculate_mtx = 1; } + if (v->hdr_info.sink_flag) + cal_out_curve(v->hdr_info.lumi_max); } else { for (i = 0; i < 3; i++) { for (j = 0; j < 2; j++) @@ -2960,22 +3438,21 @@ enum vpp_matrix_csc_e prepare_customer_matrix( m->right_shift = customer_matrix_param[15]; return VPP_MATRIX_BT2020RGB_CUSRGB; - } - - if (inverse_flag) { - if (check_primaries(s, w, v, &prmy_src, &prmy_dst)) { - gamut_mtx(prmy_dst, prmy_src, out, INORM, BL); - cal_mtx_seting(out, BL, 13, m); - } } else { - if (check_primaries(s, w, v, &prmy_src, &prmy_dst)) { - gamut_mtx(prmy_src, prmy_dst, out, INORM, BL); - cal_mtx_seting(out, BL, 13, m); + if (inverse_flag) { + if (check_primaries(s, w, v, &prmy_src, &prmy_dst)) { + gamut_mtx(prmy_dst, prmy_src, out, INORM, BL); + cal_mtx_seting(out, BL, 13, m); + } + } else { + if (check_primaries(s, w, v, &prmy_src, &prmy_dst)) { + gamut_mtx(prmy_src, prmy_dst, out, INORM, BL); + cal_mtx_seting(out, BL, 13, m); + } } + return VPP_MATRIX_BT2020RGB_CUSRGB; } - return VPP_MATRIX_BT2020RGB_CUSRGB; - - /*return VPP_MATRIX_BT2020YUV_BT2020RGB;*/ + return VPP_MATRIX_BT2020YUV_BT2020RGB; } /* Max luminance lookup table for contrast */ @@ -3036,7 +3513,6 @@ static void amvecm_cp_hdr_info(struct master_display_info_s *hdr_data, struct vframe_master_display_colour_s *p) { int i, j; - if (customer_hdmi_display_en) { hdr_data->features = (1 << 29) /* video available */ @@ -3284,8 +3760,11 @@ static int hdr_process( vinfo, &osd_m, 1); } - if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { - /************** OSD ***************/ + /************** OSD ***************/ + /*vpp matrix mux read*/ + vpp_set_mtx_en_read(); + if ((get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + && (csc_en & 0x2)) { /* RGB to YUV */ /* not using old RGB2YUV convert HW */ /* use new 10bit OSD convert matrix */ @@ -3324,13 +3803,18 @@ static int hdr_process( set_vpp_matrix(VPP_MATRIX_OSD, RGB2020_to_YUV2020l_coeff, CSC_ON); - - /************** VIDEO **************/ + } + /************** VIDEO **************/ + if ((get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + && (csc_en & 0x4)) { /* vd1 matrix bypass */ set_vpp_matrix(VPP_MATRIX_VD1, bypass_coeff, CSC_OFF); + /*INV LUT*/ + set_vpp_lut(VPP_LUT_INV_EOTF, NULL, NULL, NULL, CSC_OFF); + /* post matrix YUV2020 to RGB2020 */ set_vpp_matrix(VPP_MATRIX_POST, YUV2020l_to_RGB2020_coeff, @@ -3366,6 +3850,7 @@ static int hdr_process( else mtx[i * 3 + j] = m.matrix[i][j]; } + set_vpp_matrix(VPP_MATRIX_EOTF, mtx, CSC_ON); @@ -3377,8 +3862,8 @@ static int hdr_process( set_vpp_matrix(VPP_MATRIX_XVYCC, RGB709_to_YUV709l_coeff, CSC_ON); - } else { - + } + if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB) { /* turn vd1 matrix on */ vpp_set_matrix(VPP_MATRIX_VD1, CSC_ON, csc_type, NULL); @@ -3400,6 +3885,223 @@ static int hdr_process( else vpp_set_matrix3(CSC_OFF, VPP_MATRIX_NULL); } + /*vpp matrix mux write*/ + vpp_set_mtx_en_write(); + return need_adjust_contrast_saturation; +} + +static int hlg_process( + enum vpp_matrix_csc_e csc_type, + struct vinfo_s *vinfo, + struct vframe_master_display_colour_s *master_info) +{ + int need_adjust_contrast_saturation = 0; + int max_lumin = 10000; + struct matrix_s m = { + {0, 0, 0}, + { + {0x0d49, 0x1b4d, 0x1f6b}, + {0x1f01, 0x0910, 0x1fef}, + {0x1fdb, 0x1f32, 0x08f3}, + }, + {0, 0, 0}, + 1 + }; + struct matrix_s osd_m = { + {0, 0, 0}, + { + {0x505, 0x2A2, 0x059}, + {0x08E, 0x75B, 0x017}, + {0x022, 0x0B4, 0x72A}, + }, + {0, 0, 0}, + 1 + }; + int mtx[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(1.6607056/2), EOTF_COEFF_NORM(-0.5877533/2), + EOTF_COEFF_NORM(-0.0729065/2), + EOTF_COEFF_NORM(-0.1245575/2), EOTF_COEFF_NORM(1.1329346/2), + EOTF_COEFF_NORM(-0.0083771/2), + EOTF_COEFF_NORM(-0.0181122/2), EOTF_COEFF_NORM(-0.1005249/2), + EOTF_COEFF_NORM(1.1186371/2), + EOTF_COEFF_RIGHTSHIFT, + }; + int osd_mtx[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(0.627441), EOTF_COEFF_NORM(0.329285), + EOTF_COEFF_NORM(0.043274), + EOTF_COEFF_NORM(0.069092), EOTF_COEFF_NORM(0.919556), + EOTF_COEFF_NORM(0.011322), + EOTF_COEFF_NORM(0.016418), EOTF_COEFF_NORM(0.088058), + EOTF_COEFF_NORM(0.895554), + EOTF_COEFF_RIGHTSHIFT + }; + int i, j; + + if (master_info->present_flag & 1) { + pr_csc("\tMaster_display_colour available.\n"); + print_primaries_info(master_info); + /* for VIDEO */ + csc_type = + prepare_customer_matrix( + &master_info->primaries, + &master_info->white_point, + vinfo, &m, 0); + /* for OSD */ + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + prepare_customer_matrix( + &master_info->primaries, + &master_info->white_point, + vinfo, &osd_m, 1); + need_adjust_contrast_saturation |= 1; + } else { + /* use bt2020 primaries */ + pr_csc("\tNo master_display_colour.\n"); + /* for VIDEO */ + csc_type = + prepare_customer_matrix( + &bt2020_primaries, + &bt2020_white_point, + vinfo, &m, 0); + /* for OSD */ + if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + prepare_customer_matrix( + &bt2020_primaries, + &bt2020_white_point, + vinfo, &osd_m, 1); + } + /*vpp matrix mux read*/ + vpp_set_mtx_en_read(); + if ((get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + && (csc_en & 0x2)) { + /************** OSD ***************/ + /* RGB to YUV */ + /* not using old RGB2YUV convert HW */ + /* use new 10bit OSD convert matrix */ + /* WRITE_VPP_REG_BITS(VIU_OSD1_BLK0_CFG_W0, */ + /* 0, 7, 1); */ + /* eotf lut 709 */ + set_vpp_lut(VPP_LUT_OSD_EOTF, + osd_eotf_33_709_mapping, /* R */ + osd_eotf_33_709_mapping, /* G */ + osd_eotf_33_709_mapping, /* B */ + CSC_ON); + + /* eotf matrix 709->2020 */ + osd_mtx[EOTF_COEFF_SIZE - 1] = osd_m.right_shift; + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + if (osd_m.matrix[i][j] & 0x1000) + osd_mtx[i * 3 + j] = + -(((~osd_m.matrix[i][j]) & 0xfff) + 1); + else + osd_mtx[i * 3 + j] = osd_m.matrix[i][j]; + } + set_vpp_matrix(VPP_MATRIX_OSD_EOTF, + osd_mtx, + CSC_ON); + + /* oetf lut 2084 */ + set_vpp_lut(VPP_LUT_OSD_OETF, + osd_oetf_41_2084_mapping, /* R */ + osd_oetf_41_2084_mapping, /* G */ + osd_oetf_41_2084_mapping, /* B */ + CSC_ON); + + /* osd matrix RGB2020 to YUV2020 limit */ + set_vpp_matrix(VPP_MATRIX_OSD, + RGB2020_to_YUV2020l_coeff, + CSC_ON); + } + /************** VIDEO **************/ + if ((get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + && (csc_en & 0x4)) { + /* vd1 matrix bypass */ + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); + + /*eo oo oe*/ + set_vpp_lut(VPP_LUT_INV_EOTF, + NULL, + NULL, + NULL, + CSC_OFF); + + /* post matrix YUV2020 to RGB2020 */ + set_vpp_matrix(VPP_MATRIX_POST, + YUV2020l_to_RGB2020_coeff, + CSC_ON); + + /* eotf lut 2048 */ + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_hlg_mapping, /* R */ + eotf_33_hlg_mapping, /* G */ + eotf_33_hlg_mapping, /* B */ + CSC_ON); + + need_adjust_contrast_saturation = 0; + saturation_offset = 0; + if (hdr_flag & 8) { + need_adjust_contrast_saturation |= 2; + saturation_offset = extra_sat_lut[0]; + } + if (master_info->present_flag & 1) { + max_lumin = master_info->luminance[0] + / 10000; + if ((max_lumin <= 1200) && (max_lumin > 0)) { + if (hdr_flag & 4) + need_adjust_contrast_saturation |= 1; + if (hdr_flag & 8) + saturation_offset = extra_sat_lut[1]; + } + } + /* eotf matrix RGB2020 to RGB709 */ + mtx[EOTF_COEFF_SIZE - 1] = m.right_shift; + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + if (m.matrix[i][j] & 0x1000) + mtx[i * 3 + j] = + -(((~m.matrix[i][j]) & 0xfff) + 1); + else + mtx[i * 3 + j] = m.matrix[i][j]; + } + + set_vpp_matrix(VPP_MATRIX_EOTF, mtx, CSC_ON); + + set_vpp_lut(VPP_LUT_OETF, + oetf_289_gamma22_mapping, + oetf_289_gamma22_mapping, + oetf_289_gamma22_mapping, + CSC_ON); + + /* xvyccc matrix3: bypass */ + if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) + set_vpp_matrix(VPP_MATRIX_XVYCC, + RGB709_to_YUV709l_coeff, + CSC_ON); + } + if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB) { + /* turn vd1 matrix on */ + vpp_set_matrix(VPP_MATRIX_VD1, CSC_ON, csc_type, NULL); + /* turn post matrix on */ + vpp_set_matrix(VPP_MATRIX_POST, CSC_ON, csc_type, &m); + /* xvycc lut on */ + load_knee_lut(CSC_ON); + + vecm_latch_flag |= FLAG_VADJ1_BRI; + hdr_process_pq_enable(0); + /* if GXTVBB HDMI output(YUV) case */ + /* xvyccc matrix3: RGB to YUV */ + /* other cases */ + /* xvyccc matrix3: bypass */ + if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) + vpp_set_matrix3(CSC_ON, VPP_MATRIX_RGB_YUV709); + else + vpp_set_matrix3(CSC_OFF, VPP_MATRIX_NULL); + } + /*vpp matrix mux write*/ + vpp_set_mtx_en_write(); return need_adjust_contrast_saturation; } @@ -3428,7 +4130,8 @@ static void bypass_hdr_process( EOTF_COEFF_RIGHTSHIFT }; int i, j; - + /*vpp matrix mux read*/ + vpp_set_mtx_en_read(); if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { /************** OSD ***************/ /* RGB to YUV */ @@ -3437,9 +4140,8 @@ static void bypass_hdr_process( /* WRITE_VPP_REG_BITS*/ /*(VIU_OSD1_BLK0_CFG_W0,0, 7, 1);*/ if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && - (((vinfo->hdr_info.hdr_support & 0x4) && - (vinfo->viu_color_fmt != COLOR_FMT_RGB444)) || - (vinfo->viu_color_fmt == COLOR_FMT_RGB444))) { + ((vinfo->hdr_info.hdr_support & 0x4) && + (vinfo->viu_color_fmt != COLOR_FMT_RGB444))) { /* OSD convert to HDR to match HDR video */ /* osd eotf lut 709 */ set_vpp_lut(VPP_LUT_OSD_EOTF, @@ -3627,11 +4329,9 @@ static void bypass_hdr_process( csc_type = VPP_MATRIX_YUV709_RGB; } /* vd1 matrix on to convert YUV to RGB */ - vpp_set_matrix(VPP_MATRIX_VD1, CSC_ON, - csc_type, NULL); + vpp_set_matrix(VPP_MATRIX_VD1, CSC_ON, csc_type, NULL); /* post matrix off */ - vpp_set_matrix(VPP_MATRIX_POST, CSC_OFF, - csc_type, NULL); + vpp_set_matrix(VPP_MATRIX_POST, CSC_OFF, csc_type, NULL); /* xvycc lut off */ load_knee_lut(CSC_OFF); /* xvycc inv lut */ @@ -3661,6 +4361,261 @@ static void bypass_hdr_process( else vpp_set_matrix3(CSC_OFF, VPP_MATRIX_NULL); } + /*vpp matrix mux write*/ + vpp_set_mtx_en_write(); +} + +static void bypass_hlg_process( + enum vpp_matrix_csc_e csc_type, + struct vinfo_s *vinfo, + struct vframe_master_display_colour_s *master_info) +{ + struct matrix_s osd_m = { + {0, 0, 0}, + { + {0x505, 0x2A2, 0x059}, + {0x08E, 0x75B, 0x017}, + {0x022, 0x0B4, 0x72A}, + }, + {0, 0, 0}, + 1 + }; + int osd_mtx[EOTF_COEFF_SIZE] = { + EOTF_COEFF_NORM(0.627441), EOTF_COEFF_NORM(0.329285), + EOTF_COEFF_NORM(0.043274), + EOTF_COEFF_NORM(0.069092), EOTF_COEFF_NORM(0.919556), + EOTF_COEFF_NORM(0.011322), + EOTF_COEFF_NORM(0.016418), EOTF_COEFF_NORM(0.088058), + EOTF_COEFF_NORM(0.895554), + EOTF_COEFF_RIGHTSHIFT + }; + int i, j; + + /*vpp matrix mux read*/ + vpp_set_mtx_en_read(); + if ((get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + && (csc_en & 0x2)) { + /************** OSD ***************/ + /* RGB to YUV */ + /* not using old RGB2YUV convert HW */ + /* use new 10bit OSD convert matrix */ + /* WRITE_VPP_REG_BITS(VIU_OSD1_BLK0_CFG_W0, */ + /* 0, 7, 1); */ + if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + ((vinfo->hdr_info.hdr_support & 0x4) && + (vinfo->viu_color_fmt != COLOR_FMT_RGB444))) { + /* OSD convert to HDR to match HDR video */ + /* osd eotf lut 709 */ + set_vpp_lut(VPP_LUT_OSD_EOTF, + osd_eotf_33_709_mapping, /* R */ + osd_eotf_33_709_mapping, /* G */ + osd_eotf_33_709_mapping, /* B */ + CSC_ON); + + /* osd eotf matrix 709->2020 */ + if (master_info->present_flag & 1) { + pr_csc("\tMaster_display_colour available.\n"); + print_primaries_info(master_info); + prepare_customer_matrix( + &master_info->primaries, + &master_info->white_point, + vinfo, &osd_m, 1); + } else { + pr_csc("\tNo master_display_colour.\n"); + prepare_customer_matrix( + &bt2020_primaries, + &bt2020_white_point, + vinfo, &osd_m, 1); + } + osd_mtx[EOTF_COEFF_SIZE - 1] = osd_m.right_shift; + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) { + if (osd_m.matrix[i][j] & 0x1000) { + osd_mtx[i * 3 + j] = + (~osd_m.matrix[i][j]) & 0xfff; + osd_mtx[i * 3 + j] = + -(1 + osd_mtx[i * 3 + j]); + } else + osd_mtx[i * 3 + j] = + osd_m.matrix[i][j]; + } + set_vpp_matrix(VPP_MATRIX_OSD_EOTF, osd_mtx, CSC_ON); + + /* osd oetf lut 2084 */ + set_vpp_lut(VPP_LUT_OSD_OETF, + osd_oetf_41_2084_mapping, /* R */ + osd_oetf_41_2084_mapping, /* G */ + osd_oetf_41_2084_mapping, /* B */ + CSC_ON); + + /* osd matrix RGB2020 to YUV2020 limit */ + set_vpp_matrix(VPP_MATRIX_OSD, + RGB2020_to_YUV2020l_coeff, + CSC_ON); + } else { + /* OSD convert to 709 limited to match SDR video */ + /* eotf lut bypass */ + set_vpp_lut(VPP_LUT_OSD_EOTF, + eotf_33_linear_mapping, /* R */ + eotf_33_linear_mapping, /* G */ + eotf_33_linear_mapping, /* B */ + CSC_OFF); + + /* eotf matrix bypass */ + set_vpp_matrix(VPP_MATRIX_OSD_EOTF, + eotf_bypass_coeff, + CSC_OFF); + + /* oetf lut bypass */ + set_vpp_lut(VPP_LUT_OSD_OETF, + oetf_41_linear_mapping, /* R */ + oetf_41_linear_mapping, /* G */ + oetf_41_linear_mapping, /* B */ + CSC_OFF); + + /* osd matrix RGB709 to YUV709 limit/full */ + if (range_control) + set_vpp_matrix(VPP_MATRIX_OSD, + RGB709_to_YUV709_coeff, + CSC_ON); /* use full range */ + else + set_vpp_matrix(VPP_MATRIX_OSD, + RGB709_to_YUV709l_coeff, + CSC_ON); /* use limit range */ + } + } + /************** VIDEO **************/ + if ((get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) + && (csc_en & 0x4)) { + /* vd1 matrix: bypass */ + if (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); /* limit->limit range */ + else { + if (range_control) { + if (signal_range == 0) /* limit range */ + set_vpp_matrix(VPP_MATRIX_VD1, + YUV709l_to_YUV709f_coeff, + CSC_ON); + /* limit->full range */ + else + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); + /* full->full range */ + } else { + if (signal_range == 0) /* limit range */ + set_vpp_matrix(VPP_MATRIX_VD1, + bypass_coeff, + CSC_OFF); + /* limit->limit range */ + else + set_vpp_matrix(VPP_MATRIX_VD1, + YUV709f_to_YUV709l_coeff, + CSC_ON); + /* full->limit range */ + } + } + /*eo oo oe*/ + int_lut_sel[0] |= INVLUT_HLG; + set_vpp_lut(VPP_LUT_INV_EOTF, + int_lut_sel, + int_lut_sel, + int_lut_sel, + CSC_ON); + + /* post matrix bypass */ + if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) + /* yuv2rgb for eye protect mode */ + set_vpp_matrix(VPP_MATRIX_POST, + YUV2020l_to_RGB2020_coeff, + CSC_ON); + else /* matrix yuv2rgb for LCD */ + set_vpp_matrix(VPP_MATRIX_POST, + YUV709l_to_RGB709_coeff, + CSC_ON); + + /* eotf lut bypass */ + set_vpp_lut(VPP_LUT_EOTF, + eotf_33_hlg_mapping, /* R */ + eotf_33_hlg_mapping, /* G */ + eotf_33_hlg_mapping, /* B */ + CSC_ON); + + /* eotf matrix bypass */ + set_vpp_matrix(VPP_MATRIX_EOTF, + eotf_bypass_coeff, + CSC_ON); + + /* oetf lut bypass */ + set_vpp_lut(VPP_LUT_OETF, + oetf_289_2084_mapping, + oetf_289_2084_mapping, + oetf_289_2084_mapping, + CSC_ON); + + /* xvycc matrix full2limit or bypass */ + if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) { + if (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) + set_vpp_matrix(VPP_MATRIX_XVYCC, + RGB2020_to_YUV2020l_coeff, + CSC_ON); + else { + if (range_control) + set_vpp_matrix(VPP_MATRIX_XVYCC, + YUV709f_to_YUV709l_coeff, + CSC_ON); + else + set_vpp_matrix(VPP_MATRIX_XVYCC, + bypass_coeff, + CSC_OFF); + } + } + } else { + /* OSD */ + /* keep RGB */ + + /* VIDEO */ + if (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) { + /* vd1 matrix: convert YUV to RGB */ + csc_type = VPP_MATRIX_YUV709_RGB; + } + /* vd1 matrix on to convert YUV to RGB */ + vpp_set_matrix(VPP_MATRIX_VD1, CSC_ON, csc_type, NULL); + /* post matrix off */ + vpp_set_matrix(VPP_MATRIX_POST, CSC_OFF, csc_type, NULL); + /* xvycc lut off */ + load_knee_lut(CSC_OFF); + /* xvycc inv lut */ + + if (sdr_process_mode) + set_vpp_lut(VPP_LUT_INV_EOTF, + NULL, + NULL, + NULL, + CSC_ON); + else + set_vpp_lut(VPP_LUT_INV_EOTF, + NULL, + NULL, + NULL, + CSC_OFF); + + vecm_latch_flag |= FLAG_VADJ1_BRI; + hdr_process_pq_enable(1); + /* if GXTVBB HDMI output(YUV) case */ + /* xvyccc matrix3: RGB to YUV */ + /* other cases */ + /* xvyccc matrix3: bypass */ + if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) + vpp_set_matrix3(CSC_ON, VPP_MATRIX_RGB_YUV709); + else + vpp_set_matrix3(CSC_OFF, VPP_MATRIX_NULL); + } + /*vpp matrix mux write*/ + vpp_set_mtx_en_write(); } static void sdr_hdr_process( @@ -3670,6 +4625,8 @@ static void sdr_hdr_process( { if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM)) { + /*vpp matrix mux read*/ + vpp_set_mtx_en_read(); /* OSD convert to 709 limited to match SDR video */ /* eotf lut bypass */ set_vpp_lut(VPP_LUT_OSD_EOTF, @@ -3749,6 +4706,8 @@ static void sdr_hdr_process( set_vpp_matrix(VPP_MATRIX_XVYCC, RGB2020_to_YUV2020l_coeff, CSC_ON); + /*vpp matrix mux write*/ + vpp_set_mtx_en_write(); } else if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) || (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL)) { bypass_hdr_process(csc_type, vinfo, master_info); @@ -3763,7 +4722,7 @@ static int vpp_eye_protection_process( memcpy(&video_rgb_ogo, wb_val, sizeof(struct tcon_rgb_ogo_s)); ve_ogo_param_update(); - + vpp_set_mtx_en_read(); /* only SDR need switch csc */ if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && hdr_process_mode) @@ -3794,16 +4753,19 @@ static int vpp_eye_protection_process( bypass_coeff, CSC_ON); + vpp_set_mtx_en_write(); return 0; } -static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) +static int vpp_matrix_update( + struct vframe_s *vf, struct vinfo_s *vinfo, int flags) { enum vpp_matrix_csc_e csc_type = VPP_MATRIX_NULL; int signal_change_flag = 0; struct vframe_master_display_colour_s *p = &cur_master_display_colour; struct master_display_info_s send_info; int need_adjust_contrast_saturation = 0; + int hdmi_scs_type_changed = 0; /* Tx hdr information */ memcpy(&receiver_hdr_info, &vinfo->hdr_info, @@ -3832,12 +4794,8 @@ static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) } else sdr_process_mode = sdr_mode; /* force sdr->hdr */ - signal_change_flag = signal_type_changed(vf, vinfo); - - if ((!signal_change_flag) && (force_csc_type == 0xff)) - return; - - vecm_latch_flag |= FLAG_MATRIX_UPDATE; + if (vf && vinfo) + signal_change_flag = signal_type_changed(vf, vinfo); if (force_csc_type != 0xff) csc_type = force_csc_type; @@ -3845,7 +4803,8 @@ static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) csc_type = get_csc_type(); if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && - (vinfo->hdr_info.hdr_support & 0x4)) { + ((vinfo->hdr_info.hdr_support & 0x4) || + (signal_change_flag & SIG_HDR_SUPPORT))) { if (sdr_process_mode && (csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB)) { /* sdr source convert to hdr */ @@ -3857,8 +4816,15 @@ static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) | (0 << 25) /* limit */ | (1 << 24) /* color available */ | (9 << 16) /* bt2020 */ - | (14 << 8) /* bt2020-10 */ + | (16 << 8) /* bt2020-10 */ | (10 << 0); /* bt2020c */ + amvecm_cp_hdr_info(&send_info, p); + if (vinfo->fresh_tx_hdr_pkt) + vinfo->fresh_tx_hdr_pkt(&send_info); + if (hdmi_csc_type != VPP_MATRIX_BT2020YUV_BT2020RGB) { + hdmi_csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; + hdmi_scs_type_changed = 1; + } } else if ((hdr_process_mode == 0) && (csc_type >= VPP_MATRIX_BT2020YUV_BT2020RGB)) { /* source is hdr, send hdr info */ @@ -3868,9 +4834,18 @@ static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) | (5 << 26) /* unspecified */ | (0 << 25) /* limit */ | (1 << 24) /* color available */ - | (9 << 16) /* bt2020 */ - | (14 << 8) /* bt2020-10 */ + /* bt2020 */ + | (signal_color_primaries << 16) + /* bt2020-10 */ + | (signal_transfer_characteristic << 8) | (10 << 0); /* bt2020c */ + amvecm_cp_hdr_info(&send_info, p); + if (vinfo->fresh_tx_hdr_pkt) + vinfo->fresh_tx_hdr_pkt(&send_info); + if (hdmi_csc_type != VPP_MATRIX_BT2020YUV_BT2020RGB) { + hdmi_csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; + hdmi_scs_type_changed = 1; + } } else { /* sdr source send normal info*/ /* use the features to discribe source info */ @@ -3878,20 +4853,35 @@ static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) /* default 709 full */ (1 << 29) /* video available */ | (5 << 26) /* unspecified */ - | (1 << 25) /* full */ + | (0 << 25) /* full */ | (1 << 24) /* color available */ | (1 << 16) /* bt709 */ | (1 << 8) /* bt709 */ | (1 << 0); /* bt709 */ + if (vinfo->fresh_tx_hdr_pkt) + vinfo->fresh_tx_hdr_pkt(&send_info); + if (hdmi_csc_type != VPP_MATRIX_YUV709_RGB) { + hdmi_csc_type = VPP_MATRIX_YUV709_RGB; + hdmi_scs_type_changed = 1; + } } - amvecm_cp_hdr_info(&send_info, p); - if (vinfo->fresh_tx_hdr_pkt) - vinfo->fresh_tx_hdr_pkt(&send_info); } + if (hdmi_scs_type_changed && + (flags & CSC_FLAG_CHECK_OUTPUT) && + csc_en & 0x10) + return 1; + + if (((!signal_change_flag) && (force_csc_type == 0xff)) + && ((flags & CSC_FLAG_TOGGLE_FRAME) == 0)) + return 0; + + vecm_latch_flag |= FLAG_MATRIX_UPDATE; + if ((cur_csc_type != csc_type) - || (signal_change_flag - & (SIG_PRI_INFO | SIG_KNEE_FACTOR | SIG_HDR_MODE))) { + || (signal_change_flag + & (SIG_PRI_INFO | SIG_KNEE_FACTOR | SIG_HDR_MODE | + SIG_HDR_SUPPORT))) { /* decided by edid or panel info or user setting */ if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && hdr_process_mode) { @@ -3899,25 +4889,42 @@ static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) if ((signal_change_flag & (SIG_PRI_INFO | SIG_KNEE_FACTOR | - SIG_HDR_MODE) + SIG_HDR_MODE | + SIG_HDR_SUPPORT) ) || (cur_csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB)) { - need_adjust_contrast_saturation = - hdr_process(csc_type, vinfo, p); + if (get_hdr_type() & HLG_FLAG) + need_adjust_contrast_saturation = + hlg_process(csc_type, vinfo, p); + else + need_adjust_contrast_saturation = + hdr_process(csc_type, vinfo, p); } } else { if ((csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB) && sdr_process_mode) /* for gxl and gxm SDR to HDR process */ sdr_hdr_process(csc_type, vinfo, p); - else + else { /* for gxtvbb and gxl HDR bypass process */ - bypass_hdr_process(csc_type, vinfo, p); - - if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && - (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB)) - csc_type = VPP_MATRIX_YUV709_RGB; + if ((get_hdr_type() & HLG_FLAG) && + (vinfo->viu_color_fmt != + COLOR_FMT_RGB444)) + bypass_hlg_process(csc_type, vinfo, p); + else + bypass_hdr_process(csc_type, vinfo, p); + } + } + if (cur_hdr_process_mode != hdr_process_mode) { + cur_hdr_process_mode = hdr_process_mode; + pr_csc("hdr_process_mode changed to %d", + hdr_process_mode); + } + if (cur_sdr_process_mode != sdr_process_mode) { + cur_sdr_process_mode = sdr_process_mode; + pr_csc("sdr_process_mode changed to %d", + sdr_process_mode); } if (need_adjust_contrast_saturation & 1) { if (lut_289_en && @@ -3950,6 +4957,13 @@ static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) pr_csc("saturation offset = %d.\n", saturation_offset); cur_csc_type = csc_type; + + if ((cur_csc_type >= VPP_MATRIX_BT2020YUV_BT2020RGB) && + (cur_csc_type != 0xffff) && + (vf->source_type == VFRAME_SOURCE_TYPE_HDMI)) { + amvecm_wakeup_queue(); + pr_csc("wake up hdr status queue.\n"); + } } } @@ -3958,25 +4972,29 @@ static void vpp_matrix_update(struct vframe_s *vf, struct vinfo_s *vinfo) vpp_eye_protection_process(csc_type, vinfo); vecm_latch_flag &= ~FLAG_MATRIX_UPDATE; + return 0; } static struct vframe_s *last_vf; +static int last_vf_signal_type; static int null_vf_cnt; +static int prev_hdr_support; static unsigned int fg_vf_sw_dbg; -unsigned int null_vf_max = 5; +unsigned int null_vf_max = 1; module_param(null_vf_max, uint, 0664); MODULE_PARM_DESC(null_vf_max, "\n null_vf_max\n"); -void amvecm_matrix_process(struct vframe_s *vf) +int amvecm_matrix_process( + struct vframe_s *vf, struct vframe_s *vf_rpt, int flags) { struct vframe_s fake_vframe; struct vinfo_s *vinfo = get_current_vinfo(); + int toggle_frame; int i; if ((get_cpu_type() < MESON_CPU_MAJOR_ID_GXTVBB) || - is_meson_gxl_package_905M2() || - skip_csc_en) - return; + is_meson_gxl_package_905M2() || (csc_en == 0)) + return 0; if (reload_mtx) { for (i = 0; i < NUM_MATRIX; i++) @@ -3994,62 +5012,88 @@ void amvecm_matrix_process(struct vframe_s *vf) CSC_ON); } - /* OSD sdr -> hdr in first vsync when hdr output */ - if ((vinfo->hdr_info.hdr_support & 0x4) && (vf == NULL) && - ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || - (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM))) { - if (((sdr_process_mode != 1) && (sdr_mode > 0)) - || ((sdr_process_mode > 0) && (sdr_mode == 0))) - null_vf_cnt = null_vf_max + 1; - } - - if ((vf == last_vf) && (null_vf_cnt <= null_vf_max) && - (cur_eye_protect_mode == wb_val[0])) - return; - if (is_dolby_vision_on()) - return; + return 0; + if (flags & CSC_FLAG_CHECK_OUTPUT) { + if (vpp_matrix_update(vf, vinfo, flags) == 1) { + pr_csc("hdr/sdr output changing ...\n"); + return 1; + } + } if (vf != NULL) { - vpp_matrix_update(vf, vinfo); + if (debug_csc & 2) + pr_csc("new frame %x%s\n", + vf->signal_type, + get_video_enabled() ? " " : ", video off"); + vpp_matrix_update(vf, vinfo, flags); last_vf = vf; + last_vf_signal_type = vf->signal_type; null_vf_cnt = 0; fg_vf_sw_dbg = 1; - /* debug vframe info backup */ dbg_vf = vf; + } else if (vf_rpt != NULL) { + if (debug_csc & 2) + pr_csc("rpt frame\n"); + null_vf_cnt = 0; + fg_vf_sw_dbg = 2; + } else if (get_video_enabled() && (last_vf != NULL)) { + if (debug_csc & 2) + pr_csc("rpt frame local\n"); + null_vf_cnt = 0; + fg_vf_sw_dbg = 3; } else { - /* check last signal type */ - if ((last_vf != NULL) && - ((((last_vf->signal_type >> 16) & 0xff) == 9) - || customer_master_display_en)) - null_vf_cnt++; - - if ((((READ_VPP_REG(VPP_MISC) & (1<<10)) == 0) - && (null_vf_cnt > null_vf_max)) || - (cur_eye_protect_mode != wb_val[0])) { - /* send a faked vframe to switch matrix*/ - /* from 2020 to 601 when video disabled */ + /* handle change between TV support/not support HDR */ + if (prev_hdr_support != vinfo->hdr_info.hdr_support) { + null_vf_cnt = 0; + prev_hdr_support = vinfo->hdr_info.hdr_support; + } + /* handle eye protect mode */ + if (cur_eye_protect_mode != wb_val[0]) + null_vf_cnt = 0; + if (csc_en & 0x10) + toggle_frame = null_vf_max; + else + toggle_frame = 0; + /* when sdr mode change */ + if ((vinfo->hdr_info.hdr_support & 0x4) && + ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM))) + if (((sdr_process_mode != 1) && (sdr_mode > 0)) + || ((sdr_process_mode > 0) && (sdr_mode == 0))) + null_vf_cnt = toggle_frame; + if ((null_vf_cnt == 0) || (null_vf_cnt == toggle_frame)) { + pr_csc("Fake SDR frame\n"); + /*send a faked vframe to switch matrix*/ + /*from 2020 to 601 when video disabled */ fake_vframe.source_type = VFRAME_SOURCE_TYPE_OTHERS; fake_vframe.signal_type = 0; - fake_vframe.width = 720; - fake_vframe.height = 480; + fake_vframe.width = 1920; + fake_vframe.height = 1080; fake_vframe.prop.master_display_colour.present_flag = 0x80000000; - vpp_matrix_update(&fake_vframe, vinfo); - pr_csc("change CSC when disable video.\n"); - last_vf = vf; - null_vf_cnt = 0; - fg_vf_sw_dbg = 2; - } else - fg_vf_sw_dbg = 3; + if (null_vf_cnt == toggle_frame) + vpp_matrix_update( + &fake_vframe, vinfo, + CSC_FLAG_TOGGLE_FRAME); + else if (null_vf_cnt == 0) + vpp_matrix_update( + &fake_vframe, vinfo, + CSC_FLAG_CHECK_OUTPUT); + last_vf = NULL; + fg_vf_sw_dbg = 4; + } + if (null_vf_cnt <= null_vf_max) + null_vf_cnt++; } + return 0; } int amvecm_hdr_dbg(u32 sel) { int i, j; - + struct vframe_content_light_level_s *content_light_level; /* select debug information */ if (sel == 1) /* dump reg */ goto reg_dump; @@ -4148,6 +5192,13 @@ int amvecm_hdr_dbg(u32 sel) pr_err("\tmax,min luminance = %08x, %08x\n", dbg_vf->prop.master_display_colour.luminance[0], dbg_vf->prop.master_display_colour.luminance[1]); + content_light_level = + &dbg_vf->prop.master_display_colour.content_light_level; + pr_err("\tcontent_light_level.present_flag = %08x\n", + content_light_level->present_flag); + pr_err("\tmax_content,min max_pic_average = %08x, %08x\n", + content_light_level->max_content, + content_light_level->max_pic_average); } hdr_dump: diff --git a/drivers/amlogic/media/enhancement/amvecm/amcsc.h b/drivers/amlogic/media/enhancement/amvecm/amcsc.h index e396ba8e628f..56d36a0986d7 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amcsc.h +++ b/drivers/amlogic/media/enhancement/amvecm/amcsc.h @@ -94,6 +94,20 @@ struct matrix_s { u16 right_shift; }; +enum mtx_en_e { + POST_MTX_EN = 0, + VD2_MTX_EN = 4, + VD1_MTX_EN, + XVY_MTX_EN, + OSD1_MTX_EN +}; + +#define POST_MTX_EN_MASK (1 << POST_MTX_EN) +#define VD2_MTX_EN_MASK (1 << VD2_MTX_EN) +#define VD1_MTX_EN_MASK (1 << VD1_MTX_EN) +#define XVY_MTX_EN_MASK (1 << XVY_MTX_EN) +#define OSD1_MTX_EN_MASK (1 << OSD1_MTX_EN) + #define LUT_289_SIZE 289 extern unsigned int lut_289_mapping[LUT_289_SIZE]; extern int dnlp_en; @@ -106,7 +120,8 @@ extern uint sdr_mode; extern uint hdr_flag; extern int video_rgb_ogo_xvy_mtx_latch; -extern void amvecm_matrix_process(struct vframe_s *vf); +extern int amvecm_matrix_process( + struct vframe_s *vf, struct vframe_s *vf_rpt, int flags); extern int amvecm_hdr_dbg(u32 sel); #ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA #define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val) @@ -119,5 +134,7 @@ extern u32 VSYNC_RD_MPEG_REG(u32 adr); extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); #endif +extern u32 get_video_enabled(void); + #endif /* AM_CSC_H */ diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.c b/drivers/amlogic/media/enhancement/amvecm/amve.c index 784fa9e520dd..397a4d6cf5ca 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amve.c +++ b/drivers/amlogic/media/enhancement/amvecm/amve.c @@ -19,6 +19,7 @@ #include #include #include +#include /* #include */ #include #include @@ -55,7 +56,7 @@ unsigned long flags; #define NEW_DNLP_IN_SHARPNESS 2 #define NEW_DNLP_IN_VPP 1 -unsigned int dnlp_sel = NEW_DNLP_IN_VPP; +unsigned int dnlp_sel = NEW_DNLP_IN_SHARPNESS; module_param(dnlp_sel, int, 0664); MODULE_PARM_DESC(dnlp_sel, "dnlp_sel"); /* #endif */ @@ -147,6 +148,42 @@ MODULE_PARM_DESC(ve_dnlp_ankle, "ve_dnlp_ankle"); module_param(ve_dnlp_strength, int, 0664); MODULE_PARM_DESC(ve_dnlp_strength, "ve_dnlp_strength"); +/*static int debug_add_curve_en;*/ +int glb_scurve[65]; +int glb_clash_curve[65]; +/*static int glb_scurve_bld_rate;*/ +/*static int glb_clash_curve_bld_rate;*/ +int glb_pst_gamma[65]; +/*static int glb_pst_gamma_bld_rate;*/ + +static int debug_add_curve_en; +module_param(debug_add_curve_en, int, 0664); +MODULE_PARM_DESC(debug_add_curve_en, "debug_add_curve_en"); + +static int ve_usr_defined_test_s_mode; +module_param(ve_usr_defined_test_s_mode, int, 0664); +MODULE_PARM_DESC(ve_usr_defined_test_s_mode, "ve_usr_defined_test_s_mode"); + +static int ve_usr_defined_test_c_mode; +module_param(ve_usr_defined_test_c_mode, int, 0664); +MODULE_PARM_DESC(ve_usr_defined_test_c_mode, "ve_usr_defined_test_c_mode"); + +static int ve_usr_defined_test_g_mode; +module_param(ve_usr_defined_test_g_mode, int, 0664); +MODULE_PARM_DESC(ve_usr_defined_test_g_mode, "ve_usr_defined_test_g_mode"); + +static int glb_scurve_bld_rate; +module_param(glb_scurve_bld_rate, int, 0664); +MODULE_PARM_DESC(glb_scurve_bld_rate, "glb_scurve_bld_rate"); + +static int glb_clash_curve_bld_rate; +module_param(glb_clash_curve_bld_rate, int, 0664); +MODULE_PARM_DESC(glb_clash_curve_bld_rate, "glb_clash_curve_bld_rate"); + +static int glb_pst_gamma_bld_rate; +module_param(glb_pst_gamma_bld_rate, int, 0664); +MODULE_PARM_DESC(glb_pst_gamma_bld_rate, "glb_pst_gamma_bld_rate"); + static int dnlp_respond; module_param(dnlp_respond, int, 0664); MODULE_PARM_DESC(dnlp_respond, "dnlp_respond"); @@ -209,7 +246,7 @@ module_param(video_rgb_ogo_mode_sw, int, 0664); MODULE_PARM_DESC(video_rgb_ogo_mode_sw, "enable/disable video_rgb_ogo_mode_sw"); -static int video_rgb_ogo_xvy_mtx = 1; +int video_rgb_ogo_xvy_mtx; module_param(video_rgb_ogo_xvy_mtx, int, 0664); MODULE_PARM_DESC(video_rgb_ogo_xvy_mtx, "enable/disable video_rgb_ogo_xvy_mtx"); @@ -680,22 +717,15 @@ static unsigned int assist_cnt;/* ASSIST_SPARE8_REG1; */ static unsigned int assist_cnt2;/* ASSIST_SPARE8_REG2; */ /* video lock */ -#define VLOCK_MODE_ENC 0 -#define VLOCK_MODE_PLL 1 -#define VLOCK_MODE_MANUAL_PLL 2 -#define XTAL_VLOCK_CLOCK 24000000/*vlock use xtal clock*/ - /* 0:enc;1:pll;2:manual pll */ -static unsigned int vlock_mode = VLOCK_MODE_MANUAL_PLL; -static unsigned int vlock_en = 1; +unsigned int vlock_mode = VLOCK_MODE_MANUAL_PLL; +unsigned int vlock_en = 1; /*0:only support 50->50;60->60;24->24;30->30;*/ /*1:support 24/30/50/60/100/120 mix,such as 50->60;*/ static unsigned int vlock_adapt; static unsigned int vlock_dis_cnt_limit = 2; -/*4k@60hz test case: delta 200 is close to 500K*/ -static unsigned int vlock_delta_limit_frac = 100; -static unsigned int vlock_delta_limit_m; +static unsigned int vlock_delta_limit = 2; /*vlock_debug:bit0:disable info;bit1:format change info;bit2:force reset*/ static unsigned int vlock_debug; static unsigned int vlock_dynamic_adjust = 1; @@ -714,10 +744,39 @@ static char pre_vout_mode[64]; static bool vlock_vmode_changed; static unsigned int pre_hiu_reg_m; static unsigned int pre_hiu_reg_frac; -static unsigned int vlock_dis_cnt_step1; -static unsigned int vlock_dis_cnt_step1_limit = 300; -static unsigned int vlock_en_cnt_step1_limit = 300; +static unsigned int vlock_dis_cnt_no_vf; +static unsigned int vlock_dis_cnt_no_vf_limit = 5; +static unsigned int vlock_log_cnt;/*cnt base: vlock_log_s*/ +static unsigned int vlock_log_size = 60;/*size base: vlock_log_s*/ +static unsigned int vlock_log_delta_frac = 100; +static unsigned int vlock_log_delta_ivcnt = 0xff; +static unsigned int vlock_log_delta_ovcnt = 0xff; +static unsigned int vlock_log_delta_vcnt = 0xff; +static unsigned int vlock_log_last_ivcnt; +static unsigned int vlock_log_last_ovcnt; +static unsigned int vlock_log_delta_m; +static unsigned int vlock_log_delta_en; +module_param(vlock_log_size, uint, 0664); +MODULE_PARM_DESC(vlock_log_size, "\n vlock_log_size\n"); +module_param(vlock_log_cnt, uint, 0664); +MODULE_PARM_DESC(vlock_log_cnt, "\n vlock_log_cnt\n"); +module_param(vlock_log_delta_frac, uint, 0664); +MODULE_PARM_DESC(vlock_log_delta_frac, "\n vlock_log_delta_frac\n"); +module_param(vlock_log_delta_m, uint, 0664); +MODULE_PARM_DESC(vlock_log_delta_m, "\n vlock_log_delta_m\n"); +module_param(vlock_log_delta_en, uint, 0664); +MODULE_PARM_DESC(vlock_log_delta_en, "\n vlock_log_delta_en\n"); + +module_param(vlock_log_delta_ivcnt, uint, 0664); +MODULE_PARM_DESC(vlock_log_delta_ivcnt, "\n vlock_log_delta_ivcnt\n"); + +module_param(vlock_log_delta_ovcnt, uint, 0664); +MODULE_PARM_DESC(vlock_log_delta_ovcnt, "\n vlock_log_delta_ovcnt\n"); + +module_param(vlock_log_delta_vcnt, uint, 0664); +MODULE_PARM_DESC(vlock_log_delta_vcnt, "\n vlock_log_delta_vcnt\n"); +static unsigned int vlock_log_en; /* 3d sync parts begin */ unsigned int sync_3d_h_start; unsigned int sync_3d_h_end; @@ -1730,10 +1789,19 @@ void clash_fun(unsigned int *oMap, unsigned int *iHst, oMap[i+1] = j + (hstBgn << 4); } + if (debug_add_curve_en) { + for (i = 0; i < 65; i++) { + oMap[i] = ((128 - glb_clash_curve_bld_rate) * oMap[i] + + glb_clash_curve_bld_rate * (glb_clash_curve[i] << 2) + + 64) >> 7; + } + } + + if (prt_flg) for (i = hstBgn; i < hstEnd; i++) pr_info("#CL: [%02d: %5d]: %4d => %4d]\n", - i, iHst[i], i<<4, oMap[i]); + i, iHst[i], i << 4, oMap[i]); } /*xhu*/ @@ -2257,6 +2325,11 @@ static void dnlp_gmma_cuvs(unsigned int gmma_rate, nTmp = (nTmp*(64 - hgh_alpha) + (hgh_alpha*i<<4) + 8)>>4; + if (debug_add_curve_en) { + nTmp = ((128 - glb_scurve_bld_rate) * nTmp + + glb_scurve_bld_rate * (glb_scurve[i] << 4) + 64) >> 7; + } + if (nTmp < 0) nTmp = 0; else if (nTmp > 4095) @@ -2340,6 +2413,13 @@ static void dnlp_blkgma_bld(unsigned int *blk_gma_rat) nTmp0 = (nTmp0+32)>>6; /* 0~1024 */ blk_gma_bld[i] = nTmp0; + if (debug_add_curve_en) { + blk_gma_bld[i] = + ((128 - glb_pst_gamma_bld_rate) * blk_gma_bld[i] + + glb_pst_gamma_bld_rate * + (glb_pst_gamma[i] << 2) + 64) >> 7; + } + if ((dnlp_printk >> 2) & 0x1) pr_info("sc%04d, gm%04d * rat%04d => %04d\n", clsh_scvbld[i], blk_gma_crv[i], nT1, nTmp0); @@ -3349,6 +3429,7 @@ static void ve_dnlp_calculate_tgtx_new(struct vframe_s *vf) /* print debug log once */ if (ve_dnlp_ponce == 1 && dnlp_printk) dnlp_printk = 0; + } static void ve_dnlp_calculate_tgt(struct vframe_s *vf) @@ -3660,7 +3741,7 @@ void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask) spin_unlock_irqrestore(&vpp_lcd_gamma_lock, flags); } -void init_write_gamma_table(u16 *data, u32 rgb_mask) +void amve_write_gamma_table(u16 *data, u32 rgb_mask) { int i; int cnt = 0; @@ -4544,14 +4625,20 @@ static unsigned int vlock_check_output_hz(unsigned int sync_duration_num) } static void vlock_enable(bool enable) { - if (is_meson_gxtvbb_cpu() || - is_meson_gxbb_cpu() || is_meson_txl_cpu()) { - if (vlock_mode == VLOCK_MODE_MANUAL_PLL) + unsigned int tmp_value; + + amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &tmp_value); + if (is_meson_gxtvbb_cpu()) { + if (vlock_mode == VLOCK_MODE_MANUAL_PLL) { amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, 0, 20, 1); - else + if (is_meson_gxtvbb_cpu() && + (((tmp_value >> 21) & 0x3) != 2)) + amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, + 2, 21, 2); + } else amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, enable, 20, 1); - } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + } else if (is_meson_txl_cpu() || is_meson_txlx_cpu()) { if (vlock_mode == VLOCK_MODE_MANUAL_PLL) amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL5, 0, 3, 1); else @@ -4582,10 +4669,11 @@ static void vlock_setting(struct vframe_s *vf, /*clear accum0 value*/ WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 5, 1); } - if ((vlock_mode == VLOCK_MODE_PLL) || + if ((vlock_mode == VLOCK_MODE_AUTO_PLL) || (vlock_mode == VLOCK_MODE_MANUAL_PLL)) { /* av pal in,1080p60 hdmi out as default */ - am_set_regmap(&vlock_pll_in50hz_out60hz); + if ((vlock_debug & 0x1000) == 0) + am_set_regmap(&vlock_pll_in50hz_out60hz); /*set input & output freq*/ /*bit0~7:input freq*/ /*bit8~15:output freq*/ @@ -4604,7 +4692,7 @@ static void vlock_setting(struct vframe_s *vf, amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &hiu_reg_value); amvecm_hiu_reg_read(hiu_reg_value_2_addr, &hiu_reg_value_2); - if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) { + if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) { hiu_m_val = hiu_reg_value & 0x1FF; hiu_frac_val = hiu_reg_value_2 & 0x3FF; if (hiu_reg_value_2 & 0x800) { @@ -4701,7 +4789,7 @@ static void vlock_disable_step1(void) amvecm_hiu_reg_read(hiu_reg_addr, &tmp_value); m_reg_value = tmp_value & 0xfff; if ((m_reg_value != pre_hiu_reg_frac) && - (pre_hiu_reg_frac != 0)) { + (pre_hiu_reg_m != 0)) { tmp_value = (tmp_value & 0xfffff000) | (pre_hiu_reg_frac & 0xfff); amvecm_hiu_reg_write(hiu_reg_addr, tmp_value); @@ -4715,6 +4803,7 @@ static void vlock_disable_step1(void) amvecm_hiu_reg_write(HHI_HDMI_PLL_CNTL, tmp_value); } vlock_dis_cnt = vlock_dis_cnt_limit; + memset(pre_vout_mode, 0, sizeof(pre_vout_mode)); pre_vmode = VMODE_INIT_NULL; pre_source_type = VFRAME_SOURCE_TYPE_OTHERS; pre_source_mode = VFRAME_SOURCE_MODE_OTHERS; @@ -4725,6 +4814,7 @@ static void vlock_disable_step1(void) static void vlock_disable_step2(void) { + unsigned int temp_val; /* need delay to disable follow regs(vlsi suggest!!!) */ if (vlock_dis_cnt > 0) vlock_dis_cnt--; @@ -4739,6 +4829,9 @@ static void vlock_disable_step2(void) /* disable vid_lock_en */ WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 31, 1); vlock_state = VLOCK_STATE_DISABLE_STEP2_DONE; + amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &temp_val); + if (is_meson_gxtvbb_cpu() && (((temp_val >> 21) & 0x3) != 0)) + amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, 0, 21, 2); } } static void vlock_enable_step1(struct vframe_s *vf, struct vinfo_s *vinfo, @@ -4763,19 +4856,112 @@ static void vlock_enable_step1(struct vframe_s *vf, struct vinfo_s *vinfo, vlock_vmode_changed = 0; vlock_dis_cnt = 0; vlock_state = VLOCK_STATE_ENABLE_STEP1_DONE; - + vlock_log_cnt = 0; } +#define VLOCK_REG_NUM 33 +struct vlock_log_s { + unsigned int pll_m; + unsigned int pll_frac; + unsigned int vlock_regs[VLOCK_REG_NUM]; +}; +struct vlock_log_s *vlock_log; + +void vlock_log_start(void) +{ + unsigned int size_mem; + + size_mem = vlock_log_size * sizeof(struct vlock_log_s); + vlock_log = kzalloc(size_mem, GFP_KERNEL); + + if (vlock_log == NULL) { + kfree(vlock_log); + return; + } + + vlock_log_en = 1; + pr_info("%s done\n", __func__); +} +void vlock_log_stop(void) +{ + if (vlock_log != NULL) + kfree(vlock_log); + vlock_log_en = 0; + pr_info("%s done\n", __func__); +} +void vlock_log_print(void) +{ + unsigned int i, j; + + for (i = 0; i < vlock_log_size; i++) { + pr_info("\n*******[%d]pll_m:0x%x,pll_frac:0x%x*******\n", + i, vlock_log[i].pll_m, vlock_log[i].pll_frac); + for (j = 0; j < VLOCK_REG_NUM;) { + if ((j%8 == 0) && ((j + 7) < VLOCK_REG_NUM)) { + pr_info("0x%08x\t0x%08x\t0x%08x\t0x%08x\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", + vlock_log[i].vlock_regs[j], + vlock_log[i].vlock_regs[j+1], + vlock_log[i].vlock_regs[j+2], + vlock_log[i].vlock_regs[j+3], + vlock_log[i].vlock_regs[j+4], + vlock_log[i].vlock_regs[j+5], + vlock_log[i].vlock_regs[j+6], + vlock_log[i].vlock_regs[j+7]); + j += 8; + } else { + pr_info("0x%08x\t", + vlock_log[i].vlock_regs[j]); + j++; + } + + } + } + pr_info("%s done\n", __func__); +} + static void vlock_enable_step3(void) { unsigned int m_reg_value, tmp_value, abs_val; - unsigned int hiu_reg_addr; + unsigned int hiu_reg_addr, i; if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) hiu_reg_addr = HHI_HDMI_PLL_CNTL1; else hiu_reg_addr = HHI_HDMI_PLL_CNTL2; + /*vs_i*/ + tmp_value = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST); + abs_val = abs(vlock_log_last_ivcnt - tmp_value); + if ((abs_val > vlock_log_delta_ivcnt) && + (vlock_log_delta_en & (1 << 0))) + pr_info("%s: abs_ivcnt over 0x%x:0x%x(last:0x%x,cur:0x%x)\n", + __func__, vlock_log_delta_ivcnt, + abs_val, vlock_log_last_ivcnt, tmp_value); + vlock_log_last_ivcnt = tmp_value; + /*vs_o*/ + tmp_value = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST); + abs_val = abs(vlock_log_last_ovcnt - tmp_value); + if ((abs_val > vlock_log_delta_ovcnt) && + (vlock_log_delta_en & (1 << 1))) + pr_info("%s: abs_ovcnt over 0x%x:0x%x(last:0x%x,cur:0x%x)\n", + __func__, vlock_log_delta_ovcnt, + abs_val, vlock_log_last_ivcnt, tmp_value); + vlock_log_last_ovcnt = tmp_value; + /*delta_vs*/ + abs_val = abs(vlock_log_last_ovcnt - vlock_log_last_ivcnt); + if ((abs_val > vlock_log_delta_vcnt) && (vlock_log_delta_en & (1 << 2))) + pr_info("%s: abs_vcnt over 0x%x:0x%x(ivcnt:0x%x,ovcnt:0x%x)\n", + __func__, vlock_log_delta_vcnt, + abs_val, vlock_log_last_ivcnt, vlock_log_last_ovcnt); + m_reg_value = READ_VPP_REG(VPU_VLOCK_RO_M_INT_FRAC); + if (vlock_log_en && (vlock_log_cnt < vlock_log_size)) { + vlock_log[vlock_log_cnt].pll_frac = (m_reg_value & 0xfff) >> 2; + vlock_log[vlock_log_cnt].pll_m = (m_reg_value >> 16) & 0x1ff; + for (i = 0; i < VLOCK_REG_NUM; i++) + vlock_log[vlock_log_cnt].vlock_regs[i] = + READ_VPP_REG(0x3000 + i); + vlock_log_cnt++; + } if (m_reg_value == 0) { vlock_state = VLOCK_STATE_ENABLE_FORCE_RESET; if (vlock_debug & 0x100) @@ -4783,18 +4969,33 @@ static void vlock_enable_step3(void) __func__); return; } + /*vlsi suggest config:don't enable load signal,*/ + /*on gxtvbb this load signal will effect SSG,*/ + /*which may result in flashes black*/ + amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &tmp_value); + if (is_meson_gxtvbb_cpu() && (((tmp_value >> 21) & 0x3) != 2)) + amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, 2, 21, 2); /*frac*/ amvecm_hiu_reg_read(hiu_reg_addr, &tmp_value); abs_val = abs(((m_reg_value & 0xfff) >> 2) - (tmp_value & 0xfff)); - if ((abs_val < vlock_delta_limit_frac) && (abs_val > 2)) { + if ((abs_val > vlock_log_delta_frac) && + (vlock_log_delta_en & (1 << 3))) + pr_info("vlock frac delta:%d(0x%x,0x%x)\n", + abs_val, ((m_reg_value & 0xfff) >> 2), + (tmp_value & 0xfff)); + if (abs_val > vlock_delta_limit) { tmp_value = (tmp_value & 0xfffff000) | ((m_reg_value & 0xfff) >> 2); amvecm_hiu_reg_write(hiu_reg_addr, tmp_value); } - /*M*/ + /*m*/ amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &tmp_value); abs_val = abs(((m_reg_value >> 16) & 0x1ff) - (tmp_value & 0x1ff)); - if (abs_val <= vlock_delta_limit_m) { + if ((abs_val > vlock_log_delta_m) && (vlock_log_delta_en & (1 << 4))) + pr_info("vlock m delta:%d(0x%x,0x%x)\n", + abs_val, ((m_reg_value >> 16) & 0x1ff), + (tmp_value & 0x1ff)); + if (((m_reg_value >> 16) & 0x1ff) != (tmp_value & 0x1ff)) { tmp_value = (tmp_value & 0xfffffe00) | ((m_reg_value >> 16) & 0x1ff); amvecm_hiu_reg_write(HHI_HDMI_PLL_CNTL, tmp_value); @@ -4818,6 +5019,7 @@ void amve_vlock_process(struct vframe_s *vf) vinfo = get_current_vinfo(); input_hz = vlock_check_input_hz(vf); output_hz = vlock_check_output_hz(vinfo->sync_duration_num); + vlock_dis_cnt_no_vf = 0; if (vecm_latch_flag & FLAG_VLOCK_EN) { vlock_enable_step1(vf, vinfo, input_hz, output_hz); vlock_en = 1; @@ -4829,23 +5031,18 @@ void amve_vlock_process(struct vframe_s *vf) } if (vlock_en == 1) { if (((input_hz != output_hz) && (vlock_adapt == 0)) || - (input_hz == 0) || (output_hz == 0)) { - vlock_dis_cnt_step1++; + (input_hz == 0) || (output_hz == 0) || + (((vf->type_original & VIDTYPE_TYPEMASK) + != VIDTYPE_PROGRESSIVE) && + is_meson_txlx_package_962E())) { if ((vlock_state != VLOCK_STATE_DISABLE_STEP2_DONE) && - (vlock_dis_cnt_step1 > - vlock_dis_cnt_step1_limit) && - (vlock_state != VLOCK_STATE_NULL)) { + (vlock_state != VLOCK_STATE_NULL)) vlock_disable_step1(); - if (vlock_debug & 0x1) - pr_info("[%s]auto disable vlock module for no support case!!!\n", - __func__); - } else - vlock_state = VLOCK_STATE_DISABLE_STEP1; + if (vlock_debug & 0x1) + pr_info("[%s]auto disable vlock module for no support case!!!\n", + __func__); return; } - vlock_dis_cnt_step1 = 0; - if (vlock_state == VLOCK_STATE_ENABLE_STEP1) - vlock_state = VLOCK_STATE_ENABLE_FORCE_RESET; vlock_vmode_check(); if ((vinfo->mode != pre_vmode) || (vf->source_type != pre_source_type) || @@ -4853,16 +5050,13 @@ void amve_vlock_process(struct vframe_s *vf) (input_hz != pre_input_freq) || (output_hz != pre_output_freq) || vlock_vmode_changed || - (vlock_state == VLOCK_STATE_ENABLE_FORCE_RESET) || - (vlock_state == VLOCK_STATE_ENABLE_STEP1)) { - if (vlock_sync_limit_flag++ > vlock_en_cnt_step1_limit) - vlock_enable_step1(vf, vinfo, - input_hz, output_hz); - else - vlock_state = VLOCK_STATE_ENABLE_STEP1; - return; - } - if (vlock_state == VLOCK_STATE_ENABLE_STEP1_DONE) { + (vlock_state == VLOCK_STATE_ENABLE_FORCE_RESET)) + vlock_enable_step1(vf, vinfo, input_hz, output_hz); + if ((vlock_sync_limit_flag < 10) && + (vlock_state >= VLOCK_STATE_ENABLE_STEP1_DONE)) + vlock_sync_limit_flag++; + if ((vlock_sync_limit_flag == 5) && + (vlock_state == VLOCK_STATE_ENABLE_STEP1_DONE)) { /*input_vs_cnt =*/ /*READ_VPP_REG_BITS(VPU_VLOCK_RO_VS_I_DIST,*/ /* 0, 28);*/ @@ -4876,20 +5070,18 @@ void amve_vlock_process(struct vframe_s *vf) /*cal accum0 value*/ WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1); vlock_state = VLOCK_STATE_ENABLE_STEP2_DONE; - return; } else if (vlock_dynamic_adjust && + (vlock_sync_limit_flag > 5) && (vlock_state == VLOCK_STATE_ENABLE_STEP2_DONE) && - (is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) && + (cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) && (vlock_mode == VLOCK_MODE_MANUAL_PLL)) { vlock_enable_step3(); - return; } } } void amve_vlock_resume(void) { - vlock_sync_limit_flag = 0; if ((vlock_en == 0) || (vlock_state == VLOCK_STATE_DISABLE_STEP2_DONE) || (vlock_state == VLOCK_STATE_NULL)) @@ -4898,11 +5090,11 @@ void amve_vlock_resume(void) vlock_disable_step2(); return; } - vlock_dis_cnt_step1++; + vlock_dis_cnt_no_vf++; if ((vlock_state != VLOCK_STATE_DISABLE_STEP2_DONE) && - (vlock_dis_cnt_step1 > vlock_dis_cnt_step1_limit)) { + (vlock_dis_cnt_no_vf > vlock_dis_cnt_no_vf_limit)) { vlock_disable_step1(); - vlock_dis_cnt_step1 = 0; + vlock_dis_cnt_no_vf = 0; if (vlock_debug & 0x1) pr_info("[%s]auto disable vlock module for no vframe & run disable step1.!!!\n", __func__); @@ -4910,6 +5102,12 @@ void amve_vlock_resume(void) if (vlock_debug & 0x1) pr_info("[%s]auto disable vlock module for no vframe!!!\n", __func__); + if (vlock_dynamic_adjust && + (vlock_sync_limit_flag > 5) && + (vlock_state == VLOCK_STATE_ENABLE_STEP2_DONE) && + (cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) && + (vlock_mode == VLOCK_MODE_MANUAL_PLL)) + vlock_enable_step3(); } void vlock_param_set(unsigned int val, enum vlock_param_e sel) @@ -4927,11 +5125,8 @@ void vlock_param_set(unsigned int val, enum vlock_param_e sel) case VLOCK_DIS_CNT_LIMIT: vlock_dis_cnt_limit = val; break; - case VLOCK_DELTA_LIMIT_FRAC: - vlock_delta_limit_frac = val; - break; - case VLOCK_DELTA_LIMIT_M: - vlock_delta_limit_m = val; + case VLOCK_DELTA_LIMIT: + vlock_delta_limit = val; break; case VLOCK_DEBUG: vlock_debug = val; @@ -4939,11 +5134,8 @@ void vlock_param_set(unsigned int val, enum vlock_param_e sel) case VLOCK_DYNAMIC_ADJUST: vlock_dynamic_adjust = val; break; - case VLOCK_DIS_CNT_STEP1_LIMIT: - vlock_dis_cnt_step1_limit = val; - break; - case VLOCK_EN_CNT_STEP1_LIMIT: - vlock_en_cnt_step1_limit = val; + case VLOCK_DIS_CNT_NO_VF_LIMIT: + vlock_dis_cnt_no_vf_limit = val; break; default: pr_info("%s:unknown vlock param:%d\n", __func__, sel); @@ -4958,8 +5150,7 @@ void vlock_status(void) pr_info("vlock_en:%d\n", vlock_en); pr_info("vlock_adapt:%d\n", vlock_adapt); pr_info("vlock_dis_cnt_limit:%d\n", vlock_dis_cnt_limit); - pr_info("vlock_delta_limit_frac:%d\n", vlock_delta_limit_frac); - pr_info("vlock_delta_limit_m:%d\n", vlock_delta_limit_m); + pr_info("vlock_delta_limit:%d\n", vlock_delta_limit); pr_info("vlock_debug:0x%x\n", vlock_debug); pr_info("vlock_dynamic_adjust:%d\n", vlock_dynamic_adjust); pr_info("vlock_state:%d\n", vlock_state); @@ -4969,9 +5160,8 @@ void vlock_status(void) pr_info("pre_hiu_reg_frac:0x%x\n", pre_hiu_reg_frac); pr_info("vlock_dis_cnt:%d\n", vlock_dis_cnt); pr_info("pre_vout_mode:%s\n", pre_vout_mode); - pr_info("vlock_dis_cnt_step1:%d\n", vlock_dis_cnt_step1); - pr_info("vlock_dis_cnt_step1_limit:%d\n", vlock_dis_cnt_step1_limit); - pr_info("vlock_en_cnt_step1_limit:%d\n", vlock_en_cnt_step1_limit); + pr_info("vlock_dis_cnt_no_vf:%d\n", vlock_dis_cnt_no_vf); + pr_info("vlock_dis_cnt_no_vf_limit:%d\n", vlock_dis_cnt_no_vf_limit); } void vlock_reg_dump(void) { @@ -4988,6 +5178,7 @@ void vlock_reg_dump(void) /* sharpness process begin */ void sharpness_process(struct vframe_s *vf) { + return; } /* sharpness process end */ diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.h b/drivers/amlogic/media/enhancement/amvecm/amve.h index 6f7f8b57b59a..c6b940ae5185 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amve.h +++ b/drivers/amlogic/media/enhancement/amvecm/amve.h @@ -61,14 +61,12 @@ enum vlock_param_e { VLOCK_ADAPT, VLOCK_MODE, VLOCK_DIS_CNT_LIMIT, - VLOCK_DELTA_LIMIT_FRAC, - VLOCK_DELTA_LIMIT_M, + VLOCK_DELTA_LIMIT, VLOCK_DEBUG, VLOCK_DYNAMIC_ADJUST, VLOCK_STATE, VLOCK_SYNC_LIMIT_FLAG, - VLOCK_DIS_CNT_STEP1_LIMIT, - VLOCK_EN_CNT_STEP1_LIMIT, + VLOCK_DIS_CNT_NO_VF_LIMIT, VLOCK_PARAM_MAX, }; @@ -84,6 +82,20 @@ extern struct tcon_gamma_table_s video_gamma_table_g_adj; extern struct tcon_gamma_table_s video_gamma_table_b_adj; extern struct tcon_rgb_ogo_s video_rgb_ogo; +extern int glb_scurve[65]; +extern int glb_clash_curve[65]; +extern int glb_pst_gamma[65]; + +extern int gma_scurve0[65]; +extern int gma_scurve1[65]; +extern int gma_scurvet[65]; +extern int clash_curve[65]; +extern int clsh_scvbld[65]; +extern int blk_gma_crv[65]; +extern int blk_gma_bld[65]; +extern int blkwht_ebld[65]; + + extern spinlock_t vpp_lcd_gamma_lock; void ve_on_vs(struct vframe_s *vf); @@ -105,7 +117,7 @@ extern void ve_disable_dnlp(void); extern void vpp_enable_lcd_gamma_table(void); extern void vpp_disable_lcd_gamma_table(void); extern void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask); -extern void init_write_gamma_table(u16 *data, u32 rgb_mask); +extern void amve_write_gamma_table(u16 *data, u32 rgb_mask); extern void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p); extern void vpp_phase_lock_on_vs(unsigned int cycle, unsigned int stamp, @@ -134,6 +146,9 @@ extern void amve_vlock_resume(void); extern void vlock_param_set(unsigned int val, enum vlock_param_e sel); extern void vlock_status(void); extern void vlock_reg_dump(void); +extern void vlock_log_start(void); +extern void vlock_log_stop(void); +extern void vlock_log_print(void); int amvecm_hiu_reg_read(unsigned int reg, unsigned int *val); int amvecm_hiu_reg_write(unsigned int reg, unsigned int val); @@ -161,6 +176,7 @@ extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); /* #if defined(CONFIG_ARCH_MESON2) */ /* unsigned long long ve_get_vs_cnt(void); */ /* #endif */ +extern int video_rgb_ogo_xvy_mtx; #define VLOCK_STATE_NULL 0 #define VLOCK_STATE_ENABLE_STEP1_DONE 1 @@ -168,8 +184,16 @@ extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); #define VLOCK_STATE_DISABLE_STEP1_DONE 3 #define VLOCK_STATE_DISABLE_STEP2_DONE 4 #define VLOCK_STATE_ENABLE_FORCE_RESET 5 -#define VLOCK_STATE_ENABLE_STEP1 6 -#define VLOCK_STATE_DISABLE_STEP1 7 + +/* video lock */ +#define VLOCK_MODE_ENC 0 +#define VLOCK_MODE_AUTO_PLL 1 +#define VLOCK_MODE_MANUAL_PLL 2 +#define XTAL_VLOCK_CLOCK 24000000/*vlock use xtal clock*/ + +/* 0:enc;1:pll;2:manual pll */ +extern unsigned int vlock_mode; +extern unsigned int vlock_en; #endif diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm.c b/drivers/amlogic/media/enhancement/amvecm/amvecm.c index 155ca8a7fb88..8aaeddb3338a 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amvecm.c +++ b/drivers/amlogic/media/enhancement/amvecm/amvecm.c @@ -38,6 +38,8 @@ #include #include #include +#include +#include #ifdef CONFIG_AMLOGIC_LCD #include @@ -72,6 +74,7 @@ struct amvecm_dev_s { dev_t devno; struct device *dev; struct class *clsp; + wait_queue_head_t hdr_queue; }; static struct amvecm_dev_s amvecm_dev; @@ -102,8 +105,6 @@ static struct hdr_metadata_info_s vpp_hdr_metadata_s; void __iomem *amvecm_hiu_reg_base;/* = *ioremap(0xc883c000, 0x2000); */ -#define HIU_REG_BASE 0xc883c000 - static bool debug_amvecm; module_param(debug_amvecm, bool, 0664); MODULE_PARM_DESC(debug_amvecm, "\n debug_amvecm\n"); @@ -136,6 +137,26 @@ static unsigned int sr1_index;/* for sr1 read */ module_param(sr1_index, uint, 0664); MODULE_PARM_DESC(sr1_index, "\n sr1_index\n"); +static int mtx_sel_dbg;/* for mtx debug */ +module_param(mtx_sel_dbg, uint, 0664); +MODULE_PARM_DESC(mtx_sel_dbg, "\n mtx_sel_dbg\n"); + +unsigned int pq_user_latch_flag; +module_param(pq_user_latch_flag, uint, 0664); +MODULE_PARM_DESC(pq_user_latch_flag, "\n pq_user_latch_flag\n"); + +unsigned int pq_user_value; + +static int wb_init_bypass_coef[24] = { + 0, 0, 0, /* pre offset */ + 1024, 0, 0, + 0, 1024, 0, + 0, 0, 1024, + 0, 0, 0, /* 10'/11'/12' */ + 0, 0, 0, /* 20'/21'/22' */ + 0, 0, 0, /* offset */ + 0, 0, 0 /* mode, right_shift, clip_en */ +}; /* vpp brightness/contrast/saturation/hue */ static int __init amvecm_load_pq_val(char *str) @@ -498,17 +519,13 @@ static ssize_t amvecm_vlock_show(struct class *cla, len += sprintf(buf+len, "echo vlock_dis_cnt_limit val(D) > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, - "echo vlock_delta_limit_frac val(D) > /sys/class/amvecm/vlock\n"); - len += sprintf(buf+len, - "echo vlock_delta_limit_m val(D) > /sys/class/amvecm/vlock\n"); + "echo vlock_delta_limit val(D) > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, "echo vlock_debug val(0x111) > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, "echo vlock_dynamic_adjust val(0/1) > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, - "echo vlock_dis_cnt_step1_limit val(D) > /sys/class/amvecm/vlock\n"); - len += sprintf(buf+len, - "echo vlock_cnt_step1_limit val(D) > /sys/class/amvecm/vlock\n"); + "echo vlock_dis_cnt_no_vf_limit val(D) > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, "echo enable > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, @@ -517,6 +534,12 @@ static ssize_t amvecm_vlock_show(struct class *cla, "echo status > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, "echo dump_reg > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo log_start > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo log_stop > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo log_print > /sys/class/amvecm/vlock\n"); return len; } @@ -560,16 +583,11 @@ static ssize_t amvecm_vlock_store(struct class *cla, return -EINVAL; temp_val = val; sel = VLOCK_DIS_CNT_LIMIT; - } else if (!strncmp(parm[0], "vlock_delta_limit_frac", 22)) { + } else if (!strncmp(parm[0], "vlock_delta_limit", 17)) { if (kstrtol(parm[1], 10, &val) < 0) return -EINVAL; temp_val = val; - sel = VLOCK_DELTA_LIMIT_FRAC; - } else if (!strncmp(parm[0], "vlock_delta_limit_m", 19)) { - if (kstrtol(parm[1], 10, &val) < 0) - return -EINVAL; - temp_val = val; - sel = VLOCK_DELTA_LIMIT_M; + sel = VLOCK_DELTA_LIMIT; } else if (!strncmp(parm[0], "vlock_debug", 11)) { if (kstrtol(parm[1], 16, &val) < 0) return -EINVAL; @@ -580,16 +598,11 @@ static ssize_t amvecm_vlock_store(struct class *cla, return -EINVAL; temp_val = val; sel = VLOCK_DYNAMIC_ADJUST; - } else if (!strncmp(parm[0], "vlock_dis_cnt_step1_limit", 25)) { + } else if (!strncmp(parm[0], "vlock_dis_cnt_no_vf_limit", 25)) { if (kstrtol(parm[1], 10, &val) < 0) return -EINVAL; temp_val = val; - sel = VLOCK_DIS_CNT_STEP1_LIMIT; - } else if (!strncmp(parm[0], "vlock_cnt_step1_limit", 21)) { - if (kstrtol(parm[1], 10, &val) < 0) - return -EINVAL; - temp_val = val; - sel = VLOCK_EN_CNT_STEP1_LIMIT; + sel = VLOCK_DIS_CNT_NO_VF_LIMIT; } else if (!strncmp(parm[0], "enable", 6)) { vecm_latch_flag |= FLAG_VLOCK_EN; } else if (!strncmp(parm[0], "disable", 7)) { @@ -598,6 +611,12 @@ static ssize_t amvecm_vlock_store(struct class *cla, vlock_status(); } else if (!strncmp(parm[0], "dump_reg", 8)) { vlock_reg_dump(); + } else if (!strncmp(parm[0], "log_start", 9)) { + vlock_log_start(); + } else if (!strncmp(parm[0], "log_stop", 8)) { + vlock_log_stop(); + } else if (!strncmp(parm[0], "log_print", 9)) { + vlock_log_print(); } else { pr_info("unsupport cmd!!\n"); } @@ -877,52 +896,69 @@ void amvecm_video_latch(void) amvecm_3d_black_process(); } /* #endif */ + pq_user_latch_process(); + } -void amvecm_on_vs(struct vframe_s *vf) +int amvecm_on_vs( + struct vframe_s *vf, + struct vframe_s *toggle_vf, + int flags) { - if ((probe_ok == 0) || - (is_meson_gxm_cpu() && is_dolby_vision_on())) - return; + int result = 0; - if (vf != NULL) { - /* matrix ajust */ - amvecm_matrix_process(vf); + if ((probe_ok == 0) || for_dolby_vision_certification()) + return 0; + if (flags & CSC_FLAG_CHECK_OUTPUT) { + /* to test if output will change */ + return amvecm_matrix_process( + toggle_vf, vf, flags); + } + if ((toggle_vf != NULL) || (vf != NULL)) { + /* matrix adjust */ + result = amvecm_matrix_process(toggle_vf, vf, flags); + if (toggle_vf) + ioctrl_get_hdr_metadata(toggle_vf); + } else + result = amvecm_matrix_process(NULL, NULL, flags); + /* add some flag to trigger */ + if (vf) { amvecm_bricon_process( vd1_brightness, vd1_contrast + vd1_contrast_offset, vf); - ioctrl_get_hdr_metadata(vf); amvecm_color_process( saturation_pre + saturation_offset + satu_shift_by_con, hue_pre, vf); vpp_demo_config(vf); - } else - amvecm_matrix_process(NULL); - /* vlock processs */ - if ((get_cpu_type() >= - MESON_CPU_MAJOR_ID_GXBB) && (vf != NULL)) - amve_vlock_process(vf); - else if ((get_cpu_type() >= - MESON_CPU_MAJOR_ID_GXBB) && (vf == NULL)) - amve_vlock_resume(); + } + /* todo:vlock processs only for tv chip */ + if (is_meson_gxtvbb_cpu() || + is_meson_txl_cpu() || is_meson_txlx_cpu()) { + if (vf != NULL) + amve_vlock_process(vf); + else + amve_vlock_resume(); + } /* pq latch process */ amvecm_video_latch(); + return result; } EXPORT_SYMBOL(amvecm_on_vs); void refresh_on_vs(struct vframe_s *vf) { - if (is_meson_gxm_cpu() && is_dolby_vision_on()) + if (probe_ok == 0) return; if (vf != NULL) { vpp_get_vframe_hist_info(vf); - ve_on_vs(vf); + if (!for_dolby_vision_certification()) + ve_on_vs(vf); vpp_backup_histgram(vf); } } @@ -934,6 +970,8 @@ static int amvecm_open(struct inode *inode, struct file *file) /* Get the per-device structure that contains this cdev */ devp = container_of(inode->i_cdev, struct amvecm_dev_s, cdev); file->private_data = devp; + /*init queue*/ + init_waitqueue_head(&devp->hdr_queue); return 0; } @@ -955,14 +993,14 @@ static long amvecm_ioctl(struct file *file, if (probe_ok == 0) return ret; + + if (pq_load_en == 0) { + pr_amvecm_dbg("[amvecm..] pq ioctl function disabled !!\n"); + return ret; + } + switch (cmd) { case AMVECM_IOC_LOAD_REG: - if (pq_load_en == 0) { - ret = -EBUSY; - pr_amvecm_dbg("[amvecm..] pq ioctl function disabled !!\n"); - return ret; - } - if ((vecm_latch_flag & FLAG_REG_MAP0) && (vecm_latch_flag & FLAG_REG_MAP1) && (vecm_latch_flag & FLAG_REG_MAP2) && @@ -1125,6 +1163,120 @@ static long amvecm_compat_ioctl(struct file *file, unsigned int cmd, return ret; } #endif + +static ssize_t amvecm_dnlp_curve_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + pr_info("echo gma_scurve0 > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo gma_scurve1 > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo gma_scurvet > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo clash_curve > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo clsh_scvbld > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo blk_gma_crv > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo blk_gma_bld > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo blkwht_ebld > /sys/class/amvecm/dnlp_curve\n"); + + pr_info("echo wv glb_scurve idx value > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo wv glb_clash_curve idx value > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo wv glb_pst_gamma idx value > /sys/class/amvecm/dnlp_curve\n"); + + pr_info("echo glb_scurve > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo glb_clash_curve > /sys/class/amvecm/dnlp_curve\n"); + pr_info("echo glb_pst_gamma > /sys/class/amvecm/dnlp_curve\n"); + return 0; +} +static ssize_t amvecm_dnlp_curve_store(struct class *cla, + struct class_attribute *attr, const char *buf, size_t count) +{ + int i; + long val = 0; + unsigned int idx, value; + char *buf_orig, *parm[8] = {NULL}; + + if (!buf) + return count; + buf_orig = kstrdup(buf, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + if (!strncmp(parm[0], "wv", 2)) { + if (!strncmp(parm[1], "glb_scurve", 10)) { + if (kstrtoul(parm[2], 10, &val) < 0) + return -EINVAL; + idx = val; + if (kstrtoul(parm[3], 10, &val) < 0) + return -EINVAL; + value = val; + if (idx > 0 && idx < 66) { + glb_scurve[idx-1] = value; + pr_amvecm_dbg("idx = %d, value = %d\n", + idx, value); + } + } else if (!strncmp(parm[1], "glb_clash_curve", 15)) { + if (kstrtoul(parm[2], 10, &val) < 0) + return -EINVAL; + idx = val; + if (kstrtoul(parm[3], 10, &val) < 0) + return -EINVAL; + value = val; + if (idx > 0 && idx < 66) { + glb_clash_curve[idx-1] = value; + pr_amvecm_dbg("idx = %d, value = %d\n", + idx, value); + } + } else if (!strncmp(parm[1], "glb_pst_gamma", 13)) { + if (kstrtoul(parm[2], 10, &val) < 0) + return -EINVAL; + idx = val; + if (kstrtoul(parm[3], 10, &val) < 0) + return -EINVAL; + value = val; + if (idx > 0 && idx < 66) { + glb_pst_gamma[idx-1] = value; + pr_amvecm_dbg("idx = %d, value = %d\n", + idx, value); + } + } + } + + if (!strncmp(parm[0], "gma_scurve0", 11)) { + for (i = 0; i < 64; i++) + pr_info("gma_scurve0[%d] = %d\n", i, gma_scurve0[i]); + } else if (!strncmp(parm[0], "gma_scurve1", 11)) { + for (i = 0; i < 64; i++) + pr_info("gma_scurve1[%d] = %d\n", i, gma_scurve1[i]); + } else if (!strncmp(parm[0], "gma_scurvet", 11)) { + for (i = 0; i < 64; i++) + pr_info("gma_scurvet[%d] = %d\n", i, gma_scurvet[i]); + } else if (!strncmp(parm[0], "clash_curve", 11)) { + for (i = 0; i < 64; i++) + pr_info("clash_curve[%d] = %d\n", i, clash_curve[i]); + } else if (!strncmp(parm[0], "clsh_scvbld", 11)) { + for (i = 0; i < 64; i++) + pr_info("clsh_scvbld[%d] = %d\n", i, clsh_scvbld[i]); + } else if (!strncmp(parm[0], "blk_gma_crv", 11)) { + for (i = 0; i < 64; i++) + pr_info("blk_gma_crv[%d] = %d\n", i, blk_gma_crv[i]); + } else if (!strncmp(parm[0], "blk_gma_bld", 11)) { + for (i = 0; i < 64; i++) + pr_info("blk_gma_bld[%d] = %d\n", i, blk_gma_bld[i]); + } else if (!strncmp(parm[0], "blkwht_ebld", 11)) { + for (i = 0; i < 64; i++) + pr_info("blkwht_ebld[%d] = %d\n", i, blkwht_ebld[i]); + } else if (!strncmp(parm[0], "glb_scurve", 10)) { + for (i = 0; i < 64; i++) + pr_info("glb_scurve[%d] = %d\n", i, glb_scurve[i]); + } else if (!strncmp(parm[0], "glb_clash_curve", 15)) { + for (i = 0; i < 64; i++) + pr_info("glb_clash_curve[%d] = %d\n", + i, glb_clash_curve[i]); + } else if (!strncmp(parm[0], "glb_pst_gamma", 13)) { + for (i = 0; i < 64; i++) + pr_info("glb_pst_gamma[%d] = %d\n", + i, glb_pst_gamma[i]); + } + + kfree(buf_orig); + return count; +} static ssize_t amvecm_dnlp_show(struct class *cla, struct class_attribute *attr, char *buf) { @@ -1553,6 +1705,64 @@ static ssize_t amvecm_cm2_store(struct class *cls, return count; } +static ssize_t amvecm_cm_reg_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + pr_info("Usage: echo addr value > /sys/class/amvecm/cm_reg"); + return 0; +} + +static ssize_t amvecm_cm_reg_store(struct class *cls, + struct class_attribute *attr, + const char *buffer, size_t count) +{ + int data[5] = {0}; + unsigned int addr, value; + long val = 0; + int i, node, reg_node; + unsigned int addr_port = VPP_CHROMA_ADDR_PORT;/* 0x1d70; */ + unsigned int data_port = VPP_CHROMA_DATA_PORT;/* 0x1d71; */ + char *buf_orig, *parm[2] = {NULL}; + + if (!buffer) + return count; + buf_orig = kstrdup(buffer, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + + if (kstrtoul(parm[0], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + addr = val; + if (kstrtoul(parm[1], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + value = val; + + node = (addr - 0x100) / 8; + reg_node = (addr - 0x100) % 8; + + for (i = 0; i < 5; i++) { + if (i == reg_node) { + data[i] = value; + continue; + } + addr = node * 8 + 0x100 + i; + WRITE_VPP_REG(addr_port, addr); + data[i] = READ_VPP_REG(data_port); + } + + for (i = 0; i < 5; i++) { + addr = node * 8 + 0x100 + i; + WRITE_VPP_REG(addr_port, addr); + WRITE_VPP_REG(data_port, data[i]); + } + + kfree(buf_orig); + return count; +} + static ssize_t amvecm_gamma_show(struct class *cls, struct class_attribute *attr, char *buf) @@ -1613,23 +1823,25 @@ static ssize_t amvecm_gamma_store(struct class *cls, gamma[1] = parm[1][3 * i + 1]; gamma[2] = parm[1][3 * i + 2]; gamma[3] = '\0'; - if (kstrtol(gamma, 16, &val) < 0) + if (kstrtol(gamma, 16, &val) < 0) { + kfree(buf_orig); return -EINVAL; + } gammaR[i] = val; } switch (parm[0][2]) { case 'r': - vpp_set_lcd_gamma_table(gammaR, H_SEL_R); + amve_write_gamma_table(gammaR, H_SEL_R); break; case 'g': - vpp_set_lcd_gamma_table(gammaR, H_SEL_G); + amve_write_gamma_table(gammaR, H_SEL_G); break; case 'b': - vpp_set_lcd_gamma_table(gammaR, H_SEL_B); + amve_write_gamma_table(gammaR, H_SEL_B); break; default: break; @@ -1649,7 +1861,8 @@ static ssize_t amvecm_gamma_store(struct class *cls, static ssize_t set_gamma_pattern_show(struct class *cla, struct class_attribute *attr, char *buf) { - pr_info(" echo r g b > /sys/class/amvecm/gamma_pattern\n"); + pr_info("8bit: echo r g b > /sys/class/amvecm/gamma_pattern\n"); + pr_info("10bit: echo r g b 0xa > /sys/class/amvecm/gamma_pattern\n"); pr_info(" r g b should be hex\n"); return 0; } @@ -1661,7 +1874,7 @@ static ssize_t set_gamma_pattern_store(struct class *cls, unsigned short r_val[256], g_val[256], b_val[256]; int n = 0; char *buf_orig, *ps, *token; - char *parm[3]; + char *parm[4]; unsigned int gamma[3]; long val, i; char deliml[3] = " "; @@ -1670,6 +1883,7 @@ static ssize_t set_gamma_pattern_store(struct class *cls, buf_orig = kstrdup(buffer, GFP_KERNEL); ps = buf_orig; strcat(deliml, delim2); + *(parm + 3) = NULL; while (1) { token = strsep(&ps, deliml); if (token == NULL) @@ -1678,17 +1892,53 @@ static ssize_t set_gamma_pattern_store(struct class *cls, continue; parm[n++] = token; } - if (kstrtol(parm[0], 16, &val) < 0) - return -EINVAL; - gamma[0] = val << 2; - if (kstrtol(parm[1], 16, &val) < 0) - return -EINVAL; - gamma[1] = val << 2; + if (*(parm + 3) != NULL) { + if (kstrtol(parm[3], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + if (val == 10) { + if (kstrtol(parm[0], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + gamma[0] = val; - if (kstrtol(parm[2], 16, &val) < 0) - return -EINVAL; - gamma[2] = val << 2; + if (kstrtol(parm[1], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + gamma[1] = val; + + if (kstrtol(parm[2], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + gamma[2] = val; + } else { + kfree(buf_orig); + return count; + } + } else { + if (kstrtol(parm[0], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + gamma[0] = val << 2; + + if (kstrtol(parm[1], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + gamma[1] = val << 2; + + if (kstrtol(parm[2], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + gamma[2] = val << 2; + } for (i = 0; i < 256; i++) { r_val[i] = gamma[0]; @@ -1696,11 +1946,11 @@ static ssize_t set_gamma_pattern_store(struct class *cls, b_val[i] = gamma[2]; } - vpp_set_lcd_gamma_table(r_val, H_SEL_R); + amve_write_gamma_table(r_val, H_SEL_R); + amve_write_gamma_table(g_val, H_SEL_G); + amve_write_gamma_table(b_val, H_SEL_B); - vpp_set_lcd_gamma_table(g_val, H_SEL_G); - - vpp_set_lcd_gamma_table(b_val, H_SEL_B); + kfree(buf_orig); return count; } @@ -2055,34 +2305,53 @@ static ssize_t amvecm_dump_reg_show(struct class *cla, { unsigned int addr; unsigned int value; + unsigned int base_reg; + + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) + base_reg = 0xff900000; + else + base_reg = 0xd0100000; pr_info("----dump sharpness0 reg----\n"); for (addr = 0x3200; addr <= 0x3264; addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); - if (is_meson_txl_cpu()) { + if (is_meson_txl_cpu() || is_meson_txlx_cpu()) { for (addr = 0x3265; addr <= 0x3272; addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, + READ_VPP_REG(addr)); + } + if (is_meson_txlx_cpu()) { + for (addr = 0x3273; + addr <= 0x327f; addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); } pr_info("----dump sharpness1 reg----\n"); for (addr = (0x3200+0x80); addr <= (0x3264+0x80); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); - if (is_meson_txl_cpu()) { + if (is_meson_txl_cpu() || is_meson_txlx_cpu()) { for (addr = (0x3265+0x80); addr <= (0x3272+0x80); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, + READ_VPP_REG(addr)); + } + if (is_meson_txlx_cpu()) { + for (addr = (0x3273+0x80); + addr <= (0x327f+0x80); addr++) + pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); } - pr_info("----dump cm reg----\n"); for (addr = 0x200; addr <= 0x21e; addr++) { WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, addr); @@ -2103,57 +2372,57 @@ static ssize_t amvecm_dump_reg_show(struct class *cla, for (addr = (0x1a50); addr <= (0x1a69); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump vpp1 part1 reg----\n"); for (addr = (0x1d00); addr <= (0x1d6e); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump vpp1 part2 reg----\n"); for (addr = (0x1d72); addr <= (0x1de4); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump ndr reg----\n"); for (addr = (0x2d00); addr <= (0x2d78); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump nr3 reg----\n"); for (addr = (0x2ff0); addr <= (0x2ff6); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump vlock reg----\n"); for (addr = (0x3000); addr <= (0x3020); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump super scaler0 reg----\n"); for (addr = (0x3100); addr <= (0x3115); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump super scaler1 reg----\n"); for (addr = (0x3118); addr <= (0x312e); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump xvycc reg----\n"); for (addr = (0x3158); addr <= (0x3179); addr++) pr_info("[0x%x]vcbus[0x%04x]=0x%08x\n", - (0xd0100000+(addr<<2)), addr, + (base_reg + (addr<<2)), addr, READ_VPP_REG(addr)); pr_info("----dump reg done----\n"); return 0; @@ -2253,99 +2522,352 @@ void pc_mode_process(void) ve_enable_dnlp(); /* open cm clock gate */ cm_en = 1; - amcm_enable(); /* sharpness on */ - WRITE_VPP_REG_BITS( - SRSHARP0_SHARP_PK_NR_ENABLE, + VSYNC_WR_MPEG_REG_BITS( + SRSHARP0_PK_NR_ENABLE, 1, 1, 1); - WRITE_VPP_REG_BITS( - SRSHARP1_SHARP_PK_NR_ENABLE, + VSYNC_WR_MPEG_REG_BITS( + SRSHARP1_PK_NR_ENABLE, 1, 1, 1); - reg_val = READ_VPP_REG(SRSHARP0_HCTI_FLT_CLP_DC); - WRITE_VPP_REG(SRSHARP0_HCTI_FLT_CLP_DC, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC); + VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC, reg_val | 0x10000000); - WRITE_VPP_REG(SRSHARP1_HCTI_FLT_CLP_DC, + VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC, reg_val | 0x10000000); - reg_val = READ_VPP_REG(SRSHARP0_HLTI_FLT_CLP_DC); - WRITE_VPP_REG(SRSHARP0_HLTI_FLT_CLP_DC, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC); + VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC, reg_val | 0x10000000); - WRITE_VPP_REG(SRSHARP1_HLTI_FLT_CLP_DC, + VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC, reg_val | 0x10000000); - reg_val = READ_VPP_REG(SRSHARP0_VLTI_FLT_CON_CLP); - WRITE_VPP_REG(SRSHARP0_VLTI_FLT_CON_CLP, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP); + VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP, reg_val | 0x4000); - WRITE_VPP_REG(SRSHARP1_VLTI_FLT_CON_CLP, + VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP, reg_val | 0x4000); - reg_val = READ_VPP_REG(SRSHARP0_VCTI_FLT_CON_CLP); - WRITE_VPP_REG(SRSHARP0_VCTI_FLT_CON_CLP, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP); + VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP, reg_val | 0x4000); - WRITE_VPP_REG(SRSHARP1_VCTI_FLT_CON_CLP, + VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP, reg_val | 0x4000); - if (is_meson_txl_cpu()) { - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL, + 1, 28, 3); - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL, + 1, 28, 3); } - WRITE_VPP_REG(VPP_VADJ_CTRL, 0xd); + VSYNC_WR_MPEG_REG(VPP_VADJ_CTRL, 0xd); pc_mode_last = pc_mode; } else if ((pc_mode == 0) && (pc_mode != pc_mode_last)) { dnlp_en = 0; ve_disable_dnlp(); cm_en = 0; - amcm_disable(); - WRITE_VPP_REG_BITS( - SRSHARP0_SHARP_PK_NR_ENABLE, + VSYNC_WR_MPEG_REG_BITS( + SRSHARP0_PK_NR_ENABLE, 0, 1, 1); - WRITE_VPP_REG_BITS( - SRSHARP1_SHARP_PK_NR_ENABLE, + VSYNC_WR_MPEG_REG_BITS( + SRSHARP1_PK_NR_ENABLE, 0, 1, 1); - reg_val = READ_VPP_REG(SRSHARP0_HCTI_FLT_CLP_DC); - WRITE_VPP_REG(SRSHARP0_HCTI_FLT_CLP_DC, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC); + VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC, reg_val & 0xefffffff); - WRITE_VPP_REG(SRSHARP1_HCTI_FLT_CLP_DC, + VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC, reg_val & 0xefffffff); - reg_val = READ_VPP_REG(SRSHARP0_HLTI_FLT_CLP_DC); - WRITE_VPP_REG(SRSHARP0_HLTI_FLT_CLP_DC, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC); + VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC, reg_val & 0xefffffff); - WRITE_VPP_REG(SRSHARP1_HLTI_FLT_CLP_DC, + VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC, reg_val & 0xefffffff); - reg_val = READ_VPP_REG(SRSHARP0_VLTI_FLT_CON_CLP); - WRITE_VPP_REG(SRSHARP0_VLTI_FLT_CON_CLP, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP); + VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP, reg_val & 0xffffbfff); - WRITE_VPP_REG(SRSHARP1_VLTI_FLT_CON_CLP, + VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP, reg_val & 0xffffbfff); - reg_val = READ_VPP_REG(SRSHARP0_VCTI_FLT_CON_CLP); - WRITE_VPP_REG(SRSHARP0_VCTI_FLT_CON_CLP, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP); + VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP, reg_val & 0xffffbfff); - WRITE_VPP_REG(SRSHARP1_VCTI_FLT_CON_CLP, + VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP, reg_val & 0xffffbfff); - if (is_meson_txl_cpu()) { - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL, + 0, 28, 3); - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL, + 0, 28, 3); } - WRITE_VPP_REG(VPP_VADJ_CTRL, 0x0); + VSYNC_WR_MPEG_REG(VPP_VADJ_CTRL, 0x0); pc_mode_last = pc_mode; } } +void amvecm_black_ext_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 1, 3, 1); + else + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 0, 3, 1); +} + +void amvecm_black_ext_start_adj(unsigned int value) +{ + if (value > 255) + return; + WRITE_VPP_REG_BITS(VPP_BLACKEXT_CTRL, value, 24, 8); +} + +void amvecm_black_ext_slope_adj(unsigned int value) +{ + if (value > 255) + return; + WRITE_VPP_REG_BITS(VPP_BLACKEXT_CTRL, value, 16, 8); +} + +void amvecm_sr0_pk_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1); + else + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1); +} + +void amvecm_sr1_pk_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1); + else + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1); +} + +void amvecm_sr0_dering_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); + else + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); +} + +void amvecm_sr1_dering_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); + else + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); +} + +void amvecm_sr0_dejaggy_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); + else + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); +} + +void amvecm_sr1_dejaggy_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); + else + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); +} + +void amvecm_sr0_derection_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); + else + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); +} + +void amvecm_sr1_derection_enable(unsigned int enable) +{ + if (enable) + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); + else + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); +} + +void pq_user_latch_process(void) +{ + if (pq_user_latch_flag & PQ_USER_BLK_EN) { + pq_user_latch_flag &= ~PQ_USER_BLK_EN; + amvecm_black_ext_enable(true); + } else if (pq_user_latch_flag & PQ_USER_BLK_DIS) { + pq_user_latch_flag &= ~PQ_USER_BLK_DIS; + amvecm_black_ext_enable(false); + } else if (pq_user_latch_flag & PQ_USER_BLK_START) { + pq_user_latch_flag &= ~PQ_USER_BLK_START; + amvecm_black_ext_start_adj(pq_user_value); + } else if (pq_user_latch_flag & PQ_USER_BLK_SLOPE) { + pq_user_latch_flag &= ~PQ_USER_BLK_SLOPE; + amvecm_black_ext_slope_adj(pq_user_value); + } else if (pq_user_latch_flag & PQ_USER_SR0_PK_EN) { + pq_user_latch_flag &= ~PQ_USER_SR0_PK_EN; + amvecm_sr0_pk_enable(true); + } else if (pq_user_latch_flag & PQ_USER_SR0_PK_DIS) { + pq_user_latch_flag &= ~PQ_USER_SR0_PK_DIS; + amvecm_sr0_pk_enable(false); + } else if (pq_user_latch_flag & PQ_USER_SR1_PK_EN) { + pq_user_latch_flag &= ~PQ_USER_SR1_PK_EN; + amvecm_sr1_pk_enable(true); + } else if (pq_user_latch_flag & PQ_USER_SR1_PK_DIS) { + pq_user_latch_flag &= ~PQ_USER_SR1_PK_DIS; + amvecm_sr1_pk_enable(false); + } else if (pq_user_latch_flag & PQ_USER_SR0_DERING_EN) { + pq_user_latch_flag &= ~PQ_USER_SR0_DERING_EN; + amvecm_sr0_dering_enable(true); + } else if (pq_user_latch_flag & PQ_USER_SR0_DERING_DIS) { + pq_user_latch_flag &= ~PQ_USER_SR0_DERING_DIS; + amvecm_sr0_dering_enable(false); + } else if (pq_user_latch_flag & PQ_USER_SR1_DERING_EN) { + pq_user_latch_flag &= ~PQ_USER_SR1_DERING_EN; + amvecm_sr1_dering_enable(true); + } else if (pq_user_latch_flag & PQ_USER_SR1_DERING_DIS) { + pq_user_latch_flag &= ~PQ_USER_SR1_DERING_DIS; + amvecm_sr1_dering_enable(false); + } else if (pq_user_latch_flag & PQ_USER_SR0_DEJAGGY_EN) { + pq_user_latch_flag &= ~PQ_USER_SR0_DEJAGGY_EN; + amvecm_sr0_dejaggy_enable(true); + } else if (pq_user_latch_flag & PQ_USER_SR0_DEJAGGY_DIS) { + pq_user_latch_flag &= ~PQ_USER_SR0_DEJAGGY_DIS; + amvecm_sr0_dejaggy_enable(false); + } else if (pq_user_latch_flag & PQ_USER_SR1_DEJAGGY_EN) { + pq_user_latch_flag &= ~PQ_USER_SR1_DEJAGGY_EN; + amvecm_sr1_dejaggy_enable(true); + } else if (pq_user_latch_flag & PQ_USER_SR1_DEJAGGY_DIS) { + pq_user_latch_flag &= ~PQ_USER_SR1_DEJAGGY_DIS; + amvecm_sr1_dejaggy_enable(false); + } else if (pq_user_latch_flag & PQ_USER_SR0_DERECTION_EN) { + pq_user_latch_flag &= ~PQ_USER_SR0_DERECTION_EN; + amvecm_sr0_derection_enable(true); + } else if (pq_user_latch_flag & PQ_USER_SR0_DERECTION_DIS) { + pq_user_latch_flag &= ~PQ_USER_SR0_DERECTION_DIS; + amvecm_sr0_derection_enable(false); + } else if (pq_user_latch_flag & PQ_USER_SR1_DERECTION_EN) { + pq_user_latch_flag &= ~PQ_USER_SR1_DERECTION_EN; + amvecm_sr1_derection_enable(true); + } else if (pq_user_latch_flag & PQ_USER_SR1_DERECTION_DIS) { + pq_user_latch_flag &= ~PQ_USER_SR1_DERECTION_DIS; + amvecm_sr1_derection_enable(false); + } +} + +static const char *amvecm_pq_user_usage_str = { + "Usage:\n" + "echo blk_ext_en > /sys/class/amvecm/pq_user_set: blk ext en\n" + "echo blk_ext_dis > /sys/class/amvecm/pq_user_set: blk ext dis\n" + "echo blk_start val > /sys/class/amvecm/pq_user_set: start adj\n" + "echo blk_slope val > /sys/class/amvecm/pq_user_set: slope adj\n" + "echo sr0_pk_en > /sys/class/amvecm/pq_user_set: sr0 pk en\n" + "echo sr0_pk_dis > /sys/class/amvecm/pq_user_set: sr0 pk dis\n" + "echo sr1_pk_en > /sys/class/amvecm/pq_user_set: sr0 pk en\n" + "echo sr1_pk_dis > /sys/class/amvecm/pq_user_set: sr0 pk dis\n" + "echo sr0_dering_en > /sys/class/amvecm/pq_user_set: sr0 dr en\n" + "echo sr0_dering_dis > /sys/class/amvecm/pq_user_set: sr0 dr dis\n" + "echo sr1_dering_en > /sys/class/amvecm/pq_user_set: sr1 dr en\n" + "echo sr1_dering_dis > /sys/class/amvecm/pq_user_set: sr1 dr dis\n" + "echo sr0_dejaggy_en > /sys/class/amvecm/pq_user_set: sr0 dj en\n" + "echo sr0_dejaggy_dis > /sys/class/amvecm/pq_user_set: sr0 dj dis\n" + "echo sr1_dejaggy_en > /sys/class/amvecm/pq_user_set: sr1 dj en\n" + "echo sr1_dejaggy_dis > /sys/class/amvecm/pq_user_set: sr1 dj dis\n" + "echo sr0_derec_en > /sys/class/amvecm/pq_user_set: sr0 drec en\n" + "echo sr0_derec_dis > /sys/class/amvecm/pq_user_set: sr0 drec dis\n" + "echo sr1_derec_en > /sys/class/amvecm/pq_user_set: sr1 drec en\n" + "echo sr1_derec_dis > /sys/class/amvecm/pq_user_set: sr1 drec dis\n" + +}; + +static ssize_t amvecm_pq_user_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", amvecm_pq_user_usage_str); +} + +static ssize_t amvecm_pq_user_store(struct class *cla, + struct class_attribute *attr, + const char *buf, size_t count) +{ + char *buf_orig, *parm[8] = {NULL}; + long val = 0; + + if (!buf) + return count; + buf_orig = kstrdup(buf, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + + if (!strncmp(parm[0], "blk_ext_en", 10)) + pq_user_latch_flag |= PQ_USER_BLK_EN; + else if (!strncmp(parm[0], "blk_ext_dis", 11)) + pq_user_latch_flag |= PQ_USER_BLK_DIS; + else if (!strncmp(parm[0], "blk_start", 9)) { + if (kstrtoul(parm[1], 10, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + pq_user_value = val; + pq_user_latch_flag |= PQ_USER_BLK_START; + } else if (!strncmp(parm[0], "blk_slope", 9)) { + if (kstrtoul(parm[1], 10, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + pq_user_value = val; + pq_user_latch_flag |= PQ_USER_BLK_SLOPE; + } else if (!strncmp(parm[0], "sr0_pk_en", 9)) { + pq_user_latch_flag |= PQ_USER_SR0_PK_EN; + } else if (!strncmp(parm[0], "sr0_pk_dis", 10)) { + pq_user_latch_flag |= PQ_USER_SR0_PK_DIS; + } else if (!strncmp(parm[0], "sr1_pk_en", 9)) { + pq_user_latch_flag |= PQ_USER_SR1_PK_EN; + } else if (!strncmp(parm[0], "sr1_pk_dis", 10)) { + pq_user_latch_flag |= PQ_USER_SR1_PK_DIS; + } else if (!strncmp(parm[0], "sr0_dering_en", 13)) { + pq_user_latch_flag |= PQ_USER_SR0_DERING_EN; + } else if (!strncmp(parm[0], "sr0_dering_dis", 14)) { + pq_user_latch_flag |= PQ_USER_SR0_DERING_DIS; + } else if (!strncmp(parm[0], "sr1_dering_en", 13)) { + pq_user_latch_flag |= PQ_USER_SR1_DERING_EN; + } else if (!strncmp(parm[0], "sr1_dering_dis", 14)) { + pq_user_latch_flag |= PQ_USER_SR1_DERING_DIS; + } else if (!strncmp(parm[0], "sr0_dejaggy_en", 14)) { + pq_user_latch_flag |= PQ_USER_SR0_DEJAGGY_EN; + } else if (!strncmp(parm[0], "sr0_dejaggy_dis", 15)) { + pq_user_latch_flag |= PQ_USER_SR0_DEJAGGY_DIS; + } else if (!strncmp(parm[0], "sr1_dejaggy_en", 14)) { + pq_user_latch_flag |= PQ_USER_SR1_DEJAGGY_EN; + } else if (!strncmp(parm[0], "sr1_dejaggy_dis", 15)) { + pq_user_latch_flag |= PQ_USER_SR1_DEJAGGY_DIS; + } else if (!strncmp(parm[0], "sr0_derec_en", 12)) { + pq_user_latch_flag |= PQ_USER_SR0_DERECTION_EN; + } else if (!strncmp(parm[0], "sr0_derec_dis", 13)) { + pq_user_latch_flag |= PQ_USER_SR0_DERECTION_DIS; + } else if (!strncmp(parm[0], "sr1_derec_en", 12)) { + pq_user_latch_flag |= PQ_USER_SR1_DERECTION_EN; + } else if (!strncmp(parm[0], "sr1_derec_dis", 13)) { + pq_user_latch_flag |= PQ_USER_SR1_DERECTION_DIS; + } + + kfree(buf_orig); + return count; +} + + static ssize_t amvecm_vpp_demo_show(struct class *cla, struct class_attribute *attr, char *buf) { @@ -2462,41 +2984,17 @@ static void dump_vpp_size_info(void) cm_hsize, cm_vsize); } -static void vpp_sr3_enhance_enable(unsigned int enable) -{ - /*0x00: core 0 disable*/ - /*0x01: core 0 enable*/ - /*0x10: core 1 disable*/ - /*0x11: core 1 enable*/ - - if (enable == 0x00) { - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); - } else if (enable == 0x01) { - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); - } else if (enable == 0x10) { - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); - } else if (enable == 0x11) { - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); - } -} - static void amvecm_wb_enable(int enable) { - if (enable) { + if (enable) wb_en = 1; - WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 1, 31, 1); - } else { + else wb_en = 0; - WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 0, 31, 1); - } + + if (video_rgb_ogo_xvy_mtx) + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, enable, 6, 1); + else + WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, enable, 31, 1); } static void amvecm_sharpness_debug(int enable) @@ -2505,12 +3003,12 @@ static void amvecm_sharpness_debug(int enable) /*2:lti/cti enable 3:lti/cti disable*/ switch (enable) { case 0: - WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 1, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SHARP_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1); break; case 1: - WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 0, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SHARP_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1); break; case 2: WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 1, 28, 1); @@ -2534,6 +3032,38 @@ static void amvecm_sharpness_debug(int enable) WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 0, 14, 1); WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 0, 14, 1); break; + /*sr4 drtlpf theta en*/ + case 4: + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 4, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 3, 3); + break; + case 5: + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 4, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 3, 3); + break; + /*sr4 debanding en*/ + case 6: + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 23, 1); + + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 23, 1); + break; + case 7: + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 23, 1); + + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 23, 1); + break; default: break; } @@ -2546,8 +3076,8 @@ static void amvecm_pq_enable(int enable) amcm_enable(); - WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 1, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SHARP_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1); WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 1, 28, 1); WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 1, 28, 1); @@ -2558,7 +3088,31 @@ static void amvecm_pq_enable(int enable) WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 1, 14, 1); WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 1, 14, 1); - WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 1, 31, 1); + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); + + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); + } + /*sr4 drtlpf theta/ debanding en*/ + if (is_meson_txlx_cpu()) { + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 4, 3); + + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 23, 1); + + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 23, 1); + } + + amvecm_wb_enable(true); vecm_latch_flag |= FLAG_GAMMA_TABLE_EN; @@ -2568,8 +3122,8 @@ static void amvecm_pq_enable(int enable) amcm_disable(); - WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 0, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SHARP_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1); WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 0, 28, 1); WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 0, 28, 1); @@ -2580,7 +3134,31 @@ static void amvecm_pq_enable(int enable) WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 0, 14, 1); WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 0, 14, 1); - WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 0, 31, 1); + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); + + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); + } + /*sr4 drtlpf theta/ debanding en*/ + if (is_meson_txlx_cpu()) { + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 4, 3); + + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 23, 1); + + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 23, 1); + } + + amvecm_wb_enable(false); vecm_latch_flag |= FLAG_GAMMA_TABLE_DIS; @@ -2588,9 +3166,191 @@ static void amvecm_pq_enable(int enable) } } +static void amvecm_dither_enable(int enable) +{ + switch (enable) { + /*dither enable*/ + case 0:/*disable*/ + WRITE_VPP_REG_BITS(VPP_VE_DITHER_CTRL, 0, 0, 1); + break; + case 1:/*enable*/ + WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, 1, 0, 1); + break; + /*dither round enable*/ + case 2:/*disable*/ + WRITE_VPP_REG_BITS(VPP_VE_DITHER_CTRL, 0, 1, 1); + break; + case 3:/*enable*/ + WRITE_VPP_REG_BITS(VPP_VE_DITHER_CTRL, 1, 1, 1); + break; + default: + break; + } +} + +static void amvecm_vpp_mtx_debug(int mtx_sel, int coef_sel) +{ + if (mtx_sel & (1 << VPP_MATRIX_1)) { + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 1, 5, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 1, 8, 3); + mtx_sel_dbg &= ~(1 << VPP_MATRIX_1); + } else if (mtx_sel & (1 << VPP_MATRIX_2)) { + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 0, 8, 3); + mtx_sel_dbg &= ~(1 << VPP_MATRIX_2); + } else if (mtx_sel & (1 << VPP_MATRIX_3)) { + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 1, 6, 1); + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 3, 8, 3); + mtx_sel_dbg &= ~(1 << VPP_MATRIX_3); + } + /*coef_sel 1: 10bit yuvl2rgb 2:rgb2yuvl*/ + /*coef_sel 3: 12bit yuvl2rgb 4:rgb2yuvl*/ + if (coef_sel == 1) { + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04A80000); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x072C04A8); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1F261DDD); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x04A80876); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x0); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0xfc00e00); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0e00); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } else if (coef_sel == 2) { + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x00bb0275); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x003f1f99); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1ea601c2); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x01c21e67); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x00001fd7); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x00400200); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x00000200); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } else if (coef_sel == 3) { + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x04A80000); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x072C04A8); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1F261DDD); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x04A80876); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x0); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x8000800); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x800); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x7000000); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0000); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } else if (coef_sel == 4) { + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, 0x00bb0275); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, 0x003f1f99); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, 0x1ea601c2); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, 0x01c21e67); + WRITE_VPP_REG(VPP_MATRIX_COEF22, 0x00001fd7); + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, 0x01000000); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, 0x00000000); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, 0x0); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, 0x0); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, 0, 5, 3); + } +} +static void vpp_clip_config(unsigned int mode_sel, unsigned int color, + unsigned int color_mode) +{ + unsigned int addr_cliptop, addr_clipbot, value_cliptop, value_clipbot; + + if (mode_sel == 0) {/*vd1*/ + addr_cliptop = VPP_VD1_CLIP_MISC0; + addr_clipbot = VPP_VD1_CLIP_MISC1; + } else if (mode_sel == 1) {/*vd2*/ + addr_cliptop = VPP_VD2_CLIP_MISC0; + addr_clipbot = VPP_VD2_CLIP_MISC1; + } else if (mode_sel == 2) {/*xvycc*/ + addr_cliptop = VPP_XVYCC_MISC0; + addr_clipbot = VPP_XVYCC_MISC1; + } else if (mode_sel == 3) {/*final clip*/ + addr_cliptop = VPP_CLIP_MISC0; + addr_clipbot = VPP_CLIP_MISC1; + } else { + addr_cliptop = mode_sel; + addr_clipbot = mode_sel + 1; + } + if (color == 0) {/*default*/ + value_cliptop = 0x3fffffff; + value_clipbot = 0x0; + } else if (color == 1) {/*Blue*/ + if (color_mode == 0) {/*yuv*/ + value_cliptop = (0x29 << 22) | (0xf0 << 12) | + (0x6e << 2); + value_clipbot = (0x29 << 22) | (0xf0 << 12) | + (0x6e << 2); + } else {/*RGB*/ + value_cliptop = 0xFF << 2; + value_clipbot = 0xFF << 2; + } + } else if (color == 2) {/*Black*/ + if (color_mode == 0) {/*yuv*/ + value_cliptop = (0x10 << 22) | (0x80 << 12) | + (0x80 << 2); + value_clipbot = (0x10 << 22) | (0x80 << 12) | + (0x80 << 2); + } else { + value_cliptop = 0; + value_clipbot = 0; + } + } else { + value_cliptop = color; + value_clipbot = color; + } + WRITE_VPP_REG(addr_cliptop, value_cliptop); + WRITE_VPP_REG(addr_clipbot, value_clipbot); +} + static const char *amvecm_debug_usage_str = { "Usage:\n" - "echo vpp_size > /sys/class/amvecm/debug ; get vpp size config\n" + "echo vpp_size > /sys/class/amvecm/debug; get vpp size config\n" + "echo wb enable > /sys/class/amvecm/debug\n" + "echo wb disable > /sys/class/amvecm/debug\n" + "echo gama enable > /sys/class/amvecm/debug\n" + "echo gama disable > /sys/class/amvecm/debug\n" + "echo sr peaking_en > /sys/class/amvecm/debug\n" + "echo sr peaking_dis > /sys/class/amvecm/debug\n" + "echo sr lcti_en > /sys/class/amvecm/debug\n" + "echo sr lcti_dis > /sys/class/amvecm/debug\n" + "echo sr dejaggy_en > /sys/class/amvecm/debug\n" + "echo sr dejaggy_dis > /sys/class/amvecm/debug\n" + "echo sr dering_en > /sys/class/amvecm/debug\n" + "echo sr dering_dis > /sys/class/amvecm/debug\n" + "echo sr derec_en > /sys/class/amvecm/debug\n" + "echo sr derec_dis > /sys/class/amvecm/debug\n" + "echo sr theta_en > /sys/class/amvecm/debug\n" + "echo sr theta_dis > /sys/class/amvecm/debug\n" + "echo sr deband_en > /sys/class/amvecm/debug\n" + "echo sr deband_dis > /sys/class/amvecm/debug\n" + "echo cm enable > /sys/class/amvecm/debug\n" + "echo cm disable > /sys/class/amvecm/debug\n" + "echo dnlp enable > /sys/class/amvecm/debug\n" + "echo dnlp disable > /sys/class/amvecm/debug\n" + "echo vpp_pq enable > /sys/class/amvecm/debug\n" + "echo vpp_pq disable > /sys/class/amvecm/debug\n" + + "echo vpp_mtx xvycc_10 rgb2yuv > /sys/class/amvecm/debug; 10bit xvycc mtx\n" + "echo vpp_mtx xvycc_10 yuv2rgb > /sys/class/amvecm/debug; 10bit xvycc mtx\n" + "echo vpp_mtx post_10 rgb2yuv > /sys/class/amvecm/debug; 10bit post mtx\n" + "echo vpp_mtx post_10 yuv2rgb > /sys/class/amvecm/debug; 10bit post mtx\n" + "echo vpp_mtx vd1_10 rgb2yuv > /sys/class/amvecm/debug; 10bit vd1 mtx\n" + "echo vpp_mtx vd1_10 yuv2rgb > /sys/class/amvecm/debug; 10bit vd1 mtx\n" + "echo vpp_mtx xvycc_12 rgb2yuv > /sys/class/amvecm/debug; 12bit xvycc mtx\n" + "echo vpp_mtx xvycc_12 yuv2rgb > /sys/class/amvecm/debug; 12bit xvycc mtx\n" + "echo vpp_mtx post_12 rgb2yuv > /sys/class/amvecm/debug; 12bit post mtx\n" + "echo vpp_mtx post_12 yuv2rgb > /sys/class/amvecm/debug; 12bit post mtx\n" + "echo vpp_mtx vd1_12 rgb2yuv > /sys/class/amvecm/debug; 12bit vd1 mtx\n" + "echo vpp_mtx vd1_12 yuv2rgb > /sys/class/amvecm/debug; 12bit vd1 mtx\n" + "echo dolby_config 0/1/2.. > /sys/class/amvecm/debug; dolby dma table config\n" + "echo dolby_crc 0/1 > /sys/class/amvecm/debug; dolby_crc insert or clr\n" + "echo datapath_config param1(D) param2(D) > /sys/class/amvecm/debug; config data path\n" + "echo datapath_status > /sys/class/amvecm/debug; data path status\n" + "echo dolby_dma index(D) value(H) > /sys/class/amvecm/debug; dolby dma table modify\n" + "echo clip_config 0/1/2/.. 0/1/... 0/1 > /sys/class/amvecm/debug; config clip\n" + "echo dv_efuse > /sys/class/amvecm/debug; get dv efuse info\n" + "echo dv_el > /sys/class/amvecm/debug; get dv enhanced layer info\n" }; static ssize_t amvecm_debug_show(struct class *cla, struct class_attribute *attr, char *buf) @@ -2602,6 +3362,8 @@ static ssize_t amvecm_debug_store(struct class *cla, const char *buf, size_t count) { char *buf_orig, *parm[8] = {NULL}; + long val = 0; + unsigned int mode_sel, color, color_mode; if (!buf) return count; @@ -2609,25 +3371,7 @@ static ssize_t amvecm_debug_store(struct class *cla, parse_param_amvecm(buf_orig, (char **)&parm); if (!strncmp(parm[0], "vpp_size", 8)) dump_vpp_size_info(); - else if (!strncmp(parm[0], "4k_enhance", 10)) { - if (!strncmp(parm[1], "core0", 5)) { - if (!strncmp(parm[2], "00", 2)) { - vpp_sr3_enhance_enable(0x0); - pr_info("disable core0 sr3 dering/dejaggy/direction\n"); - } else if (!strncmp(parm[2], "01", 2)) { - vpp_sr3_enhance_enable(0x1); - pr_info("enable core0 sr3 dering/dejaggy/direction\n"); - } - } else if (!strncmp(parm[1], "core1", 2)) { - if (!strncmp(parm[2], "10", 2)) { - vpp_sr3_enhance_enable(0x10); - pr_info("disable core1 sr3 dering/dejaggy/direction\n"); - } else if (!strncmp(parm[2], "11", 2)) { - vpp_sr3_enhance_enable(0x11); - pr_info("enable core1 sr3 dering/dejaggy/direction\n"); - } - } - } else if (!strncmp(parm[0], "wb", 2)) { + else if (!strncmp(parm[0], "wb", 2)) { if (!strncmp(parm[1], "enable", 6)) { amvecm_wb_enable(1); pr_info("enable wb\n"); @@ -2656,6 +3400,42 @@ static ssize_t amvecm_debug_store(struct class *cla, } else if (!strncmp(parm[1], "lcti_dis", 8)) { amvecm_sharpness_debug(3); pr_info("disable lti cti\n"); + } else if (!strncmp(parm[1], "theta_en", 8)) { + amvecm_sharpness_debug(4); + pr_info("SR4 enable drtlpf theta\n"); + } else if (!strncmp(parm[1], "theta_dis", 9)) { + amvecm_sharpness_debug(5); + pr_info("SR4 disable drtlpf theta\n"); + } else if (!strncmp(parm[1], "deband_en", 9)) { + amvecm_sharpness_debug(6); + pr_info("SR4 enable debanding\n"); + } else if (!strncmp(parm[1], "deband_dis", 10)) { + amvecm_sharpness_debug(7); + pr_info("SR4 disable debanding\n"); + } else if (!strncmp(parm[1], "dejaggy_en", 10)) { + amvecm_sr0_dejaggy_enable(true); + amvecm_sr1_dejaggy_enable(true); + pr_info("SR3 enable dejaggy\n"); + } else if (!strncmp(parm[1], "dejaggy_dis", 11)) { + amvecm_sr0_dejaggy_enable(false); + amvecm_sr1_dejaggy_enable(false); + pr_info("SR3 disable dejaggy\n"); + } else if (!strncmp(parm[1], "dering_en", 9)) { + amvecm_sr0_dering_enable(true); + amvecm_sr1_dering_enable(true); + pr_info("SR3 enable dering\n"); + } else if (!strncmp(parm[1], "dering_dis", 10)) { + amvecm_sr0_dering_enable(false); + amvecm_sr1_dering_enable(false); + pr_info("SR3 disable dering\n"); + } else if (!strncmp(parm[1], "derec_en", 8)) { + amvecm_sr0_derection_enable(true); + amvecm_sr1_derection_enable(true); + pr_info("SR3 enable derection\n"); + } else if (!strncmp(parm[1], "derec_dis", 9)) { + amvecm_sr0_derection_enable(false); + amvecm_sr1_derection_enable(false); + pr_info("SR3 disable derection\n"); } } else if (!strncmp(parm[0], "cm", 2)) { if (!strncmp(parm[1], "enable", 6)) { @@ -2681,6 +3461,105 @@ static ssize_t amvecm_debug_store(struct class *cla, amvecm_pq_enable(0); pr_info("disable vpp_pq\n"); } + } else if (!strncmp(parm[0], "vpp_mtx", 7)) { + if (!strncmp(parm[1], "vd1_10", 6)) { + mtx_sel_dbg |= 1 << VPP_MATRIX_1; + if (!strncmp(parm[2], "yuv2rgb", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 1); + pr_info("10bit vd1 mtx yuv2rgb\n"); + } else if (!strncmp(parm[2], "rgb2yuv", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 2); + pr_info("10bit vd1 mtx rgb2yuv\n"); + } + } else if (!strncmp(parm[1], "post_10", 7)) { + mtx_sel_dbg |= 1 << VPP_MATRIX_2; + if (!strncmp(parm[2], "yuv2rgb", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 1); + pr_info("10bit post mtx yuv2rgb\n"); + } else if (!strncmp(parm[2], "rgb2yuv", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 2); + pr_info("10bit post mtx rgb2yuv\n"); + } + } else if (!strncmp(parm[1], "xvycc_10", 8)) { + mtx_sel_dbg |= 1 << VPP_MATRIX_3; + if (!strncmp(parm[2], "yuv2rgb", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 1); + pr_info("10bit xvycc mtx yuv2rgb\n"); + } else if (!strncmp(parm[2], "rgb2yuv", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 2); + pr_info("10bit xvycc mtx rgb2yuv\n"); + } + } else if (!strncmp(parm[1], "vd1_12", 6)) { + mtx_sel_dbg |= 1 << VPP_MATRIX_1; + if (!strncmp(parm[2], "yuv2rgb", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 3); + pr_info("1wbit vd1 mtx yuv2rgb\n"); + } else if (!strncmp(parm[2], "rgb2yuv", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 4); + pr_info("1wbit vd1 mtx rgb2yuv\n"); + } + } else if (!strncmp(parm[1], "post_12", 7)) { + mtx_sel_dbg |= 1 << VPP_MATRIX_2; + if (!strncmp(parm[2], "yuv2rgb", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 3); + pr_info("1wbit post mtx yuv2rgb\n"); + } else if (!strncmp(parm[2], "rgb2yuv", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 4); + pr_info("1wbit post mtx rgb2yuv\n"); + } + } else if (!strncmp(parm[1], "xvycc_12", 8)) { + mtx_sel_dbg |= 1 << VPP_MATRIX_3; + if (!strncmp(parm[2], "yuv2rgb", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 3); + pr_info("1wbit xvycc mtx yuv2rgb\n"); + } else if (!strncmp(parm[2], "rgb2yuv", 7)) { + amvecm_vpp_mtx_debug(mtx_sel_dbg, 4); + pr_info("1wbit xvycc mtx rgb2yuv\n"); + } + } + } else if (!strncmp(parm[0], "ve_dith", 7)) { + if (!strncmp(parm[1], "enable", 6)) { + amvecm_dither_enable(1); + pr_info("enable ve dither\n"); + } else if (!strncmp(parm[1], "disable", 7)) { + amvecm_dither_enable(0); + pr_info("disable ve dither\n"); + } else if (!strncmp(parm[1], "rd_en", 5)) { + amvecm_dither_enable(3); + pr_info("enable ve round dither\n"); + } else if (!strncmp(parm[1], "rd_dis", 6)) { + amvecm_dither_enable(2); + pr_info("disable ve round dither\n"); + } + } else if (!strcmp(parm[0], "clip_config")) { + if (parm[1]) { + if (kstrtoul(parm[1], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + mode_sel = val; + } else + mode_sel = 0; + if (parm[2]) { + if (kstrtoul(parm[2], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + color = val; + } else + color = 0; + if (parm[3]) { + if (kstrtoul(parm[3], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + color_mode = val; + } else + color_mode = 0; + vpp_clip_config(mode_sel, color, color_mode); + pr_info("vpp_clip_config done!\n"); + } else { + pr_info("unsupport cmd\n"); } kfree(buf_orig); @@ -2716,7 +3595,7 @@ static ssize_t amvecm_dv_mode_show(struct class *cla, pr_info("\tDOLBY_VISION_OUTPUT_MODE_HDR10 3\n"); pr_info("\tDOLBY_VISION_OUTPUT_MODE_SDR10 4\n"); pr_info("\tDOLBY_VISION_OUTPUT_MODE_SDR8 5\n"); - if (is_meson_gxm_cpu() && is_dolby_vision_enable()) + if (is_dolby_vision_enable()) pr_info("current dv_mode = %s\n", dv_mode_str[get_dolby_vision_mode()]); else @@ -2731,17 +3610,16 @@ static ssize_t amvecm_dv_mode_store(struct class *cla, size_t r; int val; - if (is_meson_gxm_cpu()) { - r = sscanf(buf, "0x%x", &val); - if ((r != 1)) - return -EINVAL; - if ((val >= 0) && (val < 6)) - set_dolby_vision_mode(dv_mode_table[val]); - else if (val & 0x200) - dolby_vision_dump_struct(); - else if (val & 0x70) - dolby_vision_dump_setting(val); - } + r = sscanf(buf, "%x\n", &val); + if ((r != 1)) + return -EINVAL; + + if ((val >= 0) && (val < 6)) + set_dolby_vision_mode(dv_mode_table[val]); + else if (val & 0x200) + dolby_vision_dump_struct(); + else if (val & 0x70) + dolby_vision_dump_setting(val); return count; } @@ -2837,17 +3715,19 @@ static ssize_t amvecm_reg_store(struct class *cla, return count; } + /* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ -void init_sharpness(void) +void init_pq_setting(void) { /*probe close sr0 peaking for switch on video*/ WRITE_VPP_REG_BITS(VPP_SRSHARP0_CTRL, 1, 0, 1); - /*WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 1,0,1);*/ - WRITE_VPP_REG_BITS(SRSHARP0_SHARP_PK_NR_ENABLE, 0, 1, 1); - WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 1, 0, 1); - - if (is_meson_txl_cpu()) { + /*default dnlp off*/ + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 0, DNLP_EN_BIT, DNLP_EN_WID); + /*end*/ + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP, 2, 16, 2); /*sr0 sr1 chroma filter bypass*/ @@ -2870,13 +3750,13 @@ static void amvecm_gamma_init(bool en) for (i = 0; i < 256; i++) data[i] = i << 2; - init_write_gamma_table( + amve_write_gamma_table( data, H_SEL_R); - init_write_gamma_table( + amve_write_gamma_table( data, H_SEL_G); - init_write_gamma_table( + amve_write_gamma_table( data, H_SEL_B); } @@ -2884,13 +3764,60 @@ static void amvecm_gamma_init(bool en) static void amvecm_wb_init(bool en) { if (en) { - WRITE_VPP_REG(VPP_GAINOFF_CTRL0, - (1024 << 16) | 1024); - WRITE_VPP_REG(VPP_GAINOFF_CTRL1, - (1024 << 16)); + if (video_rgb_ogo_xvy_mtx) { + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 3, 8, 3); + + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET0_1, + ((wb_init_bypass_coef[0] & 0xfff) << 16) + | (wb_init_bypass_coef[1] & 0xfff)); + WRITE_VPP_REG(VPP_MATRIX_PRE_OFFSET2, + wb_init_bypass_coef[2] & 0xfff); + WRITE_VPP_REG(VPP_MATRIX_COEF00_01, + ((wb_init_bypass_coef[3] & 0x1fff) << 16) + | (wb_init_bypass_coef[4] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF02_10, + ((wb_init_bypass_coef[5] & 0x1fff) << 16) + | (wb_init_bypass_coef[6] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF11_12, + ((wb_init_bypass_coef[7] & 0x1fff) << 16) + | (wb_init_bypass_coef[8] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF20_21, + ((wb_init_bypass_coef[9] & 0x1fff) << 16) + | (wb_init_bypass_coef[10] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF22, + wb_init_bypass_coef[11] & 0x1fff); + if (wb_init_bypass_coef[21]) { + WRITE_VPP_REG(VPP_MATRIX_COEF13_14, + ((wb_init_bypass_coef[12] & 0x1fff) << 16) + | (wb_init_bypass_coef[13] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF15_25, + ((wb_init_bypass_coef[14] & 0x1fff) << 16) + | (wb_init_bypass_coef[17] & 0x1fff)); + WRITE_VPP_REG(VPP_MATRIX_COEF23_24, + ((wb_init_bypass_coef[15] & 0x1fff) << 16) + | (wb_init_bypass_coef[16] & 0x1fff)); + } + WRITE_VPP_REG(VPP_MATRIX_OFFSET0_1, + ((wb_init_bypass_coef[18] & 0xfff) << 16) + | (wb_init_bypass_coef[19] & 0xfff)); + WRITE_VPP_REG(VPP_MATRIX_OFFSET2, + wb_init_bypass_coef[20] & 0xfff); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, + wb_init_bypass_coef[21], 3, 2); + WRITE_VPP_REG_BITS(VPP_MATRIX_CLIP, + wb_init_bypass_coef[22], 5, 3); + } else { + WRITE_VPP_REG(VPP_GAINOFF_CTRL0, + (1024 << 16) | 1024); + WRITE_VPP_REG(VPP_GAINOFF_CTRL1, + (1024 << 16)); + } } - WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, en, 31, 1); + if (video_rgb_ogo_xvy_mtx) + WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, en, 6, 1); + else + WRITE_VPP_REG_BITS(VPP_GAINOFF_CTRL0, en, 31, 1); } static struct class_attribute amvecm_class_attrs[] = { @@ -2898,6 +3825,9 @@ static struct class_attribute amvecm_class_attrs[] = { amvecm_debug_show, amvecm_debug_store), __ATTR(dnlp, 0644, amvecm_dnlp_show, amvecm_dnlp_store), + __ATTR(dnlp_curve, 0644, + amvecm_dnlp_curve_show, + amvecm_dnlp_curve_store), __ATTR(brightness, 0644, amvecm_brightness_show, amvecm_brightness_store), __ATTR(contrast, 0644, @@ -2914,6 +3844,9 @@ static struct class_attribute amvecm_class_attrs[] = { __ATTR(cm2, 0644, amvecm_cm2_show, amvecm_cm2_store), + __ATTR(cm_reg, 0644, + amvecm_cm_reg_show, + amvecm_cm_reg_store), __ATTR(gamma, 0644, amvecm_gamma_show, amvecm_gamma_store), @@ -2968,9 +3901,29 @@ static struct class_attribute amvecm_class_attrs[] = { amvecm_dv_mode_show, amvecm_dv_mode_store), __ATTR(reg, 0644, amvecm_reg_show, amvecm_reg_store), + __ATTR(pq_user_set, 0644, + amvecm_pq_user_show, amvecm_pq_user_store), __ATTR_NULL }; +void amvecm_wakeup_queue(void) +{ + struct amvecm_dev_s *devp = &amvecm_dev; + + wake_up(&devp->hdr_queue); +} + +static unsigned int amvecm_poll(struct file *file, poll_table *wait) +{ + struct amvecm_dev_s *devp = file->private_data; + unsigned int mask = 0; + + poll_wait(file, &devp->hdr_queue, wait); + mask = (POLLIN | POLLRDNORM); + + return mask; +} + static const struct file_operations amvecm_fops = { .owner = THIS_MODULE, .open = amvecm_open, @@ -2979,6 +3932,7 @@ static const struct file_operations amvecm_fops = { #ifdef CONFIG_COMPAT .compat_ioctl = amvecm_compat_ioctl, #endif + .poll = amvecm_poll, }; static void aml_vecm_dt_parse(struct platform_device *pdev) { @@ -3004,6 +3958,11 @@ static void aml_vecm_dt_parse(struct platform_device *pdev) pr_info("Can't find cm_en.\n"); else cm_en = val; + ret = of_property_read_u32(node, "wb_sel", &val); + if (ret) + pr_info("Can't find wb_sel.\n"); + else + video_rgb_ogo_xvy_mtx = val; } /* init module status */ amvecm_wb_init(wb_en); @@ -3082,15 +4041,19 @@ static int aml_vecm_probe(struct platform_device *pdev) if (ret) pr_info("register aml_lcd_gamma_notifier failed\n"); #endif - - amvecm_hiu_reg_base = ioremap(HIU_REG_BASE, 0x2000); - /* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ - if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) - init_sharpness(); + if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu() + || is_meson_txlx_cpu()) + init_pq_setting(); /* #endif */ vpp_get_hist_en(); + if (is_meson_txlx_cpu()) { + /*vpp_set_12bit_datapath2();*/ + /*post matrix 12bit yuv2rgb*/ + /* mtx_sel_dbg |= 1 << VPP_MATRIX_2; */ + /* amvecm_vpp_mtx_debug(mtx_sel_dbg, 1);*/ + } memset(&vpp_hist_param.vpp_histgram[0], 0, sizeof(unsigned short) * 64); /* box sdr_mode:auto, tv sdr_mode:off */ @@ -3103,6 +4066,18 @@ static int aml_vecm_probe(struct platform_device *pdev) sdr_mode = 0; hdr_flag = (1 << 0) | (1 << 1) | (0 << 2) | (0 << 3); } + /*config vlock mode*/ + /*todo:txlx & g9tv support auto pll,*/ + /*but support not good,need vlsi support optimize*/ + if (is_meson_txlx_cpu()) + vlock_mode = VLOCK_MODE_MANUAL_PLL; + else + vlock_mode = VLOCK_MODE_MANUAL_PLL; + if (is_meson_gxtvbb_cpu() || + is_meson_txl_cpu() || is_meson_txlx_cpu()) + vlock_en = 1; + else + vlock_en = 0; aml_vecm_dt_parse(pdev); if (is_meson_gxm_cpu()) dolby_vision_init_receiver(); @@ -3134,7 +4109,6 @@ fail_alloc_region: static int __exit aml_vecm_remove(struct platform_device *pdev) { struct amvecm_dev_s *devp = &amvecm_dev; - device_destroy(devp->clsp, devp->devno); cdev_del(&devp->cdev); class_destroy(devp->clsp); @@ -3192,8 +4166,15 @@ static struct platform_driver aml_vecm_driver = { static int __init aml_vecm_init(void) { - pr_info("module init\n"); + unsigned int hiu_reg_base; + + pr_info("%s:module init\n", __func__); /* remap the hiu bus */ + if (is_meson_txlx_cpu()) + hiu_reg_base = 0xff63c000; + else + hiu_reg_base = 0xc883c000; + amvecm_hiu_reg_base = ioremap(hiu_reg_base, 0x2000); if (platform_driver_register(&aml_vecm_driver)) { pr_err("failed to register bl driver module\n"); return -ENODEV; @@ -3204,7 +4185,8 @@ static int __init aml_vecm_init(void) static void __exit aml_vecm_exit(void) { - pr_info("module exit\n"); + pr_info("%s:module exit\n", __func__); + iounmap(amvecm_hiu_reg_base); platform_driver_unregister(&aml_vecm_driver); } diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h b/drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h index ca433e4cb243..f1df9884ac49 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h +++ b/drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h @@ -57,16 +57,16 @@ static struct am_regs_s vlock_pll_in50hz_out60hz = { {REG_TYPE_VCBUS, 0x3000, 0xffffffff, 0x07f13f1b }, {REG_TYPE_VCBUS, 0x3001, 0xffffffff, 0x04053c32 }, {REG_TYPE_VCBUS, 0x3002, 0xffffffff, 0x06000000 }, - {REG_TYPE_VCBUS, 0x3003, 0xffffffff, 0x2055c55c }, - {REG_TYPE_VCBUS, 0x3004, 0xffffffff, 0x0065c65c }, + {REG_TYPE_VCBUS, 0x3003, 0xffffffff, 0x20680680 }, + {REG_TYPE_VCBUS, 0x3004, 0xffffffff, 0x00000000 }, {REG_TYPE_VCBUS, 0x3005, 0xffffffff, 0x00080000 }, {REG_TYPE_VCBUS, 0x3006, 0xffffffff, 0x00070000 }, {REG_TYPE_VCBUS, 0x3007, 0xffffffff, 0x00000000 }, {REG_TYPE_VCBUS, 0x3008, 0xffffffff, 0x00000000 }, {REG_TYPE_VCBUS, 0x3009, 0xffffffff, 0x00100000 }, - {REG_TYPE_VCBUS, 0x300a, 0xffffffff, 0x00100000 }, + {REG_TYPE_VCBUS, 0x300a, 0xffffffff, 0x00004000 }, {REG_TYPE_VCBUS, 0x300b, 0xffffffff, 0x00100000 }, - {REG_TYPE_VCBUS, 0x300c, 0xffffffff, 0x00010000 }, + {REG_TYPE_VCBUS, 0x300c, 0xffffffff, 0x00000000 }, {REG_TYPE_VCBUS, 0x300d, 0xffffffff, 0x00004000 }, {REG_TYPE_VCBUS, 0x3010, 0xffffffff, 0x20001000 }, {REG_TYPE_VCBUS, 0x3016, 0xffffffff, 0x0003de00 }, diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h index 5521250baf8f..cc7f97bd3e50 100644 --- a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h +++ b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h @@ -149,6 +149,7 @@ #define VPP_VE_DEMO_CENTER_BAR 0x1da3 #define VPP_VE_H_V_SIZE 0x1da4 #define VPP_PSR_H_V_SIZE 0x1da5 +#define VPP_OUT_H_V_SIZE 0x1da5 #define VPP_VDO_MEAS_CTRL 0x1da8 #define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 #define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa @@ -203,6 +204,14 @@ #define VPP_VD2_CLIP_MISC0 0x1de3 #define VPP_VD2_CLIP_MISC1 0x1de4 +/*txlx new add*/ +#define VPP_DAT_CONV_PARA0 0x1d94 +#define VPP_DAT_CONV_PARA1 0x1d95 + +#define VD1_IF0_GEN_REG3 0x1aa7 +#define VD2_IF0_GEN_REG3 0x1aa8 + + #define VPP2_DUMMY_DATA 0x1900 #define VPP2_LINE_IN_LENGTH 0x1901 #define VPP2_PIC_IN_HEIGHT 0x1902 @@ -442,16 +451,15 @@ #define VIU_EOTF_COEF11_12 0x31d3 #define VIU_EOTF_COEF20_21 0x31d4 #define VIU_EOTF_COEF22_RS 0x31d5 -#define VIU_EOTF_LUT_ADDR_PORT 0x31d6 -#define VIU_EOTF_LUT_DATA_PORT 0x31d7 +#define VIU_EOTF_LUT_ADDR_PORT 0x31d6 +#define VIU_EOTF_LUT_DATA_PORT 0x31d7 +#define VIU_EOTF_3X3_OFST_0 0x31d8 +#define VIU_EOTF_3X3_OFST_1 0x31d9 /* sharpness */ #define SRSHARP0_PK_FINALGAIN_HP_BP 0x3222 -#define SRSHARP0_SHARP_PK_NR_ENABLE 0x3227 +#define SRSHARP0_PK_NR_ENABLE 0x3227 #define SRSHARP0_SHARP_DNLP_EN 0x3245 -#define SRSHARP1_PK_FINALGAIN_HP_BP 0x32a2 -#define SRSHARP1_SHARP_PK_NR_ENABLE 0x32a7 -#define SRSHARP1_SHARP_DNLP_EN 0x32c5 /*sr0 sr1 ybic cbic*/ #define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 0x3258 @@ -459,30 +467,167 @@ #define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 0x325c #define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 0x325e -#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 0x32d8 -#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 0x32da -#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 0x32dc -#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 0x32de - /*sr0 sr1 lti cti*/ #define SRSHARP0_HCTI_FLT_CLP_DC 0x322e/*bit28*/ #define SRSHARP0_HLTI_FLT_CLP_DC 0x3234 #define SRSHARP0_VLTI_FLT_CON_CLP 0x323a/*bit14*/ #define SRSHARP0_VCTI_FLT_CON_CLP 0x323f -#define SRSHARP1_HCTI_FLT_CLP_DC 0x32ae/*bit28*/ -#define SRSHARP1_HLTI_FLT_CLP_DC 0x32b4 -#define SRSHARP1_VLTI_FLT_CON_CLP 0x32ba/*bit14*/ -#define SRSHARP1_VCTI_FLT_CON_CLP 0x32bf - /*sr0 sr1 dejaggy/direction/dering*/ #define SRSHARP0_DEJ_CTRL 0x3264/*bit 0*/ #define SRSHARP0_SR3_DRTLPF_EN 0x3266/*bit 0-2*/ #define SRSHARP0_SR3_DERING_CTRL 0x326b/*bit 28-30*/ -#define SRSHARP1_DEJ_CTRL 0x32e4/*bit 0*/ -#define SRSHARP1_SR3_DRTLPF_EN 0x32e6/*bit 0-2*/ -#define SRSHARP1_SR3_DERING_CTRL 0x32eb/*bit 28-30*/ +/*sr4 add*/ +#define SRSHARP0_SR3_DRTLPF_THETA 0x3273 +#define SRSHARP0_SATPRT_CTRL 0x3274 +#define SRSHARP0_SATPRT_DIVM 0x3275 +#define SRSHARP0_SATPRT_LMT_RGB 0x3276 +#define SRSHARP0_DB_FLT_CTRL 0x3277 +#define SRSHARP0_DB_FLT_YC_THRD 0x3278 +#define SRSHARP0_DB_FLT_RANDLUT 0x3279 +#define SRSHARP0_DB_FLT_PXI_THRD 0x327a +#define SRSHARP0_DB_FLT_SEED_Y 0x327b +#define SRSHARP0_DB_FLT_SEED_U 0x327c +#define SRSHARP0_DB_FLT_SEED_V 0x327d +#define SRSHARP0_PKGAIN_VSLUMA_LUT_L 0x327e +#define SRSHARP0_PKGAIN_VSLUMA_LUT_H 0x327f +#define SRSHARP0_PKOSHT_VSLUMA_LUT_L 0x3203 +#define SRSHARP0_PKOSHT_VSLUMA_LUT_H 0x3204 + + +/*sharpness reg*/ +#define SRSHARP1_SHARP_HVSIZE 0x3280 +#define SRSHARP1_SHARP_HVBLANK_NUM 0x3281 +#define SRSHARP1_NR_GAUSSIAN_MODE 0x3282 +#define SRSHARP1_PK_CON_2CIRHPGAIN_TH_RATE 0x3285 +#define SRSHARP1_PK_CON_2CIRHPGAIN_LIMIT 0x3286 +#define SRSHARP1_PK_CON_2CIRBPGAIN_TH_RATE 0x3287 +#define SRSHARP1_PK_CON_2CIRBPGAIN_LIMIT 0x3288 +#define SRSHARP1_PK_CON_2DRTHPGAIN_TH_RATE 0x3289 +#define SRSHARP1_PK_CON_2DRTHPGAIN_LIMIT 0x328a +#define SRSHARP1_PK_CON_2DRTBPGAIN_TH_RATE 0x328b +#define SRSHARP1_PK_CON_2DRTBPGAIN_LIMIT 0x328c +#define SRSHARP1_PK_CIRFB_LPF_MODE 0x328d +#define SRSHARP1_PK_DRTFB_LPF_MODE 0x328e +#define SRSHARP1_PK_CIRFB_HP_CORING 0x328f +#define SRSHARP1_PK_CIRFB_BP_CORING 0x3290 +#define SRSHARP1_PK_DRTFB_HP_CORING 0x3291 +#define SRSHARP1_PK_DRTFB_BP_CORING 0x3292 +#define SRSHARP1_PK_CIRFB_BLEND_GAIN 0x3293 +#define SRSHARP1_NR_ALPY_SSD_GAIN_OFST 0x3294 +#define SRSHARP1_NR_ALP0Y_ERR2CURV_TH_RATE 0x3295 +#define SRSHARP1_NR_ALP0Y_ERR2CURV_LIMIT 0x3296 +#define SRSHARP1_NR_ALP0C_ERR2CURV_TH_RATE 0x3297 +#define SRSHARP1_NR_ALP0C_ERR2CURV_LIMIT 0x3298 +#define SRSHARP1_NR_ALP0_MIN_MAX 0x3299 +#define SRSHARP1_NR_ALP1_MIERR_CORING 0x329a +#define SRSHARP1_NR_ALP1_ERR2CURV_TH_RATE 0x329b +#define SRSHARP1_NR_ALP1_ERR2CURV_LIMIT 0x329c +#define SRSHARP1_NR_ALP1_MIN_MAX 0x329d +#define SRSHARP1_PK_ALP2_MIERR_CORING 0x329e +#define SRSHARP1_PK_ALP2_ERR2CURV_TH_RATE 0x329f +#define SRSHARP1_PK_ALP2_ERR2CURV_LIMIT 0x32a0 +#define SRSHARP1_PK_ALP2_MIN_MAX 0x32a1 +#define SRSHARP1_PK_FINALGAIN_HP_BP 0x32a2 +#define SRSHARP1_PK_OS_HORZ_CORE_GAIN 0x32a3 +#define SRSHARP1_PK_OS_VERT_CORE_GAIN 0x32a4 +#define SRSHARP1_PK_OS_ADPT_MISC 0x32a5 +#define SRSHARP1_PK_OS_STATIC 0x32a6 +#define SRSHARP1_PK_NR_ENABLE 0x32a7 +#define SRSHARP1_PK_DRT_SAD_MISC 0x32a8 +#define SRSHARP1_NR_TI_DNLP_BLEND 0x32a9 +#define SRSHARP1_TI_DIR_CORE_ALPHA 0x32aa +#define SRSHARP1_CTI_DIR_ALPHA 0x32ab +#define SRSHARP1_LTI_CTI_DF_GAIN 0x32ac +#define SRSHARP1_LTI_CTI_DIR_AC_DBG 0x32ad +#define SRSHARP1_HCTI_FLT_CLP_DC 0x32ae +#define SRSHARP1_HCTI_BST_GAIN 0x32af +#define SRSHARP1_HCTI_BST_CORE 0x32b0 +#define SRSHARP1_HCTI_CON_2_GAIN_0 0x32b1 +#define SRSHARP1_HCTI_CON_2_GAIN_1 0x32b2 +#define SRSHARP1_HCTI_OS_MARGIN 0x32b3 +#define SRSHARP1_HLTI_FLT_CLP_DC 0x32b4 +#define SRSHARP1_HLTI_BST_GAIN 0x32b5 +#define SRSHARP1_HLTI_BST_CORE 0x32b6 +#define SRSHARP1_HLTI_CON_2_GAIN_0 0x32b7 +#define SRSHARP1_HLTI_CON_2_GAIN_1 0x32b8 +#define SRSHARP1_HLTI_OS_MARGIN 0x32b9 +#define SRSHARP1_VLTI_FLT_CON_CLP 0x32ba +#define SRSHARP1_VLTI_BST_GAIN 0x32bb +#define SRSHARP1_VLTI_BST_CORE 0x32bc +#define SRSHARP1_VLTI_CON_2_GAIN_0 0x32bd +#define SRSHARP1_VLTI_CON_2_GAIN_1 0x32be +#define SRSHARP1_VCTI_FLT_CON_CLP 0x32bf +#define SRSHARP1_VCTI_BST_GAIN 0x32c0 +#define SRSHARP1_VCTI_BST_CORE 0x32c1 +#define SRSHARP1_VCTI_CON_2_GAIN_0 0x32c2 +#define SRSHARP1_VCTI_CON_2_GAIN_1 0x32c3 +#define SRSHARP1_SHARP_3DLIMIT 0x32c4 +#define SRSHARP1_DNLP_EN 0x32c5 +#define SRSHARP1_DNLP_00 0x32c6 +#define SRSHARP1_DNLP_01 0x32c7 +#define SRSHARP1_DNLP_02 0x32c8 +#define SRSHARP1_DNLP_03 0x32c9 +#define SRSHARP1_DNLP_04 0x32ca +#define SRSHARP1_DNLP_05 0x32cb +#define SRSHARP1_DNLP_06 0x32cc +#define SRSHARP1_DNLP_07 0x32cd +#define SRSHARP1_DNLP_08 0x32ce +#define SRSHARP1_DNLP_09 0x32cf +#define SRSHARP1_DNLP_10 0x32d0 +#define SRSHARP1_DNLP_11 0x32d1 +#define SRSHARP1_DNLP_12 0x32d2 +#define SRSHARP1_DNLP_13 0x32d3 +#define SRSHARP1_DNLP_14 0x32d4 +#define SRSHARP1_DNLP_15 0x32d5 +#define SRSHARP1_DEMO_CRTL 0x32d6 +#define SRSHARP1_SHARP_SR2_CTRL 0x32d7 +#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 0x32d8 +#define SRSHARP1_SHARP_SR2_YBIC_HCOEF1 0x32d9 +#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 0x32da +#define SRSHARP1_SHARP_SR2_CBIC_HCOEF1 0x32db +#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 0x32dc +#define SRSHARP1_SHARP_SR2_YBIC_VCOEF1 0x32dd +#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 0x32de +#define SRSHARP1_SHARP_SR2_CBIC_VCOEF1 0x32df +#define SRSHARP1_SHARP_SR2_MISC 0x32e0 +#define SRSHARP1_SR3_SAD_CTRL 0x32e1 +#define SRSHARP1_SR3_PK_CTRL0 0x32e2 +#define SRSHARP1_SR3_PK_CTRL1 0x32e3 +#define SRSHARP1_DEJ_CTRL 0x32e4 +#define SRSHARP1_DEJ_ALPHA 0x32e5 +#define SRSHARP1_SR3_DRTLPF_EN 0x32e6 +#define SRSHARP1_SR3_DRTLPF_ALPHA_0 0x32e7 +#define SRSHARP1_SR3_DRTLPF_ALPHA_1 0x32e8 +#define SRSHARP1_SR3_DRTLPF_ALPHA_2 0x32e9 +#define SRSHARP1_SR3_DRTLPF_ALPHA_OFST 0x32ea +#define SRSHARP1_SR3_DERING_CTRL 0x32eb +#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 0x32ec +#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 0x32ed +#define SRSHARP1_SR3_DERING_LUMA2PKOS_0TO3 0x32ee +#define SRSHARP1_SR3_DERING_LUMA2PKOS_4TO6 0x32ef +#define SRSHARP1_SR3_DERING_GAINVS_MADSAD 0x32f0 +#define SRSHARP1_SR3_DERING_GAINVS_VR2MAX 0x32f1 +#define SRSHARP1_SR3_DERING_PARAM0 0x32f2 +#define SRSHARP1_SR3_DRTLPF_THETA 0x32f3 +#define SRSHARP1_SATPRT_CTRL 0x32f4 +#define SRSHARP1_SATPRT_DIVM 0x32f5 +#define SRSHARP1_SATPRT_LMT_RGB 0x32f6 +#define SRSHARP1_DB_FLT_CTRL 0x32f7 +#define SRSHARP1_DB_FLT_YC_THRD 0x32f8 +#define SRSHARP1_DB_FLT_RANDLUT 0x32f9 +#define SRSHARP1_DB_FLT_PXI_THRD 0x32fa +#define SRSHARP1_DB_FLT_SEED_Y 0x32fb +#define SRSHARP1_DB_FLT_SEED_U 0x32fc +#define SRSHARP1_DB_FLT_SEED_V 0x32fd +#define SRSHARP1_PKGAIN_VSLUMA_LUT_L 0x32fe +#define SRSHARP1_PKGAIN_VSLUMA_LUT_H 0x32ff +#define SRSHARP1_PKOSHT_VSLUMA_LUT_L 0x3283 +#define SRSHARP1_PKOSHT_VSLUMA_LUT_H 0x3284 + +/*ve dither*/ +#define VPP_VE_DITHER_CTRL 0x3120 /* for pll bug */ #define HHI_HDMI_PLL_CNTL 0x10c8 diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c index 290090b3a79e..f971eb66cbc9 100644 --- a/drivers/amlogic/media/video_sink/video.c +++ b/drivers/amlogic/media/video_sink/video.c @@ -4603,7 +4603,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id) amlog_mask_if(toggle_cnt > 0, LOG_MASK_FRAMESKIP, "skipped\n"); -#if DEBUG_TMP + #if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) refresh_on_vs(vf); @@ -4613,7 +4613,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id) vf, CSC_FLAG_CHECK_OUTPUT) == 1) break; #endif - +#if DEBUG_TMP if (is_dolby_vision_enable() && dolby_vision_need_wait()) break; @@ -4724,6 +4724,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id) if (is_dolby_vision_enable() && dolby_vision_need_wait()) break; +#endif #if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) refresh_on_vs(vf); if (amvecm_on_vs( @@ -4731,7 +4732,6 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id) ? cur_dispbuf : NULL, vf, CSC_FLAG_CHECK_OUTPUT) == 1) break; -#endif #endif vf = video_vf_get(); if (!vf) @@ -4810,13 +4810,11 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id) #endif SET_FILTER: -#if DEBUG_TMP #if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) amvecm_on_vs( (cur_dispbuf != &vf_local) ? cur_dispbuf : NULL, toggle_frame, toggle_frame ? CSC_FLAG_TOGGLE_FRAME : 0); -#endif #endif /* filter setting management */ if ((frame_par_ready_to_set) || (frame_par_force_to_set)) { diff --git a/include/linux/amlogic/media/amvecm/amvecm.h b/include/linux/amlogic/media/amvecm/amvecm.h index 947cdf28d7e0..05ca20cd5e41 100644 --- a/include/linux/amlogic/media/amvecm/amvecm.h +++ b/include/linux/amlogic/media/amvecm/amvecm.h @@ -68,6 +68,28 @@ #define VPP_DEMO_CM_DIS (1 << 1) #define VPP_DEMO_CM_EN (1 << 0) +/*PQ USER LATCH*/ +#define PQ_USER_SR1_DERECTION_DIS (1 << 19) +#define PQ_USER_SR1_DERECTION_EN (1 << 18) +#define PQ_USER_SR0_DERECTION_DIS (1 << 17) +#define PQ_USER_SR0_DERECTION_EN (1 << 16) +#define PQ_USER_SR1_DEJAGGY_DIS (1 << 15) +#define PQ_USER_SR1_DEJAGGY_EN (1 << 14) +#define PQ_USER_SR0_DEJAGGY_DIS (1 << 13) +#define PQ_USER_SR0_DEJAGGY_EN (1 << 12) +#define PQ_USER_SR1_DERING_DIS (1 << 11) +#define PQ_USER_SR1_DERING_EN (1 << 10) +#define PQ_USER_SR0_DERING_DIS (1 << 9) +#define PQ_USER_SR0_DERING_EN (1 << 8) +#define PQ_USER_SR1_PK_DIS (1 << 7) +#define PQ_USER_SR1_PK_EN (1 << 6) +#define PQ_USER_SR0_PK_DIS (1 << 5) +#define PQ_USER_SR0_PK_EN (1 << 4) +#define PQ_USER_BLK_SLOPE (1 << 3) +#define PQ_USER_BLK_START (1 << 2) +#define PQ_USER_BLK_DIS (1 << 1) +#define PQ_USER_BLK_EN (1 << 0) + /*white balance latch*/ #define MTX_BYPASS_RGB_OGO (1 << 0) #define MTX_RGB2YUVL_RGB_OGO (1 << 1) @@ -160,9 +182,16 @@ static inline uint32_t READ_VPP_REG_BITS(uint32_t reg, extern signed int vd1_brightness, vd1_contrast; extern bool gamma_en; -extern void amvecm_on_vs(struct vframe_s *vf); +#define CSC_FLAG_TOGGLE_FRAME 1 +#define CSC_FLAG_CHECK_OUTPUT 2 + +extern int amvecm_on_vs( + struct vframe_s *display_vf, + struct vframe_s *toggle_vf, + int flags); extern void refresh_on_vs(struct vframe_s *vf); extern void pc_mode_process(void); +extern void pq_user_latch_process(void); /* master_display_info for display device */ struct hdr_metadata_info_s { @@ -195,5 +224,6 @@ extern struct vframe_s *dolby_vision_vf_peek_el(struct vframe_s *vf); extern void dolby_vision_dump_setting(int debug_flag); extern void dolby_vision_dump_struct(void); extern void enable_osd_path(int on); +extern void amvecm_wakeup_queue(void); #endif /* AMVECM_H */ diff --git a/include/linux/amlogic/media/amvecm/ve.h b/include/linux/amlogic/media/amvecm/ve.h index 5bfd32dab5e0..8e2660c42da3 100644 --- a/include/linux/amlogic/media/amvecm/ve.h +++ b/include/linux/amlogic/media/amvecm/ve.h @@ -317,6 +317,8 @@ struct hdr_osd_reg_s { uint32_t viu_osd1_eotf_coef11_12; /* 0x1ad7 */ uint32_t viu_osd1_eotf_coef20_21; /* 0x1ad8 */ uint32_t viu_osd1_eotf_coef22_rs; /* 0x1ad9 */ + uint32_t VIU_OSD1_EOTF_3X3_OFST_0; /* 0x1aa0*/ + uint32_t VIU_OSD1_EOTF_3X3_OFST_1; /* 0x1aa1*/ uint32_t viu_osd1_oetf_ctl; /* 0x1adc */ struct hdr_osd_lut_s lut_val; };