diff --git a/sound/soc/rockchip/rockchip_i2s_tdm.h b/sound/soc/rockchip/rockchip_i2s_tdm.h index be8fb93e8b34..fa41f81429f5 100644 --- a/sound/soc/rockchip/rockchip_i2s_tdm.h +++ b/sound/soc/rockchip/rockchip_i2s_tdm.h @@ -24,7 +24,7 @@ #define I2S_TXCR_RCNT_SHIFT 17 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) #define I2S_TXCR_CSR_SHIFT 15 -#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) +#define I2S_TXCR_CSR(x) ((x) << I2S_TXCR_CSR_SHIFT) #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) #define I2S_TXCR_HWT BIT(14) #define I2S_TXCR_SJM_SHIFT 12 @@ -39,7 +39,7 @@ #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) #define I2S_TXCR_PBM_SHIFT 7 -#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) +#define I2S_TXCR_PBM_MODE(x) ((x) << I2S_TXCR_PBM_SHIFT) #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) #define I2S_TXCR_TFS_SHIFT 5 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) @@ -48,7 +48,7 @@ #define I2S_TXCR_TFS_TDM_I2S (3 << I2S_TXCR_TFS_SHIFT) #define I2S_TXCR_TFS_MASK (3 << I2S_TXCR_TFS_SHIFT) #define I2S_TXCR_VDW_SHIFT 0 -#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) +#define I2S_TXCR_VDW(x) (((x) - 1) << I2S_TXCR_VDW_SHIFT) #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) /* @@ -59,7 +59,7 @@ #define I2S_RXCR_PATH_MASK(x) (0x3 << I2S_RXCR_PATH_SHIFT(x)) #define I2S_RXCR_PATH(x, v) ((v) << I2S_RXCR_PATH_SHIFT(x)) #define I2S_RXCR_CSR_SHIFT 15 -#define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT) +#define I2S_RXCR_CSR(x) ((x) << I2S_RXCR_CSR_SHIFT) #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) #define I2S_RXCR_HWT BIT(14) #define I2S_RXCR_SJM_SHIFT 12 @@ -74,7 +74,7 @@ #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) #define I2S_RXCR_PBM_SHIFT 7 -#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) +#define I2S_RXCR_PBM_MODE(x) ((x) << I2S_RXCR_PBM_SHIFT) #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) #define I2S_RXCR_TFS_SHIFT 5 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) @@ -83,7 +83,7 @@ #define I2S_RXCR_TFS_TDM_I2S (3 << I2S_RXCR_TFS_SHIFT) #define I2S_RXCR_TFS_MASK (3 << I2S_RXCR_TFS_SHIFT) #define I2S_RXCR_VDW_SHIFT 0 -#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) +#define I2S_RXCR_VDW(x) (((x) - 1) << I2S_RXCR_VDW_SHIFT) #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) /* @@ -91,7 +91,7 @@ * clock generation register */ #define I2S_CKR_TRCM_SHIFT 28 -#define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM(x) ((x) << I2S_CKR_TRCM_SHIFT) #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT) #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT) #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT) @@ -113,13 +113,13 @@ #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_TLP_SHIFT) #define I2S_CKR_TLP_MASK (1 << I2S_CKR_TLP_SHIFT) #define I2S_CKR_MDIV_SHIFT 16 -#define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT) +#define I2S_CKR_MDIV(x) (((x) - 1) << I2S_CKR_MDIV_SHIFT) #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) #define I2S_CKR_RSD_SHIFT 8 -#define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT) +#define I2S_CKR_RSD(x) (((x) - 1) << I2S_CKR_RSD_SHIFT) #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) #define I2S_CKR_TSD_SHIFT 0 -#define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT) +#define I2S_CKR_TSD(x) (((x) - 1) << I2S_CKR_TSD_SHIFT) #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) /* @@ -145,7 +145,7 @@ #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) #define I2S_DMACR_RDL_SHIFT 16 -#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT) +#define I2S_DMACR_RDL(x) (((x) - 1) << I2S_DMACR_RDL_SHIFT) #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) #define I2S_DMACR_TDE_SHIFT 8 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) @@ -159,7 +159,7 @@ * interrupt control register */ #define I2S_INTCR_RFT_SHIFT 20 -#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT) +#define I2S_INTCR_RFT(x) (((x) - 1) << I2S_INTCR_RFT_SHIFT) #define I2S_INTCR_RXOIC BIT(18) #define I2S_INTCR_RXOIE_SHIFT 17 #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT) @@ -168,7 +168,7 @@ #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) #define I2S_INTCR_TFT_SHIFT 4 -#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT) +#define I2S_INTCR_TFT(x) (((x) - 1) << I2S_INTCR_TFT_SHIFT) #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) #define I2S_INTCR_TXUIC BIT(2) #define I2S_INTCR_TXUIE_SHIFT 1 @@ -230,26 +230,26 @@ * TDM ctrl register */ #define TDM_FSYNC_WIDTH_SEL1_MSK GENMASK(20, 18) -#define TDM_FSYNC_WIDTH_SEL1(x) ((x - 1) << 18) +#define TDM_FSYNC_WIDTH_SEL1(x) (((x) - 1) << 18) #define TDM_FSYNC_WIDTH_SEL0_MSK BIT(17) #define TDM_FSYNC_WIDTH_HALF_FRAME 0 #define TDM_FSYNC_WIDTH_ONE_FRAME BIT(17) #define TDM_SHIFT_CTRL_MSK GENMASK(16, 14) #define TDM_SHIFT_CTRL(x) ((x) << 14) #define TDM_SLOT_BIT_WIDTH_MSK GENMASK(13, 9) -#define TDM_SLOT_BIT_WIDTH(x) ((x - 1) << 9) +#define TDM_SLOT_BIT_WIDTH(x) (((x) - 1) << 9) #define TDM_FRAME_WIDTH_MSK GENMASK(8, 0) -#define TDM_FRAME_WIDTH(x) ((x - 1) << 0) +#define TDM_FRAME_WIDTH(x) (((x) - 1) << 0) /* * CLKDIV * Mclk div register */ #define I2S_CLKDIV_TXM_SHIFT 0 -#define I2S_CLKDIV_TXM(x) ((x - 1) << I2S_CLKDIV_TXM_SHIFT) +#define I2S_CLKDIV_TXM(x) (((x) - 1) << I2S_CLKDIV_TXM_SHIFT) #define I2S_CLKDIV_TXM_MASK (0xff << I2S_CLKDIV_TXM_SHIFT) #define I2S_CLKDIV_RXM_SHIFT 8 -#define I2S_CLKDIV_RXM(x) ((x - 1) << I2S_CLKDIV_RXM_SHIFT) +#define I2S_CLKDIV_RXM(x) (((x) - 1) << I2S_CLKDIV_RXM_SHIFT) #define I2S_CLKDIV_RXM_MASK (0xff << I2S_CLKDIV_RXM_SHIFT) /* Clock divider id */