From 0a3b4eb46460846498daa7867d7eabb69ceff311 Mon Sep 17 00:00:00 2001
From: Liang Chen <cl@rock-chips.com>
Date: Sun, 25 Feb 2018 17:28:51 +0800
Subject: [PATCH] clk: rockchip: Add adaptive frequency scaling for pll_rk3036

Change-Id: Ifd035967afc1852df81daa2b15afea764c5b851d
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-pll.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index d3ec8e75232b..a04b1b61e5a2 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -376,6 +376,9 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
 	struct rockchip_pll_rate_table cur;
 	u64 rate64 = prate;
 
+	if (pll->sel && pll->scaling)
+		return pll->scaling;
+
 	rockchip_rk3036_pll_get_params(pll, &cur);
 
 	rate64 *= cur.fbdiv;