From 0a6460072f8b28098c279e2b4c76e833ed60e637 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Mon, 19 Feb 2024 21:02:38 +0800 Subject: [PATCH] drm/bridge: dw-hdmi-qp: Fix timer reference base error Set timer reference base According to the actual refclk frequency, otherwise cec or ddc function may be abnormal. Change-Id: Id45af649182a5158a47ee2cadb1254f2dc855d52 Signed-off-by: Algea Cao --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 8 ++++++-- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 9 +++++++++ include/drm/bridge/dw_hdmi.h | 1 + 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index a2d24238bfbb..63f1a5fd29b7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -299,6 +299,8 @@ struct dw_hdmi_qp { u32 flt_intr; u32 earc_intr; + u32 refclk_rate; + struct mutex audio_mutex; unsigned int sample_rate; unsigned int audio_cts; @@ -3782,9 +3784,11 @@ __dw_hdmi_probe(struct platform_device *pdev, if (hdmi->plat_data->get_force_timing(hdmi->plat_data->phy_data)) hdmi->force_kernel_output = true; + hdmi->refclk_rate = hdmi->plat_data->get_refclk_rate(hdmi->plat_data->phy_data); + hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); - hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); + hdmi_writel(hdmi, hdmi->refclk_rate, TIMER_BASE_CONFIG0); hdmi->logo_plug_out = false; if (hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data) == connector_status_connected && hdmi_readl(hdmi, I2CM_INTERFACE_CONTROL0)) { @@ -4105,7 +4109,7 @@ void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); - hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); + hdmi_writel(hdmi, hdmi->refclk_rate, TIMER_BASE_CONFIG0); pinctrl_pm_select_default_state(dev); diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index a42bb72e376b..14af2abac3ac 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -2906,6 +2906,13 @@ static struct drm_display_mode *dw_hdmi_rockchip_get_force_timing(void *data) return &hdmi->force_mode; } +static u32 dw_hdmi_rockchip_get_refclk_rate(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return clk_get_rate(hdmi->hdmitx_ref); +} + static const struct drm_prop_enum_list color_depth_enum_list[] = { { 0, "Automatic" }, /* Prefer highest color depth */ { 8, "24bit" }, @@ -3949,6 +3956,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, dw_hdmi_rockchip_set_hdcp14_mem; plat_data->get_force_timing = dw_hdmi_rockchip_get_force_timing; + plat_data->get_refclk_rate = + dw_hdmi_rockchip_get_refclk_rate; plat_data->property_ops = &dw_hdmi_rockchip_property_ops; secondary = rockchip_hdmi_find_by_id(dev->driver, !hdmi->id); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index b9f9491b9194..884bdc67d76f 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -268,6 +268,7 @@ struct dw_hdmi_plat_data { void (*set_ddc_io)(void *data, bool enable); void (*set_hdcp14_mem)(void *data, bool enable); struct drm_display_mode *(*get_force_timing)(void *data); + u32 (*get_refclk_rate)(void *data); /* Vendor Property support */ const struct dw_hdmi_property_ops *property_ops;