From 0ad8ee931a78086a214a1e653fe7338e9ba6c8ce Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Mon, 25 Feb 2019 16:27:35 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3399pro-npu: Add pvtm node

Change-Id: Ic3044fa2491a38ae8fcb6059b3796186eb15dfe5
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 .../boot/dts/rockchip/rk3399pro-npu.dtsi      | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
index 32bf91d09dfd..77fb76009654 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
@@ -158,6 +158,13 @@
 		reg = <0x0 0xfe000000 0x0 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
+
+		npu_pvtm: npu-pvtm {
+			compatible = "rockchip,rk1808-npu-pvtm";
+			clocks = <&cru SCLK_PVTM_NPU>;
+			clock-names = "npu";
+			status = "okay";
+		};
 	};
 
 	usb2phy_grf: syscon@fe010000 {
@@ -207,6 +214,13 @@
 		reg = <0x0 0xfe020000 0x0 0x1000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
+
+		pmu_pvtm: pmu-pvtm {
+			compatible = "rockchip,rk1808-pmu-pvtm";
+			clocks = <&cru SCLK_PVTM_PMU>;
+			clock-names = "pmu";
+			status = "okay";
+		};
 	};
 
 	usb_pcie_grf: syscon@fe040000 {
@@ -214,6 +228,20 @@
 		reg = <0x0 0xfe040000 0x0 0x1000>;
 	};
 
+	coregrf: syscon@fe050000 {
+		compatible = "rockchip,rk1808-coregrf", "syscon", "simple-mfd";
+		reg = <0x0 0xfe050000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pvtm: pvtm {
+			compatible = "rockchip,rk1808-pvtm";
+			clocks = <&cru SCLK_PVTM_CORE>;
+			clock-names = "core";
+			status = "okay";
+		};
+	};
+
 	qos_npu: qos@fe850000 {
 		compatible = "syscon";
 		reg = <0x0 0xfe850000 0x0 0x20>;