From 0ae3c5a3663faff666f7d48b3665820301ebc4f8 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Fri, 28 Aug 2020 09:51:24 +0800 Subject: [PATCH] arm64: dts: rockchip: add core dtsi for RK3568 Soc RK3568 is a Soc from Rockchip, which embedded with quad ARM Cortex-A55. This patch add basic core dtsi file for RK3568. Change-Id: Ib555d4402e4dceb4dcd59989c3a8ee14c8bfbe76 Signed-off-by: Liang Chen --- .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 2304 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 778 ++++++ .../boot/dts/rockchip/rockchip-pinconf.dtsi | 346 +++ 3 files changed, 3428 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi new file mode 100644 index 000000000000..08fef6392bf1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi @@ -0,0 +1,2304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + acodec { + /omit-if-no-ref/ + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_sync */ + <1 RK_PB1 5 &pcfg_pull_none>, + /* acodec_adcclk */ + <1 RK_PA1 5 &pcfg_pull_none>, + /* acodec_adcdata */ + <1 RK_PA0 5 &pcfg_pull_none>, + /* acodec_dac_datal */ + <1 RK_PA7 5 &pcfg_pull_none>, + /* acodec_dac_datar */ + <1 RK_PB0 5 &pcfg_pull_none>, + /* acodec_dacclk */ + <1 RK_PA3 5 &pcfg_pull_none>, + /* acodec_dacsync */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + }; + audiopwm { + /omit-if-no-ref/ + audiopwm_pins: audiopwm-pins { + rockchip,pins = + /* audiopwm_lout */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* audiopwm_lout */ + <1 RK_PA1 6 &pcfg_pull_none>, + /* audiopwm_loutp */ + <1 RK_PA0 6 &pcfg_pull_none>, + /* audiopwm_rout */ + <1 RK_PA1 4 &pcfg_pull_none>, + /* audiopwm_routn */ + <1 RK_PA7 4 &pcfg_pull_none>, + /* audiopwm_routp */ + <1 RK_PA6 4 &pcfg_pull_none>; + }; + }; + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clk */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <3 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + bt656 { + /omit-if-no-ref/ + bt656m0_pins: bt656m0-pins { + rockchip,pins = + /* bt656_clkm0 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* bt656_d0m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* bt656_d1m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* bt656_d2m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* bt656_d3m0 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* bt656_d4m0 */ + <2 RK_PD4 2 &pcfg_pull_none>, + /* bt656_d5m0 */ + <2 RK_PD5 2 &pcfg_pull_none>, + /* bt656_d6m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* bt656_d7m0 */ + <2 RK_PD7 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + bt656m1_pins: bt656m1-pins { + rockchip,pins = + /* bt656_clkm1 */ + <4 RK_PB4 5 &pcfg_pull_none>, + /* bt656_d0m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* bt656_d1m1 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* bt656_d2m1 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* bt656_d3m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* bt656_d4m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* bt656_d5m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* bt656_d6m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* bt656_d7m1 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + }; + cam { + /omit-if-no-ref/ + cam_pins: cam-pins { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>, + /* cam_clkout1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + }; + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxm0 */ + <0 RK_PB4 2 &pcfg_pull_none>, + /* can0_txm0 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxm1 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can0_txm1 */ + <2 RK_PA1 4 &pcfg_pull_none>; + }; + }; + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxm0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* can1_txm0 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxm1 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* can1_txm1 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rxm0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* can2_txm0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rxm1 */ + <2 RK_PB1 4 &pcfg_pull_none>, + /* can2_txm1 */ + <2 RK_PB2 4 &pcfg_pull_none>; + }; + }; + cif { + /omit-if-no-ref/ + cif_dvp_ctl: cif-dvp_ctl { + rockchip,pins = + /* cif_clkin */ + <4 RK_PC1 1 &pcfg_pull_none>, + /* cif_clkout */ + <4 RK_PC0 1 &pcfg_pull_none>, + /* cif_d0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d5 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* cif_d6 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* cif_d7 */ + <3 RK_PD5 1 &pcfg_pull_none>, + /* cif_d8 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* cif_d10 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d11 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d12 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d13 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d14 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d15 */ + <4 RK_PA5 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB7 1 &pcfg_pull_none>; + }; + }; + clk32k { + /omit-if-no-ref/ + clk32k_pins: clk32k-pins { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>, + /* clk32k_out0 */ + <0 RK_PB0 2 &pcfg_pull_none>, + /* clk32k_out1 */ + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + ebc { + /omit-if-no-ref/ + ebc_pins: ebc-pins { + rockchip,pins = + /* ebc_gdclk */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* ebc_gdoe */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* ebc_gdsp */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* ebc_sdce0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* ebc_sdce1 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* ebc_sdce2 */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* ebc_sdce3 */ + <4 RK_PB1 2 &pcfg_pull_none>, + /* ebc_sdclk */ + <4 RK_PC1 2 &pcfg_pull_none>, + /* ebc_sddo0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* ebc_sddo1 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* ebc_sddo2 */ + <3 RK_PD0 2 &pcfg_pull_none>, + /* ebc_sddo3 */ + <3 RK_PD1 2 &pcfg_pull_none>, + /* ebc_sddo4 */ + <3 RK_PD2 2 &pcfg_pull_none>, + /* ebc_sddo5 */ + <3 RK_PD3 2 &pcfg_pull_none>, + /* ebc_sddo6 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* ebc_sddo7 */ + <3 RK_PD5 2 &pcfg_pull_none>, + /* ebc_sddo8 */ + <3 RK_PD6 2 &pcfg_pull_none>, + /* ebc_sddo9 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* ebc_sddo10 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* ebc_sddo11 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* ebc_sddo12 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* ebc_sddo13 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* ebc_sddo14 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* ebc_sddo15 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* ebc_sdle */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* ebc_sdoe */ + <4 RK_PB7 2 &pcfg_pull_none>, + /* ebc_sdshr */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* ebc_vcom */ + <4 RK_PB2 2 &pcfg_pull_none>; + }; + }; + edpdp { + /omit-if-no-ref/ + edpdpm0_pins: edpdpm0-pins { + rockchip,pins = + /* edpdp_hpdinm0 */ + <4 RK_PC4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + edpdpm1_pins: edpdpm1-pins { + rockchip,pins = + /* edpdp_hpdinm1 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_datastrobe: emmc-datastrobe { + rockchip,pins = + <1 RK_PC6 1 &pcfg_pull_none>; + }; + }; + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko25m */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + eth1 { + /omit-if-no-ref/ + eth1m0_pins: eth1m0-pins { + rockchip,pins = + /* eth1_refclko25mm0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + eth1m1_pins: eth1m1-pins { + rockchip,pins = + /* eth1_refclko25mm1 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + }; + flash { + /omit-if-no-ref/ + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PD0 2 &pcfg_pull_none>, + /* flash_cle */ + <1 RK_PC6 3 &pcfg_pull_none>, + /* flash_cs0n */ + <1 RK_PD3 2 &pcfg_pull_none>, + /* flash_cs1n */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* flash_d0 */ + <1 RK_PB4 2 &pcfg_pull_none>, + /* flash_d1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* flash_d2 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* flash_d3 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* flash_d4 */ + <1 RK_PC0 2 &pcfg_pull_none>, + /* flash_d5 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* flash_d6 */ + <1 RK_PC2 2 &pcfg_pull_none>, + /* flash_d7 */ + <1 RK_PC3 2 &pcfg_pull_none>, + /* flash_dqs */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* flash_rdy */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* flash_volsel */ + <0 RK_PA7 1 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PC7 3 &pcfg_pull_none>, + /* flash_wrn */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + }; + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_cs1n */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + }; + gmac0 { + /omit-if-no-ref/ + gmac0_pins: gmac0-pins { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* gmac0_mdc */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* gmac0_mdio */ + <2 RK_PC4 2 &pcfg_pull_none>, + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>, + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none>, + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + }; + gmac1 { + /omit-if-no-ref/ + gmac1m0_pins: gmac1m0-pins { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>, + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none>, + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>, + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none>, + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + gmac1m1_pins: gmac1m1-pins { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>, + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none>, + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none>, + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + }; + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* gpu_pwren */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + }; + hdmitx { + /omit-if-no-ref/ + hdmitxm0_pins: hdmitxm0-pins { + rockchip,pins = + /* hdmitx_cecm0 */ + <4 RK_PD1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmitxm1_pins: hdmitxm1-pins { + rockchip,pins = + /* hdmitx_cecm1 */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmitx_scl: hdmitx-scl { + rockchip,pins = + <4 RK_PC7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmitx_sda: hdmitx-sda { + rockchip,pins = + <4 RK_PD0 1 &pcfg_pull_none>; + }; + }; + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + i2c1 { + /omit-if-no-ref/ + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <0 RK_PB3 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c1_sda */ + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_sclm0 */ + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c2_sdam0 */ + <0 RK_PB6 1 &pcfg_pull_none_drv_level_0_smt>; + }; + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_sclm1 */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c2_sdam1 */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_sclm0 */ + <1 RK_PA1 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c3_sdam0 */ + <1 RK_PA0 1 &pcfg_pull_none_drv_level_0_smt>; + }; + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_sclm1 */ + <3 RK_PB5 4 &pcfg_pull_none_drv_level_0_smt>, + /* i2c3_sdam1 */ + <3 RK_PB6 4 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_sclm0 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c4_sdam0 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_0_smt>; + }; + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_sclm1 */ + <2 RK_PB2 2 &pcfg_pull_none_drv_level_0_smt>, + /* i2c4_sdam1 */ + <2 RK_PB1 2 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_sclm0 */ + <3 RK_PB3 4 &pcfg_pull_none_drv_level_0_smt>, + /* i2c5_sdam0 */ + <3 RK_PB4 4 &pcfg_pull_none_drv_level_0_smt>; + }; + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_sclm1 */ + <4 RK_PC7 2 &pcfg_pull_none_drv_level_0_smt>, + /* i2c5_sdam1 */ + <4 RK_PD0 2 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + i2s1 { + /omit-if-no-ref/ + i2s1lrckrxm0: i2s1lrckrxm0 { + rockchip,pins = + <1 RK_PA6 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1lrcktxm0: i2s1lrcktxm0 { + rockchip,pins = + <1 RK_PA5 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1mclkm0: i2s1mclkm0 { + rockchip,pins = + <1 RK_PA2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sclkrxm0: i2s1sclkrxm0 { + rockchip,pins = + <1 RK_PA4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sclktxm0: i2s1sclktxm0 { + rockchip,pins = + <1 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi0m0: i2s1sdi0m0 { + rockchip,pins = + <1 RK_PB3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi1m0: i2s1sdi1m0 { + rockchip,pins = + <1 RK_PB2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi2m0: i2s1sdi2m0 { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi3m0: i2s1sdi3m0 { + rockchip,pins = + <1 RK_PB0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdo0m0: i2s1sdo0m0 { + rockchip,pins = + <1 RK_PA7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdo1m0: i2s1sdo1m0 { + rockchip,pins = + <1 RK_PB0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdo2m0: i2s1sdo2m0 { + rockchip,pins = + <1 RK_PB1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdo3m0: i2s1sdo3m0 { + rockchip,pins = + <1 RK_PB2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1lrckrxm1: i2s1lrckrxm1 { + rockchip,pins = + <4 RK_PA7 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1lrcktxm1: i2s1lrcktxm1 { + rockchip,pins = + <3 RK_PD0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1mclkm1: i2s1mclkm1 { + rockchip,pins = + <3 RK_PC6 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sclkrxm1: i2s1sclkrxm1 { + rockchip,pins = + <4 RK_PA6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sclktxm1: i2s1sclktxm1 { + rockchip,pins = + <3 RK_PC7 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi0m1: i2s1sdi0m1 { + rockchip,pins = + <3 RK_PD2 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi1m1: i2s1sdi1m1 { + rockchip,pins = + <3 RK_PD3 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi2m1: i2s1sdi2m1 { + rockchip,pins = + <3 RK_PD4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi3m1: i2s1sdi3m1 { + rockchip,pins = + <3 RK_PD5 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdo0m1: i2s1sdo0m1 { + rockchip,pins = + <3 RK_PD1 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdo1m1: i2s1sdo1m1 { + rockchip,pins = + <4 RK_PB0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1lrckrxm2: i2s1lrckrxm2 { + rockchip,pins = + <3 RK_PC5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1lrcktxm2: i2s1lrcktxm2 { + rockchip,pins = + <2 RK_PD2 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sclktxm2: i2s1sclktxm2 { + rockchip,pins = + <2 RK_PD1 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi0m2: i2s1sdi0m2 { + rockchip,pins = + <2 RK_PD3 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi1m2: i2s1sdi1m2 { + rockchip,pins = + <2 RK_PD4 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdi2m2: i2s1sdi2m2 { + rockchip,pins = + <2 RK_PD5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdo2m2: i2s1sdo2m2 { + rockchip,pins = + <3 RK_PC1 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1sdo3m2: i2s1sdo3m2 { + rockchip,pins = + <3 RK_PC2 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1_mclkm2: i2s1-mclkm2 { + rockchip,pins = + <2 RK_PD0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1_sclkrxm: i2s1-sclkrxm { + rockchip,pins = + <3 RK_PC3 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1_sdi3m2: i2s1-sdi3m2 { + rockchip,pins = + <2 RK_PD6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1_sdo0m2: i2s1-sdo0m2 { + rockchip,pins = + <2 RK_PD7 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1_sdo1m2: i2s1-sdo1m2 { + rockchip,pins = + <3 RK_PA0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1_sdo2m1: i2s1-sdo2m1 { + rockchip,pins = + <4 RK_PB1 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1_sdo3m: i2s1-sdo3m { + rockchip,pins = + <4 RK_PB5 4 &pcfg_pull_none>; + }; + }; + i2s2 { + /omit-if-no-ref/ + i2s2lrckrxm0: i2s2lrckrxm0 { + rockchip,pins = + <2 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2lrcktxm0: i2s2lrcktxm0 { + rockchip,pins = + <2 RK_PC3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2mclkm0: i2s2mclkm0 { + rockchip,pins = + <2 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2sclkrxm0: i2s2sclkrxm0 { + rockchip,pins = + <2 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2sclktxm0: i2s2sclktxm0 { + rockchip,pins = + <2 RK_PC2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2sdim0: i2s2sdim0 { + rockchip,pins = + <2 RK_PC5 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2sdom0: i2s2sdom0 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2lrckrxm1: i2s2lrckrxm1 { + rockchip,pins = + <4 RK_PA5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2lrcktxm1: i2s2lrcktxm1 { + rockchip,pins = + <4 RK_PA4 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2mclkm1: i2s2mclkm1 { + rockchip,pins = + <4 RK_PB6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2sclkrxm1: i2s2sclkrxm1 { + rockchip,pins = + <4 RK_PC1 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2sclktxm1: i2s2sclktxm1 { + rockchip,pins = + <4 RK_PB7 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2sdim1: i2s2sdim1 { + rockchip,pins = + <4 RK_PB2 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s2sdom1: i2s2sdom1 { + rockchip,pins = + <4 RK_PB3 5 &pcfg_pull_none>; + }; + }; + i2s3 { + /omit-if-no-ref/ + i2s3lrckm0: i2s3lrckm0 { + rockchip,pins = + <3 RK_PA4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3mclkm0: i2s3mclkm0 { + rockchip,pins = + <3 RK_PA2 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3sclkm0: i2s3sclkm0 { + rockchip,pins = + <3 RK_PA3 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3sdim0: i2s3sdim0 { + rockchip,pins = + <3 RK_PA6 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3sdom0: i2s3sdom0 { + rockchip,pins = + <3 RK_PA5 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3lrckm1: i2s3lrckm1 { + rockchip,pins = + <4 RK_PC4 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3mclkm1: i2s3mclkm1 { + rockchip,pins = + <4 RK_PC2 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3sclkm1: i2s3sclkm1 { + rockchip,pins = + <4 RK_PC3 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3sdim1: i2s3sdim1 { + rockchip,pins = + <4 RK_PC6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s3sdom1: i2s3sdom1 { + rockchip,pins = + <4 RK_PC5 5 &pcfg_pull_none>; + }; + }; + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flashtrigin */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* isp_flashtrigout */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* isp_prelighttrig */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + }; + jtag { + /omit-if-no-ref/ + jtag_pins: jtag-pins { + rockchip,pins = + /* jtag_tck */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* jtag_tms */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + lcdc { + /omit-if-no-ref/ + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d0 */ + <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d1 */ + <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d8 */ + <3 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d9 */ + <3 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d16 */ + <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d17 */ + <3 RK_PB2 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_up_drv_level_2>; + }; + }; + mcu { + /omit-if-no-ref/ + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtagtck */ + <0 RK_PB4 4 &pcfg_pull_none>, + /* mcu_jtagtdi */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* mcu_jtagtdo */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* mcu_jtagtms */ + <0 RK_PC2 4 &pcfg_pull_none>, + /* mcu_jtagtrstn */ + <0 RK_PC3 4 &pcfg_pull_none>; + }; + }; + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqnm0 */ + <0 RK_PA5 3 &pcfg_pull_none>, + /* pcie20_perstnm0 */ + <0 RK_PB6 3 &pcfg_pull_none>, + /* pcie20_wakenm0 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqnm1 */ + <2 RK_PD0 4 &pcfg_pull_none>, + /* pcie20_perstnm1 */ + <3 RK_PC1 4 &pcfg_pull_none>, + /* pcie20_wakenm1 */ + <2 RK_PD1 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie20m2_pins: pcie20m2-pins { + rockchip,pins = + /* pcie20_clkreqnm2 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_perstnm2 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie20_wakenm2 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + <0 RK_PB4 3 &pcfg_pull_none>; + }; + }; + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_perstnm0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* pcie30x1_wakenm0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_clkreqnm1 */ + <2 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x1_perstnm1 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* pcie30x1_wakenm1 */ + <2 RK_PD3 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_clkreqnm2 */ + <1 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_perstnm2 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_wakenm2 */ + <1 RK_PA3 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie30x1_buttonrstn: pcie30x1-buttonrstn { + rockchip,pins = + <0 RK_PB3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie30x1_clkreqnm0: pcie30x1-clkreqnm0 { + rockchip,pins = + <0 RK_PA4 3 &pcfg_pull_none>; + }; + }; + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqnm0 */ + <0 RK_PA6 2 &pcfg_pull_none>, + /* pcie30x2_perstnm0 */ + <0 RK_PC6 3 &pcfg_pull_none>, + /* pcie30x2_wakenm0 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqnm1 */ + <2 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_perstnm1 */ + <2 RK_PD6 4 &pcfg_pull_none>, + /* pcie30x2_wakenm1 */ + <2 RK_PD5 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqnm2 */ + <4 RK_PC2 4 &pcfg_pull_none>, + /* pcie30x2_perstnm2 */ + <4 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x2_wakenm2 */ + <4 RK_PC3 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pcie30x2_buttonrstn: pcie30x2-buttonrstn { + rockchip,pins = + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + pdm { + /omit-if-no-ref/ + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0m0 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmclk1m0: pdmclk1m0 { + rockchip,pins = + <1 RK_PA4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi0m0: pdmsdi0m0 { + rockchip,pins = + <1 RK_PB3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi1m0: pdmsdi1m0 { + rockchip,pins = + <1 RK_PB2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi2m0: pdmsdi2m0 { + rockchip,pins = + <1 RK_PB1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi3m0: pdmsdi3m0 { + rockchip,pins = + <1 RK_PB0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0m1 */ + <3 RK_PD6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi0m1: pdmsdi0m1 { + rockchip,pins = + <3 RK_PD7 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi1m1: pdmsdi1m1 { + rockchip,pins = + <4 RK_PA1 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi2m1: pdmsdi2m1 { + rockchip,pins = + <4 RK_PA2 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi3m1: pdmsdi3m1 { + rockchip,pins = + <4 RK_PA3 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmclk1m2: pdmclk1m2 { + rockchip,pins = + <3 RK_PC4 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi0m2: pdmsdi0m2 { + rockchip,pins = + <3 RK_PB3 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi1m2: pdmsdi1m2 { + rockchip,pins = + <3 RK_PB4 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi2m2: pdmsdi2m2 { + rockchip,pins = + <3 RK_PB7 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdmsdi3m2: pdmsdi3m2 { + rockchip,pins = + <3 RK_PC0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm_clk1m1: pdm-clk1m1 { + rockchip,pins = + <4 RK_PA0 4 &pcfg_pull_none>; + }; + }; + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_sleep */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug1 */ + <0 RK_PA6 3 &pcfg_pull_none>, + /* pmu_debug4 */ + <0 RK_PC6 4 &pcfg_pull_none>, + /* pmu_debug0 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* pmu_debug2 */ + <0 RK_PC4 4 &pcfg_pull_none>, + /* pmu_debug3 */ + <0 RK_PC5 4 &pcfg_pull_none>, + /* pmu_debug5 */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + }; + pwm { + /omit-if-no-ref/ + pwm_pins: pwm-pins { + rockchip,pins = + /* pwm_4 */ + <0 RK_PC3 1 &pcfg_pull_none>, + /* pwm_5 */ + <0 RK_PC4 1 &pcfg_pull_none>, + /* pwm_6 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <0 RK_PB5 4 &pcfg_pull_none>; + }; + }; + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_irm0 */ + <3 RK_PB6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_irm1 */ + <4 RK_PC0 3 &pcfg_pull_none>; + }; + }; + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + }; + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + }; + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + }; + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_irm0 */ + <3 RK_PC5 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_irm1 */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm2_m1: pwm2-m1 { + rockchip,pins = + <0 RK_PB6 4 &pcfg_pull_none>; + }; + }; + pwm3 { + /omit-if-no-ref/ + pwm3_pins: pwm3-pins { + rockchip,pins = + /* pwm3_ir */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + pwm7 { + /omit-if-no-ref/ + pwm7_pins: pwm7-pins { + rockchip,pins = + /* pwm7_ir */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PB1 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB2 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + }; + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_ou */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cpdet */ + <0 RK_PA4 2 &pcfg_pull_none>, + /* sata_cppod */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* sata_mpswitch */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + sata0 { + /omit-if-no-ref/ + sata0_pins: sata0-pins { + rockchip,pins = + /* sata0_actled */ + <4 RK_PC6 3 &pcfg_pull_none>; + }; + }; + sata1 { + /omit-if-no-ref/ + sata1_pins: sata1-pins { + rockchip,pins = + /* sata1_actled */ + <4 RK_PC5 3 &pcfg_pull_none>; + }; + }; + sata2 { + /omit-if-no-ref/ + sata2_pins: sata2-pins { + rockchip,pins = + /* sata2_actled */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + scr { + /omit-if-no-ref/ + scr_pins: scr-pins { + rockchip,pins = + /* scr_clk */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_det */ + <1 RK_PA7 3 &pcfg_pull_none>, + /* scr_io */ + <1 RK_PA3 3 &pcfg_pull_none>, + /* scr_rst */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + }; + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <2 RK_PB2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + sdmmc2 { + /omit-if-no-ref/ + sdmmc2m0_bus4: sdmmc2m0-bus4 { + rockchip,pins = + /* sdmmc2_d0m0 */ + <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m0 */ + <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m0 */ + <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m0 */ + <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc2m0_clk: sdmmc2m0-clk { + rockchip,pins = + /* sdmmc2_clkm0 */ + <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc2m0_cmd: sdmmc2m0-cmd { + rockchip,pins = + /* sdmmc2_cmdm0 */ + <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc2detm0: sdmmc2detm0 { + rockchip,pins = + <3 RK_PD4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc2pwrenm0: sdmmc2pwrenm0 { + rockchip,pins = + <3 RK_PD5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc2m1_bus4: sdmmc2m1-bus4 { + rockchip,pins = + /* sdmmc2_d2m1 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m1 */ + <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc2m1_clk: sdmmc2m1-clk { + rockchip,pins = + /* sdmmc2_clkm1 */ + <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc2m1_cmd: sdmmc2m1-cmd { + rockchip,pins = + /* sdmmc2_cmdm1 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc2detm1: sdmmc2detm1 { + rockchip,pins = + <3 RK_PA7 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc2pwrenm1: sdmmc2pwrenm1 { + rockchip,pins = + <3 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc2_bus4: sdmmc2-bus4 { + rockchip,pins = + /* sdmmc2_d0m1 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m1 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>; + }; + }; + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_txm0 */ + <1 RK_PA4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_txm1 */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_txm2 */ + <4 RK_PC4 2 &pcfg_pull_none>; + }; + }; + spi0 { + /omit-if-no-ref/ + spi0clkm0: spi0clkm0 { + rockchip,pins = + <0 RK_PB5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0cs0m0: spi0cs0m0 { + rockchip,pins = + <0 RK_PC6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0cs1m0: spi0cs1m0 { + rockchip,pins = + <0 RK_PC4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0misom0: spi0misom0 { + rockchip,pins = + <0 RK_PC5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0mosim0: spi0mosim0 { + rockchip,pins = + <0 RK_PB6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0clkm1: spi0clkm1 { + rockchip,pins = + <2 RK_PD3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0cs0m1: spi0cs0m1 { + rockchip,pins = + <2 RK_PD2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0misom1: spi0misom1 { + rockchip,pins = + <2 RK_PD0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0mosim1: spi0mosim1 { + rockchip,pins = + <2 RK_PD1 3 &pcfg_pull_none>; + }; + }; + spi1 { + /omit-if-no-ref/ + spi1clkm0: spi1clkm0 { + rockchip,pins = + <2 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1cs0m0: spi1cs0m0 { + rockchip,pins = + <2 RK_PC0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1cs1m0: spi1cs1m0 { + rockchip,pins = + <2 RK_PC6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1misom0: spi1misom0 { + rockchip,pins = + <2 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1mosim0: spi1mosim0 { + rockchip,pins = + <2 RK_PB7 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1clkm1: spi1clkm1 { + rockchip,pins = + <3 RK_PC3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1cs0m1: spi1cs0m1 { + rockchip,pins = + <3 RK_PA1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1misom1: spi1misom1 { + rockchip,pins = + <3 RK_PC2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1mosim1: spi1mosim1 { + rockchip,pins = + <3 RK_PC1 3 &pcfg_pull_none>; + }; + }; + spi2 { + /omit-if-no-ref/ + spi2clkm0: spi2clkm0 { + rockchip,pins = + <2 RK_PC1 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2cs0m0: spi2cs0m0 { + rockchip,pins = + <2 RK_PC4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2cs1m0: spi2cs1m0 { + rockchip,pins = + <2 RK_PC5 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2misom0: spi2misom0 { + rockchip,pins = + <2 RK_PC2 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2mosim0: spi2mosim0 { + rockchip,pins = + <2 RK_PC3 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2clkm1: spi2clkm1 { + rockchip,pins = + <3 RK_PA0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2cs0m1: spi2cs0m1 { + rockchip,pins = + <2 RK_PD5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2cs1m1: spi2cs1m1 { + rockchip,pins = + <2 RK_PD4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2misom1: spi2misom1 { + rockchip,pins = + <2 RK_PD7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2mosim1: spi2mosim1 { + rockchip,pins = + <2 RK_PD6 3 &pcfg_pull_none>; + }; + }; + spi3 { + /omit-if-no-ref/ + spi3clkm0: spi3clkm0 { + rockchip,pins = + <4 RK_PB3 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3cs0m0: spi3cs0m0 { + rockchip,pins = + <4 RK_PA6 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3cs1m0: spi3cs1m0 { + rockchip,pins = + <4 RK_PA7 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3misom0: spi3misom0 { + rockchip,pins = + <4 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3mosim0: spi3mosim0 { + rockchip,pins = + <4 RK_PB2 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3clkm1: spi3clkm1 { + rockchip,pins = + <4 RK_PC2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3cs0m1: spi3cs0m1 { + rockchip,pins = + <4 RK_PC6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3misom1: spi3misom1 { + rockchip,pins = + <4 RK_PC5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3mosim1: spi3mosim1 { + rockchip,pins = + <4 RK_PC3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi3_cs1m1: spi3-cs1m1 { + rockchip,pins = + <4 RK_PD1 2 &pcfg_pull_none>; + }; + }; + test { + /omit-if-no-ref/ + test_pins: test-pins { + rockchip,pins = + /* test_clkout */ + <2 RK_PA2 2 &pcfg_pull_none>; + }; + }; + tsadc { + /omit-if-no-ref/ + tsadcm0_pins: tsadcm0-pins { + rockchip,pins = + /* tsadc_shutm0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + tsadc_shutm1: tsadc-shutm1 { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC0 3 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC1 3 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <0 RK_PC7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <0 RK_PC4 3 &pcfg_pull_none>; + }; + }; + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <2 RK_PB3 2 &pcfg_pull_up>, + /* uart1_txm0 */ + <2 RK_PB4 2 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart1ctsnm0: uart1ctsnm0 { + rockchip,pins = + <2 RK_PB6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1rtsnm0: uart1rtsnm0 { + rockchip,pins = + <2 RK_PB5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <3 RK_PD7 4 &pcfg_pull_up>, + /* uart1_txm1 */ + <3 RK_PD6 4 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart1ctsnm1: uart1ctsnm1 { + rockchip,pins = + <4 RK_PC1 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1rtsnm1: uart1rtsnm1 { + rockchip,pins = + <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_txm0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <1 RK_PD6 2 &pcfg_pull_up>, + /* uart2_txm1 */ + <1 RK_PD5 2 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart2_xfer: uart2-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <0 RK_PD0 1 &pcfg_pull_up>; + }; + }; + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <1 RK_PA0 2 &pcfg_pull_up>, + /* uart3_txm0 */ + <1 RK_PA1 2 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart3ctsnm0: uart3ctsnm0 { + rockchip,pins = + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3rtsnm0: uart3rtsnm0 { + rockchip,pins = + <1 RK_PA2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rxm1 */ + <3 RK_PC0 4 &pcfg_pull_up>, + /* uart3_txm1 */ + <3 RK_PB7 4 &pcfg_pull_up>; + }; + }; + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rxm0 */ + <1 RK_PA4 2 &pcfg_pull_up>, + /* uart4_txm0 */ + <1 RK_PA6 2 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart4ctsnm0: uart4ctsnm0 { + rockchip,pins = + <1 RK_PA7 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4rtsnm0: uart4rtsnm0 { + rockchip,pins = + <1 RK_PA5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rxm1 */ + <3 RK_PB1 4 &pcfg_pull_up>, + /* uart4_txm1 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + }; + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rxm0 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_txm0 */ + <2 RK_PA2 3 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart5ctsnm0: uart5ctsnm0 { + rockchip,pins = + <1 RK_PD7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5rtsnm0: uart5rtsnm0 { + rockchip,pins = + <2 RK_PA0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rxm1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart5_txm1 */ + <3 RK_PC2 4 &pcfg_pull_up>; + }; + }; + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rxm0 */ + <2 RK_PA3 3 &pcfg_pull_up>, + /* uart6_txm0 */ + <2 RK_PA4 3 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart6ctsnm0: uart6ctsnm0 { + rockchip,pins = + <2 RK_PC0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6rtsnm0: uart6rtsnm0 { + rockchip,pins = + <2 RK_PB7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rxm1 */ + <1 RK_PD6 3 &pcfg_pull_up>, + /* uart6_txm1 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + }; + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rxm0 */ + <2 RK_PA5 3 &pcfg_pull_up>, + /* uart7_txm0 */ + <2 RK_PA6 3 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart7ctsnm0: uart7ctsnm0 { + rockchip,pins = + <2 RK_PC2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7rtsnm0: uart7rtsnm0 { + rockchip,pins = + <2 RK_PC1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rxm1 */ + <3 RK_PC5 4 &pcfg_pull_up>, + /* uart7_txm1 */ + <3 RK_PC4 4 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rxm2 */ + <4 RK_PA3 4 &pcfg_pull_up>, + /* uart7_txm2 */ + <4 RK_PA2 4 &pcfg_pull_up>; + }; + }; + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rxm0 */ + <2 RK_PC6 2 &pcfg_pull_up>, + /* uart8_txm0 */ + <2 RK_PC5 3 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart8ctsnm0: uart8ctsnm0 { + rockchip,pins = + <2 RK_PB2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8rtsnm0: uart8rtsnm0 { + rockchip,pins = + <2 RK_PB1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rxm1 */ + <3 RK_PA0 4 &pcfg_pull_up>, + /* uart8_txm1 */ + <2 RK_PD7 4 &pcfg_pull_up>; + }; + }; + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rxm0 */ + <2 RK_PA7 3 &pcfg_pull_up>, + /* uart9_txm0 */ + <2 RK_PB0 3 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart9ctsnm0: uart9ctsnm0 { + rockchip,pins = + <2 RK_PC4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart9rtsnm0: uart9rtsnm0 { + rockchip,pins = + <2 RK_PC3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rxm1 */ + <4 RK_PC6 4 &pcfg_pull_up>, + /* uart9_txm1 */ + <4 RK_PC5 4 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rxm2 */ + <4 RK_PA5 4 &pcfg_pull_up>, + /* uart9_txm2 */ + <4 RK_PA4 4 &pcfg_pull_up>; + }; + }; + vop { + /omit-if-no-ref/ + vopm0_pins: vopm0-pins { + rockchip,pins = + /* vop_pwmm0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + vopm1_pins: vopm1-pins { + rockchip,pins = + /* vop_pwmm1 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi new file mode 100644 index 000000000000..368c7a7d599a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -0,0 +1,778 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3568"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; +#if 0 + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + }; +#endif + }; + +#if 0 + arm-pmu { + compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; +#endif + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ + <0x0 0xfd460000 0 0xc0000>, /* GICR */ + <0x0 0xfd800000 0 0x10000>, /* GICC */ + <0x0 0xfd810000 0 0x10000>, /* GICH */ + <0x0 0xfd820000 0 0x10000>; /* GICV */ + interrupts = ; + its: interrupt-controller@fd420000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xfd420000 0x0 0x20000>; + }; + }; + + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; + }; + + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>, + <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, + <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru ACLK_BUS>, <&cru PCLK_BUS>, + <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, + <&cru HCLK_TOP>, <&cru PCLK_TOP>, + <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>; + assigned-clock-rates = + <32768>, <100000000>, + <100000000>, <1000000000>, + <1188000000>, <600000000>, + <150000000>, <100000000>, + <300000000>, <200000000>, + <150000000>, <100000000>, + <300000000>, <150000000>; + assigned-clock-parents = + <&pmucru CLK_RTC32K_FRAC>; + }; + + i2c0: i2c@fdd40000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfdd40000 0x0 0x1000>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fdd50000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfdd50000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 0>, <&dmac0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + pwm0: pwm@fdd70000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@fdd70010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@fdd70020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@fdd70030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3_pins>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + dmac1: dmac@fe550000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe550000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + can0: can@fe570000 { + compatible = "rockchip,canfd-1.0"; + reg = <0x0 0xfe570000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; + reset-names = "can", "can-apb"; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can1: can@fe580000 { + compatible = "rockchip,canfd-1.0"; + reg = <0x0 0xfe580000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; + reset-names = "can", "can-apb"; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can2: can@fe590000 { + compatible = "rockchip,canfd-1.0"; + reg = <0x0 0xfe590000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; + reset-names = "can", "can-apb"; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + i2c1: i2c@fe5a0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5a0000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe5b0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5b0000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe5c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5c0000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe5d0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5d0000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe5e0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5e0000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@fe600000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xfe600000 0x0 0x100>; + clocks = <&cru PCLK_WDT_NS>; + interrupts = ; + status = "okay"; + }; + + spi0: spi@fe610000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe610000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 20>, <&dmac0 21>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>; + status = "disabled"; + }; + + spi1: spi@fe620000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe620000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 22>, <&dmac0 23>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>; + status = "disabled"; + }; + + spi2: spi@fe630000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe630000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 24>, <&dmac0 25>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>; + status = "disabled"; + }; + + spi3: spi@fe640000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe640000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 26>, <&dmac0 27>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>; + status = "disabled"; + }; + + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 2>, <&dmac0 3>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + status = "disabled"; + }; + + uart2: serial@fe660000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe660000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 4>, <&dmac0 5>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart3: serial@fe670000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe670000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + status = "disabled"; + }; + + uart4: serial@fe680000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe680000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + status = "disabled"; + }; + + uart5: serial@fe690000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe690000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + status = "disabled"; + }; + + uart6: serial@fe6a0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; + status = "disabled"; + }; + + uart7: serial@fe6b0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 14>, <&dmac0 15>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; + status = "disabled"; + }; + + uart8: serial@fe6c0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 16>, <&dmac0 17>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; + status = "disabled"; + }; + + uart9: serial@fe6d0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 18>, <&dmac0 19>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; + status = "disabled"; + }; + + pwm4: pwm@fe6e0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + //pinctrl-0 = <&pwm0_pin>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@fe6e0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + //pinctrl-0 = <&pwm0_pin>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@fe6e0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + //pinctrl-0 = <&pwm0_pin>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@fe6e0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm8: pwm@fe6f0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@fe6f0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@fe6f0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@fe6f0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm12: pwm@fe700000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm13: pwm@fe700010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm14: pwm@fe700020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm15: pwm@fe700030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + saradc: saradc@fe720000 { + compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xfe720000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3568-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi new file mode 100644 index 000000000000..bba97f68371b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +&pinctrl { + + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; +}; +