From 979b9e6c84ac1d0ed3aade577f8a6b20f71f01dd Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Tue, 31 Jan 2023 16:33:06 +0800 Subject: [PATCH 001/258] media: rockchip: subdev-itf: remove empty runtime suspend/resume drivers/media/platform/rockchip/cif/subdev-itf.c:1172:12: warning: 'sditf_runtime_resume' defined but not used [-Wunused-function] error, forbidden warning:subdev-itf.c:1172 1172 | static int sditf_runtime_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ drivers/media/platform/rockchip/cif/subdev-itf.c:1167:12: warning: 'sditf_runtime_suspend' defined but not used [-Wunused-function] error, forbidden warning:subdev-itf.c:1167 1167 | static int sditf_runtime_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Jianqun Xu Change-Id: I537818f182741704e55f0bb59c623e1118bf5838 --- drivers/media/platform/rockchip/cif/subdev-itf.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/subdev-itf.c b/drivers/media/platform/rockchip/cif/subdev-itf.c index 519dc5c17ad0..eac2af4d2abf 100644 --- a/drivers/media/platform/rockchip/cif/subdev-itf.c +++ b/drivers/media/platform/rockchip/cif/subdev-itf.c @@ -1189,21 +1189,6 @@ static int rkcif_subdev_remove(struct platform_device *pdev) return 0; } -static int sditf_runtime_suspend(struct device *dev) -{ - return 0; -} - -static int sditf_runtime_resume(struct device *dev) -{ - return 0; -} - -static const struct dev_pm_ops rkcif_subdev_pm_ops = { - SET_RUNTIME_PM_OPS(sditf_runtime_suspend, - sditf_runtime_resume, NULL) -}; - static const struct of_device_id rkcif_subdev_match_id[] = { { .compatible = "rockchip,rkcif-sditf", @@ -1217,7 +1202,6 @@ struct platform_driver rkcif_subdev_driver = { .remove = rkcif_subdev_remove, .driver = { .name = "rkcif_sditf", - .pm = &rkcif_subdev_pm_ops, .of_match_table = rkcif_subdev_match_id, }, }; From a3e576bb9d8e22e1387a3ec2ba0ff9960717ee2f Mon Sep 17 00:00:00 2001 From: Huang zhibao Date: Wed, 1 Feb 2023 15:53:15 +0800 Subject: [PATCH 002/258] arm64: dts: rockchip: rk3528-evb: remove firmware node Signed-off-by: Huang zhibao Change-Id: Ie5542723077158e1c17f019bd6a8d46eafe3c1bf --- .../dts/rockchip/rk3528-evb1-ddr4-v10.dts | 23 ------------------ .../dts/rockchip/rk3528-evb2-ddr3-v10.dts | 22 ----------------- .../dts/rockchip/rk3528-evb3-lp4x-v10.dts | 23 ------------------ .../dts/rockchip/rk3528-evb4-ddr4-v10.dts | 24 +++---------------- .../dts/rockchip/rk3528-iotest-lp3-v10.dts | 24 ++----------------- 5 files changed, 5 insertions(+), 111 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10.dts index ea05ddee8e77..b0a531482bcd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10.dts @@ -7,29 +7,6 @@ #include "rk3528-evb1-ddr4-v10.dtsi" #include "rk3528-android.dtsi" -/{ - firmware { - android { - compatible = "android,firmware"; - boot_devices = "ffbf0000.mmc"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait,avb"; - }; - }; - }; - }; -}; - &sdmmc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb2-ddr3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3528-evb2-ddr3-v10.dts index d94fbf14ad17..24dbe38c338e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-evb2-ddr3-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-evb2-ddr3-v10.dts @@ -7,25 +7,3 @@ #include "rk3528-evb2-ddr3-v10.dtsi" #include "rk3528-android.dtsi" -/{ - firmware { - android { - compatible = "android,firmware"; - boot_devices = "ffbf0000.mmc"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait,avb"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dts index 8bfbdb5e4db8..07b921886bc8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-evb3-lp4x-v10.dts @@ -7,29 +7,6 @@ #include "rk3528-evb3-lp4x-v10.dtsi" #include "rk3528-android.dtsi" -/{ - firmware { - android { - compatible = "android,firmware"; - boot_devices = "ffbf0000.mmc"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait,avb"; - }; - }; - }; - }; -}; - &pdm { status = "okay"; pinctrl-0 = <&pdm_clk1 diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb4-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3528-evb4-ddr4-v10.dts index ea05ddee8e77..8b5c9e89d90c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-evb4-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-evb4-ddr4-v10.dts @@ -7,27 +7,9 @@ #include "rk3528-evb1-ddr4-v10.dtsi" #include "rk3528-android.dtsi" -/{ - firmware { - android { - compatible = "android,firmware"; - boot_devices = "ffbf0000.mmc"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait,avb"; - }; - }; - }; - }; +/ { + model = "Rockchip rk3528 evb4 board"; + compatible = "rockchip,rk3528-evb4-ddr4-v10", "rockchip,rk3528"; }; &sdmmc { diff --git a/arch/arm64/boot/dts/rockchip/rk3528-iotest-lp3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3528-iotest-lp3-v10.dts index 2e6e1f58eaef..62326ae09680 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-iotest-lp3-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-iotest-lp3-v10.dts @@ -10,27 +10,7 @@ #include "rk3528-android.dtsi" / { - model = "Rockchip RK3528 IOTEST LP3 V10 Board"; + model = "Rockchip rk3528 iotest board"; compatible = "rockchip,rk3528-iotest-lp3-v10", "rockchip,rk3528"; - - firmware { - android { - compatible = "android,firmware"; - boot_devices = "ffbf0000.mmc"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait,avb"; - }; - }; - }; - }; }; + From 8e4a5fef5b5d1d71b16989e779ab71dfb4b1b82b Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 30 Jan 2023 09:41:32 +0800 Subject: [PATCH 003/258] arm64: dts: rockchip: rk3568: Rename sdhci compatible property Since we modify the sdhci driver to match upstream, so the compatible property should be adjust to match it. Signed-off-by: Shawn Lin Change-Id: Ia768d530047db95c29d5740ed5b039e7d92428cc --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index e44833f9bc04..2f9174d1fad9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -2605,7 +2605,7 @@ }; sdhci: sdhci@fe310000 { - compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci"; + compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci"; reg = <0x0 0xfe310000 0x0 0x10000>; interrupts = ; assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, From 9fbb9ccaf7f53946afe5eee835b04a9b445cf75c Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Sun, 29 Jan 2023 17:56:33 +0800 Subject: [PATCH 004/258] mmc: sdhci-of-dwcmshc: Sync code with upstream as possible To make backport and upstream work easier. After this patch, we just need to focus some rk specific additional code. Sync to upstream commit a0753ef66c34 ("mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC"). Signed-off-by: Shawn Lin Change-Id: Ie3b76ea2848ac3570bb9bc0be09c6f6a67685658 --- drivers/mmc/host/sdhci-of-dwcmshc.c | 360 ++++++++++++++++++---------- 1 file changed, 235 insertions(+), 125 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index eb56f672eb0f..ce37d8173adb 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -27,11 +27,15 @@ /* DWCMSHC specific Mode Select value */ #define DWCMSHC_CTRL_HS400 0x7 -#define DWCMSHC_VER_ID 0x500 -#define DWCMSHC_VER_TYPE 0x504 -#define DWCMSHC_HOST_CTRL3 0x508 -#define DWCMSHC_EMMC_CONTROL 0x52c -#define DWCMSHC_EMMC_ATCTRL 0x540 +/* DWC IP vendor area 1 pointer */ +#define DWCMSHC_P_VENDOR_AREA1 0xe8 +#define DWCMSHC_AREA1_MASK GENMASK(11, 0) +/* Offset inside the vendor area 1 */ +#define DWCMSHC_HOST_CTRL3 0x8 +#define DWCMSHC_EMMC_CONTROL 0x2c +#define DWCMSHC_CARD_IS_EMMC BIT(0) +#define DWCMSHC_ENHANCED_STROBE BIT(8) +#define DWCMSHC_EMMC_ATCTRL 0x40 /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL 0x800 @@ -41,30 +45,28 @@ #define DECMSHC_EMMC_DLL_CMDOUT 0x810 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 #define DWCMSHC_EMMC_DLL_STATUS1 0x844 - #define DWCMSHC_EMMC_DLL_START BIT(0) #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) +#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 #define DWCMSHC_EMMC_DLL_START_POINT 16 #define DWCMSHC_EMMC_DLL_INC 8 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) - +#define DLL_TXCLK_TAPNUM_DEFAULT 0x10 +#define DLL_TXCLK_TAPNUM_90_DEGREES 0xA #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) -#define DLL_TXCLK_NO_INVERTER BIT(29) - +#define DLL_STRBIN_TAPNUM_DEFAULT 0x8 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) #define DLL_STRBIN_DELAY_NUM_OFFSET 16 - +#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 +#define DLL_RXCLK_NO_INVERTER 1 +#define DLL_RXCLK_INVERTER 0 +#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 #define DLL_RXCLK_TAPNUM_FROM_SW BIT(24) -#define DLL_RXCLK_NO_INVERTER BIT(29) #define DLL_RXCLK_ORI_GATE BIT(31) #define DLL_RXCLK_MAX_TAP 32 - -#define DWCMSHC_CARD_IS_EMMC BIT(0) -#define DWCMSHC_ENHANCED_STROBE BIT(8) - #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) @@ -73,11 +75,16 @@ #define DLL_LOCK_WO_TMOUT(x) \ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) -#define ROCKCHIP_MAX_CLKS 3 +#define RK35xx_MAX_CLKS 3 #define BOUNDARY_OK(addr, len) \ ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) +enum dwcmshc_rk_type { + DWCMSHC_RK3568, + DWCMSHC_RK3588, +}; + struct dwcmshc_driver_data { const struct sdhci_pltfm_data *pdata; u32 flags; @@ -93,19 +100,25 @@ struct dwcmshc_driver_data { u8 hs400_strbin_tap; }; -struct dwcmshc_priv { - struct clk *bus_clk; +struct rk35xx_priv { + /* Rockchip specified optional clocks */ + struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS]; + struct reset_control *reset; + enum dwcmshc_rk_type devtype; + u8 txclk_tapnum; u32 cclk_rate; u8 hs200_rx_tap; - - /* Rockchip specified optional clocks */ - struct clk_bulk_data rockchip_clks[ROCKCHIP_MAX_CLKS]; - struct reset_control *reset; unsigned int actual_clk; const struct dwcmshc_driver_data *drv_data; u32 acpi_en; }; +struct dwcmshc_priv { + struct clk *bus_clk; + int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */ + void *priv; /* pointer to SoC private stuff */ +}; + /* * If DMA addr spans 128MB boundary, we split the DMA transfer into two * so that each DMA transfer doesn't exceed the boundary. @@ -129,6 +142,16 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, sdhci_adma_write_desc(host, desc, addr, len, cmd); } +static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + if (pltfm_host->clk) + return sdhci_pltfm_clk_get_max_clock(host); + else + return pltfm_host->clock; +} + static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, struct mmc_request *mrq) { @@ -155,7 +178,9 @@ static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { - u16 ctrl_2, ctrl; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u16 ctrl, ctrl_2; ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); /* Select Bus Speed Mode for host */ @@ -175,9 +200,9 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, ctrl_2 |= SDHCI_CTRL_UHS_DDR50; else if (timing == MMC_TIMING_MMC_HS400) { /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ - ctrl = sdhci_readw(host, DWCMSHC_EMMC_CONTROL); + ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); ctrl |= DWCMSHC_CARD_IS_EMMC; - sdhci_writew(host, ctrl, DWCMSHC_EMMC_CONTROL); + sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); ctrl_2 |= DWCMSHC_CTRL_HS400; } @@ -190,22 +215,28 @@ static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, { u32 vendor; struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL; - vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL); + vendor = sdhci_readl(host, reg); if (ios->enhanced_strobe) vendor |= DWCMSHC_ENHANCED_STROBE; else vendor &= ~DWCMSHC_ENHANCED_STROBE; - sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL); + sdhci_writel(host, vendor, reg); } -static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) +static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); + struct rk35xx_priv *priv = dwc_priv->priv; const struct dwcmshc_driver_data *drv_data = priv->drv_data; - u32 txclk_tapnum, extra, rxclk_tapnum; + u8 rxclk_tapnum; + u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; + u32 extra, reg; int err; host->mmc->actual_clock = 0; @@ -238,9 +269,10 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_set_clock(host, clock); /* Disable cmd conflict check */ - extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3); + reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; + extra = sdhci_readl(host, reg); extra &= ~BIT(0); - sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3); + sdhci_writel(host, extra, reg); if (clock <= 52000000) { /* @@ -270,6 +302,7 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) /* Init DLL settings, clean start bit before resetting */ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); + /* Init DLL settings */ extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 0x2 << DWCMSHC_EMMC_DLL_INC | DWCMSHC_EMMC_DLL_START; @@ -285,7 +318,7 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) extra = 0x1 << 16 | /* tune clock stop en */ 0x3 << 17 | /* pre-change delay */ 0x3 << 19; /* post-change delay */ - sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL); + sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); rxclk_tapnum = priv->hs200_rx_tap; if ((drv_data->flags & RK_RXCLK_NO_INVERTER) && @@ -296,7 +329,7 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) } extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE; if (drv_data->flags & RK_RXCLK_NO_INVERTER) - extra |= DLL_RXCLK_NO_INVERTER; + extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; if (drv_data->flags & RK_RXCLK_SW_TUNING && priv->hs200_rx_tap) extra |= DLL_RXCLK_TAPNUM_FROM_SW | rxclk_tapnum; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); @@ -314,7 +347,7 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) } extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_TXCLK_TAPNUM_FROM_SW | - DLL_RXCLK_NO_INVERTER | + DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL | txclk_tapnum; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); @@ -324,19 +357,16 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } -static void rockchip_sdhci_reset(struct sdhci_host *host, u8 mask) +static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) { - struct sdhci_pltfm_host *pltfm_host; - struct dwcmshc_priv *priv; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); + struct rk35xx_priv *priv = dwc_priv->priv; - if (mask & SDHCI_RESET_ALL) { - pltfm_host = sdhci_priv(host); - priv = sdhci_pltfm_priv(pltfm_host); - if (!IS_ERR_OR_NULL(priv->reset)) { - reset_control_assert(priv->reset); - udelay(1); - reset_control_deassert(priv->reset); - } + if (mask & SDHCI_RESET_ALL && priv->reset) { + reset_control_assert(priv->reset); + udelay(1); + reset_control_deassert(priv->reset); } sdhci_reset(host, mask); @@ -354,7 +384,8 @@ static int dwcmshc_rk_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct sdhci_host *host = mmc_priv(mmc); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); + struct rk35xx_priv *priv = dwc_priv->priv; int rx_delay, dll_lock_num, ret; u32 extra; @@ -365,7 +396,7 @@ static int dwcmshc_rk_execute_tuning(struct mmc_host *mmc, u32 opcode) sdhci_reset_tuning(host); priv->hs200_rx_tap = rx_delay * 16 / dll_lock_num; extra = sdhci_readl(host, DWCMSHC_EMMC_DLL_RXCLK); - extra &= DLL_RXCLK_NO_INVERTER; + extra &= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; extra |= DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE | DLL_RXCLK_TAPNUM_FROM_SW | priv->hs200_rx_tap; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); @@ -378,17 +409,17 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = dwcmshc_set_uhs_signaling, - .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .get_max_clock = dwcmshc_get_max_clock, .reset = sdhci_reset, .adma_write_desc = dwcmshc_adma_write_desc, }; -static const struct sdhci_ops sdhci_dwcmshc_rk_ops = { - .set_clock = dwcmshc_rk_set_clock, +static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { + .set_clock = dwcmshc_rk3568_set_clock, .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = dwcmshc_set_uhs_signaling, .get_max_clock = sdhci_pltfm_clk_get_max_clock, - .reset = rockchip_sdhci_reset, + .reset = rk35xx_sdhci_reset, .adma_write_desc = dwcmshc_adma_write_desc, .request_done = sdhci_dwcmshc_request_done, }; @@ -399,20 +430,84 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, }; -static const struct sdhci_pltfm_data sdhci_dwcmshc_rk_pdata = { - .ops = &sdhci_dwcmshc_rk_ops, +#ifdef CONFIG_ACPI +static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { + .ops = &sdhci_dwcmshc_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ACMD23_BROKEN, +}; +#endif + +static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { + .ops = &sdhci_dwcmshc_rk35xx_ops, .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, }; +static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) +{ + int err; + struct rk35xx_priv *priv = dwc_priv->priv; + + priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); + if (IS_ERR(priv->reset)) { + err = PTR_ERR(priv->reset); + dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); + return err; + } + + priv->rockchip_clks[0].id = "axi"; + priv->rockchip_clks[1].id = "block"; + priv->rockchip_clks[2].id = "timer"; + err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS, + priv->rockchip_clks); + if (err) { + dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); + return err; + } + + err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks); + if (err) { + dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); + return err; + } + + if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", + &priv->txclk_tapnum)) + priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; + + /* Disable cmd conflict check */ + sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); + /* Reset previous settings */ + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); + + return 0; +} + +static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) +{ + /* + * Don't support highspeed bus mode with low clk speed as we + * cannot use DLL for this condition. + */ + if (host->mmc->f_max <= 52000000) { + dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", + host->mmc->f_max); + host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); + host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); + } +} + static const struct dwcmshc_driver_data dwcmshc_drvdata = { .pdata = &sdhci_dwcmshc_pdata, .flags = 0, }; static const struct dwcmshc_driver_data rk3568_drvdata = { - .pdata = &sdhci_dwcmshc_rk_pdata, + .pdata = &sdhci_dwcmshc_rk35xx_pdata, .flags = RK_PLATFROM | RK_RXCLK_NO_INVERTER, .hs200_tx_tap = 16, .hs400_tx_tap = 8, @@ -422,7 +517,7 @@ static const struct dwcmshc_driver_data rk3568_drvdata = { }; static const struct dwcmshc_driver_data rk3588_drvdata = { - .pdata = &sdhci_dwcmshc_rk_pdata, + .pdata = &sdhci_dwcmshc_rk35xx_pdata, .flags = RK_PLATFROM | RK_DLL_CMD_OUT, .hs200_tx_tap = 16, .hs400_tx_tap = 9, @@ -432,7 +527,7 @@ static const struct dwcmshc_driver_data rk3588_drvdata = { }; static const struct dwcmshc_driver_data rk3528_drvdata = { - .pdata = &sdhci_dwcmshc_rk_pdata, + .pdata = &sdhci_dwcmshc_rk35xx_pdata, .flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_RXCLK_SW_TUNING | RK_RXCLK_NO_INVERTER, .hs200_tx_tap = 12, .hs400_tx_tap = 6, @@ -441,51 +536,13 @@ static const struct dwcmshc_driver_data rk3528_drvdata = { .ddr50_strbin_delay_num = 10, }; -static int rockchip_pltf_init(struct sdhci_host *host, struct dwcmshc_priv *priv) -{ - int err; - - priv->rockchip_clks[0].id = "axi"; - priv->rockchip_clks[1].id = "block"; - priv->rockchip_clks[2].id = "timer"; - err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), ROCKCHIP_MAX_CLKS, - priv->rockchip_clks); - if (err) { - dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); - return err; - } - - err = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks); - if (err) { - dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); - return err; - } - - /* Disable cmd conflict check */ - sdhci_writel(host, 0x0, DWCMSHC_HOST_CTRL3); - /* Reset previous settings */ - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); - - /* - * Don't support highspeed bus mode with low clk speed as we - * cannot use DLL for this condition. - */ - if (host->mmc->f_max <= 52000000) { - host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); - host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); - } - - return 0; -} - static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { { - .compatible = "snps,dwcmshc-sdhci", - .data = &dwcmshc_drvdata, + .compatible = "rockchip,rk3588-dwcmshc", + .data = &rk3588_drvdata, }, { - .compatible = "rockchip,dwcmshc-sdhci", + .compatible = "rockchip,rk3568-dwcmshc", .data = &rk3568_drvdata, }, { @@ -493,17 +550,31 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { .data = &rk3528_drvdata, }, { - .compatible = "rockchip,rk3588-dwcmshc", - .data = &rk3588_drvdata, + .compatible = "snps,dwcmshc-sdhci", + .data = &dwcmshc_drvdata, }, {}, }; +MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); + +#ifdef CONFIG_ACPI +static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = { + { + .id = "MLNXBF30", + .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata, + }, + {} +}; +#endif static int dwcmshc_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct sdhci_pltfm_host *pltfm_host; struct sdhci_host *host; struct dwcmshc_priv *priv; + struct rk35xx_priv *rk_priv = NULL; + const struct sdhci_pltfm_data *pltfm_data; const struct dwcmshc_driver_data *drv_data; struct mmc_hsq *hsq; int err; @@ -514,8 +585,9 @@ static int dwcmshc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Error: No device match data found\n"); return -ENODEV; } + pltfm_data = drv_data->pdata; - host = sdhci_pltfm_init(pdev, drv_data->pdata, + host = sdhci_pltfm_init(pdev, pltfm_data, sizeof(struct dwcmshc_priv)); if (IS_ERR(host)) return PTR_ERR(host); @@ -523,30 +595,26 @@ static int dwcmshc_probe(struct platform_device *pdev) /* * extra adma table cnt for cross 128M boundary handling. */ - extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M); + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); if (extra > SDHCI_MAX_SEGS) extra = SDHCI_MAX_SEGS; host->adma_table_cnt += extra; pltfm_host = sdhci_priv(host); priv = sdhci_pltfm_priv(pltfm_host); - priv->drv_data = drv_data; - priv->acpi_en = has_acpi_companion(&pdev->dev); - - if (!priv->acpi_en) { - priv->reset = devm_reset_control_array_get_exclusive(&pdev->dev); - pltfm_host->clk = devm_clk_get(&pdev->dev, "core"); + if (dev->of_node) { + pltfm_host->clk = devm_clk_get(dev, "core"); if (IS_ERR(pltfm_host->clk)) { err = PTR_ERR(pltfm_host->clk); - dev_err(&pdev->dev, "failed to get core clk: %d\n", err); + dev_err(dev, "failed to get core clk: %d\n", err); goto free_pltfm; } err = clk_prepare_enable(pltfm_host->clk); if (err) goto free_pltfm; - priv->bus_clk = devm_clk_get(&pdev->dev, "bus"); + priv->bus_clk = devm_clk_get(dev, "bus"); if (!IS_ERR(priv->bus_clk)) clk_prepare_enable(priv->bus_clk); } @@ -557,6 +625,9 @@ static int dwcmshc_probe(struct platform_device *pdev) sdhci_get_of_property(pdev); + priv->vendor_specific_area1 = + sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; + host->mmc_host_ops.request = dwcmshc_request; host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; @@ -570,20 +641,45 @@ static int dwcmshc_probe(struct platform_device *pdev) if (err) goto err_clk; - err = sdhci_add_host(host); - if (err) - goto err_clk; - if (drv_data->flags & RK_PLATFROM) { - priv->hs200_rx_tap = 0; + rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); + if (!rk_priv) { + err = -ENOMEM; + goto err_clk; + } + + rk_priv->drv_data = drv_data; + rk_priv->hs200_rx_tap = 0; + rk_priv->acpi_en = has_acpi_companion(&pdev->dev); + + if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc")) + rk_priv->devtype = DWCMSHC_RK3588; + else + rk_priv->devtype = DWCMSHC_RK3568; + + priv->priv = rk_priv; + if (drv_data->flags & RK_RXCLK_SW_TUNING) host->mmc_host_ops.execute_tuning = dwcmshc_rk_execute_tuning; - err = rockchip_pltf_init(host, priv); + err = dwcmshc_rk35xx_init(host, priv); if (err) goto err_clk; } - if (!priv->acpi_en) { + host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; + + err = sdhci_setup_host(host); + if (err) + goto err_clk; + + if (rk_priv) + dwcmshc_rk35xx_postinit(host, priv); + + err = __sdhci_add_host(host); + if (err) + goto err_setup_host; + + if (rk_priv && !rk_priv->acpi_en) { pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); @@ -594,10 +690,14 @@ static int dwcmshc_probe(struct platform_device *pdev) return 0; +err_setup_host: + sdhci_cleanup_host(host); err_clk: clk_disable_unprepare(pltfm_host->clk); clk_disable_unprepare(priv->bus_clk); - clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks); + if (rk_priv) + clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, + rk_priv->rockchip_clks); free_pltfm: sdhci_pltfm_free(pdev); return err; @@ -608,13 +708,15 @@ static int dwcmshc_remove(struct platform_device *pdev) struct sdhci_host *host = platform_get_drvdata(pdev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + struct rk35xx_priv *rk_priv = priv->priv; sdhci_remove_host(host, 0); clk_disable_unprepare(pltfm_host->clk); clk_disable_unprepare(priv->bus_clk); - clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks); - + if (rk_priv) + clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, + rk_priv->rockchip_clks); sdhci_pltfm_free(pdev); return 0; @@ -626,6 +728,7 @@ static int dwcmshc_suspend(struct device *dev) struct sdhci_host *host = dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + struct rk35xx_priv *rk_priv = priv->priv; int ret; mmc_hsq_suspend(host->mmc); @@ -638,7 +741,10 @@ static int dwcmshc_suspend(struct device *dev) if (!IS_ERR(priv->bus_clk)) clk_disable_unprepare(priv->bus_clk); - clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks); + if (rk_priv) + clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, + rk_priv->rockchip_clks); + return ret; } @@ -647,6 +753,7 @@ static int dwcmshc_resume(struct device *dev) struct sdhci_host *host = dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + struct rk35xx_priv *rk_priv = priv->priv; int ret; ret = clk_prepare_enable(pltfm_host->clk); @@ -659,9 +766,12 @@ static int dwcmshc_resume(struct device *dev) return ret; } - ret = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks); - if (ret) - return ret; + if (rk_priv) { + ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, + rk_priv->rockchip_clks); + if (ret) + return ret; + } ret = sdhci_resume_host(host); if (ret) @@ -699,13 +809,13 @@ static const struct dev_pm_ops dwcmshc_pmops = { SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume) SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, dwcmshc_runtime_resume, NULL) }; -MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); static struct platform_driver sdhci_dwcmshc_driver = { .driver = { .name = "sdhci-dwcmshc", .probe_type = PROBE_PREFER_ASYNCHRONOUS, .of_match_table = sdhci_dwcmshc_dt_ids, + .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids), .pm = &dwcmshc_pmops, }, .probe = dwcmshc_probe, From 19566d91464c7cb75c87d00081d8c58a48cd4e23 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 29 Jun 2022 20:30:08 +0800 Subject: [PATCH 005/258] soc: rockchip: Adds CPU_RK3562 config Signed-off-by: Finley Xiao Change-Id: I6b2911bb567c794be5c1b77fbd4632006b08de7a --- drivers/soc/rockchip/Kconfig.cpu | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/soc/rockchip/Kconfig.cpu b/drivers/soc/rockchip/Kconfig.cpu index 368fa6f9ad44..1ffc763434bf 100644 --- a/drivers/soc/rockchip/Kconfig.cpu +++ b/drivers/soc/rockchip/Kconfig.cpu @@ -60,6 +60,9 @@ config CPU_RK3399 config CPU_RK3528 bool "RK3528" +config CPU_RK3562 + bool "RK3562" + config CPU_RK3568 bool "RK3566/8" From bacbf200df78bbb18ae6abf4028b6dc075e1d641 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 29 Jun 2022 20:30:43 +0800 Subject: [PATCH 006/258] arm64: configs: rockchip_defconfig: enable CPU_RK3562 Signed-off-by: Finley Xiao Change-Id: I374fb618f898c3bbe6ab9baadc1248fa10f371a1 --- arch/arm64/configs/rockchip_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index cf208810305a..c518d4a58a95 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -882,6 +882,7 @@ CONFIG_CPU_RK3328=y CONFIG_CPU_RK3368=y CONFIG_CPU_RK3399=y CONFIG_CPU_RK3528=y +CONFIG_CPU_RK3562=y CONFIG_CPU_RK3568=y CONFIG_CPU_RK3588=y CONFIG_ROCKCHIP_CPUINFO=y From 1d9713df4e54d552015c9d696c89d65b9d60a1a7 Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Mon, 11 Jul 2022 10:41:15 +0800 Subject: [PATCH 007/258] pinctrl: rockchip: add rk3562 support Signed-off-by: Steven Liu Change-Id: Ifaa8c80bf109ed6b710e4d1ccb3e2bf379bc0299 --- drivers/pinctrl/pinctrl-rockchip.c | 215 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 215 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index ceb7318d8ac4..a6756048aadd 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1223,6 +1223,19 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + /* rk3562 force jtag m1 */ + if (ctrl->type == RK3562) { + if (bank->bank_num == 1) { + if ((pin == RK_PB5) || (pin == RK_PB6)) { + if (mux == 1) { + regmap_update_bits(regmap, 0x504, 0x10001, 0x10001); + } else { + regmap_update_bits(regmap, 0x504, 0x10001, 0x10000); + } + } + } + } + if (ctrl->type == RK3588) { if (bank->bank_num == 0) { if ((pin >= RK_PB4) && (pin <= RK_PD7)) { @@ -2415,6 +2428,151 @@ static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RK3562_DRV_BITS_PER_PIN 8 +#define RK3562_DRV_PINS_PER_REG 2 +#define RK3562_DRV_GPIO0_OFFSET 0x20070 +#define RK3562_DRV_GPIO1_OFFSET 0x200 +#define RK3562_DRV_GPIO2_OFFSET 0x240 +#define RK3562_DRV_GPIO3_OFFSET 0x10280 +#define RK3562_DRV_GPIO4_OFFSET 0x102C0 + +static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3562_DRV_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3562_DRV_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3562_DRV_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3562_DRV_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3562_DRV_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3562_DRV_PINS_PER_REG; + *bit *= RK3562_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3562_PULL_BITS_PER_PIN 2 +#define RK3562_PULL_PINS_PER_REG 8 +#define RK3562_PULL_GPIO0_OFFSET 0x20020 +#define RK3562_PULL_GPIO1_OFFSET 0x80 +#define RK3562_PULL_GPIO2_OFFSET 0x90 +#define RK3562_PULL_GPIO3_OFFSET 0x100A0 +#define RK3562_PULL_GPIO4_OFFSET 0x100B0 + +static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3562_PULL_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3562_PULL_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3562_PULL_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3562_PULL_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3562_PULL_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3562_PULL_PINS_PER_REG; + *bit *= RK3562_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3562_SMT_BITS_PER_PIN 2 +#define RK3562_SMT_PINS_PER_REG 8 +#define RK3562_SMT_GPIO0_OFFSET 0x20030 +#define RK3562_SMT_GPIO1_OFFSET 0xC0 +#define RK3562_SMT_GPIO2_OFFSET 0xD0 +#define RK3562_SMT_GPIO3_OFFSET 0x100E0 +#define RK3562_SMT_GPIO4_OFFSET 0x100F0 + +static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3562_SMT_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3562_SMT_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3562_SMT_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3562_SMT_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3562_SMT_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3562_SMT_PINS_PER_REG; + *bit *= RK3562_SMT_BITS_PER_PIN; + + return 0; +} + #define RK3568_SR_PMU_OFFSET 0x60 #define RK3568_SR_GRF_OFFSET 0x0180 #define RK3568_SR_BANK_STRIDE 0x10 @@ -2830,7 +2988,10 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RV1126_DRV_BITS_PER_PIN; ret = strength; goto config; - } else if (ctrl->type == RV1106 || ctrl->type == RK3568 || ctrl->type == RK3528) { + } else if (ctrl->type == RV1106 || + ctrl->type == RK3528 || + ctrl->type == RK3562 || + ctrl->type == RK3568) { rmask_bits = RK3568_DRV_BITS_PER_PIN; ret = (1 << (strength + 1)) - 1; goto config; @@ -3003,6 +3164,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RK3368: case RK3399: case RK3528: + case RK3562: case RK3568: case RK3588: pull_type = bank->pull_type[pin_num / 8]; @@ -3056,6 +3218,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3368: case RK3399: case RK3528: + case RK3562: case RK3568: case RK3588: pull_type = bank->pull_type[pin_num / 8]; @@ -3166,6 +3329,7 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) data >>= bit; switch (ctrl->type) { + case RK3562: case RK3568: return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); default: @@ -3195,6 +3359,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, /* enable the write to the equivalent lower bits */ switch (ctrl->type) { + case RK3562: case RK3568: data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); rmask = data | (data >> 16); @@ -3391,6 +3556,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3368: case RK3399: case RK3528: + case RK3562: case RK3568: case RK3588: return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); @@ -4722,6 +4888,49 @@ static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = { .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit, }; +static struct rockchip_pin_bank rk3562_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20000, 0x20008, 0x20010, 0x20018), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, 0x08, 0x10, 0x18), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10040, 0x10048, 0x10050, 0x10058), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, + 0, + 0x10060, 0x10068, 0, 0), +}; + +static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = { + .pin_banks = rk3562_pin_banks, + .nr_banks = ARRAY_SIZE(rk3562_pin_banks), + .label = "RK3562-GPIO", + .type = RK3562, + .pull_calc_reg = rk3562_calc_pull_reg_and_bit, + .drv_calc_reg = rk3562_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk3568_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, @@ -4856,6 +5065,10 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk3528-pinctrl", .data = &rk3528_pin_ctrl }, #endif +#ifdef CONFIG_CPU_RK3562 + { .compatible = "rockchip,rk3562-pinctrl", + .data = &rk3562_pin_ctrl }, +#endif #ifdef CONFIG_CPU_RK3568 { .compatible = "rockchip,rk3568-pinctrl", .data = &rk3568_pin_ctrl }, diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 1a04b3799471..0566b8b7c8ef 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -200,6 +200,7 @@ enum rockchip_pinctrl_type { RK3368, RK3399, RK3528, + RK3562, RK3568, RK3588, }; From 14d8aa4a04bb9e480c0d6119e4c740f50b16254c Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 29 Jun 2022 20:31:16 +0800 Subject: [PATCH 008/258] clk: rockchip: add dt-binding header for rk3562 Add the dt-bindings header for the rk3562, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3562. Signed-off-by: Finley Xiao Signed-off-by: Liang Chen Change-Id: I25c4b2b8276f7d371ae861fdd24bd98fcf7c1629 --- include/dt-bindings/clock/rk3562-cru.h | 729 +++++++++++++++++++++++++ 1 file changed, 729 insertions(+) create mode 100644 include/dt-bindings/clock/rk3562-cru.h diff --git a/include/dt-bindings/clock/rk3562-cru.h b/include/dt-bindings/clock/rk3562-cru.h new file mode 100644 index 000000000000..bee65dbf450c --- /dev/null +++ b/include/dt-bindings/clock/rk3562-cru.h @@ -0,0 +1,729 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_APLL 1 +#define PLL_GPLL 2 +#define PLL_VPLL 3 +#define PLL_HPLL 4 +#define PLL_CPLL 5 +#define PLL_DPLL 6 + +/* cru clocks */ +#define ARMCLK 8 +#define CLK_GPU 9 +#define ACLK_RKNN 10 +#define CLK_DDR 11 +#define CLK_MATRIX_50M_SRC 12 +#define CLK_MATRIX_100M_SRC 13 +#define CLK_MATRIX_125M_SRC 14 +#define CLK_MATRIX_200M_SRC 15 +#define CLK_MATRIX_300M_SRC 16 +#define ACLK_TOP 17 +#define ACLK_TOP_VIO 18 +#define CLK_CAM0_OUT2IO 19 +#define CLK_CAM1_OUT2IO 20 +#define CLK_CAM2_OUT2IO 21 +#define CLK_CAM3_OUT2IO 22 +#define ACLK_BUS 23 +#define HCLK_BUS 24 +#define PCLK_BUS 25 +#define PCLK_I2C1 26 +#define PCLK_I2C2 27 +#define PCLK_I2C3 28 +#define PCLK_I2C4 29 +#define PCLK_I2C5 30 +#define CLK_I2C 31 +#define CLK_I2C1 32 +#define CLK_I2C2 33 +#define CLK_I2C3 34 +#define CLK_I2C4 35 +#define CLK_I2C5 36 +#define DCLK_BUS_GPIO 37 +#define DCLK_BUS_GPIO3 38 +#define DCLK_BUS_GPIO4 39 +#define PCLK_TIMER 40 +#define CLK_TIMER0 41 +#define CLK_TIMER1 42 +#define CLK_TIMER2 43 +#define CLK_TIMER3 44 +#define CLK_TIMER4 45 +#define CLK_TIMER5 46 +#define PCLK_STIMER 47 +#define CLK_STIMER0 48 +#define CLK_STIMER1 49 +#define PCLK_WDTNS 50 +#define CLK_WDTNS 51 +#define PCLK_GRF 52 +#define PCLK_SGRF 53 +#define PCLK_MAILBOX 54 +#define PCLK_INTC 55 +#define ACLK_BUS_GIC400 56 +#define ACLK_BUS_SPINLOCK 57 +#define ACLK_DCF 58 +#define PCLK_DCF 59 +#define FCLK_BUS_CM0_CORE 60 +#define CLK_BUS_CM0_RTC 61 +#define HCLK_ICACHE 62 +#define HCLK_DCACHE 63 +#define PCLK_TSADC 64 +#define CLK_TSADC 65 +#define CLK_TSADC_TSEN 66 +#define PCLK_DFT2APB 67 +#define CLK_SARADC_VCCIO156 68 +#define PCLK_GMAC 69 +#define ACLK_GMAC 70 +#define CLK_GMAC_125M_CRU_I 71 +#define CLK_GMAC_50M_CRU_I 72 +#define CLK_GMAC_50M_O 73 +#define CLK_GMAC_ETH_OUT2IO 74 +#define PCLK_APB2ASB_VCCIO156 75 +#define PCLK_TO_VCCIO156 76 +#define PCLK_DSIPHY 77 +#define PCLK_DSITX 78 +#define PCLK_CPU_EMA_DET 79 +#define PCLK_HASH 80 +#define PCLK_TOPCRU 81 +#define PCLK_ASB2APB_VCCIO156 82 +#define PCLK_IOC_VCCIO156 83 +#define PCLK_GPIO3_VCCIO156 84 +#define PCLK_GPIO4_VCCIO156 85 +#define PCLK_SARADC_VCCIO156 86 +#define PCLK_MAC100 87 +#define ACLK_MAC100 89 +#define CLK_MAC100_50M_MATRIX 90 +#define HCLK_CORE 91 +#define PCLK_DDR 92 +#define CLK_MSCH_BRG_BIU 93 +#define PCLK_DDR_HWLP 94 +#define PCLK_DDR_UPCTL 95 +#define PCLK_DDR_PHY 96 +#define PCLK_DDR_DFICTL 97 +#define PCLK_DDR_DMA2DDR 98 +#define PCLK_DDR_MON 99 +#define TMCLK_DDR_MON 100 +#define PCLK_DDR_GRF 101 +#define PCLK_DDR_CRU 102 +#define PCLK_SUBDDR_CRU 103 +#define CLK_GPU_PRE 104 +#define ACLK_GPU_PRE 105 +#define CLK_GPU_BRG 107 +#define CLK_NPU_PRE 108 +#define HCLK_NPU_PRE 109 +#define HCLK_RKNN 111 +#define ACLK_PERI 112 +#define HCLK_PERI 113 +#define PCLK_PERI 114 +#define PCLK_PERICRU 115 +#define HCLK_SAI0 116 +#define CLK_SAI0_SRC 117 +#define CLK_SAI0_FRAC 118 +#define CLK_SAI0 119 +#define MCLK_SAI0 120 +#define MCLK_SAI0_OUT2IO 121 +#define HCLK_SAI1 122 +#define CLK_SAI1_SRC 123 +#define CLK_SAI1_FRAC 124 +#define CLK_SAI1 125 +#define MCLK_SAI1 126 +#define MCLK_SAI1_OUT2IO 127 +#define HCLK_SAI2 128 +#define CLK_SAI2_SRC 129 +#define CLK_SAI2_FRAC 130 +#define CLK_SAI2 131 +#define MCLK_SAI2 132 +#define MCLK_SAI2_OUT2IO 133 +#define HCLK_DSM 134 +#define CLK_DSM 135 +#define HCLK_PDM 136 +#define MCLK_PDM 137 +#define HCLK_SPDIF 138 +#define CLK_SPDIF_SRC 139 +#define CLK_SPDIF_FRAC 140 +#define CLK_SPDIF 141 +#define MCLK_SPDIF 142 +#define HCLK_SDMMC0 143 +#define CCLK_SDMMC0 144 +#define HCLK_SDMMC1 145 +#define CCLK_SDMMC1 146 +#define SCLK_SDMMC0_DRV 147 +#define SCLK_SDMMC0_SAMPLE 148 +#define SCLK_SDMMC1_DRV 149 +#define SCLK_SDMMC1_SAMPLE 150 +#define HCLK_EMMC 151 +#define ACLK_EMMC 152 +#define CCLK_EMMC 153 +#define BCLK_EMMC 154 +#define TMCLK_EMMC 155 +#define SCLK_SFC 156 +#define HCLK_SFC 157 +#define HCLK_USB2HOST 158 +#define HCLK_USB2HOST_ARB 159 +#define PCLK_SPI1 160 +#define CLK_SPI1 161 +#define SCLK_IN_SPI1 162 +#define PCLK_SPI2 163 +#define CLK_SPI2 164 +#define SCLK_IN_SPI2 165 +#define PCLK_UART1 166 +#define PCLK_UART2 167 +#define PCLK_UART3 168 +#define PCLK_UART4 169 +#define PCLK_UART5 170 +#define PCLK_UART6 171 +#define PCLK_UART7 172 +#define PCLK_UART8 173 +#define PCLK_UART9 174 +#define CLK_UART1_SRC 175 +#define CLK_UART1_FRAC 176 +#define CLK_UART1 177 +#define SCLK_UART1 178 +#define CLK_UART2_SRC 179 +#define CLK_UART2_FRAC 180 +#define CLK_UART2 181 +#define SCLK_UART2 182 +#define CLK_UART3_SRC 183 +#define CLK_UART3_FRAC 184 +#define CLK_UART3 185 +#define SCLK_UART3 186 +#define CLK_UART4_SRC 187 +#define CLK_UART4_FRAC 188 +#define CLK_UART4 189 +#define SCLK_UART4 190 +#define CLK_UART5_SRC 191 +#define CLK_UART5_FRAC 192 +#define CLK_UART5 193 +#define SCLK_UART5 194 +#define CLK_UART6_SRC 195 +#define CLK_UART6_FRAC 196 +#define CLK_UART6 197 +#define SCLK_UART6 198 +#define CLK_UART7_SRC 199 +#define CLK_UART7_FRAC 200 +#define CLK_UART7 201 +#define SCLK_UART7 202 +#define CLK_UART8_SRC 203 +#define CLK_UART8_FRAC 204 +#define CLK_UART8 205 +#define SCLK_UART8 206 +#define CLK_UART9_SRC 207 +#define CLK_UART9_FRAC 208 +#define CLK_UART9 209 +#define SCLK_UART9 210 +#define PCLK_PWM1_PERI 211 +#define CLK_PWM1_PERI 212 +#define CLK_CAPTURE_PWM1_PERI 213 +#define PCLK_PWM2_PERI 214 +#define CLK_PWM2_PERI 215 +#define CLK_CAPTURE_PWM2_PERI 216 +#define PCLK_PWM3_PERI 217 +#define CLK_PWM3_PERI 218 +#define CLK_CAPTURE_PWM3_PERI 219 +#define PCLK_CAN0 220 +#define CLK_CAN0 221 +#define PCLK_CAN1 222 +#define CLK_CAN1 223 +#define ACLK_CRYPTO 224 +#define HCLK_CRYPTO 225 +#define PCLK_CRYPTO 226 +#define CLK_CORE_CRYPTO 227 +#define CLK_PKA_CRYPTO 228 +#define HCLK_KLAD 229 +#define PCLK_KEY_READER 230 +#define HCLK_RK_RNG_NS 231 +#define HCLK_RK_RNG_S 232 +#define HCLK_TRNG_NS 233 +#define HCLK_TRNG_S 234 +#define HCLK_CRYPTO_S 235 +#define PCLK_PERI_WDT 236 +#define TCLK_PERI_WDT 237 +#define ACLK_SYSMEM 238 +#define HCLK_BOOTROM 239 +#define PCLK_PERI_GRF 240 +#define ACLK_DMAC 241 +#define ACLK_RKDMAC 242 +#define PCLK_OTPC_NS 243 +#define CLK_SBPI_OTPC_NS 244 +#define CLK_USER_OTPC_NS 245 +#define PCLK_OTPC_S 246 +#define CLK_SBPI_OTPC_S 247 +#define CLK_USER_OTPC_S 248 +#define CLK_OTPC_ARB 249 +#define PCLK_OTPPHY 250 +#define PCLK_USB2PHY 251 +#define PCLK_PIPEPHY 252 +#define PCLK_SARADC 253 +#define CLK_SARADC 254 +#define PCLK_IOC_VCCIO234 255 +#define PCLK_PERI_GPIO1 256 +#define PCLK_PERI_GPIO2 257 +#define DCLK_PERI_GPIO 258 +#define DCLK_PERI_GPIO1 259 +#define DCLK_PERI_GPIO2 260 +#define ACLK_PHP 261 +#define PCLK_PHP 262 +#define ACLK_PCIE20_MST 263 +#define ACLK_PCIE20_SLV 264 +#define ACLK_PCIE20_DBI 265 +#define PCLK_PCIE20 266 +#define CLK_PCIE20_AUX 267 +#define ACLK_USB3OTG 268 +#define CLK_USB3OTG_SUSPEND 269 +#define CLK_USB3OTG_REF 270 +#define CLK_PIPEPHY_REF_FUNC 271 +#define CLK_200M_PMU 272 +#define CLK_RTC_32K 273 +#define CLK_RTC32K_FRAC 274 +#define BUSCLK_PDPMU0 275 +#define PCLK_PMU0_CRU 276 +#define PCLK_PMU0_PMU 277 +#define CLK_PMU0_PMU 278 +#define PCLK_PMU0_HP_TIMER 279 +#define CLK_PMU0_HP_TIMER 280 +#define CLK_PMU0_32K_HP_TIMER 281 +#define PCLK_PMU0_PVTM 282 +#define CLK_PMU0_PVTM 283 +#define PCLK_IOC_PMUIO 284 +#define PCLK_PMU0_GPIO0 285 +#define DBCLK_PMU0_GPIO0 286 +#define PCLK_PMU0_GRF 287 +#define PCLK_PMU0_SGRF 288 +#define CLK_DDR_FAIL_SAFE 289 +#define PCLK_PMU0_SCRKEYGEN 290 +#define PCLK_PMU1_CRU 291 +#define HCLK_PMU1_MEM 292 +#define PCLK_PMU0_I2C0 293 +#define CLK_PMU0_I2C0 294 +#define PCLK_PMU1_UART0 295 +#define CLK_PMU1_UART0_SRC 296 +#define CLK_PMU1_UART0_FRAC 297 +#define CLK_PMU1_UART0 298 +#define SCLK_PMU1_UART0 299 +#define PCLK_PMU1_SPI0 300 +#define CLK_PMU1_SPI0 301 +#define SCLK_IN_PMU1_SPI0 302 +#define PCLK_PMU1_PWM0 303 +#define CLK_PMU1_PWM0 304 +#define CLK_CAPTURE_PMU1_PWM0 305 +#define CLK_PMU1_WIFI 306 +#define FCLK_PMU1_CM0_CORE 307 +#define CLK_PMU1_CM0_RTC 308 +#define PCLK_PMU1_WDTNS 309 +#define CLK_PMU1_WDTNS 310 +#define PCLK_PMU1_MAILBOX 311 +#define CLK_PIPEPHY_DIV 312 +#define CLK_PIPEPHY_XIN24M 313 +#define CLK_PIPEPHY_REF 314 +#define CLK_24M_SSCSRC 315 +#define CLK_USB2PHY_XIN24M 316 +#define CLK_USB2PHY_REF 317 +#define CLK_MIPIDSIPHY_XIN24M 318 +#define CLK_MIPIDSIPHY_REF 319 +#define ACLK_RGA_PRE 320 +#define HCLK_RGA_PRE 321 +#define ACLK_RGA 322 +#define HCLK_RGA 323 +#define CLK_RGA_CORE 324 +#define ACLK_JDEC 325 +#define HCLK_JDEC 326 +#define ACLK_VDPU_PRE 327 +#define CLK_RKVDEC_HEVC_CA 328 +#define HCLK_VDPU_PRE 329 +#define ACLK_RKVDEC 330 +#define HCLK_RKVDEC 331 +#define CLK_RKVENC_CORE 332 +#define ACLK_VEPU_PRE 333 +#define HCLK_VEPU_PRE 334 +#define ACLK_RKVENC 335 +#define HCLK_RKVENC 336 +#define ACLK_VI 337 +#define HCLK_VI 338 +#define PCLK_VI 339 +#define ACLK_ISP 340 +#define HCLK_ISP 341 +#define CLK_ISP 342 +#define ACLK_VICAP 343 +#define HCLK_VICAP 344 +#define DCLK_VICAP 345 +#define CSIRX0_CLK_DATA 346 +#define CSIRX1_CLK_DATA 347 +#define CSIRX2_CLK_DATA 348 +#define CSIRX3_CLK_DATA 349 +#define PCLK_CSIHOST0 350 +#define PCLK_CSIHOST1 351 +#define PCLK_CSIHOST2 352 +#define PCLK_CSIHOST3 353 +#define PCLK_CSIPHY0 354 +#define PCLK_CSIPHY1 355 +#define ACLK_VO_PRE 356 +#define HCLK_VO_PRE 357 +#define ACLK_VOP 358 +#define HCLK_VOP 359 +#define DCLK_VOP 360 +#define DCLK_VOP1 361 + +#define CLK_NR_CLKS (DCLK_VOP1 + 1) + +/* soft-reset indices */ + +/********Name=SOFTRST_CON01,Offset=0x404********/ +#define SRST_A_TOP_BIU 16 +#define SRST_A_TOP_VIO_BIU 17 +#define SRST_REF_PVTPLL_LOGIC 18 +/********Name=SOFTRST_CON03,Offset=0x40C********/ +#define SRST_NCOREPORESET0 48 +#define SRST_NCOREPORESET1 49 +#define SRST_NCOREPORESET2 50 +#define SRST_NCOREPORESET3 51 +#define SRST_NCORESET0 52 +#define SRST_NCORESET1 53 +#define SRST_NCORESET2 54 +#define SRST_NCORESET3 55 +#define SRST_NL2RESET 56 +/********Name=SOFTRST_CON04,Offset=0x410********/ +#define SRST_DAP 73 +#define SRST_P_DBG_DAPLITE 74 +#define SRST_REF_PVTPLL_CORE 77 +/********Name=SOFTRST_CON05,Offset=0x414********/ +#define SRST_A_CORE_BIU 80 +#define SRST_P_CORE_BIU 81 +#define SRST_H_CORE_BIU 82 +/********Name=SOFTRST_CON06,Offset=0x418********/ +#define SRST_A_NPU_BIU 98 +#define SRST_H_NPU_BIU 99 +#define SRST_A_RKNN 100 +#define SRST_H_RKNN 101 +#define SRST_REF_PVTPLL_NPU 102 +/********Name=SOFTRST_CON08,Offset=0x420********/ +#define SRST_A_GPU_BIU 131 +#define SRST_GPU 132 +#define SRST_REF_PVTPLL_GPU 133 +#define SRST_GPU_BRG_BIU 134 +/********Name=SOFTRST_CON09,Offset=0x424********/ +#define SRST_RKVENC_CORE 144 +#define SRST_A_VEPU_BIU 147 +#define SRST_H_VEPU_BIU 148 +#define SRST_A_RKVENC 149 +#define SRST_H_RKVENC 150 +/********Name=SOFTRST_CON10,Offset=0x428********/ +#define SRST_RKVDEC_HEVC_CA 162 +#define SRST_A_VDPU_BIU 165 +#define SRST_H_VDPU_BIU 166 +#define SRST_A_RKVDEC 167 +#define SRST_H_RKVDEC 168 +/********Name=SOFTRST_CON11,Offset=0x42C********/ +#define SRST_A_VI_BIU 179 +#define SRST_H_VI_BIU 180 +#define SRST_P_VI_BIU 181 +#define SRST_ISP 184 +#define SRST_A_VICAP 185 +#define SRST_H_VICAP 186 +#define SRST_D_VICAP 187 +#define SRST_I0_VICAP 188 +#define SRST_I1_VICAP 189 +#define SRST_I2_VICAP 190 +#define SRST_I3_VICAP 191 +/********Name=SOFTRST_CON12,Offset=0x430********/ +#define SRST_P_CSIHOST0 192 +#define SRST_P_CSIHOST1 193 +#define SRST_P_CSIHOST2 194 +#define SRST_P_CSIHOST3 195 +#define SRST_P_CSIPHY0 196 +#define SRST_P_CSIPHY1 197 +/********Name=SOFTRST_CON13,Offset=0x434********/ +#define SRST_A_VO_BIU 211 +#define SRST_H_VO_BIU 212 +#define SRST_A_VOP 214 +#define SRST_H_VOP 215 +#define SRST_D_VOP 216 +#define SRST_D_VOP1 217 +/********Name=SOFTRST_CON14,Offset=0x438********/ +#define SRST_A_RGA_BIU 227 +#define SRST_H_RGA_BIU 228 +#define SRST_A_RGA 230 +#define SRST_H_RGA 231 +#define SRST_RGA_CORE 232 +#define SRST_A_JDEC 233 +#define SRST_H_JDEC 234 +/********Name=SOFTRST_CON15,Offset=0x43C********/ +#define SRST_B_EBK_BIU 242 +#define SRST_P_EBK_BIU 243 +#define SRST_AHB2AXI_EBC 244 +#define SRST_H_EBC 245 +#define SRST_D_EBC 246 +#define SRST_H_EINK 247 +#define SRST_P_EINK 248 +/********Name=SOFTRST_CON16,Offset=0x440********/ +#define SRST_P_PHP_BIU 258 +#define SRST_A_PHP_BIU 259 +#define SRST_P_PCIE20 263 +#define SRST_PCIE20_POWERUP 264 +#define SRST_USB3OTG 266 +/********Name=SOFTRST_CON17,Offset=0x444********/ +#define SRST_PIPEPHY 275 +/********Name=SOFTRST_CON18,Offset=0x448********/ +#define SRST_A_BUS_BIU 291 +#define SRST_H_BUS_BIU 292 +#define SRST_P_BUS_BIU 293 +/********Name=SOFTRST_CON19,Offset=0x44C********/ +#define SRST_P_I2C1 304 +#define SRST_P_I2C2 305 +#define SRST_P_I2C3 306 +#define SRST_P_I2C4 307 +#define SRST_P_I2C5 308 +#define SRST_I2C1 310 +#define SRST_I2C2 311 +#define SRST_I2C3 312 +#define SRST_I2C4 313 +#define SRST_I2C5 314 +/********Name=SOFTRST_CON20,Offset=0x450********/ +#define SRST_BUS_GPIO3 325 +#define SRST_BUS_GPIO4 326 +/********Name=SOFTRST_CON21,Offset=0x454********/ +#define SRST_P_TIMER 336 +#define SRST_TIMER0 337 +#define SRST_TIMER1 338 +#define SRST_TIMER2 339 +#define SRST_TIMER3 340 +#define SRST_TIMER4 341 +#define SRST_TIMER5 342 +#define SRST_P_STIMER 343 +#define SRST_STIMER0 344 +#define SRST_STIMER1 345 +/********Name=SOFTRST_CON22,Offset=0x458********/ +#define SRST_P_WDTNS 352 +#define SRST_WDTNS 353 +#define SRST_P_GRF 354 +#define SRST_P_SGRF 355 +#define SRST_P_MAILBOX 356 +#define SRST_P_INTC 357 +#define SRST_A_BUS_GIC400 358 +#define SRST_A_BUS_GIC400_DEBUG 359 +/********Name=SOFTRST_CON23,Offset=0x45C********/ +#define SRST_A_BUS_SPINLOCK 368 +#define SRST_A_DCF 369 +#define SRST_P_DCF 370 +#define SRST_F_BUS_CM0_CORE 371 +#define SRST_T_BUS_CM0_JTAG 373 +#define SRST_H_ICACHE 376 +#define SRST_H_DCACHE 377 +/********Name=SOFTRST_CON24,Offset=0x460********/ +#define SRST_P_TSADC 384 +#define SRST_TSADC 385 +#define SRST_TSADCPHY 386 +#define SRST_P_DFT2APB 388 +/********Name=SOFTRST_CON25,Offset=0x464********/ +#define SRST_A_GMAC 401 +#define SRST_P_APB2ASB_VCCIO156 405 +#define SRST_P_DSIPHY 408 +#define SRST_P_DSITX 409 +#define SRST_P_CPU_EMA_DET 410 +#define SRST_P_HASH 411 +#define SRST_P_TOPCRU 415 +/********Name=SOFTRST_CON26,Offset=0x468********/ +#define SRST_P_ASB2APB_VCCIO156 416 +#define SRST_P_IOC_VCCIO156 417 +#define SRST_P_GPIO3_VCCIO156 418 +#define SRST_P_GPIO4_VCCIO156 419 +#define SRST_P_SARADC_VCCIO156 420 +#define SRST_SARADC_VCCIO156 421 +#define SRST_SARADC_VCCIO156_PHY 422 +/********Name=SOFTRST_CON27,Offset=0x46c********/ +#define SRST_A_MAC100 433 + +/* (0x10200 - 0x400) / 4 * 16 = 260096 */ +/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/ +#define SRST_P_PMU0_CRU 260096 +#define SRST_P_PMU0_PMU 260097 +#define SRST_PMU0_PMU 260098 +#define SRST_P_PMU0_HP_TIMER 260099 +#define SRST_PMU0_HP_TIMER 260100 +#define SRST_PMU0_32K_HP_TIMER 260101 +#define SRST_P_PMU0_PVTM 260102 +#define SRST_PMU0_PVTM 260103 +#define SRST_P_IOC_PMUIO 260104 +#define SRST_P_PMU0_GPIO0 260105 +#define SRST_PMU0_GPIO0 260106 +#define SRST_P_PMU0_GRF 260107 +#define SRST_P_PMU0_SGRF 260108 +/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/ +#define SRST_DDR_FAIL_SAFE 260112 +#define SRST_P_PMU0_SCRKEYGEN 260113 +/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/ +#define SRST_P_PMU0_I2C0 260136 +#define SRST_PMU0_I2C0 260137 + +/* (0x18200 - 0x400) / 4 * 16 = 391168 */ +/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/ +#define SRST_P_PMU1_CRU 391168 +#define SRST_H_PMU1_MEM 391170 +#define SRST_H_PMU1_BIU 391171 +#define SRST_P_PMU1_BIU 391172 +#define SRST_P_PMU1_UART0 391175 +#define SRST_S_PMU1_UART0 391178 +/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/ +#define SRST_P_PMU1_SPI0 391184 +#define SRST_PMU1_SPI0 391185 +#define SRST_P_PMU1_PWM0 391187 +#define SRST_PMU1_PWM0 391188 +/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/ +#define SRST_F_PMU1_CM0_CORE 391200 +#define SRST_T_PMU1_CM0_JTAG 391202 +#define SRST_P_PMU1_WDTNS 391203 +#define SRST_PMU1_WDTNS 391204 +#define SRST_PMU1_MAILBOX 391208 + +/* (0x20200 - 0x400) / 4 * 16 = 522240 */ +/********Name=DDRSOFTRST_CON00,Offset=0x20200********/ +#define SRST_MSCH_BRG_BIU 522244 +#define SRST_P_MSCH_BIU 522245 +#define SRST_P_DDR_HWLP 522246 +#define SRST_P_DDR_PHY 522248 +#define SRST_P_DDR_DFICTL 522249 +#define SRST_P_DDR_DMA2DDR 522250 +/********Name=DDRSOFTRST_CON01,Offset=0x20204********/ +#define SRST_P_DDR_MON 522256 +#define SRST_TM_DDR_MON 522257 +#define SRST_P_DDR_GRF 522258 +#define SRST_P_DDR_CRU 522259 +#define SRST_P_SUBDDR_CRU 522260 + +/* (0x28200 - 0x400) / 4 * 16 = 653312 */ +/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/ +#define SRST_MSCH_BIU 653313 +#define SRST_DDR_PHY 653316 +#define SRST_DDR_DFICTL 653317 +#define SRST_DDR_SCRAMBLE 653318 +#define SRST_DDR_MON 653319 +#define SRST_A_DDR_SPLIT 653320 +#define SRST_DDR_DMA2DDR 653321 + +/* (0x30400 - 0x400) / 4 * 16 = 786432 */ +/********Name=PERISOFTRST_CON01,Offset=0x30404********/ +#define SRST_A_PERI_BIU 786451 +#define SRST_H_PERI_BIU 786452 +#define SRST_P_PERI_BIU 786453 +#define SRST_P_PERICRU 786454 +/********Name=PERISOFTRST_CON02,Offset=0x30408********/ +#define SRST_H_SAI0_8CH 786464 +#define SRST_M_SAI0_8CH 786467 +#define SRST_H_SAI1_8CH 786469 +#define SRST_M_SAI1_8CH 786472 +#define SRST_H_SAI2_2CH 786474 +#define SRST_M_SAI2_2CH 786477 +/********Name=PERISOFTRST_CON03,Offset=0x3040C********/ +#define SRST_H_DSM 786481 +#define SRST_DSM 786482 +#define SRST_H_PDM 786484 +#define SRST_M_PDM 786485 +#define SRST_H_SPDIF 786488 +#define SRST_M_SPDIF 786491 +/********Name=PERISOFTRST_CON04,Offset=0x30410********/ +#define SRST_H_SDMMC0 786496 +#define SRST_H_SDMMC1 786498 +#define SRST_H_EMMC 786504 +#define SRST_A_EMMC 786505 +#define SRST_C_EMMC 786506 +#define SRST_B_EMMC 786507 +#define SRST_T_EMMC 786508 +#define SRST_S_SFC 786509 +#define SRST_H_SFC 786510 +/********Name=PERISOFTRST_CON05,Offset=0x30414********/ +#define SRST_H_USB2HOST 786512 +#define SRST_H_USB2HOST_ARB 786513 +#define SRST_USB2HOST_UTMI 786514 +/********Name=PERISOFTRST_CON06,Offset=0x30418********/ +#define SRST_P_SPI1 786528 +#define SRST_SPI1 786529 +#define SRST_P_SPI2 786531 +#define SRST_SPI2 786532 +/********Name=PERISOFTRST_CON07,Offset=0x3041C********/ +#define SRST_P_UART1 786544 +#define SRST_P_UART2 786545 +#define SRST_P_UART3 786546 +#define SRST_P_UART4 786547 +#define SRST_P_UART5 786548 +#define SRST_P_UART6 786549 +#define SRST_P_UART7 786550 +#define SRST_P_UART8 786551 +#define SRST_P_UART9 786552 +#define SRST_S_UART1 786555 +#define SRST_S_UART2 786558 +/********Name=PERISOFTRST_CON08,Offset=0x30420********/ +#define SRST_S_UART3 786561 +#define SRST_S_UART4 786564 +#define SRST_S_UART5 786567 +#define SRST_S_UART6 786570 +#define SRST_S_UART7 786573 +/********Name=PERISOFTRST_CON09,Offset=0x30424********/ +#define SRST_S_UART8 786576 +#define SRST_S_UART9 786579 +/********Name=PERISOFTRST_CON10,Offset=0x30428********/ +#define SRST_P_PWM1_PERI 786592 +#define SRST_PWM1_PERI 786593 +#define SRST_P_PWM2_PERI 786595 +#define SRST_PWM2_PERI 786596 +#define SRST_P_PWM3_PERI 786598 +#define SRST_PWM3_PERI 786599 +/********Name=PERISOFTRST_CON11,Offset=0x3042C********/ +#define SRST_P_CAN0 786608 +#define SRST_CAN0 786609 +#define SRST_P_CAN1 786610 +#define SRST_CAN1 786611 +/********Name=PERISOFTRST_CON12,Offset=0x30430********/ +#define SRST_A_CRYPTO 786624 +#define SRST_H_CRYPTO 786625 +#define SRST_P_CRYPTO 786626 +#define SRST_CORE_CRYPTO 786627 +#define SRST_PKA_CRYPTO 786628 +#define SRST_H_KLAD 786629 +#define SRST_P_KEY_READER 786630 +#define SRST_H_RK_RNG_NS 786631 +#define SRST_H_RK_RNG_S 786632 +#define SRST_H_TRNG_NS 786633 +#define SRST_H_TRNG_S 786634 +#define SRST_H_CRYPTO_S 786635 +/********Name=PERISOFTRST_CON13,Offset=0x30434********/ +#define SRST_P_PERI_WDT 786640 +#define SRST_T_PERI_WDT 786641 +#define SRST_A_SYSMEM 786642 +#define SRST_H_BOOTROM 786643 +#define SRST_P_PERI_GRF 786644 +#define SRST_A_DMAC 786645 +#define SRST_A_RKDMAC 786646 +/********Name=PERISOFTRST_CON14,Offset=0x30438********/ +#define SRST_P_OTPC_NS 786656 +#define SRST_SBPI_OTPC_NS 786657 +#define SRST_USER_OTPC_NS 786658 +#define SRST_P_OTPC_S 786659 +#define SRST_SBPI_OTPC_S 786660 +#define SRST_USER_OTPC_S 786661 +#define SRST_OTPC_ARB 786662 +#define SRST_P_OTPPHY 786663 +#define SRST_OTP_NPOR 786664 +/********Name=PERISOFTRST_CON15,Offset=0x3043C********/ +#define SRST_P_USB2PHY 786672 +#define SRST_USB2PHY_POR 786676 +#define SRST_USB2PHY_OTG 786677 +#define SRST_USB2PHY_HOST 786678 +#define SRST_P_PIPEPHY 786679 +/********Name=PERISOFTRST_CON16,Offset=0x30440********/ +#define SRST_P_SARADC 786692 +#define SRST_SARADC 786693 +#define SRST_SARADC_PHY 786694 +#define SRST_P_IOC_VCCIO234 786700 +/********Name=PERISOFTRST_CON17,Offset=0x30444********/ +#define SRST_P_PERI_GPIO1 786704 +#define SRST_P_PERI_GPIO2 786705 +#define SRST_PERI_GPIO1 786706 +#define SRST_PERI_GPIO2 786707 + +#endif From a621b1189cf1a41c9b85ce94a6eca978968c2cd6 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 29 Jun 2022 20:31:42 +0800 Subject: [PATCH 009/258] clk: rockchip: Add clock controller for the RK3562 Add the clock tree definition for the new RK3562 SoC. Signed-off-by: Finley Xiao Signed-off-by: Tao Huang Signed-off-by: Sugar Zhang Change-Id: Ia96ad61555537333a8ac54158360e1d23d971135 --- drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3562.c | 1229 +++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 39 + 4 files changed, 1276 insertions(+) create mode 100644 drivers/clk/rockchip/clk-rk3562.c diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index ec996617047e..191515a53c13 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -114,6 +114,13 @@ config CLK_RK3528 help Build the driver for RK3528 Clock Driver. +config CLK_RK3562 + tristate "Rockchip RK3562 clock controller support" + depends on CPU_RK3562 || COMPILE_TEST + default y + help + Build the driver for RK3562 Clock Driver. + config CLK_RK3568 tristate "Rockchip RK3568 clock controller support" depends on CPU_RK3568 || COMPILE_TEST diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index dfccfeded89a..65e7dc9c5bb1 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -34,5 +34,6 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o +obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c new file mode 100644 index 000000000000..b1080fb1f652 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3562.c @@ -0,0 +1,1229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + * Author: Finley Xiao + */ + +#include +#include +#include +#include +#include +#include +#include +#include "clk.h" + +#define RK3562_GRF_SOC_STATUS0 0x430 + +enum rk3562_plls { + apll, gpll, vpll, hpll, cpll, dpll, +}; + +static struct rockchip_pll_rate_table rk3562_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), + RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), + RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), + RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), + RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), + RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), + RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), + RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), + RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), + RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), + RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), + RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), + RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), + { /* sentinel */ }, +}; + +#define RK3562_DIV_PCLK_CORE_MASK 0xf +#define RK3562_DIV_PCLK_CORE_SHIFT 0 +#define RK3562_DIV_ACLK_CORE_MASK 0x7 +#define RK3562_DIV_ACLK_CORE_SHIFT 0 + +#define RK3562_CLKSEL1(_aclk_core) \ +{ \ + .reg = RK3562_CLKSEL_CON(11), \ + .val = HIWORD_UPDATE(_aclk_core, RK3562_DIV_ACLK_CORE_MASK, \ + RK3562_DIV_ACLK_CORE_SHIFT), \ +} + +#define RK3562_CLKSEL2(_pclk) \ +{ \ + .reg = RK3562_CLKSEL_CON(12), \ + .val = HIWORD_UPDATE(_pclk, RK3562_DIV_PCLK_CORE_MASK, \ + RK3562_DIV_PCLK_CORE_SHIFT), \ +} + +#define RK3562_CPUCLK_RATE(_prate, _acore, _pclk) \ +{ \ + .prate = _prate##U, \ + .divs = { \ + RK3562_CLKSEL1(_acore), \ + RK3562_CLKSEL2(_pclk), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3562_cpuclk_rates[] __initdata = { + RK3562_CPUCLK_RATE(2016000000, 1, 9), + RK3562_CPUCLK_RATE(1896000000, 1, 9), + RK3562_CPUCLK_RATE(1800000000, 1, 9), + RK3562_CPUCLK_RATE(1704000000, 1, 9), + RK3562_CPUCLK_RATE(1608000000, 1, 9), + RK3562_CPUCLK_RATE(1584000000, 1, 9), + RK3562_CPUCLK_RATE(1560000000, 1, 9), + RK3562_CPUCLK_RATE(1536000000, 1, 9), + RK3562_CPUCLK_RATE(1512000000, 1, 9), + RK3562_CPUCLK_RATE(1488000000, 1, 7), + RK3562_CPUCLK_RATE(1464000000, 1, 7), + RK3562_CPUCLK_RATE(1440000000, 1, 7), + RK3562_CPUCLK_RATE(1416000000, 1, 7), + RK3562_CPUCLK_RATE(1392000000, 1, 7), + RK3562_CPUCLK_RATE(1368000000, 1, 7), + RK3562_CPUCLK_RATE(1344000000, 1, 7), + RK3562_CPUCLK_RATE(1320000000, 1, 7), + RK3562_CPUCLK_RATE(1296000000, 1, 7), + RK3562_CPUCLK_RATE(1272000000, 1, 7), + RK3562_CPUCLK_RATE(1248000000, 1, 7), + RK3562_CPUCLK_RATE(1224000000, 1, 7), + RK3562_CPUCLK_RATE(1200000000, 1, 7), + RK3562_CPUCLK_RATE(1104000000, 1, 7), + RK3562_CPUCLK_RATE(1008000000, 1, 7), + RK3562_CPUCLK_RATE(912000000, 1, 5), + RK3562_CPUCLK_RATE(816000000, 1, 5), + RK3562_CPUCLK_RATE(696000000, 1, 5), + RK3562_CPUCLK_RATE(600000000, 1, 5), + RK3562_CPUCLK_RATE(408000000, 1, 3), + RK3562_CPUCLK_RATE(312000000, 1, 3), + RK3562_CPUCLK_RATE(216000000, 1, 3), + RK3562_CPUCLK_RATE(96000000, 1, 1), +}; + +static const struct rockchip_cpuclk_reg_data rk3562_cpuclk_data = { + .core_reg[0] = RK3562_CLKSEL_CON(10), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, + .mux_core_shift = 7, + .mux_core_mask = 0x1, +}; + +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" }; +PNAME(gpll_cpll_pvtpll_apll_p) = { "gpll", "cpll", "log_pvtpll", "apll" }; +PNAME(gpll_cpll_hpll_xin24m_p) = { "gpll", "cpll", "hpll", "xin24m" }; +PNAME(gpll_cpll_vpll_hpll_p) = { "gpll", "cpll", "vpll", "hpll" }; +PNAME(gpll_hpll_vpll_apll_p) = { "gpll", "hpll", "vpll", "apll" }; +PNAME(gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; +PNAME(gpll_cpll_xin24m_apll_p) = { "gpll", "cpll", "xin24m", "apll" }; +PNAME(gpll_cpll_xin24m_hpll_p) = { "gpll", "cpll", "xin24m", "hpll" }; +PNAME(vpll_hpll_gpll_cpll_p) = { "vpll", "hpll", "gpll", "cpll" }; +PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PNAME(mux_50m_xin24m_p) = { "clk_matrix_50m_src", "xin24m" }; +PNAME(mux_100m_50m_xin24m_p) = { "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; +PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" }; +PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" }; +PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" }; +PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; +PNAME(mux_200m_100m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "xin24m" }; +PNAME(mux_300m_200m_100m_xin24m_p) = { "clk_matrix_300m_src", "clk_matrix_200m_src", "clk_matrix_100m_src", "xin24m" }; +PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_io" }; +PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" }; +PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_io" }; +PNAME(mclk_sai1_out2io_p) = { "mclk_sai1", "xin_osc0_half" }; +PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_io" }; +PNAME(mclk_sai2_out2io_p) = { "mclk_sai2", "xin_osc0_half" }; +PNAME(clk_spdif_p) = { "clk_spdif_src", "clk_spdif_frac", "xin_osc0_half" }; +PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_32k_pvtm" }; +PNAME(clk_pmu1_uart0_p) = { "clk_pmu1_uart0_src", "clk_pmu1_uart0_frac", "xin24m" }; +PNAME(clk_pipephy_ref_p) = { "clk_pipephy_div", "clk_pipephy_xin24m" }; +PNAME(clk_usbphy_ref_p) = { "clk_usb2phy_xin24m", "clk_24m_sscsrc" }; +PNAME(clk_mipidsi_ref_p) = { "clk_mipidsiphy_xin24m", "clk_24m_sscsrc" }; + +static struct rockchip_pll_clock rk3562_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, + 0, RK3562_PLL_CON(0), + RK3562_MODE_CON, 0, 0, 0, rk3562_pll_rates), + [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + 0, RK3562_PLL_CON(24), + RK3562_MODE_CON, 2, 3, 0, rk3562_pll_rates), + [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, + 0, RK3562_PLL_CON(32), + RK3562_MODE_CON, 6, 4, 0, rk3562_pll_rates), + [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, + 0, RK3562_PLL_CON(40), + RK3562_MODE_CON, 8, 5, 0, rk3562_pll_rates), + [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, + 0, RK3562_PMU1_PLL_CON(0), + RK3562_PMU1_MODE_CON, 0, 2, 0, rk3562_pll_rates), + [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, + 0, RK3562_SUBDDR_PLL_CON(0), + RK3562_SUBDDR_MODE_CON, 0, 1, 0, NULL), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3562_clk_sai0_fracmux __initdata = + MUX(CLK_SAI0, "clk_sai0", clk_sai0_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(3), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_sai1_fracmux __initdata = + MUX(CLK_SAI1, "clk_sai1", clk_sai1_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(5), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_sai2_fracmux __initdata = + MUX(CLK_SAI2, "clk_sai2", clk_sai2_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(8), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_spdif_fracmux __initdata = + MUX(CLK_SPDIF, "clk_spdif", clk_spdif_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(15), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart1_fracmux __initdata = + MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(21), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart2_fracmux __initdata = + MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(23), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart3_fracmux __initdata = + MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(25), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart4_fracmux __initdata = + MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(27), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart5_fracmux __initdata = + MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(29), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart6_fracmux __initdata = + MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(31), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart7_fracmux __initdata = + MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(33), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart8_fracmux __initdata = + MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(35), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart9_fracmux __initdata = + MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(37), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_rtc32k_pmu_fracmux __initdata = + MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3562_PMU0_CLKSEL_CON(1), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_pmu1_uart0_fracmux __initdata = + MUX(CLK_PMU1_UART0, "clk_pmu1_uart0", clk_pmu1_uart0_p, CLK_SET_RATE_PARENT, + RK3562_PMU1_CLKSEL_CON(2), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + /* PD_TOP */ + COMPOSITE(CLK_MATRIX_50M_SRC, "clk_matrix_50m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE(CLK_MATRIX_100M_SRC, "clk_matrix_100m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE(CLK_MATRIX_125M_SRC, "clk_matrix_125m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(CLK_MATRIX_200M_SRC, "clk_matrix_200m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE(CLK_MATRIX_300M_SRC, "clk_matrix_300m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(ACLK_TOP_VIO, "aclk_top_vio", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(CLK_24M_SSCSRC, "clk_24m_sscsrc", vpll_hpll_gpll_cpll_p, 0, + RK3562_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE(CLK_CAM0_OUT2IO, "clk_cam0_out2io", gpll_cpll_xin24m_apll_p, 0, + RK3562_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE(CLK_CAM1_OUT2IO, "clk_cam1_out2io", gpll_cpll_xin24m_apll_p, 0, + RK3562_CLKSEL_CON(8), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE(CLK_CAM2_OUT2IO, "clk_cam2_out2io", gpll_cpll_xin24m_apll_p, 0, + RK3562_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE(CLK_CAM3_OUT2IO, "clk_cam3_out2io", gpll_cpll_xin24m_apll_p, 0, + RK3562_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 15, GFLAGS), + FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), + + /* PD_BUS */ + COMPOSITE(ACLK_BUS, "aclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(40), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(18), 0, GFLAGS), + COMPOSITE(HCLK_BUS, "hclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(40), 15, 1, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(18), 1, GFLAGS), + COMPOSITE(PCLK_BUS, "pclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(18), 2, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 0, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 1, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 2, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 3, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 4, GFLAGS), + COMPOSITE_NODIV(CLK_I2C, "clk_i2c", mux_200m_100m_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(41), 8, 2, MFLAGS, + RK3562_CLKGATE_CON(19), 5, GFLAGS), + GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 6, GFLAGS), + GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 7, GFLAGS), + GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 8, GFLAGS), + GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 9, GFLAGS), + GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 10, GFLAGS), + COMPOSITE_NODIV(DCLK_BUS_GPIO, "dclk_bus_gpio", mux_xin24m_32k_p, 0, + RK3562_CLKSEL_CON(41), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(20), 4, GFLAGS), + GATE(DCLK_BUS_GPIO3, "dclk_bus_gpio3", "dclk_bus_gpio", 0, + RK3562_CLKGATE_CON(20), 5, GFLAGS), + GATE(DCLK_BUS_GPIO4, "dclk_bus_gpio4", "dclk_bus_gpio", 0, + RK3562_CLKGATE_CON(20), 6, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, + RK3562_CLKGATE_CON(21), 0, GFLAGS), + GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, + RK3562_CLKGATE_CON(21), 1, GFLAGS), + GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, + RK3562_CLKGATE_CON(21), 2, GFLAGS), + GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, + RK3562_CLKGATE_CON(21), 3, GFLAGS), + GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, + RK3562_CLKGATE_CON(21), 4, GFLAGS), + GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, + RK3562_CLKGATE_CON(21), 5, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, + RK3562_CLKGATE_CON(21), 6, GFLAGS), + GATE(PCLK_STIMER, "pclk_stimer", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 7, GFLAGS), + GATE(CLK_STIMER0, "clk_stimer0", "xin24m", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 8, GFLAGS), + GATE(CLK_STIMER1, "clk_stimer1", "xin24m", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 9, GFLAGS), + GATE(PCLK_WDTNS, "pclk_wdtns", "pclk_bus", 0, + RK3562_CLKGATE_CON(22), 0, GFLAGS), + GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0, + RK3562_CLKGATE_CON(22), 1, GFLAGS), + GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 2, GFLAGS), + GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 3, GFLAGS), + GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, + RK3562_CLKGATE_CON(22), 4, GFLAGS), + GATE(PCLK_INTC, "pclk_intc", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 5, GFLAGS), + GATE(ACLK_BUS_GIC400, "aclk_bus_gic400", "aclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 6, GFLAGS), + GATE(ACLK_BUS_SPINLOCK, "aclk_bus_spinlock", "aclk_bus", 0, + RK3562_CLKGATE_CON(23), 0, GFLAGS), + GATE(ACLK_DCF, "aclk_dcf", "aclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 1, GFLAGS), + GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 2, GFLAGS), + GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus", 0, + RK3562_CLKGATE_CON(23), 3, GFLAGS), + GATE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", "clk_rtc_32k", 0, + RK3562_CLKGATE_CON(23), 4, GFLAGS), + GATE(HCLK_ICACHE, "hclk_icache", "hclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 8, GFLAGS), + GATE(HCLK_DCACHE, "hclk_dcache", "hclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 9, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, + RK3562_CLKGATE_CON(24), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, + RK3562_CLKSEL_CON(43), 0, 11, DFLAGS, + RK3562_CLKGATE_CON(24), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, + RK3562_CLKSEL_CON(43), 11, 5, DFLAGS, + RK3562_CLKGATE_CON(24), 3, GFLAGS), + GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(24), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_SARADC_VCCIO156, "clk_saradc_vccio156", "xin24m", 0, + RK3562_CLKSEL_CON(44), 0, 12, DFLAGS, + RK3562_CLKGATE_CON(24), 9, GFLAGS), + GATE(PCLK_GMAC, "pclk_gmac", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 0, GFLAGS), + GATE(ACLK_GMAC, "aclk_gmac", "aclk_bus", 0, + RK3562_CLKGATE_CON(25), 1, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC_125M_CRU_I, "clk_gmac_125m_cru_i", mux_125m_xin24m_p, 0, + RK3562_CLKSEL_CON(45), 8, 1, MFLAGS, + RK3562_CLKGATE_CON(25), 2, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC_50M_CRU_I, "clk_gmac_50m_cru_i", mux_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(45), 7, 1, MFLAGS, + RK3562_CLKGATE_CON(25), 3, GFLAGS), + COMPOSITE(CLK_GMAC_ETH_OUT2IO, "clk_gmac_eth_out2io", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_CLKGATE_CON(25), 4, GFLAGS), + GATE(PCLK_APB2ASB_VCCIO156, "pclk_apb2asb_vccio156", "pclk_bus", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(25), 5, GFLAGS), + GATE(PCLK_TO_VCCIO156, "pclk_to_vccio156", "pclk_bus", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(25), 6, GFLAGS), + GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 8, GFLAGS), + GATE(PCLK_DSITX, "pclk_dsitx", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 9, GFLAGS), + GATE(PCLK_CPU_EMA_DET, "pclk_cpu_ema_det", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(25), 10, GFLAGS), + GATE(PCLK_HASH, "pclk_hash", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 11, GFLAGS), + GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(25), 15, GFLAGS), + GATE(PCLK_ASB2APB_VCCIO156, "pclk_asb2apb_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(26), 0, GFLAGS), + GATE(PCLK_IOC_VCCIO156, "pclk_ioc_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(26), 1, GFLAGS), + GATE(PCLK_GPIO3_VCCIO156, "pclk_gpio3_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 2, GFLAGS), + GATE(PCLK_GPIO4_VCCIO156, "pclk_gpio4_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 3, GFLAGS), + GATE(PCLK_SARADC_VCCIO156, "pclk_saradc_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 4, GFLAGS), + GATE(PCLK_MAC100, "pclk_mac100", "pclk_bus", 0, + RK3562_CLKGATE_CON(27), 0, GFLAGS), + GATE(ACLK_MAC100, "aclk_mac100", "aclk_bus", 0, + RK3562_CLKGATE_CON(27), 1, GFLAGS), + COMPOSITE_NODIV(CLK_MAC100_50M_MATRIX, "clk_mac100_50m_matrix", mux_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(47), 7, 1, MFLAGS, + RK3562_CLKGATE_CON(27), 2, GFLAGS), + + /* PD_CORE */ + COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(11), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3562_CLKGATE_CON(4), 3, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(12), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3562_CLKGATE_CON(4), 5, GFLAGS), + COMPOSITE_NOMUX(HCLK_CORE, "hclk_core", "gpll", CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(13), 0, 6, DFLAGS, + RK3562_CLKGATE_CON(5), 2, GFLAGS), + GATE(0, "pclk_dbg_daplite", "pclk_dbg_pre", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(4), 10, GFLAGS), + + /* PD_DDR */ + FACTOR_GATE(0, "clk_gpll_mux_to_ddr", "gpll", 0, 1, 4, + RK3328_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL, + RK3562_DDR_CLKSEL_CON(1), 8, 5, DFLAGS, + RK3562_DDR_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_MSCH_BRG_BIU, "clk_msch_brg_biu", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL, + RK3562_DDR_CLKSEL_CON(1), 0, 4, DFLAGS, + RK3562_DDR_CLKGATE_CON(0), 4, GFLAGS), + GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 6, GFLAGS), + GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_DDR_PHY, "pclk_ddr_phy", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_DDR_DFICTL, "pclk_ddr_dfictl", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 9, GFLAGS), + GATE(PCLK_DDR_DMA2DDR, "pclk_ddr_dma2ddr", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 0, GFLAGS), + GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 1, GFLAGS), + GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_DDR_CRU, "pclk_ddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 3, GFLAGS), + GATE(PCLK_SUBDDR_CRU, "pclk_subddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 4, GFLAGS), + + /* PD_GPU */ + COMPOSITE(CLK_GPU_PRE, "clk_gpu_pre", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(18), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE_NOMUX(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre", 0, + RK3562_CLKSEL_CON(19), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(8), 2, GFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre", 0, + RK3562_CLKGATE_CON(8), 4, GFLAGS), + COMPOSITE_NODIV(CLK_GPU_BRG, "clk_gpu_brg", mux_200m_100m_p, 0, + RK3562_CLKSEL_CON(19), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(8), 8, GFLAGS), + + /* PD_NPU */ + COMPOSITE(CLK_NPU_PRE, "clk_npu_pre", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu_pre", 0, + RK3562_CLKSEL_CON(16), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(6), 1, GFLAGS), + GATE(ACLK_RKNN, "aclk_rknn", "clk_npu_pre", 0, + RK3562_CLKGATE_CON(6), 4, GFLAGS), + GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_pre", 0, + RK3562_CLKGATE_CON(6), 5, GFLAGS), + + /* PD_PERI */ + COMPOSITE(ACLK_PERI, "aclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(HCLK_PERI, "hclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(PCLK_PERI, "pclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PERICRU, "pclk_pericru", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(1), 6, GFLAGS), + GATE(HCLK_SAI0, "hclk_sai0", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 0, GFLAGS), + COMPOSITE(CLK_SAI0_SRC, "clk_sai0_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI0_FRAC, "clk_sai0_frac", "clk_sai0_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(2), 0, + RK3562_PERI_CLKGATE_CON(2), 2, GFLAGS, + &rk3562_clk_sai0_fracmux), + GATE(MCLK_SAI0, "mclk_sai0", "clk_sai0", 0, + RK3562_PERI_CLKGATE_CON(2), 3, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", mclk_sai0_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(3), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 4, GFLAGS), + GATE(HCLK_SAI1, "hclk_sai1", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 5, GFLAGS), + COMPOSITE(CLK_SAI1_SRC, "clk_sai1_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 6, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI1_FRAC, "clk_sai1_frac", "clk_sai1_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(4), 0, + RK3562_PERI_CLKGATE_CON(2), 7, GFLAGS, + &rk3562_clk_sai1_fracmux), + GATE(MCLK_SAI1, "mclk_sai1", "clk_sai1", 0, + RK3562_PERI_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", mclk_sai1_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(5), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 9, GFLAGS), + GATE(HCLK_SAI2, "hclk_sai2", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE(CLK_SAI2_SRC, "clk_sai2_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI2_FRAC, "clk_sai2_frac", "clk_sai2_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(7), 0, + RK3562_PERI_CLKGATE_CON(2), 12, GFLAGS, + &rk3562_clk_sai2_fracmux), + GATE(MCLK_SAI2, "mclk_sai2", "clk_sai2", 0, + RK3562_PERI_CLKGATE_CON(2), 13, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", mclk_sai2_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(8), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 14, GFLAGS), + GATE(HCLK_DSM, "hclk_dsm", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 1, GFLAGS), + GATE(CLK_DSM, "clk_dsm", "mclk_sai1", 0, + RK3562_PERI_CLKGATE_CON(3), 2, GFLAGS), + GATE(HCLK_PDM, "hclk_pdm", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 4, GFLAGS), + COMPOSITE(MCLK_PDM, "mclk_pdm", gpll_cpll_hpll_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(3), 5, GFLAGS), + GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 8, GFLAGS), + COMPOSITE(CLK_SPDIF_SRC, "clk_spdif_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(3), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(14), 0, + RK3562_PERI_CLKGATE_CON(3), 10, GFLAGS, + &rk3562_clk_spdif_fracmux), + GATE(MCLK_SPDIF, "mclk_spdif", "clk_spdif", 0, + RK3562_PERI_CLKGATE_CON(3), 11, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 0, GFLAGS), + COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", gpll_cpll_xin24m_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 1, GFLAGS), + MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "cclk_sdmmc0", RK3562_SDMMC0_CON0, 1), + MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "cclk_sdmmc0", RK3562_SDMMC0_CON1, 1), + GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 2, GFLAGS), + COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", gpll_cpll_xin24m_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(17), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 3, GFLAGS), + MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "cclk_sdmmc1", RK3562_SDMMC1_CON0, 1), + MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "cclk_sdmmc1", RK3562_SDMMC1_CON1, 1), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 8, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 9, GFLAGS), + COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_xin24m_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 10, GFLAGS), + COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 11, GFLAGS), + GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(4), 12, GFLAGS), + COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 13, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 14, GFLAGS), + GATE(HCLK_USB2HOST, "hclk_usb2host", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(5), 0, GFLAGS), + GATE(HCLK_USB2HOST_ARB, "hclk_usb2host_arb", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(5), 1, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 12, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(6), 1, GFLAGS), + GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0, + RK3562_PERI_CLKGATE_CON(6), 2, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(6), 3, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 14, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(6), 4, GFLAGS), + GATE(SCLK_IN_SPI2, "sclk_in_spi2", "sclk_in_spi2_io", 0, + RK3562_PERI_CLKGATE_CON(6), 5, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 0, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 1, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 2, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 3, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 4, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 5, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 6, GFLAGS), + GATE(PCLK_UART8, "pclk_uart8", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 7, GFLAGS), + GATE(PCLK_UART9, "pclk_uart9", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(21), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(22), 0, + RK3562_PERI_CLKGATE_CON(7), 10, GFLAGS, + &rk3562_clk_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3562_PERI_CLKGATE_CON(7), 11, GFLAGS), + COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(23), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(24), 0, + RK3562_PERI_CLKGATE_CON(7), 13, GFLAGS, + &rk3562_clk_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3562_PERI_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(26), 0, + RK3562_PERI_CLKGATE_CON(8), 0, GFLAGS, + &rk3562_clk_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3562_PERI_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(27), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 2, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(28), 0, + RK3562_PERI_CLKGATE_CON(8), 3, GFLAGS, + &rk3562_clk_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3562_PERI_CLKGATE_CON(8), 4, GFLAGS), + COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(30), 0, + RK3562_PERI_CLKGATE_CON(8), 6, GFLAGS, + &rk3562_clk_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3562_PERI_CLKGATE_CON(8), 7, GFLAGS), + COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(31), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(32), 0, + RK3562_PERI_CLKGATE_CON(8), 9, GFLAGS, + &rk3562_clk_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3562_PERI_CLKGATE_CON(8), 10, GFLAGS), + COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(34), 0, + RK3562_PERI_CLKGATE_CON(8), 12, GFLAGS, + &rk3562_clk_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3562_PERI_CLKGATE_CON(8), 13, GFLAGS), + COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(35), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(36), 0, + RK3562_PERI_CLKGATE_CON(8), 15, GFLAGS, + &rk3562_clk_uart8_fracmux), + GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, + RK3562_PERI_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(37), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(9), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(38), 0, + RK3562_PERI_CLKGATE_CON(9), 2, GFLAGS, + &rk3562_clk_uart9_fracmux), + GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, + RK3562_PERI_CLKGATE_CON(9), 3, GFLAGS), + GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 0, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 0, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 1, GFLAGS), + GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 2, GFLAGS), + GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 3, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 6, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 4, GFLAGS), + GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 5, GFLAGS), + GATE(PCLK_PWM3_PERI, "pclk_pwm3_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 6, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3_PERI, "clk_pwm3_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 8, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 7, GFLAGS), + GATE(CLK_CAPTURE_PWM3_PERI, "clk_capture_pwm3_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 8, GFLAGS), + GATE(PCLK_CAN0, "pclk_can0", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(11), 1, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(11), 2, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(41), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(11), 3, GFLAGS), + GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(12), 0, GFLAGS), + GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(12), 1, GFLAGS), + GATE(PCLK_CRYPTO, "pclk_crypto", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(12), 2, GFLAGS), + COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_200m_100m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(43), 0, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(12), 3, GFLAGS), + COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(43), 6, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(12), 4, GFLAGS), + GATE(HCLK_KLAD, "hclk_klad", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(12), 5, GFLAGS), + GATE(PCLK_KEY_READER, "pclk_key_reader", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(12), 6, GFLAGS), + GATE(HCLK_RK_RNG_NS, "hclk_rk_rng_ns", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(12), 7, GFLAGS), + GATE(HCLK_RK_RNG_S, "hclk_rk_rng_s", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(12), 8, GFLAGS), + GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(12), 9, GFLAGS), + GATE(HCLK_TRNG_S, "hclk_trng_s", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(12), 10, GFLAGS), + GATE(HCLK_CRYPTO_S, "hclk_crypto_s", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(12), 11, GFLAGS), + GATE(PCLK_PERI_WDT, "pclk_peri_wdt", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE_NODIV(TCLK_PERI_WDT, "tclk_peri_wdt", mux_xin24m_32k_p, 0, + RK3562_PERI_CLKSEL_CON(43), 15, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(13), 1, GFLAGS), + GATE(ACLK_SYSMEM, "aclk_sysmem", "aclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 2, GFLAGS), + GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 3, GFLAGS), + GATE(PCLK_PERI_GRF, "pclk_peri_grf", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 4, GFLAGS), + GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 5, GFLAGS), + GATE(ACLK_RKDMAC, "aclk_rkdmac", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 6, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(14), 0, GFLAGS), + GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(14), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0, + RK3562_PERI_CLKSEL_CON(44), 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(14), 2, GFLAGS), + GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(14), 3, GFLAGS), + GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(14), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKSEL_CON(44), 8, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(14), 5, GFLAGS), + GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(14), 6, GFLAGS), + GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(14), 7, GFLAGS), + GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(15), 0, GFLAGS), + GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(15), 7, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(16), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, + RK3562_PERI_CLKSEL_CON(46), 0, 12, DFLAGS, + RK3562_PERI_CLKGATE_CON(16), 5, GFLAGS), + GATE(PCLK_IOC_VCCIO234, "pclk_ioc_vccio234", "pclk_peri", CLK_IS_CRITICAL, + RK3562_PERI_CLKGATE_CON(16), 12, GFLAGS), + GATE(PCLK_PERI_GPIO1, "pclk_peri_gpio1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(17), 0, GFLAGS), + GATE(PCLK_PERI_GPIO2, "pclk_peri_gpio2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(17), 1, GFLAGS), + COMPOSITE_NODIV(DCLK_PERI_GPIO, "dclk_peri_gpio", mux_xin24m_32k_p, 0, + RK3562_PERI_CLKSEL_CON(47), 8, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(17), 4, GFLAGS), + GATE(DCLK_PERI_GPIO1, "dclk_peri_gpio1", "dclk_peri_gpio", 0, + RK3562_PERI_CLKGATE_CON(17), 2, GFLAGS), + GATE(DCLK_PERI_GPIO2, "dclk_peri_gpio2", "dclk_peri_gpio", 0, + RK3562_PERI_CLKGATE_CON(17), 3, GFLAGS), + + /* PD_PHP */ + COMPOSITE(ACLK_PHP, "aclk_php", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(16), 0, GFLAGS), + COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, + RK3562_CLKSEL_CON(36), 8, 4, DFLAGS, + RK3562_CLKGATE_CON(16), 1, GFLAGS), + GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 4, GFLAGS), + GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 5, GFLAGS), + GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 6, GFLAGS), + GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_php", 0, + RK3562_CLKGATE_CON(16), 7, GFLAGS), + GATE(CLK_PCIE20_AUX, "clk_pcie20_aux", "xin24m", 0, + RK3562_CLKGATE_CON(16), 8, GFLAGS), + GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 10, GFLAGS), + COMPOSITE_NODIV(CLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0, + RK3562_CLKSEL_CON(36), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(16), 11, GFLAGS), + GATE(CLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0, + RK3562_CLKGATE_CON(16), 12, GFLAGS), + GATE(CLK_PIPEPHY_REF_FUNC, "clk_pipephy_ref_func", "pclk_pcie20", 0, + RK3562_CLKGATE_CON(17), 3, GFLAGS), + + /* PD_PMU1 */ + COMPOSITE_NOMUX(CLK_200M_PMU, "clk_200m_pmu", "cpll", CLK_IS_CRITICAL, + RK3562_PMU1_CLKSEL_CON(0), 0, 5, DFLAGS, + RK3562_PMU1_CLKGATE_CON(0), 1, GFLAGS), + /* PD_PMU0 */ + COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IS_CRITICAL, + RK3562_PMU0_CLKSEL_CON(0), 0, + RK3562_PMU0_CLKGATE_CON(0), 15, GFLAGS, + &rk3562_rtc32k_pmu_fracmux), + COMPOSITE_NOMUX(BUSCLK_PDPMU0, "busclk_pdpmu0", "clk_200m_pmu", CLK_IS_CRITICAL, + RK3562_PMU0_CLKSEL_CON(1), 3, 2, DFLAGS, + RK3562_PMU0_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_PMU0_CRU, "pclk_pmu0_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 0, GFLAGS), + GATE(PCLK_PMU0_PMU, "pclk_pmu0_pmu", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 1, GFLAGS), + GATE(CLK_PMU0_PMU, "clk_pmu0_pmu", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU0_HP_TIMER, "pclk_pmu0_hp_timer", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 3, GFLAGS), + GATE(CLK_PMU0_HP_TIMER, "clk_pmu0_hp_timer", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 4, GFLAGS), + GATE(CLK_PMU0_32K_HP_TIMER, "clk_pmu0_32k_hp_timer", "clk_rtc_32k", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_PMU0_PVTM, "pclk_pmu0_pvtm", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(0), 6, GFLAGS), + GATE(CLK_PMU0_PVTM, "clk_pmu0_pvtm", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_IOC_PMUIO, "pclk_ioc_pmuio", "busclk_pdpmu0", CLK_IS_CRITICAL, + RK3562_PMU0_CLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_PMU0_GPIO0, "pclk_pmu0_gpio0", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(0), 9, GFLAGS), + GATE(DBCLK_PMU0_GPIO0, "dbclk_pmu0_gpio0", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_PMU0_GRF, "pclk_pmu0_grf", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 11, GFLAGS), + GATE(PCLK_PMU0_SGRF, "pclk_pmu0_sgrf", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(1), 0, GFLAGS), + GATE(PCLK_PMU0_SCRKEYGEN, "pclk_pmu0_scrkeygen", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PIPEPHY_DIV, "clk_pipephy_div", "cpll", 0, + RK3562_PMU0_CLKSEL_CON(2), 0, 6, DFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_PIPEPHY_XIN24M, "clk_pipephy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_NODIV(CLK_PIPEPHY_REF, "clk_pipephy_ref", clk_pipephy_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 7, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 2, GFLAGS), + GATE(CLK_USB2PHY_XIN24M, "clk_usb2phy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 4, GFLAGS), + COMPOSITE_NODIV(CLK_USB2PHY_REF, "clk_usb2phy_ref", clk_usbphy_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 8, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 5, GFLAGS), + GATE(CLK_MIPIDSIPHY_XIN24M, "clk_mipidsiphy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 6, GFLAGS), + COMPOSITE_NODIV(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", clk_mipidsi_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 15, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 7, GFLAGS), + GATE(PCLK_PMU0_I2C0, "pclk_pmu0_i2c0", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE(CLK_PMU0_I2C0, "clk_pmu0_i2c0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU0_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 9, GFLAGS), + /* PD_PMU1 */ + GATE(PCLK_PMU1_CRU, "pclk_pmu1_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU1_CLKGATE_CON(0), 0, GFLAGS), + GATE(HCLK_PMU1_MEM, "hclk_pmu1_mem", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU1_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU1_UART0, "pclk_pmu1_uart0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_UART0_SRC, "clk_pmu1_uart0_src", "cpll", 0, + RK3562_PMU1_CLKSEL_CON(2), 0, 4, DFLAGS, + RK3562_PMU1_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_PMU1_UART0_FRAC, "clk_pmu1_uart0_frac", "clk_pmu1_uart0_src", CLK_SET_RATE_PARENT, + RK3562_PMU1_CLKSEL_CON(3), 0, + RK3562_PMU1_CLKGATE_CON(0), 9, GFLAGS, + &rk3562_clk_pmu1_uart0_fracmux), + GATE(SCLK_PMU1_UART0, "sclk_pmu1_uart0", "clk_pmu1_uart0", 0, + RK3562_PMU1_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_PMU1_SPI0, "pclk_pmu1_spi0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(CLK_PMU1_SPI0, "clk_pmu1_spi0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU1_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 2, DFLAGS, + RK3562_PMU1_CLKGATE_CON(1), 1, GFLAGS), + GATE(SCLK_IN_PMU1_SPI0, "sclk_in_pmu1_spi0", "sclk_in_pmu1_spi0_io", 0, + RK3562_PMU1_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PMU1_PWM0, "pclk_pmu1_pwm0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE(CLK_PMU1_PWM0, "clk_pmu1_pwm0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU1_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 2, DFLAGS, + RK3562_PMU1_CLKGATE_CON(1), 4, GFLAGS), + GATE(CLK_CAPTURE_PMU1_PWM0, "clk_capture_pmu1_pwm0", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(1), 5, GFLAGS), + GATE(CLK_PMU1_WIFI, "clk_pmu1_wifi", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(1), 6, GFLAGS), + GATE(FCLK_PMU1_CM0_CORE, "fclk_pmu1_cm0_core", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_PMU1_CM0_RTC, "clk_pmu1_cm0_rtc", "clk_rtc_32k", 0, + RK3562_PMU1_CLKGATE_CON(2), 1, GFLAGS), + GATE(PCLK_PMU1_WDTNS, "pclk_pmu1_wdtns", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(2), 3, GFLAGS), + GATE(CLK_PMU1_WDTNS, "clk_pmu1_wdtns", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(2), 4, GFLAGS), + GATE(PCLK_PMU1_MAILBOX, "pclk_pmu1_mailbox", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(3), 8, GFLAGS), + + /* PD_RGA */ + COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_jdec", 0, + RK3562_CLKSEL_CON(32), 8, 3, DFLAGS, + RK3562_CLKGATE_CON(14), 1, GFLAGS), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_jdec", 0, + RK3562_CLKGATE_CON(14), 6, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, + RK3562_CLKGATE_CON(14), 7, GFLAGS), + COMPOSITE(CLK_RGA_CORE, "clk_rga_core", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(14), 8, GFLAGS), + GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_jdec", 0, + RK3562_CLKGATE_CON(14), 9, GFLAGS), + GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, + RK3562_CLKGATE_CON(14), 10, GFLAGS), + + /* PD_VDPU */ + COMPOSITE(ACLK_VDPU_PRE, "aclk_vdpu_pre", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(10), 0, GFLAGS), + COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_CLKGATE_CON(10), 3, GFLAGS), + COMPOSITE_NOMUX(HCLK_VDPU_PRE, "hclk_vdpu_pre", "aclk_vdpu", 0, + RK3562_CLKSEL_CON(24), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(10), 4, GFLAGS), + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_vdpu", 0, + RK3562_CLKGATE_CON(10), 7, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdpu_pre", 0, + RK3562_CLKGATE_CON(10), 8, GFLAGS), + + /* PD_VEPU */ + COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(20), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE(ACLK_VEPU_PRE, "aclk_vepu_pre", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_CLKGATE_CON(9), 1, GFLAGS), + COMPOSITE_NOMUX(HCLK_VEPU_PRE, "hclk_vepu_pre", "aclk_vepu", 0, + RK3562_CLKSEL_CON(21), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(9), 2, GFLAGS), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_vepu", 0, + RK3562_CLKGATE_CON(9), 5, GFLAGS), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_vepu", 0, + RK3562_CLKGATE_CON(9), 6, GFLAGS), + + /* PD_VI */ + COMPOSITE(ACLK_VI, "aclk_vi", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi_isp", 0, + RK3562_CLKSEL_CON(26), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi_isp", 0, + RK3562_CLKSEL_CON(26), 8, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 2, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vi_isp", 0, + RK3562_CLKGATE_CON(11), 6, GFLAGS), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, + RK3562_CLKGATE_CON(11), 7, GFLAGS), + COMPOSITE(CLK_ISP, "clk_isp", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(27), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 8, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_isp", 0, + RK3562_CLKGATE_CON(11), 9, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, + RK3562_CLKGATE_CON(11), 10, GFLAGS), + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_pvtpll_apll_p, 0, + RK3562_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 11, GFLAGS), + GATE(CSIRX0_CLK_DATA, "csirx0_clk_data", "csirx0_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 12, GFLAGS), + GATE(CSIRX1_CLK_DATA, "csirx1_clk_data", "csirx1_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 13, GFLAGS), + GATE(CSIRX2_CLK_DATA, "csirx2_clk_data", "csirx2_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 14, GFLAGS), + GATE(CSIRX3_CLK_DATA, "csirx3_clk_data", "csirx3_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 15, GFLAGS), + GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 0, GFLAGS), + GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 1, GFLAGS), + GATE(PCLK_CSIHOST2, "pclk_csihost2", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_CSIHOST3, "pclk_csihost3", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 3, GFLAGS), + GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 4, GFLAGS), + GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 5, GFLAGS), + + /* PD_VO */ + COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", gpll_cpll_vpll_hpll_p, 0, + RK3562_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo", 0, + RK3562_CLKSEL_CON(29), 0, 5, DFLAGS, + RK3562_CLKGATE_CON(13), 1, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vo", 0, + RK3562_CLKGATE_CON(13), 6, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo_pre", 0, + RK3562_CLKGATE_CON(13), 7, GFLAGS), + COMPOSITE(DCLK_VOP, "dclk_vop", gpll_hpll_vpll_apll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3562_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_CLKGATE_CON(13), 8, GFLAGS), + COMPOSITE(DCLK_VOP1, "dclk_vop1", gpll_hpll_vpll_apll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3562_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_CLKGATE_CON(13), 9, GFLAGS), +}; + +static void __iomem *rk3562_cru_base; + +static void rk3562_dump_cru(void) +{ + if (rk3562_cru_base) { + pr_warn("CRU:\n"); + print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, + 32, 4, rk3562_cru_base, + 0x600, false); + } +} + +static void __init rk3562_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + struct clk **clks; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + rk3562_cru_base = reg_base; + + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); + return; + } + clks = ctx->clk_data.clks; + + rockchip_clk_register_plls(ctx, rk3562_pll_clks, + ARRAY_SIZE(rk3562_pll_clks), + RK3562_GRF_SOC_STATUS0); + + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", + 2, clks[PLL_APLL], clks[PLL_GPLL], + &rk3562_cpuclk_data, rk3562_cpuclk_rates, + ARRAY_SIZE(rk3562_cpuclk_rates)); + + rockchip_clk_register_branches(ctx, rk3562_clk_branches, + ARRAY_SIZE(rk3562_clk_branches)); + + /* (0x30444 - 0x400) / 4 + 1 = 49170 */ + rockchip_register_softrst(np, 49170, reg_base + RK3562_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_register_restart_notifier(ctx, RK3562_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); + + if (!rk_dump_cru) + rk_dump_cru = rk3562_dump_cru; +} + +CLK_OF_DECLARE(rk3562_cru, "rockchip,rk3562-cru", rk3562_clk_init); + +#ifdef MODULE +struct clk_rk3562_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3562_inits clk_3562_cru_init = { + .inits = rk3562_clk_init, +}; + +static const struct of_device_id clk_rk3562_match_table[] = { + { + .compatible = "rockchip,rk3562-cru", + .data = &clk_3562_cru_init, + }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_rk3562_match_table); + +static int clk_rk3562_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + const struct clk_rk3562_inits *init_data; + + match = of_match_device(clk_rk3562_match_table, &pdev->dev); + if (!match || !match->data) + return -EINVAL; + + init_data = match->data; + if (init_data->inits) + init_data->inits(np); + + return 0; +} + +static struct platform_driver clk_rk3562_driver = { + .probe = clk_rk3562_probe, + .driver = { + .name = "clk-rk3562", + .of_match_table = clk_rk3562_match_table, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(clk_rk3562_driver); + +MODULE_DESCRIPTION("Rockchip RK3562 Clock Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:clk-rk3562"); +#endif /* MODULE */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index f580f069a26d..4ace4dfb0a3f 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -332,6 +332,45 @@ struct clk; #define RK3528_GLB_SRST_FST 0xc08 #define RK3528_GLB_SRST_SND 0xc0c +#define RK3562_PMU0_CRU_BASE 0x10000 +#define RK3562_PMU1_CRU_BASE 0x18000 +#define RK3562_DDR_CRU_BASE 0x20000 +#define RK3562_SUBDDR_CRU_BASE 0x28000 +#define RK3562_PERI_CRU_BASE 0x30000 + +#define RK3562_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40) +#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20) +#define RK3562_MODE_CON 0x600 +#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380) +#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380) +#define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100) +#define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180) +#define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200) +#define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100) +#define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180) +#define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200) +#define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100) +#define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300) +#define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400) +#define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100) +#define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180) +#define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200) +#define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100) +#define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180) +#define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200) +#define RK3562_GLB_SRST_FST 0x614 +#define RK3562_GLB_SRST_SND 0x618 +#define RK3562_GLB_RST_CON 0x61c +#define RK3562_GLB_RST_ST 0x620 +#define RK3562_SDMMC0_CON0 0x624 +#define RK3562_SDMMC0_CON1 0x628 +#define RK3562_SDMMC1_CON0 0x62c +#define RK3562_SDMMC1_CON1 0x630 + #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) #define RK3568_MODE_CON0 0xc0 #define RK3568_MISC_CON0 0xc4 From 13dc7de2e408f3ff4bcb10c09b69b5a96476911c Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 29 Jun 2022 20:32:13 +0800 Subject: [PATCH 010/258] dt-bindings: add power-domain header for RK3562 SoC According to a description from TRM, add all the power domains. Signed-off-by: Finley Xiao Change-Id: Ia188dad23c884521775f9e608203d1281b093a39 --- include/dt-bindings/power/rk3562-power.h | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3562-power.h diff --git a/include/dt-bindings/power/rk3562-power.h b/include/dt-bindings/power/rk3562-power.h new file mode 100644 index 000000000000..94b26b5bea5f --- /dev/null +++ b/include/dt-bindings/power/rk3562-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#ifndef __DT_BINDINGS_POWER_RK3562_POWER_H__ +#define __DT_BINDINGS_POWER_RK3562_POWER_H__ + +/* VD_CORE */ +#define RK3562_PD_CPU_0 0 +#define RK3562_PD_CPU_1 1 +#define RK3562_PD_CPU_2 2 +#define RK3562_PD_CPU_3 3 +#define RK3562_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3562_PD_PMU 5 +#define RK3562_PD_PMU_ALIVE 6 + +/* VD_NPU */ +#define RK3562_PD_NPU 7 + +/* VD_GPU */ +#define RK3562_PD_GPU 8 + +/* VD_LOGIC */ +#define RK3562_PD_DDR 9 +#define RK3562_PD_VEPU 10 +#define RK3562_PD_VDPU 11 +#define RK3562_PD_VI 12 +#define RK3562_PD_VO 13 +#define RK3562_PD_RGA 14 +#define RK3562_PD_PHP 15 +#define RK3562_PD_LOGIC_ALIVE 16 + +#endif From 402eeba39bec83e3f39ea3146abc58f3fca42594 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 29 Jun 2022 20:32:46 +0800 Subject: [PATCH 011/258] soc: rockchip: power-domain: add power domain support for rk3562 This driver is modified to support RK3562 SoC. Add support to ungate clk. Add support to shut down memory for rk3562. Signed-off-by: Finley Xiao Change-Id: Ideeaf378b0548a9a32e05345f56a6d6bfb037a20 --- drivers/soc/rockchip/pm_domains.c | 97 +++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 585b24e28bdf..9e630d8e8349 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -52,6 +53,9 @@ struct rockchip_domain_info { int req_w_mask; int mem_status_mask; int repair_status_mask; + int clk_ungate_mask; + int clk_ungate_w_mask; + int mem_num; bool keepon_startup; bool always_on; u32 pwr_offset; @@ -69,6 +73,8 @@ struct rockchip_pmu_info { u32 chain_status_offset; u32 mem_status_offset; u32 repair_status_offset; + u32 clk_ungate_offset; + u32 mem_sd_offset; u32 core_pwrcnt_offset; u32 gpu_pwrcnt_offset; @@ -202,6 +208,23 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd) .keepon_startup = keepon, \ } +#define DOMAIN_M_C_SD(_name, pwr, status, req, idle, ack, clk, mem, wakeup, keepon) \ +{ \ + .name = _name, \ + .pwr_w_mask = (pwr) << 16, \ + .pwr_mask = (pwr), \ + .status_mask = (status), \ + .req_w_mask = (req) << 16, \ + .req_mask = (req), \ + .idle_mask = (idle), \ + .ack_mask = (ack), \ + .clk_ungate_mask = (clk), \ + .clk_ungate_w_mask = (clk) << 16, \ + .mem_num = (mem), \ + .active_wakeup = wakeup, \ + .keepon_startup = keepon, \ +} + #define DOMAIN_M_O(_name, pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon) \ { \ .name = _name, \ @@ -286,6 +309,12 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd) #define DOMAIN_RK3528(pwr, req, always, wakeup) \ DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false) +#define DOMAIN_RK3562(name, pwr, req, mem, wakeup) \ + DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, false) + +#define DOMAIN_RK3562_PROTECT(name, pwr, req, mem, wakeup) \ + DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, true) + #define DOMAIN_RK3568(name, pwr, req, wakeup) \ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false) @@ -316,6 +345,42 @@ static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu) return val; } +static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate) +{ + const struct rockchip_domain_info *pd_info = pd->info; + struct rockchip_pmu *pmu = pd->pmu; + unsigned int val; + + if (!pd_info->clk_ungate_mask) + return 0; + if (!pmu->info->clk_ungate_offset) + return 0; + + val = ungate ? (pd_info->clk_ungate_mask | pd_info->clk_ungate_w_mask) : + pd_info->clk_ungate_w_mask; + regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val); + + return 0; +} + +static int rockchip_pmu_mem_shut_down(struct rockchip_pm_domain *pd, bool sd) +{ + const struct rockchip_domain_info *pd_info = pd->info; + struct rockchip_pmu *pmu = pd->pmu; + unsigned int i; + + if (!pd_info->mem_num) + return 0; + if (!pmu->info->mem_sd_offset) + return 0; + + for (i = 0; i < pd_info->mem_num; i++) + regmap_write(pmu->regmap, pmu->info->mem_sd_offset, + (sd << i) | (1 << (i + 16))); + + return 0; +} + static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, bool idle) { @@ -709,6 +774,7 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) rockchip_pmu_unlock(pd); return ret; } + rockchip_pmu_ungate_clk(pd, true); if (!power_on) { rockchip_pmu_save_qos(pd); @@ -721,6 +787,7 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) genpd->name); goto out; } + rockchip_pmu_mem_shut_down(pd, true); } ret = rockchip_do_pmu_set_power_domain(pd, power_on); @@ -731,6 +798,7 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) } if (power_on) { + rockchip_pmu_mem_shut_down(pd, false); /* if powering up, leave idle mode */ ret = rockchip_pmu_set_idle_request(pd, false); if (ret) { @@ -746,6 +814,7 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) } out: + rockchip_pmu_ungate_clk(pd, false); clk_bulk_disable(pd->num_clks, pd->clks); if (!power_on && !IS_ERR(pd->supply)) @@ -1569,6 +1638,17 @@ static const struct rockchip_domain_info rk3528_pm_domains[] = { [RK3528_PD_VPU] = DOMAIN_RK3528(0, BIT(8), true, false), }; +static const struct rockchip_domain_info rk3562_pm_domains[] = { + [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), 0, false), + [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), 0, false), + [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), 0, false), + [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), 0, false), + [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), 0, false), + [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), 0, false), + [RK3562_PD_VO] = DOMAIN_RK3562_PROTECT("vo", BIT(6), BIT(4), 16, false), + [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), 0, false), +}; + static const struct rockchip_domain_info rk3568_pm_domains[] = { [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), @@ -1782,6 +1862,19 @@ static const struct rockchip_pmu_info rk3528_pmu = { .domain_info = rk3528_pm_domains, }; +static const struct rockchip_pmu_info rk3562_pmu = { + .pwr_offset = 0x210, + .status_offset = 0x230, + .req_offset = 0x110, + .idle_offset = 0x128, + .ack_offset = 0x120, + .clk_ungate_offset = 0x140, + .mem_sd_offset = 0x300, + + .num_domains = ARRAY_SIZE(rk3562_pm_domains), + .domain_info = rk3562_pm_domains, +}; + static const struct rockchip_pmu_info rk3568_pmu = { .pwr_offset = 0xa0, .status_offset = 0x98, @@ -1867,6 +1960,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .data = (void *)&rk3528_pmu, }, #endif + { + .compatible = "rockchip,rk3562-power-controller", + .data = (void *)&rk3562_pmu, + }, { .compatible = "rockchip,rk3568-power-controller", .data = (void *)&rk3568_pmu, From 8d580cfd196e34ca46452ae595419d23faf0d8af Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 29 Jun 2022 20:33:08 +0800 Subject: [PATCH 012/258] arm64: dts: rockchip: add core dtsi for RK3562 Soc RK3562 is a Soc from Rockchip, which embedded with quad ARM Cortex-A53. Signed-off-by: Finley Xiao Signed-off-by: Steven Liu Signed-off-by: Yu Qiaowei Signed-off-by: Jason Zhu Signed-off-by: Frank Wang Signed-off-by: Xuhui Lin Signed-off-by: Sugar Zhang Signed-off-by: Li Huang Signed-off-by: Damon Ding Signed-off-by: David Wu Signed-off-by: Cai YiWei Signed-off-by: shengfei Xu Signed-off-by: Shaohan Yao Signed-off-by: Sandy Huang Signed-off-by: Guochun Huang Signed-off-by: Chandler Chen Signed-off-by: William Wu Signed-off-by: Jon Lin Signed-off-by: Zhang Yubing Signed-off-by: Simon Xue Signed-off-by: Lin Jinhan Signed-off-by: Felix Zeng Signed-off-by: Zefa Chen Signed-off-by: Jake Wu Signed-off-by: Yifeng Zhao Signed-off-by: Joseph Chen Signed-off-by: Huibin Hong Signed-off-by: Shawn Lin Signed-off-by: Liang Chen Change-Id: I0d8d52eee06b7e962434510fbfb214c01d25ef36 --- .../boot/dts/rockchip/rk3562-pinctrl.dtsi | 2341 ++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3562.dtsi | 2444 +++++++++++++++++ 2 files changed, 4785 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi new file mode 100644 index 000000000000..aad7b893c543 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi @@ -0,0 +1,2341 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + cam { + /omit-if-no-ref/ + camm0_pins: camm0-pins { + rockchip,pins = + /* cam_clk0_out_m0 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* cam_clk1_out_m0 */ + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_pins: camm1-pins { + rockchip,pins = + /* cam_clk0_out_m1 */ + <4 RK_PB1 3 &pcfg_pull_none>, + /* cam_clk1_out_m1 */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk2_out: cam-clk2-out { + rockchip,pins = + /* cam_clk2_out */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + cam_clk3_out: cam-clk3-out { + rockchip,pins = + /* cam_clk3_out */ + <3 RK_PB5 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rx_m0 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* can0_tx_m0 */ + <3 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rx_m1 */ + <3 RK_PB7 6 &pcfg_pull_none>, + /* can0_tx_m1 */ + <3 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m2_pins: can0m2-pins { + rockchip,pins = + /* can0_rx_m2 */ + <0 RK_PC7 2 &pcfg_pull_none>, + /* can0_tx_m2 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rx_m0 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* can1_tx_m0 */ + <1 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rx_m1 */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* can1_tx_m1 */ + <0 RK_PC0 4 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clk_32k_in: clk-32k-in { + rockchip,pins = + /* clk_32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + clk0 { + /omit-if-no-ref/ + clk0_32k_out: clk0-32k-out { + rockchip,pins = + /* clk0_32k_out */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + clk1 { + /omit-if-no-ref/ + clk1_32k_out: clk1-32k-out { + rockchip,pins = + /* clk1_32k_out */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + }; + + dsm { + /omit-if-no-ref/ + dsm_pins: dsm-pins { + rockchip,pins = + /* dsm_aud_ln */ + <1 RK_PB4 5 &pcfg_pull_none>, + /* dsm_aud_lp */ + <1 RK_PB3 5 &pcfg_pull_none>, + /* dsm_aud_rn */ + <1 RK_PB6 6 &pcfg_pull_none>, + /* dsm_aud_rp */ + <1 RK_PB5 6 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins = + /* emmc_strb */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + ethm0_pins: ethm0-pins { + rockchip,pins = + /* eth_clk_25m_out_m0 */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ethm1_pins: ethm1-pins { + rockchip,pins = + /* eth_clk_25m_out_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PB1 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PA0 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PA1 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PA2 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins = + /* fspi_csn0 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins = + /* fspi_csn1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <4 RK_PB4 5 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PB5 5 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <3 RK_PD2 5 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <3 RK_PD3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <3 RK_PA0 1 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <3 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <4 RK_PA5 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <4 RK_PA6 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PB6 5 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PB7 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <3 RK_PC2 1 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PC3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <1 RK_PC7 4 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD0 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins = + /* i2s0_lrck_m0 */ + <3 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + /* i2s0_mclk_m0 */ + <3 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins = + /* i2s0_sclk_m0 */ + <3 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi0: i2s0m0-sdi0 { + rockchip,pins = + /* i2s0_sdi0_m0 */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi1: i2s0m0-sdi1 { + rockchip,pins = + /* i2s0_sdi1_m0 */ + <3 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi2: i2s0m0-sdi2 { + rockchip,pins = + /* i2s0_sdi2_m0 */ + <3 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi3: i2s0m0-sdi3 { + rockchip,pins = + /* i2s0_sdi3_m0 */ + <3 RK_PA6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo0: i2s0m0-sdo0 { + rockchip,pins = + /* i2s0_sdo0_m0 */ + <3 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo1: i2s0m0-sdo1 { + rockchip,pins = + /* i2s0_sdo1_m0 */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo2: i2s0m0-sdo2 { + rockchip,pins = + /* i2s0_sdo2_m0 */ + <3 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo3: i2s0m0-sdo3 { + rockchip,pins = + /* i2s0_sdo3_m0 */ + <3 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins = + /* i2s0_lrck_m1 */ + <1 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + /* i2s0_mclk_m1 */ + <1 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins = + /* i2s0_sclk_m1 */ + <1 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi0: i2s0m1-sdi0 { + rockchip,pins = + /* i2s0_sdi0_m1 */ + <1 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi1: i2s0m1-sdi1 { + rockchip,pins = + /* i2s0_sdi1_m1 */ + <1 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi2: i2s0m1-sdi2 { + rockchip,pins = + /* i2s0_sdi2_m1 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi3: i2s0m1-sdi3 { + rockchip,pins = + /* i2s0_sdi3_m1 */ + <1 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo0: i2s0m1-sdo0 { + rockchip,pins = + /* i2s0_sdo0_m1 */ + <1 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo1: i2s0m1-sdo1 { + rockchip,pins = + /* i2s0_sdo1_m1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo2: i2s0m1-sdo2 { + rockchip,pins = + /* i2s0_sdo2_m1 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo3: i2s0m1-sdo3 { + rockchip,pins = + /* i2s0_sdo3_m1 */ + <2 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + /* i2s1_lrck_m0 */ + <3 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1_mclk_m0 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + /* i2s1_sclk_m0 */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1_sdi0_m0 */ + <3 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1_sdi1_m0 */ + <3 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1_sdi2_m0 */ + <3 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1_sdi3_m0 */ + <3 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1_sdo0_m0 */ + <3 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1_sdo1_m0 */ + <4 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1_sdo2_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1_sdo3_m0 */ + <4 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + /* i2s1_lrck_m1 */ + <3 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1_mclk_m1 */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + /* i2s1_sclk_m1 */ + <3 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1_sdi0_m1 */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1_sdi1_m1 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1_sdi2_m1 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1_sdi3_m1 */ + <3 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1_sdo0_m1 */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1_sdo1_m1 */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1_sdo2_m1 */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1_sdo3_m1 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2_lrck_m0 */ + <1 RK_PD6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2_mclk_m0 */ + <2 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2_sclk_m0 */ + <1 RK_PD5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2_sdi_m0 */ + <2 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2_sdo_m0 */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2_lrck_m1 */ + <4 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2_mclk_m1 */ + <3 RK_PD6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + /* i2s2_sclk_m1 */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2_sdi_m1 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2_sdo_m1 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flash_trigin */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* isp_flash_trigout */ + <3 RK_PC3 2 &pcfg_pull_none>, + /* isp_prelight_trigout */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_cpu_mcu_tck_m0 */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m0 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_cpu_mcu_tck_m1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m1 */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqn_m0 */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* pcie20_perstn_m0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* pcie20_waken_m0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqn_m1 */ + <3 RK_PA6 4 &pcfg_pull_none>, + /* pcie20_perstn_m1 */ + <3 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_waken_m1 */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk0: pdmm0-clk0 { + rockchip,pins = + /* pdm_clk0_m0 */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdm_clk1_m0 */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdm_sdi0_m0 */ + <3 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdm_sdi1_m0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdm_sdi2_m0 */ + <3 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdm_sdi3_m0 */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk0: pdmm1-clk0 { + rockchip,pins = + /* pdm_clk0_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdm_clk1_m1 */ + <4 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdm_sdi0_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdm_sdi1_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdm_sdi2_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdm_sdi3_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA3 0 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <0 RK_PA2 0 &pcfg_output_low>; + }; + + /omit-if-no-ref/ + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PC5 4 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PC6 4 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <1 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_m0 */ + <0 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_m1 */ + <1 RK_PD0 3 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <1 RK_PD1 4 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <1 RK_PD2 4 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <1 RK_PD3 4 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_m0 */ + <0 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_m1 */ + <1 RK_PD4 4 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PA4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PC1 4 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PC2 4 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <1 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <1 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_m0 */ + <1 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_m1 */ + <1 RK_PC4 4 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <3 RK_PB4 5 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <4 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <1 RK_PD7 5 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_m0 */ + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_m1 */ + <2 RK_PA0 5 &pcfg_pull_none>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + ref_pins: ref-pins { + rockchip,pins = + /* ref_clk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmiim0_miim: rgmiim0-miim { + rockchip,pins = + /* rgmii_mdc_m0 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* rgmii_mdio_m0 */ + <4 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_er: rgmiim0-rx_er { + rockchip,pins = + /* rgmii_rxer_m0 */ + <4 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_bus2: rgmiim0-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0_m0 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_rxdv_m0 */ + <4 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_tx_bus2: rgmiim0-tx_bus2 { + rockchip,pins = + /* rgmii_txd0_m0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_txd1_m0 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_txen_m0 */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_clk: rgmiim0-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk_m0 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* rgmii_txclk_m0 */ + <3 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_bus: rgmiim0-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2_m0 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* rgmii_txd2_m0 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_txd3_m0 */ + <3 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_clk: rgmiim0-clk { + rockchip,pins = + /* rgmiim0_clk */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_miim: rgmiim1-miim { + rockchip,pins = + /* rgmii_mdc_m1 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_er: rgmiim1-rx_er { + rockchip,pins = + /* rgmii_rxer_m1 */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_bus2: rgmiim1-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0_m1 */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_tx_bus2: rgmiim1-tx_bus2 { + rockchip,pins = + /* rgmii_txd0_m1 */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* rgmii_txd1_m1 */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* rgmii_txen_m1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_clk: rgmiim1-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk_m1 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_bus: rgmiim1-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2_m1 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* rgmii_txd2_m1 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_txd3_m1 */ + <1 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_clk: rgmiim1-clk { + rockchip,pins = + /* rgmiim1_clk */ + <1 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + rmii { + /omit-if-no-ref/ + rmii_pins: rmii-pins { + rockchip,pins = + /* rmii_clk */ + <1 RK_PD5 5 &pcfg_pull_none>, + /* rmii_mdc */ + <1 RK_PC7 5 &pcfg_pull_none>, + /* rmii_mdio */ + <1 RK_PD0 5 &pcfg_pull_none>, + /* rmii_rxd0 */ + <1 RK_PD4 5 &pcfg_pull_none>, + /* rmii_rxd1 */ + <1 RK_PD7 6 &pcfg_pull_none>, + /* rmii_rxdv_crs */ + <1 RK_PD6 5 &pcfg_pull_none>, + /* rmii_rxer */ + <2 RK_PA0 6 &pcfg_pull_none>, + /* rmii_txd0 */ + <1 RK_PD1 5 &pcfg_pull_none>, + /* rmii_txd1 */ + <1 RK_PD2 5 &pcfg_pull_none>, + /* rmii_txen */ + <1 RK_PD3 5 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_detn */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_detn */ + <1 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_tx_m0 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_tx_m1 */ + <0 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_tx_m2 */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* spi0_miso_m0 */ + <0 RK_PC5 3 &pcfg_pull_none>, + /* spi0_mosi_m0 */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_csn0: spi0m0-csn0 { + rockchip,pins = + /* spi0m0_csn0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0m0_csn1: spi0m0-csn1 { + rockchip,pins = + /* spi0m0_csn1 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <3 RK_PB5 4 &pcfg_pull_none>, + /* spi0_miso_m1 */ + <3 RK_PC0 4 &pcfg_pull_none>, + /* spi0_mosi_m1 */ + <3 RK_PB4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_csn0: spi0m1-csn0 { + rockchip,pins = + /* spi0m1_csn0 */ + <3 RK_PB7 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0m1_csn1: spi0m1-csn1 { + rockchip,pins = + /* spi0m1_csn1 */ + <3 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clk_m0 */ + <3 RK_PD6 4 &pcfg_pull_none>, + /* spi1_miso_m0 */ + <4 RK_PA3 4 &pcfg_pull_none>, + /* spi1_mosi_m0 */ + <4 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_csn0: spi1m0-csn0 { + rockchip,pins = + /* spi1m0_csn0 */ + <3 RK_PD7 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1m0_csn1: spi1m0-csn1 { + rockchip,pins = + /* spi1m0_csn1 */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <1 RK_PC0 4 &pcfg_pull_none>, + /* spi1_miso_m1 */ + <1 RK_PB4 4 &pcfg_pull_none>, + /* spi1_mosi_m1 */ + <1 RK_PB3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_csn0: spi1m1-csn0 { + rockchip,pins = + /* spi1m1_csn0 */ + <1 RK_PB6 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1m1_csn1: spi1m1-csn1 { + rockchip,pins = + /* spi1m1_csn1 */ + <1 RK_PB5 4 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clk_m0 */ + <4 RK_PB6 4 &pcfg_pull_none>, + /* spi2_miso_m0 */ + <3 RK_PD2 4 &pcfg_pull_none>, + /* spi2_mosi_m0 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_csn0: spi2m0-csn0 { + rockchip,pins = + /* spi2m0_csn0 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2m0_csn1: spi2m0-csn1 { + rockchip,pins = + /* spi2m0_csn1 */ + <4 RK_PB4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clk_m1 */ + <2 RK_PA1 4 &pcfg_pull_none>, + /* spi2_miso_m1 */ + <2 RK_PA0 4 &pcfg_pull_none>, + /* spi2_mosi_m1 */ + <1 RK_PD7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_csn0: spi2m1-csn0 { + rockchip,pins = + /* spi2m1_csn0 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi2m1_csn1: spi2m1-csn1 { + rockchip,pins = + /* spi2m1_csn1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_pins: tsadcm0-pins { + rockchip,pins = + /* tsadc_shut_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_pins: tsadcm1-pins { + rockchip,pins = + /* tsadc_shut_m1 */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins = + /* tsadc_shut_org */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <1 RK_PB3 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <1 RK_PB4 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <1 RK_PD1 1 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <1 RK_PD2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <1 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <4 RK_PA6 3 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PA5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PC1 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PC0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA1 2 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <3 RK_PA2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <4 RK_PB5 6 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB4 6 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <4 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <3 RK_PC0 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB7 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_ctsn: uart3m1-ctsn { + rockchip,pins = + /* uart3m1_ctsn */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m1_rtsn: uart3m1-rtsn { + rockchip,pins = + /* uart3m1_rtsn */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PD1 3 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PD0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <3 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rx_m1 */ + <1 RK_PD5 3 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <1 RK_PD6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_ctsn: uart4m1-ctsn { + rockchip,pins = + /* uart4m1_ctsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m1_rtsn: uart4m1-rtsn { + rockchip,pins = + /* uart4m1_rtsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <1 RK_PB7 3 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <3 RK_PA7 5 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PA6 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <3 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <0 RK_PC7 1 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <0 RK_PC6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <4 RK_PB0 5 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <4 RK_PA7 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins = + /* uart6m1_ctsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins = + /* uart6m1_rtsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <3 RK_PC7 3 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PC4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <3 RK_PD2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <3 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <1 RK_PB3 3 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB4 3 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rx_m0 */ + <3 RK_PB3 3 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <3 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rx_m1 */ + <3 RK_PD5 3 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins = + /* uart8m1_ctsn */ + <3 RK_PD7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins = + /* uart8m1_rtsn */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <4 RK_PB3 3 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <4 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ + <3 RK_PC3 3 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <3 RK_PC2 3 &pcfg_pull_up>; + }; + }; + + vo { + /omit-if-no-ref/ + vo_pins: vo-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d0 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d1 */ + <4 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d8 */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d9 */ + <4 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* vo_lcdc_d16 */ + <4 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d17 */ + <4 RK_PB1 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + vo { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_2>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m0: rgb3x8-pins-m0 { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m1: rgb3x8-pins-m1 { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgb565_pins: rgb565-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgb666_pins: rgb666-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi new file mode 100644 index 000000000000..dd768e8d4437 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -0,0 +1,2444 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3562"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi2dphy0 = &csi2_dphy0; + csi2dphy1 = &csi2_dphy1; + csi2dphy2 = &csi2_dphy2; + csi2dphy3 = &csi2_dphy3; + csi2dphy4 = &csi2_dphy4; + csi2dphy5 = &csi2_dphy5; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + rkcif_mipi_lvds0= &rkcif_mipi_lvds; + rkcif_mipi_lvds1= &rkcif_mipi_lvds1; + rkcif_mipi_lvds2= &rkcif_mipi_lvds2; + rkcif_mipi_lvds3= &rkcif_mipi_lvds3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &sfc; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + hclk_vepu: hclk_vepu@ff100324 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100324 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VI>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vdpu: aclk_vdpu@ff100328 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100328 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_TOP_VIO>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vi_isp: aclk_vi_isp@ff10032c { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff10032c 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_TOP_VIO>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vo: aclk_vo@ff100334 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100334 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_TOP_VIO>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vepu: aclk_vepu@ff100324 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100324 0 0x10>; + clock-names = "link"; + clocks = <&aclk_vi_isp>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rga_jdec: aclk_rga_jdec@ff100338 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100338 0 0x10>; + clock-names = "link"; + clocks = <&aclk_vo>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <862500 862500 1150000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <937500 937500 1150000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1012500 1012500 1150000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1100000 1100000 1150000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1150000 1150000 1150000>; + clock-latency-ns = <40000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + + /* dphy0 full mode */ + csi2_dphy0: csi2-dphy0 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>; + status = "disabled"; + }; + + /* dphy0 split mode 01 */ + csi2_dphy1: csi2-dphy1 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>; + status = "disabled"; + }; + + /* dphy0 split mode 23 */ + csi2_dphy2: csi2-dphy2 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>; + status = "disabled"; + }; + + /* dphy1 full mode */ + csi2_dphy3: csi2-dphy3 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy1 split mode 01 */ + csi2_dphy4: csi2-dphy4 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy1 split mode 23 */ + csi2_dphy5: csi2-dphy5 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy1_hw>; + status = "disabled"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <3>; + rockchip,resetgroup-count = <3>; + status = "disabled"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rkcif_mipi_lvds: rkcif-mipi-lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds1: rkcif-mipi-lvds1 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds2: rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds3: rkcif-mipi-lvds3 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkisp_vir0: rkisp-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rkisp_vir1: rkisp-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rkisp_vir2: rkisp-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rkisp_vir3: rkisp-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + trips { + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + scmi_shmem: scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + }; + + usbdrd30: usbdrd { + compatible = "rockchip,rk3562-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>; + clock-names = "ref", "suspend", "bus", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: usb@fe500000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe500000 0x0 0x400000>; + interrupts = ; + dr_mode = "otg"; + phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3562_PD_PHP>; + resets = <&cru SRST_USB3OTG>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + quirk-skip-phy-init; + status = "disabled"; + }; + }; + + gic: interrupt-controller@fe901000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfe901000 0 0x1000>, + <0x0 0xfe902000 0 0x2000>, + <0x0 0xfe904000 0 0x2000>, + <0x0 0xfe906000 0 0x2000>; + interrupts = ; + }; + + usb_host0_ehci: usb@fed00000 { + compatible = "generic-ehci"; + reg = <0x0 0xfed00000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fed40000 { + compatible = "generic-ohci"; + reg = <0x0 0xfed40000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + debug: debug@fed90000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfed90000 0x0 0x2000>, + <0x0 0xfed92000 0x0 0x2000>, + <0x0 0xfed94000 0x0 0x2000>, + <0x0 0xfed96000 0x0 0x2000>; + }; + + qos_dma2ddr: qos@fee03800 { + compatible = "syscon"; + reg = <0x0 0xfee03800 0x0 0x20>; + }; + + qos_mcu: qos@fee10000 { + compatible = "syscon"; + reg = <0x0 0xfee10000 0x0 0x20>; + }; + + qos_dft_apb: qos@fee10100 { + compatible = "syscon"; + reg = <0x0 0xfee10100 0x0 0x20>; + }; + + qos_gmac: qos@fee10200 { + compatible = "syscon"; + reg = <0x0 0xfee10200 0x0 0x20>; + }; + + qos_mac100: qos@fee10300 { + compatible = "syscon"; + reg = <0x0 0xfee10300 0x0 0x20>; + }; + + qos_dcf: qos@fee10400 { + compatible = "syscon"; + reg = <0x0 0xfee10400 0x0 0x20>; + }; + + qos_cpu: qos@fee20000 { + compatible = "syscon"; + reg = <0x0 0xfee20000 0x0 0x20>; + }; + + qos_daplite_apb: qos@fee20100 { + compatible = "syscon"; + reg = <0x0 0xfee20100 0x0 0x20>; + }; + + qos_gpu: qos@fee30000 { + compatible = "syscon"; + reg = <0x0 0xfee30000 0x0 0x20>; + priority-init = <0x202>; + }; + + qos_npu: qos@fee40000 { + compatible = "syscon"; + reg = <0x0 0xfee40000 0x0 0x20>; + }; + + qos_rkvdec: qos@fee50000 { + compatible = "syscon"; + reg = <0x0 0xfee50000 0x0 0x20>; + }; + + qos_vepu: qos@fee60000 { + compatible = "syscon"; + reg = <0x0 0xfee60000 0x0 0x20>; + }; + + qos_isp: qos@fee70000 { + compatible = "syscon"; + reg = <0x0 0xfee70000 0x0 0x20>; + }; + + qos_vicap: qos@fee70100 { + compatible = "syscon"; + reg = <0x0 0xfee70100 0x0 0x20>; + }; + + qos_vop: qos@fee80000 { + compatible = "syscon"; + reg = <0x0 0xfee80000 0x0 0x20>; + }; + + qos_jpeg: qos@fee90000 { + compatible = "syscon"; + reg = <0x0 0xfee90000 0x0 0x20>; + }; + + qos_rga_rd: qos@fee90100 { + compatible = "syscon"; + reg = <0x0 0xfee90100 0x0 0x20>; + }; + + qos_rga_wr: qos@fee90200 { + compatible = "syscon"; + reg = <0x0 0xfee90200 0x0 0x20>; + }; + + qos_pcie: qos@feea0000 { + compatible = "syscon"; + reg = <0x0 0xfeea0000 0x0 0x20>; + }; + + qos_usb3: qos@feea0100 { + compatible = "syscon"; + reg = <0x0 0xfeea0100 0x0 0x20>; + }; + + qos_crypto_apb: qos@feeb0000 { + compatible = "syscon"; + reg = <0x0 0xfeeb0000 0x0 0x20>; + }; + + qos_crypto: qos@feeb0100 { + compatible = "syscon"; + reg = <0x0 0xfeeb0100 0x0 0x20>; + }; + + qos_dmac: qos@feeb0200 { + compatible = "syscon"; + reg = <0x0 0xfeeb0200 0x0 0x20>; + }; + + qos_emmc: qos@feeb0300 { + compatible = "syscon"; + reg = <0x0 0xfeeb0300 0x0 0x20>; + }; + + qos_fspi: qos@feeb0400 { + compatible = "syscon"; + reg = <0x0 0xfeeb0400 0x0 0x20>; + }; + + qos_rkdma: qos@feeb0500 { + compatible = "syscon"; + reg = <0x0 0xfeeb0500 0x0 0x20>; + }; + + qos_sdmmc0: qos@feeb0600 { + compatible = "syscon"; + reg = <0x0 0xfeeb0600 0x0 0x20>; + }; + + qos_sdmmc1: qos@feeb0700 { + compatible = "syscon"; + reg = <0x0 0xfeeb0700 0x0 0x20>; + }; + + qos_usb2: qos@feeb0800 { + compatible = "syscon"; + reg = <0x0 0xfeeb0800 0x0 0x20>; + }; + + pmu_grf: syscon@ff010000 { + compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff010000 0x0 0x10000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + }; + }; + + sys_grf: syscon@ff030000 { + compatible = "rockchip,rk3562-sys-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff030000 0x0 0x10000>; + + lvds: lvds { + compatible = "rockchip,rk3562-lvds"; + phys = <&video_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_lvds>; + status = "disabled"; + }; + + lvds_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_lvds>; + status = "disabled"; + }; + }; + }; + }; + + rgb: rgb { + compatible = "rockchip,rk3562-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <&vo_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_rgb>; + status = "disabled"; + }; + + rgb_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_rgb>; + status = "disabled"; + }; + }; + }; + }; + }; + + peri_grf: syscon@ff040000 { + compatible = "rockchip,rk3562-peri-grf", "syscon"; + reg = <0x0 0xff040000 0x0 0x10000>; + }; + + ioc_grf: syscon@ff060000 { + compatible = "rockchip,rk3562-ioc-grf", "syscon"; + reg = <0x0 0xff060000 0x0 0x30000>; + }; + + usbphy_grf: syscon@ff090000 { + compatible = "rockchip,rk3562-usbphy-grf", "syscon"; + reg = <0x0 0xff090000 0x0 0x8000>; + }; + + pipephy_grf: syscon@ff098000 { + compatible = "rockchip,rk3562-pipephy-grf", "syscon"; + reg = <0x0 0xff098000 0x0 0x8000>; + }; + + cru: clock-controller@ff100000 { + compatible = "rockchip,rk3562-cru"; + reg = <0x0 0xff100000 0x0 0x40000>; + rockchip,grf = <&sys_grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>; + assigned-clock-rates = + <1188000000>, <1000000000>; + }; + + i2c0: i2c@ff200000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff200000 0x0 0x1000>; + clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@ff210000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff210000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 0>; + status = "disabled"; + }; + + spi0: spi@ff220000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff220000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>; + clock-names = "spiclk", "apb_pclk", "sclk_in"; + dmas = <&dmac 13>, <&dmac 12>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + pwm0: pwm@ff230000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@ff230010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@ff230020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@ff230030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_pins>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pmu: power-management@ff258000 { + compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff258000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3562-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_GPU */ + pd_gpu@RK3562_PD_GPU { + reg = ; + pm_qos = <&qos_gpu>; + /* Make the source clock clk_matrix_200m_src enable */ + clocks = <&cru CLK_GPU_BRG>; + }; + /* These power domains are grouped by VD_NPU */ + pd_npu@RK3562_PD_NPU { + reg = ; + pm_qos = <&qos_npu>; + }; + /* These power domains are grouped by VD_LOGIC */ + pd_vdpu@RK3562_PD_VDPU { + reg = ; + pm_qos = <&qos_rkvdec>; + }; + pd_vi@RK3562_PD_VI { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + pm_qos = <&qos_isp>, + <&qos_vicap>; + + pd_vepu@RK3562_PD_VEPU { + reg = ; + pm_qos = <&qos_vepu>; + }; + }; + pd_vo@RK3562_PD_VO { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + pm_qos = <&qos_vop>; + + pd_rga@RK3562_PD_RGA { + reg = ; + pm_qos = <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_jpeg>; + }; + }; + pd_php@RK3562_PD_PHP { + reg = ; + pm_qos = <&qos_pcie>, + <&qos_usb3>; + }; + }; + }; + + pmu_mailbox: mailbox@ff290000 { + compatible = "rockchip,rk3562-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xff290000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_PMU1_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + rknpu: npu@ff300000 { + compatible = "rockchip,rk3562-rknpu"; + reg = <0x0 0xff300000 0x0 0x10000>; + interrupts = ; + clocks = <&scmi_clk ACLK_RKNN>, <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; + clock-names = "scmi_clk", "aclk", "hclk"; + assigned-clocks = <&cru ACLK_RKNN>; + assigned-clock-rates = <600000000>; + resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3562_PD_NPU>; + operating-points-v2 = <&npu_opp_table>; + iommus = <&rknpu_mmu>; + status = "disabled"; + }; + + npu_opp_table: npu-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&npu_leakage>; + nvmem-cell-names = "leakage"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <875000 875000 1000000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <937500 937500 1000000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000 1000000 1000000>; + }; + }; + + rknpu_mmu: iommu@ff30a000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff30a000 0x0 0x40>; + interrupts = ; + interrupt-names = "rknpu_mmu"; + clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3562_PD_NPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + gpu: gpu@ff320000 { + compatible = "arm,mali-bifrost"; + reg = <0x0 0xff320000 0x0 0x4000>; + + interrupts = , + , + ; + interrupt-names = "GPU", "MMU", "JOB"; + + upthreshold = <40>; + downdifferential = <10>; + + clocks = <&scmi_clk CLK_GPU>, <&cru CLK_GPU>, + <&cru CLK_GPU_BRG>, <&cru ACLK_GPU_PRE>; + clock-names = "clk_mali", "clk_gpu", "clk_gpu_brg", "aclk_gpu"; + power-domains = <&power RK3562_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; + + status = "disabled"; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&gpu_leakage>; + nvmem-cell-names = "leakage"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <837500 837500 1000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000 900000 1000000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <975000 975000 1000000>; + }; + }; + + rkvdec: rkvdec@ff340100 { + compatible = "rockchip,rkv-decoder-rk3562", "rockchip,rkv-decoder-v2"; + reg = <0x0 0xff340100 0x0 0x400>, <0x0 0xff340000 0x0 0x100>; + reg-names = "regs", "link"; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac"; + rockchip,normal-rates = <198000000>, <0>, <396000000>; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <198000000>, <396000000>; + resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names = "video_a", "video_h", "video_hevc_cabac"; + power-domains = <&power RK3562_PD_VDPU>; + iommus = <&rkvdec_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + rockchip,task-capacity = <16>; + status = "disabled"; + }; + + rkvdec_mmu: iommu@ff340800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff340800 0x0 0x40>, <0x0 0xff340900 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "aclk", "iface", "clk_hevc_cabac"; + power-domains = <&power RK3562_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rkvenc: rkvenc@ff360000 { + compatible = "rockchip,rkv-encoder-rk3562", "rockchip,rkv-encoder-v2"; + reg = <0x0 0xff360000 0x0 0x6000>; + interrupts = ; + interrupt-names = "irq_rkvenc"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_RKVENC_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <297000000>, <0>, <297000000>; + resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, + <&cru SRST_RKVENC_CORE>; + reset-names = "video_a", "video_h", "video_core"; + assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; + assigned-clock-rates = <297000000>, <297000000>; + power-domains = <&power RK3562_PD_VEPU>; + iommus = <&rkvenc_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <1>; + rockchip,resetgroup-node = <1>; + status = "disabled"; + }; + + rkvenc_mmu: iommu@ff36f000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff36f000 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvenc_mmu"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3562_PD_VEPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi0_csi2: mipi0-csi2@ff380000 { + compatible = "rockchip,rk3562-mipi-csi2"; + reg = <0x0 0xff380000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSIHOST0>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSIHOST0>; + reset-names = "srst_csihost_p"; + status = "disabled"; + }; + + mipi1_csi2: mipi1-csi2@ff390000 { + compatible = "rockchip,rk3562-mipi-csi2"; + reg = <0x0 0xff390000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSIHOST1>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSIHOST1>; + reset-names = "srst_csihost_p"; + status = "disabled"; + }; + + mipi2_csi2: mipi2-csi2@ff3a0000 { + compatible = "rockchip,rk3562-mipi-csi2"; + reg = <0x0 0xff3a0000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSIHOST2>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSIHOST2>; + reset-names = "srst_csihost_p"; + status = "disabled"; + }; + + mipi3_csi2: mipi3-csi2@ff3b0000 { + compatible = "rockchip,rk3562-mipi-csi2"; + reg = <0x0 0xff3b0000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSIHOST3>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSIHOST3>; + reset-names = "srst_csihost_p"; + status = "disabled"; + }; + + csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 { + compatible = "rockchip,rk3562-csi2-dphy-hw"; + reg = <0x0 0xff3c0000 0x0 0x10000>; + clocks = <&cru PCLK_CSIPHY0>; + clock-names = "pclk"; + resets = <&cru SRST_P_CSIPHY0>; + reset-names = "srst_p_csiphy0"; + rockchip,grf = <&sys_grf>; + status = "disabled"; + }; + + csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 { + compatible = "rockchip,rk3562-csi2-dphy-hw"; + reg = <0x0 0xff3d0000 0x0 0x10000>; + clocks = <&cru PCLK_CSIPHY1>; + clock-names = "pclk"; + resets = <&cru SRST_P_CSIPHY1>; + reset-names = "srst_p_csiphy1"; + rockchip,grf = <&sys_grf>; + status = "disabled"; + }; + + rkcif: rkcif@ff3e0000 { + compatible = "rockchip,rk3562-cif"; + reg = <0x0 0xff3e0000 0x0 0x800>; + reg-names = "cif_regs"; + interrupts = ; + interrupt-names = "cif-intr"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>; + clock-names = "aclk_cif", "hclk_cif", "dclk_cif"; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, + <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>, + <&cru SRST_I3_VICAP>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", + "rst_cif_i0", "rst_cif_i1", "rst_cif_i2", + "rst_cif_i3"; + power-domains = <&power RK3562_PD_VI>; + rockchip,grf = <&sys_grf>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mmu: iommu@ff3e0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff3e0800 0x0 0x100>; + interrupts = ; + interrupt-names = "cif_mmu"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3562_PD_VI>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + status = "disabled"; + }; + + rkisp: isp@ff3f0000 { + compatible = "rockchip,rk3562-rkisp"; + reg = <0x0 0xff3f0000 0x0 0x7f00>; + interrupts = , + , + ; + interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp_core"; + power-domains = <&power RK3562_PD_VI>; + iommus = <&rkisp_mmu>; + status = "disabled"; + }; + + rkisp_mmu: iommu@ff3f7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff3f7f00 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + power-domains = <&power RK3562_PD_VI>; + status = "disabled"; + }; + + vop: vop@ff400000 { + compatible = "rockchip,rk3562-vop"; + reg = <0x0 0xff400000 0x0 0x2000>, <0x0 0xff405000 0x0 0x1000>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP>, + <&cru DCLK_VOP1>; + clock-names = "aclk_vop", + "hclk_vop", + "dclk_vp0", + "dclk_vp1"; + resets = <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_D_VOP>, + <&cru SRST_D_VOP1>; + reset-names = "axi", + "ahb", + "dclk_vp0", + "dclk_vp1"; + iommus = <&vop_mmu>; + power-domains = <&power RK3562_PD_VO>; + rockchip,grf = <&ioc_grf>; + assigned-clocks = <&cru DCLK_VOP>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&cru PLL_VPLL>, <&cru PLL_HPLL>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vp0_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&rgb_in_vp0>; + }; + + vp0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vp0>; + }; + + vp0_out_lvds: endpoint@2 { + reg = <2>; + remote-endpoint = <&lvds_in_vp0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vp1_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&rgb_in_vp1>; + }; + + vp1_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vp1>; + }; + + vp1_out_lvds: endpoint@2 { + reg = <2>; + remote-endpoint = <&lvds_in_vp1>; + }; + }; + }; + }; + + vop_mmu: iommu@ff407e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff407e00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "disabled"; + }; + + rga2: rga@ff440000 { + compatible = "rockchip,rga2_core0"; + reg = <0x0 0xff440000 0x0 0x1000>; + interrupts = ; + interrupt-names = "rga2_irq"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; + iommus = <&rga2_mmu>; + power-domains = <&power RK3562_PD_RGA>; + status = "disabled"; + }; + + rga2_mmu: iommu@ff440f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff440f00 0x0 0x100>; + interrupts = ; + interrupt-names = "rga2_mmu"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3562_PD_RGA>; + status = "disabled"; + }; + + jpegd: jpegd@ff450000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xff450000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,disable-auto-freq; + resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; + reset-names = "video_a", "video_h"; + power-domains = <&power RK3562_PD_RGA>; + iommus = <&jpegd_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,resetgroup-node = <2>; + status = "disabled"; + }; + + jpegd_mmu: iommu@ff450480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff450480 0x0 0x40>; + interrupts = ; + interrupt-names = "jpegd_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; + power-domains = <&power RK3562_PD_RGA>; + #iommu-cells = <0>; + status = "disabled"; + }; + + pcie2x1: pcie@ff500000 { + compatible = "rockchip,rk3562-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + max-link-speed = <2>; + num-lanes = <1>; + phys = <&combphy_pu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3562_PD_PHP>; + ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 + 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 + 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; + reg = <0x0 0xfe000000 0x0 0x400000>, + <0x0 0xff500000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + status = "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + }; + }; + + spi1: spi@ff640000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff640000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 15>, <&dmac 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + spi2: spi@ff650000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff650000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 17>, <&dmac 16>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + uart1: serial@ff670000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff670000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 10>, <&dmac 1>; /* tx:10 rx:1 */ + status = "disabled"; + }; + + uart2: serial@ff680000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff680000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 2>; /* rx:2 */ + status = "disabled"; + }; + + uart3: serial@ff690000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff690000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 3>; /* rx:3 */ + status = "disabled"; + }; + + uart4: serial@ff6a0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 4>; /* rx:4 */ + status = "disabled"; + }; + + uart5: serial@ff6b0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 11>, <&dmac 5>; /* tx:11 rx:5 */ + status = "disabled"; + }; + + uart6: serial@ff6c0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 6>; /* rx:6 */ + status = "disabled"; + }; + + uart7: serial@ff6d0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 7>; /* rx:7 */ + status = "disabled"; + }; + + uart8: serial@ff6e0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6e0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 8>; /* rx:8 */ + status = "disabled"; + }; + + uart9: serial@ff6f0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6f0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 9>; /* rx:9 */ + status = "disabled"; + }; + + pwm4: pwm@ff700000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m0_pins>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@ff700010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@ff700020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@ff700030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7m0_pins>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm8: pwm@ff710000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@ff710010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@ff710020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@ff710030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm12: pwm@ff720000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m0_pins>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm13: pwm@ff720010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m0_pins>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm14: pwm@ff720020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m0_pins>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm15: pwm@ff720030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m0_pins>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + saradc0: saradc@ff730000 { + compatible = "rockchip,rk3562-saradc"; + reg = <0x0 0xff730000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + u2phy: usb2-phy@ff740000 { + compatible = "rockchip,rk3562-usb2phy"; + reg = <0x0 0xff740000 0x0 0x10000>; + clocks = <&cru CLK_USB2PHY_REF>, <&cru PCLK_USB2PHY>; + clock-names = "phyclk", "pclk"; + #clock-cells = <0>; + clock-output-names = "usb480m_phy"; + rockchip,usbgrf = <&usbphy_grf>; + status = "disabled"; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", "linestate"; + status = "disabled"; + }; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + combphy_pu: phy@ff750000 { + compatible = "rockchip,rk3562-naneng-combphy"; + reg = <0x0 0xff750000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, + <&cru PCLK_PHP>; + clock-names = "refclk", "apbclk", "pipe_clk"; + assigned-clocks = <&cru CLK_PIPEPHY_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY>, <&cru SRST_PIPEPHY>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&peri_grf>; + rockchip,pipe-phy-grf = <&pipephy_grf>; + status = "disabled"; + }; + + sai0: sai@ff800000 { + compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; + reg = <0x0 0xff800000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 19>, <&dmac 18>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0 + &i2s0m0_sdo1 + &i2s0m0_sdo2 + &i2s0m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai1: sai@ff810000 { + compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; + reg = <0x0 0xff810000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 21>, <&dmac 20>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai2: sai@ff820000 { + compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; + reg = <0x0 0xff820000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 23>, <&dmac 22>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m0_lrck + &i2s2m0_sclk + &i2s2m0_sdi + &i2s2m0_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm: pdm@ff830000 { + compatible = "rockchip,rk3562-pdm", "rockchip,rv1126-pdm"; + reg = <0x0 0xff830000 0x0 0x1000>; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac 31>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm0_clk0 + &pdmm0_clk1 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_8ch: spdif@ff840000 { + compatible = "rockchip,rk3562-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xff840000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac 30>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_pins>; + status = "disabled"; + }; + + acdcdig_dsm: codec-digital@ff850000 { + compatible = "rockchip,rk3562-codec-digital", "rockchip,codec-digital-v1"; + reg = <0x0 0xff850000 0x0 0x1000>; + clocks = <&cru CLK_DSM>, <&cru HCLK_DSM>; + clock-names = "dac", "pclk"; + resets = <&cru SRST_DSM>; + reset-names = "reset" ; + rockchip,grf = <&sys_grf>; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&dsm_pins>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sfc: spi@ff860000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff860000 0x0 0x10000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhci: mmc@ff870000 { + compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3528-dwcmshc"; + reg = <0x0 0xff870000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdmmc0: mmc@ff880000 { + compatible = "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff880000 0x0 0x10000>; + interrupts = ; + max-frequency = <200000000>; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + fifo-depth = <0x100>; + status = "disabled"; + }; + + sdmmc1: mmc@ff890000 { + compatible = "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff890000 0x0 0x10000>; + interrupts = ; + max-frequency = <200000000>; + clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + resets = <&cru SRST_H_SDMMC1>; + reset-names = "reset"; + fifo-depth = <0x100>; + status = "disabled"; + }; + + crypto: crypto@ff8a0000 { + compatible = "rockchip,crypto-v4"; + reg = <0x0 0xff8a0000 0x0 0x2000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, + <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; + clock-names = "aclk", "hclk", "sclk", "pka"; + assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; + assigned-clock-rates = <200000000>, <300000000>; + resets = <&cru SRST_CORE_CRYPTO>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@ff8e0000 { + compatible = "rockchip,rkrng"; + reg = <0x0 0xff8e0000 0x0 0x200>; + interrupts = ; + clocks = <&cru HCLK_RK_RNG_NS>; + clock-names = "hclk_trng"; + resets = <&cru SRST_H_RK_RNG_NS>; + reset-names = "reset"; + status = "disabled"; + }; + + otp: otp@ff930000 { + compatible = "rockchip,rk3562-otp"; + reg = <0x0 0xff930000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, + <&cru PCLK_OTPC_NS>, <&cru CLK_OTPC_ARB>, + <&cru PCLK_OTPPHY>; + clock-names = "usr", "sbpi", "apb", "arb", "phy"; + resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, + <&cru SRST_P_OTPC_NS>, <&cru SRST_OTPC_ARB>, + <&cru SRST_P_OTPPHY>; + reset-names = "usr", "sbpi", "apb", "arb", "phy"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + log_leakage: log-leakage@1b { + reg = <0x1b 0x1>; + }; + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x1>; + }; + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x1>; + }; + }; + + dmac: dma-controller@ff990000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff990000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + rkdmac: dma-controller@ff9a0000 { + compatible = "rockchip,rk3562-dma", "rockchip,dma-v1"; + reg = <0x0 0xff9a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru ACLK_RKDMAC>; + clock-names = "aclk"; + #dma-cells = <1>; + dma-channels = <42>; + dma-requests = <42>; + rockchip,grf = <&peri_grf>; + }; + + hwlock: hwspinlock@ff9e0000 { + compatible = "rockchip,hwspinlock"; + reg = <0x0 0xff9e0000 0x0 0x100>; + #hwlock-cells = <1>; + status = "disabled"; + }; + + i2c1: i2c@ffa00000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa00000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ffa10000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa10000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ffa20000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa20000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffa30000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa30000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ffa40000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa40000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@ffa60000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xffa60000 0x0 0x100>; + clocks = <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + tsadc: tsadc@ffa70000 { + compatible = "rockchip,rk3562-tsadc"; + reg = <0x0 0xffa70000 0x0 0x400>; + rockchip,grf = <&sys_grf>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "tsadc_tsen", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; + assigned-clock-rates = <1200000>, <12000000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, <&cru SRST_TSADCPHY>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "disabled"; + }; + + gmac0: ethernet@ffa80000 { + compatible = "rockchip,rk3562-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xffa80000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&ioc_grf>; + clocks = <&cru CLK_GMAC_125M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>, + <&cru PCLK_GMAC>, <&cru ACLK_GMAC>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac"; + resets = <&cru SRST_A_GMAC>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + saradc1: saradc@ffaa0000 { + compatible = "rockchip,rk3562-saradc"; + reg = <0x0 0xffaa0000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC_VCCIO156>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + mailbox: mailbox@ffae0000 { + compatible = "rockchip,rk3562-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xffae0000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + dsi: dsi@ffb10000 { + compatible = "rockchip,rk3562-mipi-dsi"; + reg = <0x0 0xffb10000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSITX>; + clock-names = "pclk"; + resets = <&cru SRST_P_DSITX>; + reset-names = "apb"; + phys = <&video_phy>; + phy-names = "dphy"; + rockchip,grf = <&sys_grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dsi>; + status = "disabled"; + }; + + dsi_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dsi>; + status = "disabled"; + }; + }; + }; + }; + + video_phy: phy@ffb20000 { + compatible = "rockchip,rk3562-dsi-dphy", "rockchip,rk3562-video-phy", + "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; + reg = <0x0 0xffb20000 0x0 0x10000>, + <0x0 0xffb10000 0x0 0x10000>; + reg-names = "phy", "host"; + clocks = <&cru CLK_MIPIDSIPHY_REF>, + <&cru PCLK_DSIPHY>, <&cru PCLK_DSITX>; + clock-names = "ref", "pclk", "pclk_host"; + #clock-cells = <0>; + resets = <&cru SRST_P_DSIPHY>; + reset-names = "apb"; + #phy-cells = <0>; + status = "disabled"; + }; + + gmac1: ethernet@ffb30000 { + compatible = "rockchip,rk3562-gmac"; + reg = <0x0 0xffb30000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&ioc_grf>; + clocks = <&cru CLK_MAC100_50M_MATRIX>, <&cru CLK_MAC100_50M_MATRIX>, + <&cru PCLK_MAC100>, <&cru ACLK_MAC100>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac"; + resets = <&cru SRST_A_MAC100>; + reset-names = "stmmaceth"; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3562-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff260000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff620000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff630000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffac0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffac0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffad0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffad0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3562-pinctrl.dtsi" From 2df94e825936b2fd9fa9f326996a2f814278d29f Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 27 Oct 2022 09:24:44 +0800 Subject: [PATCH 013/258] arm64: dts: rockchip: Add RK3562 evaluation board devicetree evb1: LPDDR4/LPDDR4X + RK817 + ECM MIC evb2: DDR4 + RK809 + RTC IC with external BAT + SPI Flash + MEMS MIC The rk3562-evb1 and rk3562-evb2 force the maximum-speed of usb dwc3 controller to high-speed, it needs the following two properties to fix usb compatibility issues. 1. Set "snps,dis_u2_susphy_quirk" to disable dwc3 controller suspend phy automatically. And the usb phy driver can manage phy suspend/normal mode by itself. 2. Set "snps,usb2-lpm-disable" to disable usb2 lpm for dwc3 xhci controller. It can fix some usb disks with lpm broken issue. Signed-off-by: Finley Xiao Signed-off-by: Li Huang Signed-off-by: shengfei Xu Signed-off-by: Guochun Huang Signed-off-by: Chandler Chen Signed-off-by: Frank Wang Signed-off-by: William Wu Signed-off-by: Yifeng Zhao Signed-off-by: Lin Jinhan Signed-off-by: Jake Wu Signed-off-by: Yu Qiaowei Signed-off-by: Damon Ding Signed-off-by: Sandy Huang Signed-off-by: Elaine Zhang Signed-off-by: Binyuan Lan Signed-off-by: Jason Zhu Signed-off-by: Alex Zhao Signed-off-by: Huibin Hong Signed-off-by: Jon Lin Signed-off-by: David Wu Signed-off-by: Shawn Lin Signed-off-by: Sugar Zhang Signed-off-by: Felix Zeng Signed-off-by: Wangqiang Guo Change-Id: I066b6daa6d0f36ff0b28564f07f4d371c2796fd6 --- arch/arm64/boot/dts/rockchip/Makefile | 4 + .../boot/dts/rockchip/rk3562-android.dtsi | 100 +++ arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi | 583 ++++++++++++++++++ .../rockchip/rk3562-evb1-lp4x-v10-linux.dts | 9 + .../dts/rockchip/rk3562-evb1-lp4x-v10.dts | 9 + .../dts/rockchip/rk3562-evb1-lp4x-v10.dtsi | 460 ++++++++++++++ .../rockchip/rk3562-evb2-ddr4-v10-linux.dts | 9 + .../dts/rockchip/rk3562-evb2-ddr4-v10.dts | 9 + .../dts/rockchip/rk3562-evb2-ddr4-v10.dtsi | 411 ++++++++++++ .../arm64/boot/dts/rockchip/rk3562-linux.dtsi | 89 +++ .../arm64/boot/dts/rockchip/rk3562-rk809.dtsi | 269 ++++++++ .../arm64/boot/dts/rockchip/rk3562-rk817.dtsi | 257 ++++++++ 12 files changed, 2209 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-android.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-linux.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 2c47b49f1cab..7efb6619b0d6 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -73,6 +73,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb2-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb3-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-iotest-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-android.dtsi new file mode 100644 index 000000000000..cf0728c8fbb7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-android.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_dsi>; + }; + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_lvds>; + }; + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_rgb>; + }; + }; +}; + +&vop { + support-multi-area; +}; + +&rng { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi new file mode 100644 index 000000000000..778f22fe87b1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc0 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <414000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <800000>; + }; + + back-key { + linux,code = ; + label = "back"; + press-threshold-microvolt = <1200000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + pdm_codec: dummy-codec { + status = "okay"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdm_codec>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rk-spdif-sound"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&i2c2 { + status = "okay"; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + /* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm5 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&saradc0 { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux.dts new file mode 100644 index 000000000000..a2ac8538e783 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-linux.dtsi" +#include "rk3562-rk817.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dts new file mode 100644 index 000000000000..296cee08bfc9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi new file mode 100644 index 000000000000..b2eb35ad17c8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "dt-bindings/usb/pd.h" +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include +#include + +/ { + model = "Rockchip RK3562 EVB1 LP4X V10 Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + rk817_sound: rk817-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&dcdc_boost>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vbat_3v8: vbat-3v8 { + compatible = "regulator-fixed"; + regulator-name = "vbat_3v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <3300000 0x0 + 3300000 0x1>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm7 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x42>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_rgmii_clk + &rgmiim0_rgmii_bus + ðm0_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&otg_switch>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + }; + }; +}; + +&i2c5 { + status = "okay"; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio0 RK_PA7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <3>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <3>; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&dsi { + status = "okay"; +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&dsi_in_vp1 { + status = "disabled"; +}; + +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; + +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0>; +}; + +&sdmmc0 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; + phy-supply = <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + + dr_mode = "otg"; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-linux.dts new file mode 100644 index 000000000000..fe9c20f71ee9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-linux.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-linux.dtsi" +#include "rk3562-rk809.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts new file mode 100644 index 000000000000..8d26ce9c67c6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi new file mode 100644 index 000000000000..bb29df29d92d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include +#include + +/ { + model = "Rockchip RK3562 EVB2 DDR4 V10 Board"; + compatible = "rockchip,rk3562-evb2-ddr4-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + }; + + vcc3v3_clk: vcc3v3-clk { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc25_ddr: vcc25-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc25_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&dsi { + status = "okay"; +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&dsi_in_vp1 { + status = "disabled"; +}; + +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x42>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_rgmii_clk + &rgmiim0_rgmii_bus + ðm0_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c5 { + status = "okay"; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio1 RK_PC7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <3>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <3>; + }; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm6 { + status = "okay"; +}; + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0>; +}; + +&sdmmc0 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&spdif_8ch { + pinctrl-0 = <&spdifm0_pins>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; + phy-supply = <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&vcc5v0_usb_otg>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi new file mode 100644 index 000000000000..a8ead0c9270c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_dsi>; + }; + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_lvds>; + }; + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_rgb>; + }; + }; +}; + +&rng { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi new file mode 100644 index 000000000000..13f19d71171c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru MCLK_SAI0_OUT2IO>; + clock-names = "mclk"; + assigned-clocks = <&cru MCLK_SAI0_OUT2IO>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi new file mode 100644 index 000000000000..a89d9ca2d593 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru MCLK_SAI0_OUT2IO>; + clock-names = "mclk"; + assigned-clocks = <&cru MCLK_SAI0_OUT2IO>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; From 4aa12ffbf8bec40d082054ddb630187f89faacf6 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 2 Nov 2022 16:15:24 +0800 Subject: [PATCH 014/258] arm64: dts: rockchip: Add RK3562 iotest board devicetree Signed-off-by: Finley Xiao Signed-off-by: shengfei Xu Signed-off-by: Jake Wu Change-Id: I1de47c3fc46e1e95c9ad77efa2b697edffdd5c6d --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3562-iotest-lp3-v10.dts | 82 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 7efb6619b0d6..f5e86742752e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts new file mode 100644 index 000000000000..528741967486 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-android.dtsi" + +/ { + model = "Rockchip RK3562 IOTEST LP3 V10 Board"; + compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; +}; + +#include "rk3562-rk809.dtsi" + +&combphy_pu { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; From 1a5b510ed765b750f67a4d0ea8c994f0fc02d390 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Wed, 9 Nov 2022 14:26:26 +0800 Subject: [PATCH 015/258] arm64: dts: rockchip: Add RK3562 EVB1 LP4X V10 LVDS Board Signed-off-by: Zhang Yubing Change-Id: I08e08546dec92b62a15b4e4cd3434a00df72eb6f --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3562-evb1-lp4x-v10-lvds.dts | 120 ++++++++++++++++++ 2 files changed, 121 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-lvds.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f5e86742752e..6e597457138a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-iotest-lp3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-lvds.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-lvds.dts new file mode 100644 index 000000000000..4a6ba3d1dacf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-lvds.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + + +/ { + panel-lvds { + compatible = "simple-panel"; + status = "okay"; + backlight = <&backlight>; + reset-delay-ms = <20>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <164>; + height-mm = <100>; + + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + }; + +}; + +&backlight { + pwms = <&pwm5 0 25000 0>; + status = "okay"; +}; + +&dsi { + status = "disabled"; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp0 { + status = "okay"; +}; + +&lvds_in_vp1 { + status = "disabled"; +}; + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm5 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + status = "okay"; +}; + +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; From ed8b64e07c95391d792c1904d1da7c543ec13608 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 30 Dec 2022 10:39:01 +0800 Subject: [PATCH 016/258] arm64: dts: rockchip: Add RK3562 test1 and test2 board devicetree Signed-off-by: Finley Xiao Signed-off-by: Frank Wang Signed-off-by: David Wu Signed-off-by: Shawn Lin Signed-off-by: shengfei Xu Change-Id: I1884bb4385a739b212f924f9996fe250ca0e8ffd --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../dts/rockchip/rk3562-test1-ddr3-v10.dts | 9 + .../dts/rockchip/rk3562-test1-ddr3-v10.dtsi | 209 ++++++++++++++++++ .../dts/rockchip/rk3562-test2-ddr4-v10.dts | 9 + .../dts/rockchip/rk3562-test2-ddr4-v10.dtsi | 91 ++++++++ 5 files changed, 320 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 6e597457138a..9f163afcdefd 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -79,6 +79,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts new file mode 100644 index 000000000000..e8b79e3ff265 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-test1-ddr3-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi new file mode 100644 index 000000000000..23601ec2e332 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include + +/ { + model = "Rockchip RK3562 TEST1 DDR3 V10 Board"; + compatible = "rockchip,rk3562-test1-ddr3-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc25_ddr: vcc25-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc25_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x3f>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim + &rgmiim1_tx_bus2 + &rgmiim1_rx_bus2 + &rgmiim1_rgmii_clk + &rgmiim1_rgmii_bus + ðm1_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; + +&pinctrl { + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd &sdmmc1_det>; + /* Should disable gmac0 and fix hardware if enabling sdmmc1 */ + status = "disabled"; +}; + +&pwm6 { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; + phy-supply = <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&vcc5v0_usb_otg>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts new file mode 100644 index 000000000000..811628398e79 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-test2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi new file mode 100644 index 000000000000..312abc96ca57 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include + +/ { + model = "Rockchip RK3562 TEST2 DDR4 V10 Board"; + compatible = "rockchip,rk3562-test2-ddr4-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_clk>; + + phy-handle = <&rmii_phy>; + status = "okay"; +}; + +&mdio0 { + rmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pwm6 { + status = "okay"; +}; From 6125424e878bfb15fd73028f4a9473bef2507fcf Mon Sep 17 00:00:00 2001 From: Binyuan Lan Date: Sat, 24 Dec 2022 15:30:59 +0000 Subject: [PATCH 017/258] arm64: dts: rockchip: add rk3562-rk817-tablet-v10 board devicetree Change-Id: If251014d87c787978da5541b85e0121b89555296 Signed-off-by: Binyuan Lan Signed-off-by: Guochun Huang --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3562-rk817-tablet-v10.dts | 1050 +++++++++++++++++ 2 files changed, 1051 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 9f163afcdefd..bf7425e643fb 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-rk817-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts new file mode 100644 index 000000000000..4702884fc428 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts @@ -0,0 +1,1050 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3562.dtsi" +#include "rk3562-android.dtsi" + +/ { + model = "Rockchip RK3562 RK817 TABLET LP4 Board"; + compatible = "rockchip,rk3562-rk817-tablet", "rockchip,rk3562"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc0 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 50 51 52 53 54 + 55 55 56 57 58 59 60 61 + 62 63 64 64 65 65 66 67 + 68 69 70 71 71 72 73 74 + 75 76 77 78 79 79 80 81 + 82 83 84 85 86 86 87 88 + 89 90 91 92 93 94 94 95 + 96 97 98 99 100 101 101 102 + 103 104 105 106 107 107 108 109 + 110 111 112 113 114 115 115 116 + 117 118 119 120 121 122 123 123 + 124 125 126 127 128 129 130 130 + 131 132 133 134 135 136 136 137 + 138 139 140 141 142 143 143 144 + 145 146 147 147 148 149 150 151 + 152 153 154 155 156 156 157 158 + 159 157 158 159 160 161 162 162 + 163 164 165 166 167 168 169 169 + 170 171 172 173 174 175 175 176 + 177 178 179 180 181 182 182 183 + 184 185 186 187 188 189 190 190 + 191 192 193 194 195 196 197 197 + 198 199 200 201 202 203 204 204 + 205 206 207 208 209 209 210 211 + 212 213 213 214 214 215 215 216 + 216 217 217 218 218 219 219 220 + >; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + status = "okay"; + }; + + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc0 4>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <3300000 0x0 + 3300000 0x1>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm7 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + WIFI,vbat_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi"; + reg = <0>; + + backlight = <&backlight>; + //power-supply=<&vcc_3v3>; + enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>; + + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <135>; + height-mm = <216>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 15 00 02 E0 00 + //--- PASSWORD ----// + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 80 03 + //--- Page1 ----// + 15 00 02 E0 01 + //Set VCOM + 15 00 02 00 00 + 15 00 02 01 3B + //Set VCOM_Reverse + //15 00 02 03 00 + //15 00 02 04 A0 + 15 00 02 0C 74 + //Set Gamma Power, VGMP,VGMN,VGSP,VGSN + 15 00 02 17 00 + 15 00 02 18 AF //VGMP=4.8V + 15 00 02 19 00 //VGSP=0.3V + 15 00 02 1A 00 + 15 00 02 1B AF + 15 00 02 1C 00 + //SETPANEL + 15 00 02 35 26 //ASP=0110 + //SETPANEL + 15 00 02 37 09 //SS=1,BGR=1 + //SET RGBCYC + 15 00 02 38 04 //JDT=100 column inversion + 15 00 02 39 00 //RGB_N_EQ1, 0x12 + 15 00 02 3A 01 //RGB_N_EQ2, 0x18 + 15 00 02 3C 78 //SET EQ3 for TE_H + 15 00 02 3D FF //SET CHGEN_ON, + 15 00 02 3E FF //SET CHGEN_OFF, + 15 00 02 3F 7F //SET CHGEN_OFF2, + //Set TCON + 15 00 02 40 06 //RSO=800 RGB + 15 00 02 41 A0 //LN=640->1280 line + 15 00 02 42 81 //SLT + 15 00 02 43 14 //VFP=20 + 15 00 02 44 23 //VBP=24 + 15 00 02 45 28 //HBP=40 + //--- power voltage ----// + 15 00 02 55 02 //DCDCM=0001, JD PWR_IC + 15 00 02 57 69 + 15 00 02 59 0A //VCL = -2.9V + 15 00 02 5A 2A //VGH = 15V + 15 00 02 5B 17 //VGL = -11V + //--- Gamma ----// + 15 00 02 5D 7F + 15 00 02 5E 6B + 15 00 02 5F 5C + 15 00 02 60 4F + 15 00 02 61 4D + 15 00 02 62 3F + 15 00 02 63 42 + 15 00 02 64 2B + 15 00 02 65 44 + 15 00 02 66 43 + 15 00 02 67 43 + 15 00 02 68 63 + 15 00 02 69 52 + 15 00 02 6A 5A + 15 00 02 6B 4F + 15 00 02 6C 4E + 15 00 02 6D 20 + 15 00 02 6E 0F + 15 00 02 6F 00 + 15 00 02 70 7F + 15 00 02 71 6B + 15 00 02 72 5C + 15 00 02 73 4F + 15 00 02 74 4D + 15 00 02 75 3F + 15 00 02 76 42 + 15 00 02 77 2B + 15 00 02 78 44 + 15 00 02 79 43 + 15 00 02 7A 43 + 15 00 02 7B 63 + 15 00 02 7C 52 + 15 00 02 7D 5A + 15 00 02 7E 4F + 15 00 02 7F 4E + 15 00 02 80 20 + 15 00 02 81 0F + 15 00 02 82 00 + //Page2, for GIP + 15 00 02 E0 02 + //GIP_L Pin mapping + 15 00 02 00 02 //STV3 -> STV2 + 15 00 02 01 02 //Stv3 -> STV2 + 15 00 02 02 00 //STV4 -> STV0 + 15 00 02 03 00 //STV4 -> STV0 + 15 00 02 04 1E //VDS -> VGH + 15 00 02 05 1E //VDS -> VGH + 15 00 02 06 1F //VSD -> VGL + 15 00 02 07 1F //VSD -> VGL + 15 00 02 08 1F + 15 00 02 09 17 //VDD2 -> FLM + 15 00 02 0A 17 //VDD2 -> FLM + 15 00 02 0B 37 //VDD1 -> INV_FLM + 15 00 02 0C 37 //VDD1 -> INV_FLM + 15 00 02 0D 47 //CLK8 -> CLK3 + 15 00 02 0E 47 //CLK8 -> CLK3 + 15 00 02 0F 45 //CLK6 -> CLK1 + 15 00 02 10 45 //CLK6 -> CLK1 + 15 00 02 11 4B //CLK4 -> CLK7 + 15 00 02 12 4B //CLK4 -> CLK7 + 15 00 02 13 49 //CLK2 -> CLK5 + 15 00 02 14 49 //CLK2 -> CLK5 + 15 00 02 15 1F //VGL + //GIP_R Pin mapping + 15 00 02 16 01 //STV1 -> STV1 + 15 00 02 17 01 //STV1 -> STV1 + 15 00 02 18 00 //STV2 -> STV0 + 15 00 02 19 00 //STV2 -> STV0 + 15 00 02 1A 1E //VDS -> VGH + 15 00 02 1B 1E //VDS -> VGH + 15 00 02 1C 1F //VSD -> VGL + 15 00 02 1D 1F //VSD -> VGL + 15 00 02 1E 1F + 15 00 02 1F 17 //VDD2 -> FLM + 15 00 02 20 17 //VDD2 -> FLM + 15 00 02 21 37 //VDD1 -> INV_FLM + 15 00 02 22 37 //VDD1 -> INV_FLM + 15 00 02 23 46 //CLK7 -> CLK2 + 15 00 02 24 46 //CLK7 -> CLK2 + 15 00 02 25 44 //CLK5 -> CLK0 + 15 00 02 26 44 //CLK5 -> CLK0 + 15 00 02 27 4A //CLK3 -> CLK6 + 15 00 02 28 4A //CLK3 -> CLK6 + 15 00 02 29 48 //CLK1 -> CLK4 + 15 00 02 2A 48 //CLK1 -> CLK4 + 15 00 02 2B 1F //VGL + //GIP_L_GS Pin mapping + 15 00 02 2C 01 //STV3 -> STV1 + 15 00 02 2D 01 + 15 00 02 2E 00 //STV4 -> STV0 + 15 00 02 2F 00 + 15 00 02 30 1F //VDS -> VGL + 15 00 02 31 1F + 15 00 02 32 1E //VSD -> VGH + 15 00 02 33 1E + 15 00 02 34 1F // + 15 00 02 35 17 //VDD2 -> FLM + 15 00 02 36 17 + 15 00 02 37 37 //VDD1 -> INV_FLM + 15 00 02 38 37 + 15 00 02 39 08 //CLK8 -> CLK4 + 15 00 02 3A 08 + 15 00 02 3B 0A //CLK6 -> CLK6 + 15 00 02 3C 0A + 15 00 02 3D 04 //CLK4 -> CLK0 + 15 00 02 3E 04 + 15 00 02 3F 06 //CLK2 -> CLK2 + 15 00 02 40 06 + 15 00 02 41 1F //VGL + //GIP_R_GS Pin mapping + 15 00 02 42 02 //STV1 -> STV2 + 15 00 02 43 02 + 15 00 02 44 00 //STV2 -> STV0 + 15 00 02 45 00 + 15 00 02 46 1F //VDS -> VGL + 15 00 02 47 1F + 15 00 02 48 1E //VSD -> VGH + 15 00 02 49 1E + 15 00 02 4A 1F // + 15 00 02 4B 17 //VDD2 -> FLM + 15 00 02 4C 17 + 15 00 02 4D 37 //VDD1 -> INV_FLM + 15 00 02 4E 37 + 15 00 02 4F 09 //CLK7 -> CLK5 + 15 00 02 50 09 + 15 00 02 51 0B //CLK5 -> CLK7 + 15 00 02 52 0B + 15 00 02 53 05 //CLK3 -> CLK1 + 15 00 02 54 05 + 15 00 02 55 07 //CLK1 -> CLK3 + 15 00 02 56 07 + 15 00 02 57 1F //VGL + //GIP Timing + 15 00 02 58 40 + 15 00 02 5B 30 //STV_NUM,STV_S0 + 15 00 02 5C 16 //STV_S0 + 15 00 02 5D 34 //STV_W / S1 + 15 00 02 5E 05 //STV_S2 + 15 00 02 5F 02 //STV_S3 + 15 00 02 63 00 //SETV_ON + 15 00 02 64 6A //SETV_OFF + 15 00 02 67 73 + 15 00 02 68 1D //CKV_S0 + 15 00 02 69 08 + 15 00 02 6A 6A + 15 00 02 6B 08 //Dummy clk + 15 00 02 6C 00 + 15 00 02 6D 00 + 15 00 02 6E 00 + 15 00 02 6F 88 + 15 00 02 75 FF + 15 00 02 77 DD //VEN_EN=1 + 15 00 02 78 3F + 15 00 02 79 15 //0x0C + 15 00 02 7A 17 //VEN_S0 + 15 00 02 7D 14 //VEN_ON + 15 00 02 7E 82 //VEN_OFF + //Page4 + 15 00 02 E0 04 + 15 00 02 00 0E + 15 00 02 02 B3 + 15 00 02 09 61 + 15 00 02 0E 48 + //Page0 + 15 00 02 E0 00 + 15 00 02 E6 02 + 15 00 02 E7 0C + 05 78 01 11 + 05 64 01 29 + ]; + + panel-exit-sequence = [ + 05 01 01 28 + 05 03 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <70000000>; + hactive = <800>; + vactive = <1280>; + + hfront-porch = <40>; + hsync-len = <20>; + hback-porch = <20>; + + vfront-porch = <20>; + vsync-len = <4>; + vback-porch = <20>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&dsi_in_vp1 { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v2_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc1v2_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3671 3686 3712 3738 3756 3773 + 3787 3802 3819 3840 3868 3916 3959 + 3998 4041 4087 4138 4191 4247 4313>; + design_capacity = <5780>; + design_qmax = <6358>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3950>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4350>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + gate_function_disable = <1>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru MCLK_SAI0_OUT2IO>; + clock-names = "mclk"; + assigned-clocks = <&cru MCLK_SAI0_OUT2IO>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + hp-volume = <20>; + spk-volume = <25>; + use-ext-amplifier; + spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + + ts@40 { + compatible = "GSL,GSL3673_800X1280"; + reg = <0x40>; + irq_gpio_number = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + rst_gpio_number = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_gpio>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio0 RK_PA7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; +}; + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0>; +}; + +&video_phy { + status = "okay"; +}; + +&pinctrl { + tp { + tp_gpio: tp-gpio { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>, + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_enable_gpio: lcd-enable-gpio { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&saradc0 { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <200000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&otg_switch>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + + dr_mode = "otg"; + extcon = <&u2phy>; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; From 4663ac10bca93cb40535362483c81f264be8d475 Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Thu, 12 Jan 2023 18:01:05 +0800 Subject: [PATCH 018/258] arm64: dts: rockchip: Add RK3562 linux amp dts Signed-off-by: Steven Liu Change-Id: I896bb705fbabfe032879bd03d21964f220141e76 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi | 33 +++++++++++++++++++ .../rk3562-evb1-lp4x-v10-linux-amp.dts | 10 ++++++ 3 files changed, 44 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index bf7425e643fb..5ceabe5c4144 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-iotest-lp3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux-amp.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi new file mode 100644 index 000000000000..80e194e2bcec --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/ { + rockchip_amp: rockchip-amp { + compatible = "rockchip,mcu-amp"; + clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>, + <&cru SCLK_UART5>, <&cru PCLK_UART5>, + <&cru PCLK_TIMER>, <&cru CLK_TIMER5>; + clock-names = "fclk_bus_cm0_core", "clk_bus_cm0_rtc", + "baudclk", "apb_pclk", "pclk", "timer"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* mcu address */ + mcu_reserved: mcu@8200000 { + reg = <0x0 0x8200000 0x0 0x100000>; + no-map; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts new file mode 100644 index 000000000000..0dd16a1d8c7b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-linux.dtsi" +#include "rk3562-rk817.dtsi" +#include "rk3562-amp.dtsi" From 21c141e2dc2a0bc7fab0a90a960d8c4135ab41a0 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 10 Jan 2023 20:41:41 +0800 Subject: [PATCH 019/258] arm64: dts: rockchip: rk3562-evb: add sii902x bt1120/bt656 to hdmi board vp0->mipi dsi vp1->bt1120/bt656->hdmi Signed-off-by: Damon Ding Signed-off-by: Sandy Huang Change-Id: Id0c7be8a3532d116997219461fd7722e2aae740a --- arch/arm64/boot/dts/rockchip/Makefile | 1 + ...2-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts | 112 ++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 5ceabe5c4144..3847116b4d09 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux-amp.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-rk817-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts new file mode 100644 index 000000000000..345b63bc52ce --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" + +/ { + model = "Rockchip RK3562 EVB2 DDR4 V10 Board + RK EVB BT1120 TO HDMI V10 Ext Board"; + compatible = "rockchip,rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3562"; +}; + +&dsi { + status = "okay"; +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&dsi_in_vp1 { + status = "disabled"; +}; + +/* + * The pins of gamc0 and bt1120 are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c1m1_xfer>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi_int>; + interrupt-parent = <&gpio4>; + interrupts = ; + reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + /* + * MEDIA_BUS_FMT_YUYV8_1X16 for bt1120 + * MEDIA_BUS_FMT_UYVY8_2X8 for bt656 + */ + bus-format = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +&pinctrl { + sii902x { + sii902x_hdmi_int: sii902x-hdmi-int { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + /* + * <&bt1120_pins> for bt1120 + * <&bt656_pins> for bt656 + */ + pinctrl-0 = <&bt1120_pins>; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "disabled"; +}; + +&rgb_in_vp1 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; From 2b098cb6c80b588c826730780387df9ffd3e78fc Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Sun, 29 Jan 2023 18:08:20 +0800 Subject: [PATCH 020/258] arm64: dts: rockchip: rk3562-evb: Add spdif and pdm support Signed-off-by: Jason Zhu Change-Id: Ibff940d2007fe5c6316879fa38819d598e674325 --- arch/arm64/boot/dts/rockchip/Makefile | 2 ++ .../rockchip/rk3562-evb1-lp4x-v10-spdif.dts | 17 ++++++++++++++ .../rk3562-evb2-ddr4-v10-pdm-mic-array.dts | 22 +++++++++++++++++++ 3 files changed, 41 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-spdif.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-pdm-mic-array.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 3847116b4d09..50b429240eb4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -77,8 +77,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux-amp.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-pdm-mic-array.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-rk817-tablet-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-spdif.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-spdif.dts new file mode 100644 index 000000000000..58ab5ac649e0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-spdif.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb1-lp4x-v10.dts" + +&spdif_8ch { + /* The pin is conflict with sdmmc0 cmd */ + pinctrl-0 = <&spdifm2_pins>; + status = "okay"; +}; + +&sdmmc0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-pdm-mic-array.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-pdm-mic-array.dts new file mode 100644 index 000000000000..b10f50b3b72c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-pdm-mic-array.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dts" + +&pdm { + /* The pin pdmm0_clk1 is conflict with i2s0_mclk which used by rk809_codec */ + pinctrl-0 = <&pdmm0_clk0 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + status = "okay"; +}; + +&pdm_mic_array { + status = "okay"; +}; + From 86921d7d8362f002bd3c3c0fef56bff889a9a550 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 27 Oct 2022 16:43:01 +0800 Subject: [PATCH 021/258] nvmem: rockchip-otp: Add support for rk3562 This adds the necessary data for handling otp on the rk3562. Signed-off-by: Finley Xiao Change-Id: I5083f7881146b18532bcee170ef78274b31ee4be --- drivers/nvmem/rockchip-otp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 68542607d962..09570fa94542 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -772,6 +772,17 @@ static const struct rockchip_data rk3528_data = { .reg_read = rk3568_otp_read, }; +static const char * const rk3562_otp_clocks[] = { + "usr", "sbpi", "apb", "arb", "phy", +}; + +static const struct rockchip_data rk3562_data = { + .size = 0x80, + .clocks = rk3562_otp_clocks, + .num_clks = ARRAY_SIZE(rk3562_otp_clocks), + .reg_read = rk3568_otp_read, +}; + static const char * const rk3568_otp_clocks[] = { "usr", "sbpi", "apb", "phy", }; @@ -845,6 +856,12 @@ static const struct of_device_id rockchip_otp_match[] = { .data = (void *)&rk3528_data, }, #endif +#ifdef CONFIG_CPU_RK3562 + { + .compatible = "rockchip,rk3562-otp", + .data = (void *)&rk3562_data, + }, +#endif #ifdef CONFIG_CPU_RK3568 { .compatible = "rockchip,rk3568-otp", From dfdb9d1b2f5efeda127d6256108de3a3ae78b8da Mon Sep 17 00:00:00 2001 From: Shaohan Yao Date: Fri, 28 Oct 2022 15:06:35 +0800 Subject: [PATCH 022/258] thermal: rockchip: Support the rk3562 SoC in thermal driver There are one Temperature Sensor on rk3562, channel 0 is for chip. Signed-off-by: Shaohan Yao Change-Id: Ided46b86470bb9cd506206bb4880ca024c0ec5cf --- drivers/thermal/rockchip_thermal.c | 105 +++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index afc3f233a888..06157da8886d 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -269,7 +269,10 @@ struct rockchip_thermal_data { #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ #define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */ #define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ +#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */ +#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ +#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */ #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ @@ -289,6 +292,8 @@ struct rockchip_thermal_data { #define RK3528_GRF_TSADC_CON 0x40030 +#define RK3562_GRF_TSADC_CON 0x0580 + #define RK3568_GRF_TSADC_CON 0x0600 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) @@ -655,6 +660,45 @@ static const struct tsadc_table rk3528_code_table[] = { {TSADCV5_DATA_MASK, 125000}, }; +static const struct tsadc_table rk3562_code_table[] = { + {0, -40000}, + {1419, -40000}, + {1428, -35000}, + {1436, -30000}, + {1445, -25000}, + {1453, -20000}, + {1462, -15000}, + {1470, -10000}, + {1479, -5000}, + {1487, 0}, + {1496, 5000}, + {1504, 10000}, + {1512, 15000}, + {1521, 20000}, + {1529, 25000}, + {1538, 30000}, + {1546, 35000}, + {1555, 40000}, + {1563, 45000}, + {1572, 50000}, + {1580, 55000}, + {1589, 60000}, + {1598, 65000}, + {1606, 70000}, + {1615, 75000}, + {1623, 80000}, + {1632, 85000}, + {1640, 90000}, + {1648, 95000}, + {1657, 100000}, + {1666, 105000}, + {1674, 110000}, + {1682, 115000}, + {1691, 120000}, + {1699, 125000}, + {TSADCV2_DATA_MASK, 125000}, +}; + static const struct tsadc_table rk3568_code_table[] = { {0, -40000}, {1584, -40000}, @@ -1107,6 +1151,37 @@ static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs, } } +static void rk_tsadcv12_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + writel_relaxed(TSADCV12_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); + writel_relaxed(TSADCV12_AUTO_PERIOD_HT_TIME, + regs + TSADCV3_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); + writel_relaxed(TSADCV12_Q_MAX_VAL, regs + TSADCV9_Q_MAX); + writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, + regs + TSADCV2_AUTO_CON); + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + + if (!IS_ERR(grf)) { + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); + udelay(15); + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); + usleep_range(100, 200); + } +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -1767,6 +1842,30 @@ static const struct rockchip_tsadc_chip rk3528_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3562_tsadc_data = { + .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + .chn_num = 1, /* one channels for tsadc */ + + .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + + .initialize = rk_tsadcv12_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv4_tshut_mode, + + .table = { + .id = rk3562_code_table, + .length = ARRAY_SIZE(rk3562_code_table), + .data_mask = TSADCV2_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct rockchip_tsadc_chip rk3568_tsadc_data = { .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ @@ -1899,6 +1998,12 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .data = (void *)&rk3528_tsadc_data, }, #endif +#ifdef CONFIG_CPU_RK3562 + { + .compatible = "rockchip,rk3562-tsadc", + .data = (void *)&rk3562_tsadc_data, + }, +#endif #ifdef CONFIG_CPU_RK3568 { .compatible = "rockchip,rk3568-tsadc", From 989ea6103a04961592b68d7e66284fa0e6ba7644 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Mon, 10 Oct 2022 07:41:49 +0000 Subject: [PATCH 023/258] drm/rockchip: dsi: Add support for rk3562 Signed-off-by: Guochun Huang Change-Id: I7ab1d79d069be85bb34060dd4cfc60464b7ded55 --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 9528d51fa6d5..4c0a795d5e22 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -179,6 +179,11 @@ #define RK3399_TXRX_ENABLECLK BIT(6) #define RK3399_TXRX_BASEDIR BIT(5) +#define RK3562_SYS_GRF_VO_CON1 0x05d0 +#define RK3562_DSI_FORCETXSTOPMODE (0xf << 4) +#define RK3562_DSI_TURNDISABLE (0x1 << 2) +#define RK3562_DSI_FORCERXMODE (0x1 << 0) + #define RK3568_GRF_VO_CON2 0x0368 #define RK3568_GRF_VO_CON3 0x036c #define RK3568_DSI_FORCETXSTOPMODE (0xf << 4) @@ -221,6 +226,7 @@ enum soc_type { RK3128, RK3288, RK3399, + RK3562, RK3568, RV1126, }; @@ -1378,6 +1384,22 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3562_chip_data[] = { + { + .reg = 0xffb10000, + + .lanecfg1_grf_reg = RK3562_SYS_GRF_VO_CON1, + .lanecfg1 = HIWORD_UPDATE(0, RK3562_DSI_TURNDISABLE | + RK3562_DSI_FORCERXMODE | + RK3562_DSI_FORCETXSTOPMODE), + + .max_data_lanes = 4, + .max_bit_rate_per_lane = 1200000000UL, + .soc_type = RK3562, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { .reg = 0xfe060000, @@ -1437,6 +1459,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { }, { .compatible = "rockchip,rk3399-mipi-dsi", .data = &rk3399_chip_data, + }, { + .compatible = "rockchip,rk3562-mipi-dsi", + .data = &rk3562_chip_data, }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = &rk3568_chip_data, From 36e5e07f5c19a29d2c95a53f4b287246bf3e5219 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Thu, 20 Oct 2022 11:33:12 +0800 Subject: [PATCH 024/258] drm/rockchip: vop3: add support rk3562 Signed-off-by: Sandy Huang Change-Id: I3e7b430331640590591b7828672c756cee5fca92 --- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 358 +++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 6 + 3 files changed, 365 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 4292cb36a186..0d268f079edb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -27,6 +27,7 @@ #define VOP2_BUILD(version) ((version) & 0xffff) #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263) +#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350) #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023) #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index e8d93ef7beec..2f09c2728933 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -959,6 +959,168 @@ static const struct vop2_video_port_data rk3528_vop_video_ports[] = { }, }; +static const struct vop2_video_port_regs rk3562_vop_vp0_regs = { + .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0), + .overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0), + .dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0), + .out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0), + .core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4), + .p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5), + .dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6), + .dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7), + .dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8), + .post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15), + .pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16), + .dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17), + .dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18), + .dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20), + .gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22), + .dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28), + .standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), + .bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xffff, 0), + .bg_dly = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xff, 24), + .pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0), + .hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0), + .vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0), + .post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), + .post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0), + .htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0), + .hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0), + .dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16), + .sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15), + .dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0), + .vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0), + .vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), + .vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0), + .vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), + .bcsh_brightness = VOP_REG(RK3568_VP0_BCSH_BCS, 0xff, 0), + .bcsh_contrast = VOP_REG(RK3568_VP0_BCSH_BCS, 0x1ff, 8), + .bcsh_sat_con = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3ff, 20), + .bcsh_out_mode = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3, 30), + .bcsh_sin_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 0), + .bcsh_cos_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 16), + .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 6), + .bcsh_r2y_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 4), + .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 2), + .bcsh_y2r_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 0), + .bcsh_en = VOP_REG(RK3568_VP0_BCSH_COLOR_BAR, 0x1, 31), + .edpi_te_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 28), + .edpi_wms_hold_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 30), + .edpi_wms_fs = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 31), + .lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4), + .cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0), + .cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2), + .cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0), + + .mcu_pix_total = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 0), + .mcu_cs_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 6), + .mcu_cs_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 10), + .mcu_rw_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 16), + .mcu_rw_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 20), + .mcu_clk_sel = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 26), + .mcu_hold_mode = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 27), + .mcu_frame_st = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 28), + .mcu_rs = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 29), + .mcu_bypass = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 30), + .mcu_type = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 31), + .mcu_rw_bypass_port = VOP_REG(RK3562_VP0_MCU_RW_BYPASS_PORT, 0xffffffff, 0), + .layer_sel = VOP_REG(RK3528_OVL_PORT0_LAYER_SEL, 0xffff, 0), +}; + +static const struct vop2_video_port_regs rk3562_vop_vp1_regs = { + .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1), + .overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0), + .dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0), + .out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0), + .core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4), + .p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5), + .dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6), + .dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7), + .dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8), + .post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15), + .pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16), + .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17), + .dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18), + .dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20), + .gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22), + .dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28), + .standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), + .bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xffff, 0), + .bg_dly = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xff, 24), + .pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0), + .hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0), + .vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0), + .post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), + .post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0), + .htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0xffffffff, 0), + .hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0xffffffff, 0), + .dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16), + .sw_dsp_vtotal_imd = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1, 15), + .dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0), + .vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0), + .vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), + .vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0), + .vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), + .bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0), + .bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8), + .bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20), + .bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30), + .bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0), + .bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16), + .bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6), + .bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4), + .bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2), + .bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0), + .bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31), + .edpi_te_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 28), + .edpi_wms_hold_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 30), + .edpi_wms_fs = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 31), + .lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4), + .mcu_pix_total = VOP_REG(RK3562_VP1_MCU_CTRL, 0x3f, 0), + .mcu_cs_pst = VOP_REG(RK3562_VP1_MCU_CTRL, 0xf, 6), + .mcu_cs_pend = VOP_REG(RK3562_VP1_MCU_CTRL, 0x3f, 10), + .mcu_rw_pst = VOP_REG(RK3562_VP1_MCU_CTRL, 0xf, 16), + .mcu_rw_pend = VOP_REG(RK3562_VP1_MCU_CTRL, 0x3f, 20), + .mcu_clk_sel = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 26), + .mcu_hold_mode = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 27), + .mcu_frame_st = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 28), + .mcu_rs = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 29), + .mcu_bypass = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 30), + .mcu_type = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 31), + .mcu_rw_bypass_port = VOP_REG(RK3562_VP1_MCU_RW_BYPASS_PORT, 0xffffffff, 0), + .layer_sel = VOP_REG(RK3528_OVL_PORT1_LAYER_SEL, 0xffff, 0), +}; + +static const struct vop2_video_port_data rk3562_vop_video_ports[] = { + { + .id = 0, + .soc_id = { 0x3562, 0x3562 }, + .lut_dma_rid = 14, + .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN, + .gamma_lut_len = 1024, + .cubic_lut_len = 729, /* 9x9x9 */ + .max_output = { 2048, 4096 }, + .win_dly = 8, + .layer_mix_dly = 8, + .intr = &rk3568_vp0_intr, + .regs = &rk3562_vop_vp0_regs, + .ovl_regs = &rk3528_vop_vp0_ovl_regs, + }, + { + .id = 1, + .soc_id = { 0x3562, 0x3562 }, + .lut_dma_rid = 14, + .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN, + .gamma_lut_len = 1024, + .max_output = { 2048, 4096 }, + .win_dly = 8, + .layer_mix_dly = 8, + .intr = &rk3568_vp1_intr, + .regs = &rk3562_vop_vp1_regs, + .ovl_regs = &rk3528_vop_vp1_ovl_regs, + }, +}; + static const struct vop2_video_port_regs rk3568_vop_vp0_regs = { .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0), @@ -2422,6 +2584,126 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { }, }; +/* + * RK3562 VOP with 4 Esmart win. + * Every Esmart win support 4 multi-region and each Esmart win can by used by VP0 or VP1 + * + * Scale filter mode: + * + * * Esmart: + * * Support prescale down: + * * H: gt2/avg2 or gt4/avg4 + * * V: gt2 or gt4 + * * After prescale down: + * * nearest-neighbor/bilinear/bicubic for scale up + * * nearest-neighbor/bilinear/average for scale down + */ +static const struct vop2_win_data rk3562_vop_win_data[] = { + { + .name = "Esmart0-win0", + .phys_id = ROCKCHIP_VOP2_ESMART0, + .formats = formats_for_esmart, + .nformats = ARRAY_SIZE(formats_for_esmart), + .format_modifiers = format_modifiers, + .base = 0x0, + .layer_sel_id = { 0, 0, 0xff, 0xff }, + .supported_rotations = DRM_MODE_REFLECT_Y, + .hsu_filter_mode = VOP2_SCALE_UP_BIC, + .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .vsu_filter_mode = VOP2_SCALE_UP_BIL, + .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .regs = &rk3568_esmart_win_data, + .area = rk3568_area_data, + .area_size = ARRAY_SIZE(rk3568_area_data), + .type = DRM_PLANE_TYPE_PRIMARY, + .axi_id = 0, + .axi_yrgb_id = 0x02, + .axi_uv_id = 0x03, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 27, 45, 48 }, + .feature = WIN_FEATURE_MULTI_AREA, + }, + + { + .name = "Esmart1-win0", + .phys_id = ROCKCHIP_VOP2_ESMART1, + .formats = formats_for_esmart, + .nformats = ARRAY_SIZE(formats_for_esmart), + .format_modifiers = format_modifiers, + .base = 0x200, + .layer_sel_id = { 1, 1, 0xff, 0xff }, + .supported_rotations = DRM_MODE_REFLECT_Y, + .hsu_filter_mode = VOP2_SCALE_UP_BIC, + .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .vsu_filter_mode = VOP2_SCALE_UP_BIL, + .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .regs = &rk3568_esmart_win_data, + .area = rk3568_area_data, + .area_size = ARRAY_SIZE(rk3568_area_data), + .type = DRM_PLANE_TYPE_OVERLAY, + .axi_id = 0, + .axi_yrgb_id = 0x04, + .axi_uv_id = 0x05, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 27, 45, 48 }, + .feature = WIN_FEATURE_MULTI_AREA, + }, + + { + .name = "Esmart2-win0", + .phys_id = ROCKCHIP_VOP2_ESMART2, + .base = 0x400, + .formats = formats_for_esmart, + .nformats = ARRAY_SIZE(formats_for_esmart), + .format_modifiers = format_modifiers, + .layer_sel_id = { 2, 2, 0xff, 0xff }, + .supported_rotations = DRM_MODE_REFLECT_Y, + .hsu_filter_mode = VOP2_SCALE_UP_BIC, + .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .vsu_filter_mode = VOP2_SCALE_UP_BIL, + .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .regs = &rk3568_esmart_win_data, + .area = rk3568_area_data, + .area_size = ARRAY_SIZE(rk3568_area_data), + .type = DRM_PLANE_TYPE_PRIMARY, + .axi_id = 0, + .axi_yrgb_id = 0x06, + .axi_uv_id = 0x07, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 27, 45, 48 }, + .feature = WIN_FEATURE_MULTI_AREA, + }, + + { + .name = "Esmart3-win0", + .phys_id = ROCKCHIP_VOP2_ESMART3, + .formats = formats_for_esmart, + .nformats = ARRAY_SIZE(formats_for_esmart), + .format_modifiers = format_modifiers, + .base = 0x600, + .layer_sel_id = { 3, 3, 0xff, 0xff }, + .supported_rotations = DRM_MODE_REFLECT_Y, + .hsu_filter_mode = VOP2_SCALE_UP_BIC, + .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .vsu_filter_mode = VOP2_SCALE_UP_BIL, + .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .regs = &rk3568_esmart_win_data, + .area = rk3568_area_data, + .area_size = ARRAY_SIZE(rk3568_area_data), + .type = DRM_PLANE_TYPE_OVERLAY, + .axi_id = 0, + .axi_yrgb_id = 0x08, + .axi_uv_id = 0x0d, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 27, 45, 48 }, + .feature = WIN_FEATURE_MULTI_AREA, + }, +}; + /* * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win. * Every cluster can work as 4K win or split into two win. @@ -3186,6 +3468,46 @@ static const struct vop2_ctrl rk3528_vop_ctrl = { .win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_ESMART3_CTRL, 0xff, 0), }; +static const struct vop_grf_ctrl rk3562_sys_grf_ctrl = { + .grf_dclk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3), +}; + +static const struct vop2_ctrl rk3562_vop_ctrl = { + .cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15), + .wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14), + .auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31), + .aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7), + .if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28), + .version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16), + .lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0), + .rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0), + .mipi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 4), + .lvds0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 5), + .bt1120_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 6), + .bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7), + .rgb_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8), + .mipi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16), + .lvds0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18), + .bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5), + .bt656_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 6), + .bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9), + .bt1120_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 10), + .lvds_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0), + .lvds_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3), + .mipi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 12), + .mipi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 15), + .gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 12), + .esmart_lb_mode = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 26), + .win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 16), + .win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 20), + .win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 24), + .win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 28), + .win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_ESMART0_CTRL, 0xff, 0), + .win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_ESMART1_CTRL, 0xff, 0), + .win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_ESMART2_CTRL, 0xff, 0), + .win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_ESMART3_CTRL, 0xff, 0), +}; + static const struct vop_grf_ctrl rk3568_sys_grf_ctrl = { .grf_bt656_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 1), .grf_bt1120_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 2), @@ -3369,6 +3691,19 @@ static const struct vop_dump_regs rk3528_dump_regs[] = { { RK3528_HDR_LUT_CTRL, "HDR", {0}, 0 }, }; +static const struct vop_dump_regs rk3562_dump_regs[] = { + { RK3568_REG_CFG_DONE, "SYS", {0}, 0 }, + { RK3528_OVL_SYS, "OVL_SYS", {0}, 0 }, + { RK3528_OVL_PORT0_CTRL, "OVL_VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 }, + { RK3528_OVL_PORT1_CTRL, "OVL_VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 }, + { RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 }, + { RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 }, + { RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 }, + { RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 }, + { RK3568_SMART0_CTRL0, "Esmart2", VOP_REG(RK3568_SMART0_CTRL0, 0x1, 0), 1 }, + { RK3568_SMART1_CTRL0, "Esmart3", VOP_REG(RK3568_SMART1_CTRL0, 0x1, 0), 1 }, +}; + static const struct vop_dump_regs rk3568_dump_regs[] = { { RK3568_REG_CFG_DONE, "SYS", {0}, 0 }, { RK3568_OVL_CTRL, "OVL", {0}, 0 }, @@ -3423,6 +3758,27 @@ static const struct vop2_data rk3528_vop = { .dump_regs_size = ARRAY_SIZE(rk3528_dump_regs), }; +static const struct vop2_data rk3562_vop = { + .version = VOP_VERSION_RK3562, + .nr_vps = 2, + .nr_mixers = 3, + .nr_layers = 4, + .nr_gammas = 2, + .esmart_lb_mode = VOP3_ESMART_2K_2K_2K_2K_MODE, + .max_input = { 4096, 4096 }, + .max_output = { 4096, 4096 }, + .ctrl = &rk3562_vop_ctrl, + .sys_grf = &rk3562_sys_grf_ctrl, + .axi_intr = rk3528_vop_axi_intr, + .nr_axi_intr = ARRAY_SIZE(rk3528_vop_axi_intr), + .vp = rk3562_vop_video_ports, + .wb = &rk3568_vop_wb_data, + .win = rk3562_vop_win_data, + .win_size = ARRAY_SIZE(rk3562_vop_win_data), + .dump_regs = rk3562_dump_regs, + .dump_regs_size = ARRAY_SIZE(rk3562_dump_regs), +}; + static const struct vop2_data rk3568_vop = { .version = VOP_VERSION_RK3568, .nr_vps = 3, @@ -3484,6 +3840,8 @@ static const struct vop2_data rk3588_vop = { static const struct of_device_id vop2_dt_match[] = { { .compatible = "rockchip,rk3528-vop", .data = &rk3528_vop }, + { .compatible = "rockchip,rk3562-vop", + .data = &rk3562_vop }, { .compatible = "rockchip,rk3568-vop", .data = &rk3568_vop }, { .compatible = "rockchip,rk3588-vop", diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 340ffa62666a..0cfa38fcb969 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1039,6 +1039,8 @@ #define RV1126_GRF_IOFUNC_CON3 0x1026c +#define RK3562_GRF_IOC_VO_IO_CON 0x00500 + /* rk3568 vop registers definition */ #define RK3568_GRF_VO_CON1 0x0364 @@ -1133,6 +1135,8 @@ #define RK3568_VP0_BCSH_BCS 0xC64 #define RK3568_VP0_BCSH_H 0xC68 #define RK3568_VP0_BCSH_COLOR_BAR 0xC6C +#define RK3562_VP0_MCU_CTRL 0xCF8 +#define RK3562_VP0_MCU_RW_BYPASS_PORT 0xCFC #define RK3528_VP0_ACM_CTRL 0xCD0 #define RK3528_VP0_CSC_COE01_02 0xCD4 @@ -1170,6 +1174,8 @@ #define RK3568_VP1_BCSH_BCS 0xD64 #define RK3568_VP1_BCSH_H 0xD68 #define RK3568_VP1_BCSH_COLOR_BAR 0xD6C +#define RK3562_VP1_MCU_CTRL 0xDF8 +#define RK3562_VP1_MCU_RW_BYPASS_PORT 0xDFC #define RK3568_VP2_DSP_CTRL 0xE00 #define RK3568_VP2_DUAL_CHANNEL_CTRL 0xE04 From 636cad1344debe3e4830590aae36cf693bae6a34 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 10 Jan 2023 19:36:01 +0800 Subject: [PATCH 025/258] drm/rockchip: vop3: fix init value error for rk3562 vp1 This two bit is reserved for hdr and it is enabled by default, is less this commit, vp1 will display black screen always. Signed-off-by: Sandy Huang Change-Id: I38862d187a1e26322c3e8930b615c4eb9d5f4ef8 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 5650d639fd01..f6a9239993a2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -3761,10 +3761,10 @@ static void vop2_initial(struct drm_crtc *crtc) } /* - * This is unused and error init value for rk3528 vp1, if less of this config, + * This is unused and error init value for rk3528/rk3562 vp1, if less of this config, * vp1 can't display normally. */ - if (vop2->version == VOP_VERSION_RK3528) + if (vop2->version == VOP_VERSION_RK3528 || vop2->version == VOP_VERSION_RK3562) vop2_mask_write(vop2, 0x700, 0x3, 4, 0, 0, true); VOP_CTRL_SET(vop2, cfg_done_en, 1); From a2bb42f79146e972146ccc97ce462d334423f450 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 3 Jan 2023 15:07:52 +0800 Subject: [PATCH 026/258] drm/rockchip: rgb: add support rk3562 Signed-off-by: Sandy Huang Change-Id: Iefbb7f45bbafcd5bbfb6840d0968c9b6aef6b709 --- drivers/gpu/drm/rockchip/rockchip_rgb.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index c6ca9596ca1f..8797a5eb0437 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -54,6 +54,9 @@ #define RK3288_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 8, 8) #define RK3288_LVDS_CON_TTL_EN(x) HIWORD_UPDATE(x, 6, 6) +#define RK3562_GRF_IOC_VO_IO_CON 0x500 +#define RK3562_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6) + #define RK3568_GRF_VO_CON1 0X0364 #define RK3568_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6) @@ -974,6 +977,20 @@ static const struct rockchip_rgb_data rk3288_rgb = { .funcs = &rk3288_rgb_funcs, }; +static void rk3562_rgb_enable(struct rockchip_rgb *rgb) +{ + regmap_write(rgb->grf, RK3562_GRF_IOC_VO_IO_CON, + RK3562_RGB_DATA_BYPASS(rgb->data_sync_bypass)); +} + +static const struct rockchip_rgb_funcs rk3562_rgb_funcs = { + .enable = rk3562_rgb_enable, +}; + +static const struct rockchip_rgb_data rk3562_rgb = { + .funcs = &rk3562_rgb_funcs, +}; + static void rk3568_rgb_enable(struct rockchip_rgb *rgb) { regmap_write(rgb->grf, RK3568_GRF_VO_CON1, @@ -1027,6 +1044,7 @@ static const struct of_device_id rockchip_rgb_dt_ids[] = { { .compatible = "rockchip,rk3288-rgb", .data = &rk3288_rgb }, { .compatible = "rockchip,rk3308-rgb", }, { .compatible = "rockchip,rk3368-rgb", }, + { .compatible = "rockchip,rk3562-rgb", .data = &rk3562_rgb }, { .compatible = "rockchip,rk3568-rgb", .data = &rk3568_rgb }, { .compatible = "rockchip,rk3588-rgb", }, { .compatible = "rockchip,rv1106-rgb", .data = &rv1106_rgb}, From 36c9d7fd8fa59b463cfede5adc5c65316776b28c Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Wed, 9 Nov 2022 11:31:42 +0800 Subject: [PATCH 027/258] drm/rockchip: lvds: add support rk3562 Signed-off-by: Zhang Yubing Change-Id: I95a42245599c2440b6405fcfd048e9b32b1636c9 --- drivers/gpu/drm/rockchip/rockchip_lvds.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c index ce4b3a251146..8b3a1812c40d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -61,6 +61,9 @@ #define RK3368_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 11, 11) #define RK3368_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 6, 6) +#define RK3562_GRF_VO_CON0 0x05d0 +#define RK3562_GRF_VO_CON1 0x05d4 + #define RK3568_GRF_VO_CON0 0x0360 #define RK3568_LVDS1_SELECT(x) HIWORD_UPDATE(x, 13, 12) #define RK3568_LVDS1_MSBSEL(x) HIWORD_UPDATE(x, 11, 11) @@ -646,6 +649,25 @@ static int __maybe_unused rockchip_secondary_lvds_probe(struct rockchip_lvds *lv return 0; } +static void rk3562_lvds_enable(struct rockchip_lvds *lvds) +{ + regmap_write(lvds->grf, RK3562_GRF_VO_CON1, + RK3568_LVDS0_MODE_EN(1) | RK3568_LVDS0_P2S_EN(1) | + RK3568_LVDS0_DCLK_INV_SEL(1)); + regmap_write(lvds->grf, RK3562_GRF_VO_CON0, + RK3568_LVDS0_SELECT(lvds->format) | RK3568_LVDS0_MSBSEL(1)); +} + +static void rk3562_lvds_disable(struct rockchip_lvds *lvds) +{ + regmap_write(lvds->grf, RK3562_GRF_VO_CON1, RK3568_LVDS0_MODE_EN(0)); +} + +static const struct rockchip_lvds_funcs rk3562_lvds_funcs = { + .enable = rk3562_lvds_enable, + .disable = rk3562_lvds_disable, +}; + static void rk3568_lvds_enable(struct rockchip_lvds *lvds) { regmap_write(lvds->grf, RK3568_GRF_VO_CON2, @@ -670,6 +692,7 @@ static const struct of_device_id rockchip_lvds_dt_ids[] = { { .compatible = "rockchip,rk3126-lvds", .data = &rk3126_lvds_funcs }, { .compatible = "rockchip,rk3288-lvds", .data = &rk3288_lvds_funcs }, { .compatible = "rockchip,rk3368-lvds", .data = &rk3368_lvds_funcs }, + { .compatible = "rockchip,rk3562-lvds", .data = &rk3562_lvds_funcs }, { .compatible = "rockchip,rk3568-lvds", .data = &rk3568_lvds_funcs }, {} }; From 63f30f754157cbe8eb4701a0f4f0e0f4a1a47c7c Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Mon, 14 Nov 2022 10:23:04 +0800 Subject: [PATCH 028/258] phy: rockchip: inno-usb2: add usb2 phy support for rk3562 RK3652 has one USB2.0 PHY with two ports, the OTG port support OTG and BC1.2, the SoC provide USB GRF and APB to access the registers. This adds vbus detection function control and make the below tuning to enhance the usb2-phy SQ for RK3562 SoC. - enable pre-emphasis during non-chirp phase - set HS eye height to 425mv - turn off differential receiver by default to save power Signed-off-by: Frank Wang Signed-off-by: William Wu Change-Id: If93c3a072be4c532aa823cf3cd9f05fe9414f727 --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index cb485829dfaa..0536c08e216e 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -2741,6 +2741,34 @@ static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy) return ret; } +static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy) +{ + int ret = 0; + + /* Turn off differential receiver by default to save power */ + phy_clear_bits(rphy->phy_base + 0x0030, BIT(2)); + phy_clear_bits(rphy->phy_base + 0x0430, BIT(2)); + + /* Enable pre-emphasis during non-chirp phase */ + phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04); + phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04); + + /* Set HS eye height to 425mv(default is 400mv) */ + phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4)); + phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4)); + + /* Set the bvalid filter time to 10ms based on the u2phy grf pclk 100MHz */ + ret |= regmap_write(rphy->grf, 0x0138, FILTER_COUNTER); + + /* Set the id filter time to 10ms based on the u2phy grf pclk 100MHz */ + ret |= regmap_write(rphy->grf, 0x013c, FILTER_COUNTER); + + /* Enable host port wakeup irq */ + ret |= regmap_write(rphy->grf, 0x010c, 0x80008000); + + return ret; +} + static int rk3568_usb2phy_tuning(struct rockchip_usb2phy *rphy) { int ret = 0; @@ -3626,6 +3654,65 @@ static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { } }; +static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = { + { + .reg = 0xff740000, + .num_ports = 2, + .phy_tuning = rk3562_usb2phy_tuning, + .vbus_detect = rockchip_usb2phy_vbus_det_control, + .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, + .ls_filter_con = { 0x0130, 19, 0, 0x30100, 0x00020 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, + .bvalid_grf_sel = { 0x0108, 15, 14, 0, 3 }, + .bypass_dm_en = { 0x0108, 2, 2, 0, 1}, + .bypass_sel = { 0x0108, 3, 3, 0, 1}, + .iddig_output = { 0x0100, 10, 10, 0, 1 }, + .iddig_en = { 0x0100, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, + .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + .vbus_det_en = { 0x003c, 7, 7, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0110, 1, 1, 0, 1 }, + .ls_det_st = { 0x0114, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0118, 1, 1, 0, 1 }, + .utmi_ls = { 0x0120, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } + } + }, + .chg_det = { + .chg_mode = { 0x0100, 8, 0, 0, 0x1d7 }, + .cp_det = { 0x0120, 24, 24, 0, 1 }, + .dcp_det = { 0x0120, 23, 23, 0, 1 }, + .dp_det = { 0x0120, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { { .reg = 0xfe8a0000, @@ -3986,6 +4073,9 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = { #ifdef CONFIG_CPU_RK3528 { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs }, #endif +#ifdef CONFIG_CPU_RK3562 + { .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs }, +#endif #ifdef CONFIG_CPU_RK3568 { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, #endif From 0cdb526c1f28f08f97b88345eafd9cae62debcee Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 1 Dec 2022 20:38:15 +0800 Subject: [PATCH 029/258] phy: rockchip-naneng-combo: Support rk3562 Change-Id: I4da12613bb01c477f8fca9c38c516f5dab0851d9 Signed-off-by: Jon Lin --- .../rockchip/phy-rockchip-naneng-combphy.c | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 146e714cc614..3ace49e41bbd 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -561,6 +561,191 @@ static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { .combphy_cfg = rk3528_combphy_cfg, }; +static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + struct clk *refclk = NULL; + unsigned long rate; + int i; + u32 val; + + /* Configure PHY reference clock frequency */ + for (i = 0; i < priv->num_clks; i++) { + if (!strncmp(priv->clks[i].id, "refclk", 6)) { + refclk = priv->clks[i].clk; + break; + } + } + + if (!refclk) { + dev_err(priv->dev, "No refclk found\n"); + return -EINVAL; + } + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + + /* Set PLL KVCO fine tuning signals */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(0x4, priv->mmio + (0xb << 2)); + + /* Set PLL input clock divider 1/2 */ + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + /* Set PLL loop divider */ + writel(0x32, priv->mmio + (0x11 << 2)); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(0xf0, priv->mmio + (0xa << 2)); + + param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(refclk); + + switch (rate) { + case 24000000: + if (priv->mode == PHY_TYPE_USB3) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(7, 6); + val |= 0x01 << 6; + writel(val, priv->mmio + (0x0e << 2)); + + val = readl(priv->mmio + (0x0f << 2)); + val &= ~GENMASK(7, 0); + val |= 0x5f; + writel(val, priv->mmio + (0x0f << 2)); + } + break; + case 25000000: + param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + case 100000000: + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Enable controlling random jitter, aka RMJ */ + writel(0x4, priv->mmio + (0xb << 2)); + + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + writel(0x32, priv->mmio + (0x11 << 2)); + writel(0xf0, priv->mmio + (0xa << 2)); + } + break; + default: + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { + param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { + val = readl(priv->mmio + (0xc << 2)); + val |= 0x3 << 4 | 0x1 << 7; + writel(val, priv->mmio + (0xc << 2)); + + val = readl(priv->mmio + (0xd << 2)); + val |= 0x1; + writel(val, priv->mmio + (0xd << 2)); + } + } + + if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) { + val = readl(priv->mmio + (0x7 << 2)); + val |= BIT(4); + writel(val, priv->mmio + (0x7 << 2)); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + /* peri-grf */ + .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct clk_bulk_data rk3562_clks[] = { + { .id = "refclk" }, + { .id = "apbclk" }, + { .id = "pipe_clk" }, +}; + +static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { + .num_clks = ARRAY_SIZE(rk3562_clks), + .clks = rk3562_clks, + .grfcfg = &rk3562_combphy_grfcfgs, + .combphy_cfg = rk3562_combphy_cfg, + .force_det_out = true, +}; + static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; @@ -1061,6 +1246,10 @@ static const struct of_device_id rockchip_combphy_of_match[] = { .compatible = "rockchip,rk3528-naneng-combphy", .data = &rk3528_combphy_cfgs, }, + { + .compatible = "rockchip,rk3562-naneng-combphy", + .data = &rk3562_combphy_cfgs, + }, { .compatible = "rockchip,rk3568-naneng-combphy", .data = &rk3568_combphy_cfgs, From 4f0c9ccc79c373aa97084b3b1ab0651ca4248227 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 1 Dec 2022 20:39:15 +0800 Subject: [PATCH 030/258] pcie: rockchip: dw: Support rk3562 rk_pcie_of_data is the same with RK3528. Change-Id: I161dfd939ff72e72a61588ff5ed953d2b600f48d Signed-off-by: Jon Lin Signed-off-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index f2b67f8a610d..25a33e8252b4 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -1542,6 +1542,10 @@ static const struct of_device_id rk_pcie_of_match[] = { .compatible = "rockchip,rk3528-pcie", .data = &rk3528_pcie_rc_of_data, }, + { + .compatible = "rockchip,rk3562-pcie", + .data = &rk3528_pcie_rc_of_data, + }, { .compatible = "rockchip,rk3568-pcie", .data = &rk_pcie_rc_of_data, From 319dab507b2d04280586e1fe8385a1bb5a2c9460 Mon Sep 17 00:00:00 2001 From: Chandler Chen Date: Mon, 26 Sep 2022 15:11:27 +0800 Subject: [PATCH 031/258] video: rockchip: mpp: rkvenc2: match rk3562 encoder compatible Signed-off-by: Chandler Chen Change-Id: I575b599d52825aa6d91cd562aed16d664efe765e --- drivers/video/rockchip/mpp/mpp_rkvenc2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/rockchip/mpp/mpp_rkvenc2.c b/drivers/video/rockchip/mpp/mpp_rkvenc2.c index 4264a38629cb..d68e1316c315 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvenc2.c +++ b/drivers/video/rockchip/mpp/mpp_rkvenc2.c @@ -2001,6 +2001,12 @@ static const struct of_device_id mpp_rkvenc_dt_match[] = { .data = &rkvenc_540c_data, }, #endif +#ifdef CONFIG_CPU_RK3562 + { + .compatible = "rockchip,rkv-encoder-rk3562", + .data = &rkvenc_540c_data, + }, +#endif #ifdef CONFIG_CPU_RK3588 { .compatible = "rockchip,rkv-encoder-v2-core", From d76a85467f99b42b2e5f4b47857510f625d4d7dc Mon Sep 17 00:00:00 2001 From: Chandler Chen Date: Thu, 15 Sep 2022 14:59:52 +0800 Subject: [PATCH 032/258] video: rockchip: mpp: link mode support for rk3562 Signed-off-by: Chandler Chen Change-Id: I8fe2d951554ed2f178c8509aabe166427ccaf096 --- drivers/video/rockchip/mpp/mpp_rkvdec2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/rockchip/mpp/mpp_rkvdec2.c b/drivers/video/rockchip/mpp/mpp_rkvdec2.c index 53fd57c6c519..e39f76800966 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvdec2.c +++ b/drivers/video/rockchip/mpp/mpp_rkvdec2.c @@ -1262,6 +1262,12 @@ static const struct of_device_id mpp_rkvdec2_dt_match[] = { .compatible = "rockchip,rkv-decoder-rk3528", .data = &rkvdec_vdpu382_data, }, +#endif +#ifdef CONFIG_CPU_RK3562 + { + .compatible = "rockchip,rkv-decoder-rk3562", + .data = &rkvdec_vdpu382_data, + }, #endif {}, }; From d66101a3fe2cd339a15d15661f486fa1ff876f54 Mon Sep 17 00:00:00 2001 From: Simon Xue Date: Thu, 15 Dec 2022 16:07:42 +0800 Subject: [PATCH 033/258] iio: adc: rockchip_saradc: add rk3562 Change-Id: Id4d47ff54d194a4312487f4a07698d3cd6405112 Signed-off-by: Simon Xue --- drivers/iio/adc/rockchip_saradc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index 8a8f73127ba5..a923fb0b2410 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -327,6 +327,25 @@ static const struct rockchip_saradc_data rk3528_saradc_data = { .read = rockchip_saradc_read_v2, }; +static const struct iio_chan_spec rockchip_rk3562_saradc_iio_channels[] = { + SARADC_CHANNEL(0, "adc0", 10), + SARADC_CHANNEL(1, "adc1", 10), + SARADC_CHANNEL(2, "adc2", 10), + SARADC_CHANNEL(3, "adc3", 10), + SARADC_CHANNEL(4, "adc4", 10), + SARADC_CHANNEL(5, "adc5", 10), + SARADC_CHANNEL(6, "adc6", 10), + SARADC_CHANNEL(7, "adc7", 10), +}; + +static const struct rockchip_saradc_data rk3562_saradc_data = { + .channels = rockchip_rk3562_saradc_iio_channels, + .num_channels = ARRAY_SIZE(rockchip_rk3562_saradc_iio_channels), + .clk_rate = 1000000, + .start = rockchip_saradc_start_v2, + .read = rockchip_saradc_read_v2, +}; + static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = { SARADC_CHANNEL(0, "adc0", 10), SARADC_CHANNEL(1, "adc1", 10), @@ -392,6 +411,9 @@ static const struct of_device_id rockchip_saradc_match[] = { }, { .compatible = "rockchip,rk3528-saradc", .data = &rk3528_saradc_data, + }, { + .compatible = "rockchip,rk3562-saradc", + .data = &rk3562_saradc_data, }, { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_data, From 91eb711c9c1a182711f023cad3adbafcd85381ff Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 16 Dec 2022 18:36:22 +0800 Subject: [PATCH 034/258] ethernet: stmmac: dwmac-rk: Add gmac support for rk3562 Add constants and callback functions for the dwmac on RK3562 soc. As can be seen, the base structure is the same. Signed-off-by: David Wu Change-Id: I79a86c29bbbcd86b29cc6c59fd9f6d931fd556c6 --- .../bindings/net/rockchip-dwmac.yaml | 3 + .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 202 ++++++++++++++++++ 2 files changed, 205 insertions(+) diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml index f6b82fc206d6..d876efa3a336 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -25,6 +25,7 @@ select: - rockchip,rk3368-gmac - rockchip,rk3399-gmac - rockchip,rk3528-gmac + - rockchip,rk3562-gmac - rockchip,rk3568-gmac - rockchip,rk3588-gmac - rockchip,rv1106-gmac @@ -50,10 +51,12 @@ properties: - rockchip,rk3366-gmac - rockchip,rk3368-gmac - rockchip,rk3399-gmac + - rockchip,rk3562-gmac - rockchip,rv1108-gmac - items: - enum: - rockchip,rk3528-gmac + - rockchip,rk3562-gmac - rockchip,rk3568-gmac - rockchip,rk3588-gmac - rockchip,rv1106-gmac diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index 562c7413929c..fc4398406338 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -221,6 +221,12 @@ static int xpcs_setup(struct rk_priv_data *bsp_priv, int mode) ((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \ (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0)) +#define GMAC_RGMII_CLK_DIV_BY_ID(soc, id, div) \ + (soc##_GMAC##id##_CLK_RGMII_DIV##div) + +#define GMAC_RMII_CLK_DIV_BY_ID(soc, id, div) \ + (soc##_GMAC##id##_CLK_RMII_DIV##div) + /* Integrated EPHY */ #define RK_GRF_MACPHY_CON0 0xb00 @@ -1527,6 +1533,199 @@ static const struct rk_gmac_ops rk3528_ops = { .integrated_phy_power = rk3528_integrated_sphy_power, }; +/* sys_grf */ +#define RK3562_GRF_SYS_SOC_CON0 0X0400 +#define RK3562_GRF_SYS_SOC_CON1 0X0404 + +#define RK3562_GMAC0_CLK_RMII_MODE GRF_BIT(5) +#define RK3562_GMAC0_CLK_RGMII_MODE GRF_CLR_BIT(5) + +#define RK3562_GMAC0_CLK_RMII_GATE GRF_BIT(6) +#define RK3562_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(6) + +#define RK3562_GMAC0_CLK_RMII_DIV2 GRF_BIT(7) +#define RK3562_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(7) + +#define RK3562_GMAC0_CLK_RGMII_DIV1 \ + (GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) +#define RK3562_GMAC0_CLK_RGMII_DIV5 \ + (GRF_BIT(7) | GRF_BIT(8)) +#define RK3562_GMAC0_CLK_RGMII_DIV50 \ + (GRF_CLR_BIT(7) | GRF_BIT(8)) + +#define RK3562_GMAC0_CLK_RMII_DIV2 GRF_BIT(7) +#define RK3562_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(7) + +#define RK3562_GMAC0_CLK_SELET_CRU GRF_CLR_BIT(9) +#define RK3562_GMAC0_CLK_SELET_IO GRF_BIT(9) + +#define RK3562_GMAC1_CLK_RMII_GATE GRF_BIT(12) +#define RK3562_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(12) + +#define RK3562_GMAC1_CLK_RMII_DIV2 GRF_BIT(13) +#define RK3562_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(13) + +#define RK3562_GMAC1_RMII_SPEED100 GRF_BIT(11) +#define RK3562_GMAC1_RMII_SPEED10 GRF_CLR_BIT(11) + +#define RK3562_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(15) +#define RK3562_GMAC1_CLK_SELET_IO GRF_BIT(15) + +/* ioc_grf */ +#define RK3562_GRF_IOC_GMAC_IOFUNC0_CON0 0X10400 +#define RK3562_GRF_IOC_GMAC_IOFUNC0_CON1 0X10404 +#define RK3562_GRF_IOC_GMAC_IOFUNC1_CON0 0X00400 +#define RK3562_GRF_IOC_GMAC_IOFUNC1_CON1 0X00404 + +#define RK3562_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) +#define RK3562_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) +#define RK3562_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) +#define RK3562_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) + +#define RK3562_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) +#define RK3562_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) + +#define RK3562_GMAC0_IO_EXTCLK_SELET_CRU GRF_CLR_BIT(2) +#define RK3562_GMAC0_IO_EXTCLK_SELET_IO GRF_BIT(2) + +#define RK3562_GMAC1_IO_EXTCLK_SELET_CRU GRF_CLR_BIT(3) +#define RK3562_GMAC1_IO_EXTCLK_SELET_IO GRF_BIT(3) + +static void rk3562_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) +{ + struct device *dev = &bsp_priv->pdev->dev; + + if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { + dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n"); + return; + } + + if (bsp_priv->bus_id > 0) + return; + + regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, + RK3562_GMAC0_CLK_RGMII_MODE); + + regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1, + DELAY_ENABLE(RK3562, tx_delay, rx_delay)); + regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON0, + DELAY_VALUE(RK3562, tx_delay, rx_delay)); + + regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, + DELAY_ENABLE(RK3562, tx_delay, rx_delay)); + regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON0, + DELAY_VALUE(RK3562, tx_delay, rx_delay)); +} + +static void rk3562_set_to_rmii(struct rk_priv_data *bsp_priv) +{ + struct device *dev = &bsp_priv->pdev->dev; + + if (IS_ERR(bsp_priv->grf)) { + dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); + return; + } + + if (!bsp_priv->bus_id) + regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, + RK3562_GMAC0_CLK_RMII_MODE); +} + +static void rk3562_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) +{ + struct device *dev = &bsp_priv->pdev->dev; + unsigned int val = 0, offset, id = bsp_priv->bus_id; + + switch (speed) { + case 10: + if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { + if (id > 0) { + val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 20); + regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, + RK3562_GMAC1_RMII_SPEED10); + } else { + val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 20); + } + } else { + val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 50); + } + break; + case 100: + if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { + if (id > 0) { + val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 2); + regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, + RK3562_GMAC1_RMII_SPEED100); + } else { + val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 2); + } + } else { + val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 5); + } + break; + case 1000: + if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) + val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 1); + else + goto err; + break; + default: + goto err; + } + + offset = (bsp_priv->bus_id > 0) ? RK3562_GRF_SYS_SOC_CON1 : + RK3562_GRF_SYS_SOC_CON0; + regmap_write(bsp_priv->grf, offset, val); + + return; +err: + dev_err(dev, "unknown speed value for GMAC speed=%d", speed); +} + +static void rk3562_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, + bool enable) +{ + struct device *dev = &bsp_priv->pdev->dev; + unsigned int value; + + if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) { + dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n"); + return; + } + + if (!bsp_priv->bus_id) { + value = input ? RK3562_GMAC0_CLK_SELET_IO : + RK3562_GMAC0_CLK_SELET_CRU; + value |= enable ? RK3562_GMAC0_CLK_RMII_NOGATE : + RK3562_GMAC0_CLK_RMII_GATE; + regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, value); + + value = input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO : + RK3562_GMAC0_IO_EXTCLK_SELET_CRU; + regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1, value); + regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value); + } else { + value = input ? RK3562_GMAC1_CLK_SELET_IO : + RK3562_GMAC1_CLK_SELET_CRU; + value |= enable ? RK3562_GMAC1_CLK_RMII_NOGATE : + RK3562_GMAC1_CLK_RMII_GATE; + regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON1, value); + + value = input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO : + RK3562_GMAC1_IO_EXTCLK_SELET_CRU; + regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value); + } +} + +static const struct rk_gmac_ops rk3562_ops = { + .set_to_rgmii = rk3562_set_to_rgmii, + .set_to_rmii = rk3562_set_to_rmii, + .set_rgmii_speed = rk3562_set_gmac_speed, + .set_rmii_speed = rk3562_set_gmac_speed, + .set_clock_selection = rk3562_set_clock_selection, +}; + #define RK3568_GRF_GMAC0_CON0 0X0380 #define RK3568_GRF_GMAC0_CON1 0X0384 #define RK3568_GRF_GMAC1_CON0 0X0388 @@ -2668,6 +2867,9 @@ static const struct of_device_id rk_gmac_dwmac_match[] = { #ifdef CONFIG_CPU_RK3528 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, #endif +#ifdef CONFIG_CPU_RK3562 + { .compatible = "rockchip,rk3562-gmac", .data = &rk3562_ops }, +#endif #ifdef CONFIG_CPU_RK3568 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, #endif From 00afdab272753d82ce7393b6ccf79837a4569f0c Mon Sep 17 00:00:00 2001 From: Felix Zeng Date: Fri, 16 Dec 2022 16:37:27 +0800 Subject: [PATCH 035/258] driver: rknpu: Update rknpu driver, version: 0.8.3 * Add support for rk3562 Signed-off-by: Felix Zeng Change-Id: I0d1c7e74f3ed69f835e92d4a540a06fc3d218897 --- drivers/rknpu/include/rknpu_drv.h | 11 +++--- drivers/rknpu/include/rknpu_ioctl.h | 1 - drivers/rknpu/rknpu_drv.c | 61 +++++++++++++++++++---------- drivers/rknpu/rknpu_gem.c | 17 ++++---- drivers/rknpu/rknpu_job.c | 10 ++--- 5 files changed, 60 insertions(+), 40 deletions(-) diff --git a/drivers/rknpu/include/rknpu_drv.h b/drivers/rknpu/include/rknpu_drv.h index f5a6b269c38a..cd881d91933f 100644 --- a/drivers/rknpu/include/rknpu_drv.h +++ b/drivers/rknpu/include/rknpu_drv.h @@ -30,10 +30,10 @@ #define DRIVER_NAME "rknpu" #define DRIVER_DESC "RKNPU driver" -#define DRIVER_DATE "20220829" +#define DRIVER_DATE "20221110" #define DRIVER_MAJOR 0 #define DRIVER_MINOR 8 -#define DRIVER_PATCHLEVEL 2 +#define DRIVER_PATCHLEVEL 3 #define LOG_TAG "RKNPU" @@ -54,7 +54,7 @@ #define LOG_DEV_DEBUG(dev, fmt, args...) dev_dbg(dev, LOG_TAG ": " fmt, ##args) #define LOG_DEV_ERROR(dev, fmt, args...) dev_err(dev, LOG_TAG ": " fmt, ##args) -struct npu_reset_data { +struct rknpu_reset_data { const char *srst_a_name; const char *srst_h_name; }; @@ -66,9 +66,10 @@ struct rknpu_config { __u32 pc_data_amount_scale; __u32 pc_task_number_bits; __u32 pc_task_number_mask; + __u32 pc_task_status_offset; __u32 bw_enable; - const struct npu_irqs_data *irqs; - const struct npu_reset_data *resets; + const struct rknpu_irqs_data *irqs; + const struct rknpu_reset_data *resets; int num_irqs; int num_resets; }; diff --git a/drivers/rknpu/include/rknpu_ioctl.h b/drivers/rknpu/include/rknpu_ioctl.h index 49d4442e62f7..fc7225fb7b47 100644 --- a/drivers/rknpu/include/rknpu_ioctl.h +++ b/drivers/rknpu/include/rknpu_ioctl.h @@ -25,7 +25,6 @@ #define RKNPU_OFFSET_PC_DATA_AMOUNT 0x14 #define RKNPU_OFFSET_PC_TASK_CONTROL 0x30 #define RKNPU_OFFSET_PC_DMA_BASE_ADDR 0x34 -#define RKNPU_OFFSET_PC_TASK_STATUS 0x3c #define RKNPU_OFFSET_INT_MASK 0x20 #define RKNPU_OFFSET_INT_CLEAR 0x24 diff --git a/drivers/rknpu/rknpu_drv.c b/drivers/rknpu/rknpu_drv.c index 26d10c233cc9..6316bd39f1f3 100644 --- a/drivers/rknpu/rknpu_drv.c +++ b/drivers/rknpu/rknpu_drv.c @@ -79,37 +79,30 @@ module_param(bypass_soft_reset, int, 0644); MODULE_PARM_DESC(bypass_soft_reset, "bypass RKNPU soft reset if set it to 1, disabled by default"); -struct npu_irqs_data { +struct rknpu_irqs_data { const char *name; irqreturn_t (*irq_hdl)(int irq, void *ctx); }; -static const struct npu_irqs_data rk356x_npu_irqs[] = { +static const struct rknpu_irqs_data rknpu_irqs[] = { { "npu_irq", rknpu_core0_irq_handler } }; -static const struct npu_irqs_data rk3588_npu_irqs[] = { +static const struct rknpu_irqs_data rk3588_npu_irqs[] = { { "npu0_irq", rknpu_core0_irq_handler }, { "npu1_irq", rknpu_core1_irq_handler }, { "npu2_irq", rknpu_core2_irq_handler } }; -static const struct npu_irqs_data rv110x_npu_irqs[] = { - { "npu_irq", rknpu_core0_irq_handler } -}; +static const struct rknpu_reset_data rknpu_resets[] = { { "srst_a", + "srst_h" } }; -static const struct npu_reset_data rk356x_npu_resets[] = { { "srst_a", - "srst_h" } }; - -static const struct npu_reset_data rk3588_npu_resets[] = { +static const struct rknpu_reset_data rk3588_npu_resets[] = { { "srst_a0", "srst_h0" }, { "srst_a1", "srst_h1" }, { "srst_a2", "srst_h2" } }; -static const struct npu_reset_data rv110x_npu_resets[] = { { "srst_a", - "srst_h" } }; - static const struct rknpu_config rk356x_rknpu_config = { .bw_priority_addr = 0xfe180008, .bw_priority_length = 0x10, @@ -117,11 +110,12 @@ static const struct rknpu_config rk356x_rknpu_config = { .pc_data_amount_scale = 1, .pc_task_number_bits = 12, .pc_task_number_mask = 0xfff, + .pc_task_status_offset = 0x3c, .bw_enable = 1, - .irqs = rk356x_npu_irqs, - .resets = rk356x_npu_resets, - .num_irqs = ARRAY_SIZE(rk356x_npu_irqs), - .num_resets = ARRAY_SIZE(rk356x_npu_resets) + .irqs = rknpu_irqs, + .resets = rknpu_resets, + .num_irqs = ARRAY_SIZE(rknpu_irqs), + .num_resets = ARRAY_SIZE(rknpu_resets) }; static const struct rknpu_config rk3588_rknpu_config = { @@ -131,6 +125,7 @@ static const struct rknpu_config rk3588_rknpu_config = { .pc_data_amount_scale = 2, .pc_task_number_bits = 12, .pc_task_number_mask = 0xfff, + .pc_task_status_offset = 0x3c, .bw_enable = 0, .irqs = rk3588_npu_irqs, .resets = rk3588_npu_resets, @@ -145,11 +140,27 @@ static const struct rknpu_config rv1106_rknpu_config = { .pc_data_amount_scale = 2, .pc_task_number_bits = 16, .pc_task_number_mask = 0xffff, + .pc_task_status_offset = 0x3c, .bw_enable = 1, - .irqs = rv110x_npu_irqs, - .resets = rv110x_npu_resets, - .num_irqs = ARRAY_SIZE(rv110x_npu_irqs), - .num_resets = ARRAY_SIZE(rv110x_npu_resets) + .irqs = rknpu_irqs, + .resets = rknpu_resets, + .num_irqs = ARRAY_SIZE(rknpu_irqs), + .num_resets = ARRAY_SIZE(rknpu_resets) +}; + +static const struct rknpu_config rk3562_rknpu_config = { + .bw_priority_addr = 0x0, + .bw_priority_length = 0x0, + .dma_mask = DMA_BIT_MASK(40), + .pc_data_amount_scale = 2, + .pc_task_number_bits = 16, + .pc_task_number_mask = 0xffff, + .pc_task_status_offset = 0x48, + .bw_enable = 1, + .irqs = rknpu_irqs, + .resets = rknpu_resets, + .num_irqs = ARRAY_SIZE(rknpu_irqs), + .num_resets = ARRAY_SIZE(rknpu_resets) }; /* driver probe and init */ @@ -170,6 +181,10 @@ static const struct of_device_id rknpu_of_match[] = { .compatible = "rockchip,rv1106-rknpu", .data = &rv1106_rknpu_config, }, + { + .compatible = "rockchip,rk3562-rknpu", + .data = &rk3562_rknpu_config, + }, {}, }; @@ -245,13 +260,17 @@ static int rknpu_action(struct rknpu_device *rknpu_dev, ret = rknpu_get_drv_version(&args->value); break; case RKNPU_GET_FREQ: +#ifndef FPGA_PLATFORM args->value = clk_get_rate(rknpu_dev->clks[0].clk); +#endif ret = 0; break; case RKNPU_SET_FREQ: break; case RKNPU_GET_VOLT: +#ifndef FPGA_PLATFORM args->value = regulator_get_voltage(rknpu_dev->vdd); +#endif ret = 0; break; case RKNPU_SET_VOLT: diff --git a/drivers/rknpu/rknpu_gem.c b/drivers/rknpu/rknpu_gem.c index 6e0e4428517d..38d3197fad76 100644 --- a/drivers/rknpu/rknpu_gem.c +++ b/drivers/rknpu/rknpu_gem.c @@ -115,15 +115,14 @@ static void rknpu_gem_put_pages(struct rknpu_gem_object *rknpu_obj) rknpu_obj->kv_addr = NULL; } - dma_unmap_sg(drm->dev, rknpu_obj->sgt->sgl, rknpu_obj->sgt->nents, - DMA_BIDIRECTIONAL); - - drm_gem_put_pages(&rknpu_obj->base, rknpu_obj->pages, true, true); - if (rknpu_obj->sgt != NULL) { + dma_unmap_sg(drm->dev, rknpu_obj->sgt->sgl, + rknpu_obj->sgt->nents, DMA_BIDIRECTIONAL); sg_free_table(rknpu_obj->sgt); kfree(rknpu_obj->sgt); } + + drm_gem_put_pages(&rknpu_obj->base, rknpu_obj->pages, true, true); } #endif @@ -641,8 +640,9 @@ struct rknpu_gem_object *rknpu_gem_object_create(struct drm_device *drm, if (rknpu_obj) LOG_DEBUG( "created dma addr: %pad, cookie: %p, ddr size: %lu, sram size: %lu, attrs: %#lx, flags: %#x\n", - &rknpu_obj->dma_addr, rknpu_obj->cookie, rknpu_obj->size, - rknpu_obj->sram_size, rknpu_obj->dma_attrs, rknpu_obj->flags); + &rknpu_obj->dma_addr, rknpu_obj->cookie, + rknpu_obj->size, rknpu_obj->sram_size, + rknpu_obj->dma_attrs, rknpu_obj->flags); return rknpu_obj; @@ -1233,7 +1233,8 @@ int rknpu_gem_sync_ioctl(struct drm_device *dev, void *data, length = args->size; offset = args->offset; - if (IS_ENABLED(CONFIG_ROCKCHIP_RKNPU_SRAM) && rknpu_obj->sram_size > 0) { + if (IS_ENABLED(CONFIG_ROCKCHIP_RKNPU_SRAM) && + rknpu_obj->sram_size > 0) { struct drm_gem_object *obj = &rknpu_obj->base; struct rknpu_device *rknpu_dev = obj->dev->dev_private; unsigned long sram_offset = diff --git a/drivers/rknpu/rknpu_job.c b/drivers/rknpu/rknpu_job.c index 9e50467b22ec..c34be432889e 100644 --- a/drivers/rknpu/rknpu_job.c +++ b/drivers/rknpu/rknpu_job.c @@ -193,8 +193,8 @@ static inline int rknpu_job_wait(struct rknpu_job *job) args->task_counter = 0; rknpu_core_base = rknpu_dev->base[core_index]; if (args->flags & RKNPU_JOB_PC) { - uint32_t task_status = - REG_READ(RKNPU_OFFSET_PC_TASK_STATUS); + uint32_t task_status = REG_READ( + rknpu_dev->config->pc_task_status_offset); args->task_counter = (task_status & rknpu_dev->config->pc_task_number_mask); @@ -490,7 +490,7 @@ static void rknpu_job_abort(struct rknpu_job *job) job->flags, REG_READ(RKNPU_OFFSET_INT_STATUS), REG_READ(RKNPU_OFFSET_INT_RAW_STATUS), job->int_mask[core_index], - (REG_READ(RKNPU_OFFSET_PC_TASK_STATUS) & + (REG_READ(rknpu_dev->config->pc_task_status_offset) & rknpu_dev->config->pc_task_number_mask), ktime_to_us(ktime_sub(ktime_get(), job->timestamp))); rknpu_soft_reset(rknpu_dev); @@ -560,7 +560,7 @@ static inline irqreturn_t rknpu_irq_handler(int irq, void *data, int core_index) "invalid irq status: %#x, raw status: %#x, require mask: %#x, task counter: %#x\n", status, REG_READ(RKNPU_OFFSET_INT_RAW_STATUS), job->int_mask[core_index], - (REG_READ(RKNPU_OFFSET_PC_TASK_STATUS) & + (REG_READ(rknpu_dev->config->pc_task_status_offset) & rknpu_dev->config->pc_task_number_mask)); REG_WRITE(RKNPU_INT_CLEAR, RKNPU_OFFSET_INT_CLEAR); return IRQ_HANDLED; @@ -779,7 +779,7 @@ int rknpu_get_hw_version(struct rknpu_device *rknpu_dev, uint32_t *version) return -EINVAL; *version = REG_READ(RKNPU_OFFSET_VERSION) + - REG_READ(RKNPU_OFFSET_VERSION_NUM); + (REG_READ(RKNPU_OFFSET_VERSION_NUM) & 0xffff); return 0; } From c84d1a60a854577d6805a31fb7ec5a7289a8331c Mon Sep 17 00:00:00 2001 From: Felix Zeng Date: Thu, 2 Feb 2023 14:29:07 +0800 Subject: [PATCH 036/258] driver: rknpu: Update rknpu driver, version: 0.8.5 * Fix rk3562 bw clear bug * Fix failed submit errors in the case of multi-core multi-threading Signed-off-by: Felix Zeng Change-Id: Id5ae389bb78697d0ef7a8f3e476f1733422fe649 --- drivers/rknpu/include/rknpu_drv.h | 5 +++-- drivers/rknpu/rknpu_drv.c | 20 ++++++++++++-------- drivers/rknpu/rknpu_job.c | 31 +++++++++++++++++++++++++------ 3 files changed, 40 insertions(+), 16 deletions(-) diff --git a/drivers/rknpu/include/rknpu_drv.h b/drivers/rknpu/include/rknpu_drv.h index cd881d91933f..67da03cb63bb 100644 --- a/drivers/rknpu/include/rknpu_drv.h +++ b/drivers/rknpu/include/rknpu_drv.h @@ -30,10 +30,10 @@ #define DRIVER_NAME "rknpu" #define DRIVER_DESC "RKNPU driver" -#define DRIVER_DATE "20221110" +#define DRIVER_DATE "20230202" #define DRIVER_MAJOR 0 #define DRIVER_MINOR 8 -#define DRIVER_PATCHLEVEL 3 +#define DRIVER_PATCHLEVEL 5 #define LOG_TAG "RKNPU" @@ -67,6 +67,7 @@ struct rknpu_config { __u32 pc_task_number_bits; __u32 pc_task_number_mask; __u32 pc_task_status_offset; + __u32 pc_dma_ctrl; __u32 bw_enable; const struct rknpu_irqs_data *irqs; const struct rknpu_reset_data *resets; diff --git a/drivers/rknpu/rknpu_drv.c b/drivers/rknpu/rknpu_drv.c index 6316bd39f1f3..bbcf19af8794 100644 --- a/drivers/rknpu/rknpu_drv.c +++ b/drivers/rknpu/rknpu_drv.c @@ -111,6 +111,7 @@ static const struct rknpu_config rk356x_rknpu_config = { .pc_task_number_bits = 12, .pc_task_number_mask = 0xfff, .pc_task_status_offset = 0x3c, + .pc_dma_ctrl = 0, .bw_enable = 1, .irqs = rknpu_irqs, .resets = rknpu_resets, @@ -126,6 +127,7 @@ static const struct rknpu_config rk3588_rknpu_config = { .pc_task_number_bits = 12, .pc_task_number_mask = 0xfff, .pc_task_status_offset = 0x3c, + .pc_dma_ctrl = 0, .bw_enable = 0, .irqs = rk3588_npu_irqs, .resets = rk3588_npu_resets, @@ -141,6 +143,7 @@ static const struct rknpu_config rv1106_rknpu_config = { .pc_task_number_bits = 16, .pc_task_number_mask = 0xffff, .pc_task_status_offset = 0x3c, + .pc_dma_ctrl = 0, .bw_enable = 1, .irqs = rknpu_irqs, .resets = rknpu_resets, @@ -156,6 +159,7 @@ static const struct rknpu_config rk3562_rknpu_config = { .pc_task_number_bits = 16, .pc_task_number_mask = 0xffff, .pc_task_status_offset = 0x48, + .pc_dma_ctrl = 1, .bw_enable = 1, .irqs = rknpu_irqs, .resets = rknpu_resets, @@ -1127,7 +1131,7 @@ static struct devfreq_cooling_power npu_cooling_power = { #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE static int rk3588_npu_get_soc_info(struct device *dev, struct device_node *np, - int *bin, int *process) + int *bin, int *process) { int ret = 0; u8 value = 0; @@ -1137,11 +1141,11 @@ static int rk3588_npu_get_soc_info(struct device *dev, struct device_node *np, if (of_property_match_string(np, "nvmem-cell-names", "specification_serial_number") >= 0) { - ret = rockchip_nvmem_cell_read_u8(np, - "specification_serial_number", - &value); + ret = rockchip_nvmem_cell_read_u8( + np, "specification_serial_number", &value); if (ret) { - dev_err(dev, + LOG_DEV_ERROR( + dev, "Failed to get specification_serial_number\n"); return ret; } @@ -1154,13 +1158,13 @@ static int rk3588_npu_get_soc_info(struct device *dev, struct device_node *np, } if (*bin < 0) *bin = 0; - dev_info(dev, "bin=%d\n", *bin); + LOG_DEV_INFO(dev, "bin=%d\n", *bin); return ret; } static int rk3588_npu_set_soc_info(struct device *dev, struct device_node *np, - int bin, int process, int volt_sel) + int bin, int process, int volt_sel) { struct opp_table *opp_table; u32 supported_hw[2]; @@ -1179,7 +1183,7 @@ static int rk3588_npu_set_soc_info(struct device *dev, struct device_node *np, supported_hw[1] = BIT(volt_sel); opp_table = dev_pm_opp_set_supported_hw(dev, supported_hw, 2); if (IS_ERR(opp_table)) { - dev_err(dev, "failed to set supported opp\n"); + LOG_DEV_ERROR(dev, "failed to set supported opp\n"); return PTR_ERR(opp_table); } diff --git a/drivers/rknpu/rknpu_job.c b/drivers/rknpu/rknpu_job.c index c34be432889e..6be7824a90ce 100644 --- a/drivers/rknpu/rknpu_job.c +++ b/drivers/rknpu/rknpu_job.c @@ -162,6 +162,7 @@ static inline int rknpu_job_wait(struct rknpu_job *job) unsigned long flags; int wait_count = 0; int ret = -EINVAL; + int i = 0; subcore_data = &rknpu_dev->subcore_datas[core_index]; @@ -176,9 +177,18 @@ static inline int rknpu_job_wait(struct rknpu_job *job) if (job->in_queue[core_index]) { spin_lock_irqsave(&rknpu_dev->lock, flags); - list_del_init(&job->head[core_index]); subcore_data->task_num -= rknn_get_task_number(job, core_index); - job->in_queue[core_index] = false; + if (job->use_core_num == 1) { + list_del_init(&job->head[core_index]); + job->in_queue[core_index] = false; + } else if (job->use_core_num > 1) { + for (i = 0; i < job->use_core_num; i++) { + if (job->in_queue[i]) { + list_del_init(&job->head[i]); + job->in_queue[i] = false; + } + } + } spin_unlock_irqrestore(&rknpu_dev->lock, flags); return ret < 0 ? ret : -EINVAL; } @@ -443,16 +453,16 @@ static void rknpu_job_schedule(struct rknpu_job *job) job->run_count = 1; } + spin_lock_irqsave(&rknpu_dev->irq_lock, flags); for (i = 0; i < rknpu_dev->config->num_irqs; i++) { if (job->args->core_mask & rknpu_core_mask(i)) { subcore_data = &rknpu_dev->subcore_datas[i]; - spin_lock_irqsave(&rknpu_dev->irq_lock, flags); list_add_tail(&job->head[i], &subcore_data->todo_list); subcore_data->task_num += rknn_get_task_number(job, i); job->in_queue[i] = true; - spin_unlock_irqrestore(&rknpu_dev->irq_lock, flags); } } + spin_unlock_irqrestore(&rknpu_dev->irq_lock, flags); for (i = 0; i < rknpu_dev->config->num_irqs; i++) { if (job->args->core_mask & rknpu_core_mask(i)) @@ -853,8 +863,17 @@ int rknpu_clear_rw_amount(struct rknpu_device *rknpu_dev) spin_lock(&rknpu_dev->lock); - REG_WRITE(0x80000101, RKNPU_OFFSET_CLR_ALL_RW_AMOUNT); - REG_WRITE(0x00000101, RKNPU_OFFSET_CLR_ALL_RW_AMOUNT); + if (rknpu_dev->config->pc_dma_ctrl) { + uint32_t pc_data_addr = REG_READ(RKNPU_OFFSET_PC_DATA_ADDR); + + REG_WRITE(0x1, RKNPU_OFFSET_PC_DATA_ADDR); + REG_WRITE(0x80000101, RKNPU_OFFSET_CLR_ALL_RW_AMOUNT); + REG_WRITE(0x00000101, RKNPU_OFFSET_CLR_ALL_RW_AMOUNT); + REG_WRITE(pc_data_addr, RKNPU_OFFSET_PC_DATA_ADDR); + } else { + REG_WRITE(0x80000101, RKNPU_OFFSET_CLR_ALL_RW_AMOUNT); + REG_WRITE(0x00000101, RKNPU_OFFSET_CLR_ALL_RW_AMOUNT); + } spin_unlock(&rknpu_dev->lock); From 89500b069145f9488df5b8c6cda99764c32f0e26 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 20 Dec 2022 19:52:05 +0800 Subject: [PATCH 037/258] clk: rockchip: link: Add gate link for rk3562 Signed-off-by: Finley Xiao Change-Id: I80165ca3ef844973349ad7560e8b3e7f51dad6fc --- drivers/clk/rockchip/clk-link.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/rockchip/clk-link.c b/drivers/clk/rockchip/clk-link.c index 8e86cc18411b..78ff9b53c165 100644 --- a/drivers/clk/rockchip/clk-link.c +++ b/drivers/clk/rockchip/clk-link.c @@ -74,6 +74,20 @@ static int register_clocks(struct rockchip_link_clk *priv, struct device *dev) return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, clk); } +static const struct rockchip_link_info rk3562_clk_gate_link_info[] = { + GATE_LINK("aclk_rga_jdec", "aclk_rga_pre", 3), + GATE_LINK("aclk_vdpu", "aclk_vdpu_pre", 5), + GATE_LINK("aclk_vepu", "aclk_vepu_pre", 3), + GATE_LINK("aclk_vi_isp", "aclk_vi", 3), + GATE_LINK("aclk_vo", "aclk_vo_pre", 3), + GATE_LINK("hclk_vepu", "hclk_vepu_pre", 4), +}; + +static const struct rockchip_link rk3562_clk_gate_link = { + .num = ARRAY_SIZE(rk3562_clk_gate_link_info), + .info = rk3562_clk_gate_link_info, +}; + static const struct rockchip_link_info rk3588_clk_gate_link_info[] = { GATE_LINK("aclk_isp1_pre", "aclk_isp1_root", 6), GATE_LINK("hclk_isp1_pre", "hclk_isp1_root", 8), @@ -105,6 +119,10 @@ static const struct rockchip_link rk3588_clk_gate_link = { }; static const struct of_device_id rockchip_clk_link_of_match[] = { + { + .compatible = "rockchip,rk3562-clock-gate-link", + .data = (void *)&rk3562_clk_gate_link, + }, { .compatible = "rockchip,rk3588-clock-gate-link", .data = (void *)&rk3588_clk_gate_link, From 25fad519b37c42768e43384daa9a15400e96b0d7 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Wed, 3 Aug 2022 09:05:30 +0800 Subject: [PATCH 038/258] media: rockchip: vicap support rk3562 Signed-off-by: Zefa Chen Change-Id: I47d5bba77b694f9135ff9a71e80a00030d631e23 --- drivers/media/platform/rockchip/cif/dev.c | 52 ++++++--- drivers/media/platform/rockchip/cif/hw.c | 100 +++++++++++++++++- drivers/media/platform/rockchip/cif/hw.h | 1 + .../media/platform/rockchip/cif/mipi-csi2.c | 14 +++ .../media/platform/rockchip/cif/mipi-csi2.h | 2 + 5 files changed, 156 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/dev.c b/drivers/media/platform/rockchip/cif/dev.c index e52cd6a222d2..b34785b4a83b 100644 --- a/drivers/media/platform/rockchip/cif/dev.c +++ b/drivers/media/platform/rockchip/cif/dev.c @@ -632,10 +632,16 @@ void rkcif_write_register(struct rkcif_device *dev, if (dev->inf_id == RKCIF_MIPI_LVDS && index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 && index <= CIF_REG_MIPI_ON_PAD) { - if (dev->chip_id == CHIP_RK3588_CIF) + if (dev->chip_id == CHIP_RK3588_CIF) { csi_offset = dev->csi_host_idx * 0x100; - else if (dev->chip_id == CHIP_RV1106_CIF) + } else if (dev->chip_id == CHIP_RV1106_CIF) { csi_offset = dev->csi_host_idx * 0x200; + } else if (dev->chip_id == CHIP_RK3562_CIF) { + if (dev->csi_host_idx < 3) + csi_offset = dev->csi_host_idx * 0x200; + else + csi_offset = 0x500; + } } if (index < CIF_REG_INDEX_MAX) { if (index == CIF_REG_DVP_CTRL || reg->offset != 0x0) @@ -658,10 +664,16 @@ void rkcif_write_register_or(struct rkcif_device *dev, if (dev->inf_id == RKCIF_MIPI_LVDS && index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 && index <= CIF_REG_MIPI_ON_PAD) { - if (dev->chip_id == CHIP_RK3588_CIF) + if (dev->chip_id == CHIP_RK3588_CIF) { csi_offset = dev->csi_host_idx * 0x100; - else if (dev->chip_id == CHIP_RV1106_CIF) + } else if (dev->chip_id == CHIP_RV1106_CIF) { csi_offset = dev->csi_host_idx * 0x200; + } else if (dev->chip_id == CHIP_RK3562_CIF) { + if (dev->csi_host_idx < 3) + csi_offset = dev->csi_host_idx * 0x200; + else + csi_offset = 0x500; + } } if (index < CIF_REG_INDEX_MAX) { @@ -688,10 +700,16 @@ void rkcif_write_register_and(struct rkcif_device *dev, if (dev->inf_id == RKCIF_MIPI_LVDS && index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 && index <= CIF_REG_MIPI_ON_PAD) { - if (dev->chip_id == CHIP_RK3588_CIF) + if (dev->chip_id == CHIP_RK3588_CIF) { csi_offset = dev->csi_host_idx * 0x100; - else if (dev->chip_id == CHIP_RV1106_CIF) + } else if (dev->chip_id == CHIP_RV1106_CIF) { csi_offset = dev->csi_host_idx * 0x200; + } else if (dev->chip_id == CHIP_RK3562_CIF) { + if (dev->csi_host_idx < 3) + csi_offset = dev->csi_host_idx * 0x200; + else + csi_offset = 0x500; + } } if (index < CIF_REG_INDEX_MAX) { @@ -718,10 +736,16 @@ unsigned int rkcif_read_register(struct rkcif_device *dev, if (dev->inf_id == RKCIF_MIPI_LVDS && index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 && index <= CIF_REG_MIPI_ON_PAD) { - if (dev->chip_id == CHIP_RK3588_CIF) + if (dev->chip_id == CHIP_RK3588_CIF) { csi_offset = dev->csi_host_idx * 0x100; - else if (dev->chip_id == CHIP_RV1106_CIF) + } else if (dev->chip_id == CHIP_RV1106_CIF) { csi_offset = dev->csi_host_idx * 0x200; + } else if (dev->chip_id == CHIP_RK3562_CIF) { + if (dev->csi_host_idx < 3) + csi_offset = dev->csi_host_idx * 0x200; + else + csi_offset = 0x500; + } } if (index < CIF_REG_INDEX_MAX) { @@ -1300,7 +1324,8 @@ static int rkcif_create_link(struct rkcif_device *dev, } } if (dev->chip_id == CHIP_RK3588_CIF || - dev->chip_id == CHIP_RV1106_CIF) { + dev->chip_id == CHIP_RV1106_CIF || + dev->chip_id == CHIP_RK3562_CIF) { for (id = 0; id < stream_num; id++) { source_entity = &linked_sensor.sd->entity; sink_entity = &dev->scale_vdev[id].vnode.vdev.entity; @@ -1660,7 +1685,8 @@ static int rkcif_register_platform_subdevs(struct rkcif_device *cif_dev) } if (cif_dev->chip_id == CHIP_RK3588_CIF || - cif_dev->chip_id == CHIP_RV1106_CIF) { + cif_dev->chip_id == CHIP_RV1106_CIF || + cif_dev->chip_id == CHIP_RK3562_CIF) { ret = rkcif_register_scale_vdevs(cif_dev, RKCIF_MAX_SCALE_CH, true); if (ret < 0) { @@ -1687,7 +1713,8 @@ static int rkcif_register_platform_subdevs(struct rkcif_device *cif_dev) err_unreg_stream_vdev: rkcif_unregister_stream_vdevs(cif_dev, stream_num); if (cif_dev->chip_id == CHIP_RK3588_CIF || - cif_dev->chip_id == CHIP_RV1106_CIF) { + cif_dev->chip_id == CHIP_RV1106_CIF || + cif_dev->chip_id == CHIP_RK3562_CIF) { rkcif_unregister_scale_vdevs(cif_dev, RKCIF_MAX_SCALE_CH); rkcif_unregister_tools_vdevs(cif_dev, RKCIF_MAX_TOOLS_CH); } @@ -1899,7 +1926,8 @@ int rkcif_plat_init(struct rkcif_device *cif_dev, struct device_node *node, int } if (cif_dev->chip_id == CHIP_RK3588_CIF || - cif_dev->chip_id == CHIP_RV1106_CIF) { + cif_dev->chip_id == CHIP_RV1106_CIF || + cif_dev->chip_id == CHIP_RK3562_CIF) { rkcif_init_scale_vdev(cif_dev, RKCIF_SCALE_CH0); rkcif_init_scale_vdev(cif_dev, RKCIF_SCALE_CH1); rkcif_init_scale_vdev(cif_dev, RKCIF_SCALE_CH2); diff --git a/drivers/media/platform/rockchip/cif/hw.c b/drivers/media/platform/rockchip/cif/hw.c index fbbc797c5f29..f9e621852e99 100644 --- a/drivers/media/platform/rockchip/cif/hw.c +++ b/drivers/media/platform/rockchip/cif/hw.c @@ -865,6 +865,88 @@ static const struct cif_reg rv1106_cif_regs[] = { [CIF_REG_GRF_CIFIO_VENC] = CIF_REG(RV1106_CIF_GRF_VENC_WRAPPER), }; +static const char * const rk3562_cif_clks[] = { + "aclk_cif", + "hclk_cif", + "dclk_cif", +}; + +static const char * const rk3562_cif_rsts[] = { + "rst_cif_a", + "rst_cif_h", + "rst_cif_d", + "rst_cif_i0", + "rst_cif_i1", + "rst_cif_i2", + "rst_cif_i3", +}; + +static const struct cif_reg rk3562_cif_regs[] = { + [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0), + [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1), + [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0), + [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1), + [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0), + [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1), + [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0), + [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1), + [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL), + [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0), + [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0), + [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0), + [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0), + [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0), + [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1), + [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1), + [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1), + [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1), + [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1), + [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2), + [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2), + [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2), + [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2), + [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2), + [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3), + [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3), + [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3), + [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3), + [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3), + [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN), + [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT), + [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1), + [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3), + [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1), + [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3), + [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START), + [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START), + [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START), + [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START), + [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0), + [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1), + [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2), + [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3), + [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0), + [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1), + [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2), + [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3), + [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD), + + [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL), + [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN), + [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST), + + [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL), + [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL), + [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0), + [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0), + [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0), + [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0), + + [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL), + [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE), + [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP), +}; + static const struct rkcif_hw_match_data px30_cif_match_data = { .chip_id = CHIP_PX30_CIF, .clks = px30_cif_clks, @@ -964,6 +1046,15 @@ static const struct rkcif_hw_match_data rv1106_cif_match_data = { .cif_regs = rv1106_cif_regs, }; +static const struct rkcif_hw_match_data rk3562_cif_match_data = { + .chip_id = CHIP_RK3562_CIF, + .clks = rk3562_cif_clks, + .clks_num = ARRAY_SIZE(rk3562_cif_clks), + .rsts = rk3562_cif_rsts, + .rsts_num = ARRAY_SIZE(rk3562_cif_rsts), + .cif_regs = rk3562_cif_regs, +}; + static const struct of_device_id rkcif_plat_of_match[] = { #ifdef CONFIG_CPU_PX30 { @@ -1028,6 +1119,12 @@ static const struct of_device_id rkcif_plat_of_match[] = { .compatible = "rockchip,rv1106-cif", .data = &rv1106_cif_match_data, }, +#endif +#ifdef CONFIG_CPU_RK3562 + { + .compatible = "rockchip,rk3562-cif", + .data = &rk3562_cif_match_data, + }, #endif {}, }; @@ -1318,7 +1415,8 @@ static void rkcif_hw_shutdown(struct platform_device *pdev) return; if (cif_hw->chip_id == CHIP_RK3588_CIF || - cif_hw->chip_id == CHIP_RV1106_CIF) { + cif_hw->chip_id == CHIP_RV1106_CIF || + cif_hw->chip_id == CHIP_RK3562_CIF) { write_cif_reg(cif_hw->base_addr, 0, 0); } else { for (i = 0; i < cif_hw->dev_num; i++) { diff --git a/drivers/media/platform/rockchip/cif/hw.h b/drivers/media/platform/rockchip/cif/hw.h index 73c05e789a40..c8fb955f7aff 100644 --- a/drivers/media/platform/rockchip/cif/hw.h +++ b/drivers/media/platform/rockchip/cif/hw.h @@ -102,6 +102,7 @@ enum rkcif_chip_id { CHIP_RK3568_CIF, CHIP_RK3588_CIF, CHIP_RV1106_CIF, + CHIP_RK3562_CIF, }; struct rkcif_hw_match_data { diff --git a/drivers/media/platform/rockchip/cif/mipi-csi2.c b/drivers/media/platform/rockchip/cif/mipi-csi2.c index 1b80309d9af9..75e40a79c12c 100644 --- a/drivers/media/platform/rockchip/cif/mipi-csi2.c +++ b/drivers/media/platform/rockchip/cif/mipi-csi2.c @@ -812,6 +812,11 @@ static irqreturn_t rk_csirx_irq1_handler(int irq, void *ctx) snprintf(err_str, CSI_ERRSTR_LEN, "%s(ecc2)", err_str); } + if (val & CSIHOST_ERR1_ERR_CTRL) { + csi2_find_err_vc((val >> 16) & 0xf, vc_info); + snprintf(err_str, CSI_ERRSTR_LEN, "%s(ctrl,vc:%s) ", err_str, vc_info); + } + pr_err("%s ERR1:0x%x %s\n", csi2->dev_name, val, err_str); if (is_add_cnt) { @@ -919,6 +924,11 @@ static const struct csi2_match_data rk3588_csi2_match_data = { .num_pads = CSI2_NUM_PADS_MAX, }; +static const struct csi2_match_data rk3562_csi2_match_data = { + .chip_id = CHIP_RK3562_CSI2, + .num_pads = CSI2_NUM_PADS_MAX, +}; + static const struct of_device_id csi2_dt_ids[] = { { .compatible = "rockchip,rk1808-mipi-csi2", @@ -940,6 +950,10 @@ static const struct of_device_id csi2_dt_ids[] = { .compatible = "rockchip,rk3588-mipi-csi2", .data = &rk3588_csi2_match_data, }, + { + .compatible = "rockchip,rk3562-mipi-csi2", + .data = &rk3562_csi2_match_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, csi2_dt_ids); diff --git a/drivers/media/platform/rockchip/cif/mipi-csi2.h b/drivers/media/platform/rockchip/cif/mipi-csi2.h index 04f6301fd991..5f5a04e0c608 100644 --- a/drivers/media/platform/rockchip/cif/mipi-csi2.h +++ b/drivers/media/platform/rockchip/cif/mipi-csi2.h @@ -61,6 +61,7 @@ #define CSIHOST_ERR1_ERR_FRM_DATA 0x0000f000 #define CSIHOST_ERR1_ERR_CRC 0x0f000000 #define CSIHOST_ERR1_ERR_ECC2 0x10000000 +#define CSIHOST_ERR1_ERR_CTRL 0x000f0000 #define CSIHOST_ERR2_PHYERR_ESC 0x0000000f #define CSIHOST_ERR2_PHYERR_SOTHS 0x000000f0 @@ -87,6 +88,7 @@ enum rkcsi2_chip_id { CHIP_RV1126_CSI2, CHIP_RK3568_CSI2, CHIP_RK3588_CSI2, + CHIP_RK3562_CSI2, }; enum csi2_pads { From 6d31ebb3ecd0e5d8774596479c1fd87bd2aa74fa Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Tue, 3 Jan 2023 15:45:13 +0800 Subject: [PATCH 039/258] phy: rockchip: csi2-dphy: support rk3562 Signed-off-by: Zefa Chen Change-Id: I938047b37e2feba021a19f953f859679468fee1a --- .../rockchip/phy-rockchip-csi2-dphy-common.h | 1 + .../phy/rockchip/phy-rockchip-csi2-dphy-hw.c | 126 +++++++++++++++--- drivers/phy/rockchip/phy-rockchip-csi2-dphy.c | 9 ++ 3 files changed, 121 insertions(+), 15 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h index 9d4ea147c9c3..0ec812bcb014 100644 --- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h +++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h @@ -19,6 +19,7 @@ enum csi2_dphy_chip_id { CHIP_ID_RK3588 = 0x1, CHIP_ID_RK3588_DCPHY = 0x2, CHIP_ID_RV1106 = 0x3, + CHIP_ID_RK3562 = 0x4, }; enum csi2_dphy_rx_pads { diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c index 527962352337..1440844f0185 100644 --- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c +++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c @@ -24,6 +24,10 @@ #include #include "phy-rockchip-csi2-dphy-common.h" +/* RK3562 DPHY GRF REG OFFSET */ +#define RK3562_GRF_VI_CON0 (0x0520) +#define RK3562_GRF_VI_CON1 (0x0524) + /* GRF REG OFFSET */ #define GRF_VI_CON0 (0x0340) #define GRF_VI_CON1 (0x0344) @@ -156,6 +160,15 @@ enum grf_reg_id { /* below is for rv1106 only */ GRF_MIPI_HOST0_SEL, GRF_LVDS_HOST0_SEL, + /* below is for rk3562 */ + GRF_DPHY1_CLK_INV_SEL, + GRF_DPHY1_CLK1_INV_SEL, + GRF_DPHY1_CSI2PHY_CLKLANE1_EN, + GRF_DPHY1_CSI2PHY_FORCERXMODE, + GRF_DPHY1_CSI2PHY_CLKLANE_EN, + GRF_DPHY1_CSI2PHY_DATALANE_EN, + GRF_DPHY1_CSI2PHY_DATALANE_EN0, + GRF_DPHY1_CSI2PHY_DATALANE_EN1, }; enum csi2dphy_reg_id { @@ -422,6 +435,45 @@ static const struct csi2dphy_reg rv1106_csi2dphy_regs[] = { [CSI2PHY_CLK_INV] = CSI2PHY_REG(CSI2_DPHY_CLK_INV), }; +static const struct grf_reg rk3562_grf_dphy_regs[] = { + [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON0, 4, 0), + [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 4, 4), + [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON0, 2, 4), + [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON0, 2, 6), + [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 8), + [GRF_DPHY_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 9), + [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON0, 1, 10), + [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 11), + [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 12), + [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(RK3562_GRF_VI_CON0, 1, 13), + [GRF_DPHY1_CSI2PHY_FORCERXMODE] = GRF_REG(RK3562_GRF_VI_CON1, 4, 0), + [GRF_DPHY1_CSI2PHY_DATALANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 4, 4), + [GRF_DPHY1_CSI2PHY_DATALANE_EN0] = GRF_REG(RK3562_GRF_VI_CON1, 2, 4), + [GRF_DPHY1_CSI2PHY_DATALANE_EN1] = GRF_REG(RK3562_GRF_VI_CON1, 2, 6), + [GRF_DPHY1_CSI2PHY_CLKLANE_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 8), + [GRF_DPHY1_CLK_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 9), + [GRF_DPHY1_CSI2PHY_CLKLANE1_EN] = GRF_REG(RK3562_GRF_VI_CON1, 1, 10), + [GRF_DPHY1_CLK1_INV_SEL] = GRF_REG(RK3562_GRF_VI_CON1, 1, 11), +}; + +static const struct csi2dphy_reg rk3562_csi2dphy_regs[] = { + [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE), + [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN), + [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE), + [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN), + [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE), + [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN), + [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE), + [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN), + [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE), + [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN), + [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE), + [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN), + [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE), + [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN), + [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN), +}; + /* These tables must be sorted by .range_h ascending. */ static const struct hsfreq_range rk3568_csi2_dphy_hw_hsfreq_ranges[] = { { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06}, @@ -525,15 +577,21 @@ static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy, write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0)); write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1); - if (hw->drv_data->chip_id < CHIP_ID_RK3588) + if (hw->drv_data->chip_id != CHIP_ID_RK3588) write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val); else write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val); } else { - write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, - GENMASK(sensor->lanes - 1, 0)); - write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1); - if (hw->drv_data->chip_id < CHIP_ID_RK3588) + if (hw->drv_data->chip_id <= CHIP_ID_RK3588) { + write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, + GENMASK(sensor->lanes - 1, 0)); + write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1); + } else { + write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN, + GENMASK(sensor->lanes - 1, 0)); + write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1); + } + if (hw->drv_data->chip_id != CHIP_ID_RK3588) write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val); else write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val); @@ -562,6 +620,8 @@ static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy, write_grf_reg(hw, GRF_MIPI_HOST0_SEL, 0x1); else write_grf_reg(hw, GRF_LVDS_HOST0_SEL, 0x1); + } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) { + write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val); } break; case 2: @@ -579,21 +639,37 @@ static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy, } else if (hw->drv_data->chip_id == CHIP_ID_RK3588) { write_sys_grf_reg(hw, GRF_DPHY_CSIHOST3_SEL, 0x1); write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val); + } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) { + write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val); } break; case 4: - write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val); - write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0); - write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0, - GENMASK(sensor->lanes - 1, 0)); - write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1); + if (hw->drv_data->chip_id == CHIP_ID_RK3588) { + write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val); + write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0); + write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0, + GENMASK(sensor->lanes - 1, 0)); + write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1); + } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) { + write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val); + write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN0, + GENMASK(sensor->lanes - 1, 0)); + write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE_EN, 0x1); + } break; case 5: - write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val); - write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1); - write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1, - GENMASK(sensor->lanes - 1, 0)); - write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1); + if (hw->drv_data->chip_id == CHIP_ID_RK3588) { + write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val); + write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1); + write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1, + GENMASK(sensor->lanes - 1, 0)); + write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1); + } else if (hw->drv_data->chip_id == CHIP_ID_RK3562) { + write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val); + write_grf_reg(hw, GRF_DPHY1_CSI2PHY_DATALANE_EN1, + GENMASK(sensor->lanes - 1, 0)); + write_grf_reg(hw, GRF_DPHY1_CSI2PHY_CLKLANE1_EN, 0x1); + } break; default: break; @@ -822,6 +898,11 @@ static void rv1106_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw) hw->grf_regs = rv1106_grf_dphy_regs; } +static void rk3562_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw) +{ + hw->grf_regs = rk3562_grf_dphy_regs; +} + static const struct dphy_hw_drv_data rk3568_csi2_dphy_hw_drv_data = { .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges, .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges), @@ -855,6 +936,17 @@ static const struct dphy_hw_drv_data rv1106_csi2_dphy_hw_drv_data = { .stream_off = csi2_dphy_hw_stream_off, }; +static const struct dphy_hw_drv_data rk3562_csi2_dphy_hw_drv_data = { + .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges, + .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges), + .csi2dphy_regs = rk3562_csi2dphy_regs, + .grf_regs = rk3562_grf_dphy_regs, + .individual_init = rk3562_csi2_dphy_hw_individual_init, + .chip_id = CHIP_ID_RK3562, + .stream_on = csi2_dphy_hw_stream_on, + .stream_off = csi2_dphy_hw_stream_off, +}; + static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = { { .compatible = "rockchip,rk3568-csi2-dphy-hw", @@ -868,6 +960,10 @@ static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = { .compatible = "rockchip,rv1106-csi2-dphy-hw", .data = &rv1106_csi2_dphy_hw_drv_data, }, + { + .compatible = "rockchip,rk3562-csi2-dphy-hw", + .data = &rk3562_csi2_dphy_hw_drv_data, + }, {} }; MODULE_DEVICE_TABLE(of, rockchip_csi2_dphy_hw_match_id); diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c b/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c index d6980d49787d..7e53e599314a 100644 --- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c +++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c @@ -697,6 +697,11 @@ static struct dphy_drv_data rv1106_dphy_drv_data = { .vendor = PHY_VENDOR_INNO, }; +static struct dphy_drv_data rk3562_dphy_drv_data = { + .dev_name = "csi2dphy", + .vendor = PHY_VENDOR_INNO, +}; + static const struct of_device_id rockchip_csi2_dphy_match_id[] = { { .compatible = "rockchip,rk3568-csi2-dphy", @@ -710,6 +715,10 @@ static const struct of_device_id rockchip_csi2_dphy_match_id[] = { .compatible = "rockchip,rv1106-csi2-dphy", .data = &rv1106_dphy_drv_data, }, + { + .compatible = "rockchip,rk3562-csi2-dphy", + .data = &rk3562_dphy_drv_data, + }, {} }; MODULE_DEVICE_TABLE(of, rockchip_csi2_dphy_match_id); From e7394324b8955069d4790e108e139450a4f76a8d Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Thu, 12 Jan 2023 17:34:14 +0800 Subject: [PATCH 040/258] mmc: sdhci-of-dwcmshc: add config for rk3562 Signed-off-by: Yifeng Zhao Change-Id: I5b15d23c3e02d1f172623cb03e61bc0d1561c544 --- drivers/mmc/host/sdhci-of-dwcmshc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index ce37d8173adb..251e9d3cc2d8 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -536,6 +536,16 @@ static const struct dwcmshc_driver_data rk3528_drvdata = { .ddr50_strbin_delay_num = 10, }; +static const struct dwcmshc_driver_data rk3562_drvdata = { + .pdata = &sdhci_dwcmshc_rk35xx_pdata, + .flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_RXCLK_SW_TUNING | RK_RXCLK_NO_INVERTER, + .hs200_tx_tap = 12, + .hs400_tx_tap = 6, + .hs400_cmd_tap = 6, + .hs400_strbin_tap = 1, + .ddr50_strbin_delay_num = 10, +}; + static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { { .compatible = "rockchip,rk3588-dwcmshc", @@ -549,6 +559,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { .compatible = "rockchip,rk3528-dwcmshc", .data = &rk3528_drvdata, }, + { + .compatible = "rockchip,rk3562-dwcmshc", + .data = &rk3562_drvdata, + }, { .compatible = "snps,dwcmshc-sdhci", .data = &dwcmshc_drvdata, From 889250e4494feb7c8a5bed3ef5431fbb4356241d Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Wed, 1 Feb 2023 17:50:27 +0800 Subject: [PATCH 041/258] drm/rockchip: Kconfig: select vop2 if RK3528 or RK3562 Change-Id: I55168a6a9e635bdbb8005331fc05a3266be0e968 Signed-off-by: Nickey Yang --- drivers/gpu/drm/rockchip/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index b772476ee7c0..8d5dda562c88 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -61,11 +61,10 @@ config ROCKCHIP_VOP config ROCKCHIP_VOP2 bool "Rockchip VOP2 driver" - default y if CPU_RK3568 || CPU_RK3588 + default y if CPU_RK3528 || CPU_RK3562 || CPU_RK3568 || CPU_RK3588 help This selects support for the VOP2 driver. If you want to - enable VOP2 on RK3566 and RK3568 based SoC, you should - select this option. + enable VOP2 on Rockchip SoC, you should select this option. config ROCKCHIP_ANALOGIX_DP bool "Rockchip specific extensions for Analogix DP driver" From 6a240f097459fc96787f897d5240094c7f18c344 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Wed, 11 Jan 2023 19:36:39 +0800 Subject: [PATCH 042/258] drm/rockchip: vop3: add bt1120/bt656 support for rk3562 Signed-off-by: Damon Ding Signed-off-by: Sandy Huang Change-Id: I61ff4d3398b20697e461aca6961992703b40d8db --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 16 +++++++++++----- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 ++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 2 +- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index f6a9239993a2..f5a6c13cdca1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -6145,7 +6145,7 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) if (mode->hdisplay > vp_data->max_output.width) return MODE_BAD_HVALUE; - if (mode->flags & DRM_MODE_FLAG_DBLCLK) + if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656) request_clock *= 2; aclk_rate = clk_get_rate(vop2->aclk) / 1000; @@ -6379,10 +6379,11 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_connector *connector; struct drm_connector_list_iter conn_iter; struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode); + struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(new_crtc_state); drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); - if (mode->flags & DRM_MODE_FLAG_DBLCLK) + if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656) adj_mode->crtc_clock *= 2; drm_connector_list_iter_begin(crtc->dev, &conn_iter); @@ -7281,7 +7282,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state vop2_lock(vop2); DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x) for vp%d dclk: %d\n", - hdisplay, vdisplay, interlaced ? "i" : "p", + hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p", drm_mode_vrefresh(adjusted_mode), vcstate->output_type, vcstate->output_if, vp->id, adjusted_mode->crtc_clock * 1000); @@ -7355,7 +7356,12 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state if (ret < 0) goto out; - VOP_CTRL_SET(vop2, bt656_en, 1); + if (vop2->version == VOP_VERSION_RK3588) { + VOP_CTRL_SET(vop2, bt656_en, 1); + } else { + VOP_CTRL_SET(vop2, rgb_en, 1); + VOP_CTRL_SET(vop2, bt656_en, 1); + } VOP_CTRL_SET(vop2, rgb_mux, vp_data->id); VOP_GRF_SET(vop2, sys_grf, grf_bt656_clk_inv, !dclk_inv); VOP_CTRL_SET(vop2, bt656_dclk_pol, !dclk_inv); @@ -7576,7 +7582,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state if (vcstate->max_refresh_rate && vcstate->min_refresh_rate) VOP_MODULE_SET(vop2, vp, sw_dsp_vtotal_imd, 1); - if (vop2->version == VOP_VERSION_RK3568) { + if (vop2->version == VOP_VERSION_RK3568 || vop2->version == VOP_VERSION_RK3562) { if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656) VOP_MODULE_SET(vop2, vp, core_dclk_div, 1); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 2f09c2728933..724072eb33fa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -3469,6 +3469,8 @@ static const struct vop2_ctrl rk3528_vop_ctrl = { }; static const struct vop_grf_ctrl rk3562_sys_grf_ctrl = { + .grf_bt656_clk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3), + .grf_bt1120_clk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3), .grf_dclk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3), }; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 0cfa38fcb969..56a34972b19b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1039,7 +1039,7 @@ #define RV1126_GRF_IOFUNC_CON3 0x1026c -#define RK3562_GRF_IOC_VO_IO_CON 0x00500 +#define RK3562_GRF_IOC_VO_IO_CON 0x10500 /* rk3568 vop registers definition */ From 6e6b592df0e6343d30aabbead0a29a2ecf99724c Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Thu, 2 Feb 2023 14:32:28 +0800 Subject: [PATCH 043/258] drm/rockchip: vop2: just init extend clk on rk3588 Signed-off-by: Nickey Yang Change-Id: Id206084a9b26a312aa65f4c60f2ce30e5741575c --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index f5a6c13cdca1..572719fac06f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -3965,7 +3965,7 @@ static int vop2_extend_clk_init(struct vop2 *vop2) INIT_LIST_HEAD(&vop2->extend_clk_list_head); - if (vop2->version < VOP_VERSION_RK3588) + if (vop2->version != VOP_VERSION_RK3588) return 0; for (i = 0; i < ARRAY_SIZE(extend_clk_name); i++) { From 8815d92a814ce0720cb82d456d921664a308a8cb Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Mon, 30 Jan 2023 17:15:44 +0800 Subject: [PATCH 044/258] drm/rockchip: vop2: add support output width and dclk prop userspace can check the crtc capability according the following conditions: 1. drmModeModeInfo.hdisplay <= OUTPUT_WIDTH 2. drmModeModeInfo.htotal * drmModeModeInfo.vtotal * drmModeModeInfo.vrefresh <= OUTPUT_DCLK Signed-off-by: Sandy Huang Change-Id: Iaa8f5b324ddecb046918c81b6e569d469f543f72 --- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 34 ++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 26 +++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index e002d6bf3041..92967fd48363 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -398,6 +398,40 @@ int rockchip_drm_add_modes_noedid(struct drm_connector *connector) } EXPORT_SYMBOL(rockchip_drm_add_modes_noedid); +static const struct rockchip_drm_width_dclk { + int width; + u32 dclk_khz; +} rockchip_drm_dclk[] = { + {1920, 148500}, + {2048, 200000}, + {2560, 280000}, + {3840, 594000}, + {4096, 594000}, + {7680, 2376000}, +}; + +u32 rockchip_drm_get_dclk_by_width(int width) +{ + int i = 0; + u32 dclk_khz; + + for (i = 0; i < ARRAY_SIZE(rockchip_drm_dclk); i++) { + if (width == rockchip_drm_dclk[i].width) { + dclk_khz = rockchip_drm_dclk[i].dclk_khz; + break; + } + } + + if (i == ARRAY_SIZE(rockchip_drm_dclk)) { + DRM_ERROR("Can't not find %d width solution and use 148500 khz as max dclk\n", width); + + dclk_khz = 148500; + } + + return dclk_khz; +} +EXPORT_SYMBOL(rockchip_drm_get_dclk_by_width); + static int cea_db_tag(const u8 *db) { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index fbf7cd80acf5..3739d5cb4657 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -489,6 +489,7 @@ int rockchip_drm_add_modes_noedid(struct drm_connector *connector); void rockchip_drm_te_handle(struct drm_crtc *crtc); void drm_mode_convert_to_split_mode(struct drm_display_mode *mode); void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode); +u32 rockchip_drm_get_dclk_by_width(int width); #if IS_REACHABLE(CONFIG_DRM_ROCKCHIP) int rockchip_drm_get_sub_dev_type(void); u32 rockchip_drm_get_scan_line_time_ns(void); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 572719fac06f..d3fb68b94705 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -754,6 +754,14 @@ struct vop2_video_port { * @post_csc_data_prop: post csc data interaction with userspace */ struct drm_property *post_csc_data_prop; + /** + * @output_width_prop: vp max output width prop + */ + struct drm_property *output_width_prop; + /** + * @output_dclk_prop: vp max output dclk prop + */ + struct drm_property *output_dclk_prop; /** * @primary_plane_phy_id: vp primary plane phy id, the primary plane @@ -10465,6 +10473,24 @@ static int vop2_crtc_create_feature_property(struct vop2 *vop2, struct drm_crtc vp->feature_prop = prop; drm_object_attach_property(&crtc->base, vp->feature_prop, feature); + prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_WIDTH", + 0, vop2->data->vp[vp->id].max_output.width); + if (!prop) { + DRM_DEV_ERROR(vop2->dev, "create OUTPUT_WIDTH prop for vp%d failed\n", vp->id); + return -ENOMEM; + } + vp->output_width_prop = prop; + drm_object_attach_property(&crtc->base, vp->output_width_prop, 0); + + prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_DCLK", + 0, rockchip_drm_get_dclk_by_width(vop2->data->vp[vp->id].max_output.width) * 1000); + if (!prop) { + DRM_DEV_ERROR(vop2->dev, "create OUTPUT_DCLK prop for vp%d failed\n", vp->id); + return -ENOMEM; + } + vp->output_dclk_prop = prop; + drm_object_attach_property(&crtc->base, vp->output_dclk_prop, 0); + return 0; } From 20b6c50cc333db26a64a3329a71d7c9eaa69ad62 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sun, 29 Jan 2023 19:15:23 +0800 Subject: [PATCH 045/258] arm64: dts: rockchip: rk3562: set driver strength of rgb pins to level2 Signed-off-by: Damon Ding Change-Id: I3710d3529d5263e4b0646fa4ee4af5312951aae4 --- .../boot/dts/rockchip/rk3562-pinctrl.dtsi | 132 +++++++++--------- 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi index aad7b893c543..dcf7feb3f554 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi @@ -2190,152 +2190,152 @@ rgb3x8_pins_m0: rgb3x8-pins-m0 { rockchip,pins = /* vo_lcdc_clk */ - <4 RK_PB7 1 &pcfg_pull_none>, + <4 RK_PB7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d3 */ - <3 RK_PC4 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d4 */ - <3 RK_PC5 1 &pcfg_pull_none>, + <3 RK_PC5 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d5 */ - <3 RK_PC6 1 &pcfg_pull_none>, + <3 RK_PC6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d6 */ - <3 RK_PC7 1 &pcfg_pull_none>, + <3 RK_PC7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d7 */ - <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD0 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d10 */ - <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d11 */ - <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d12 */ - <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_den */ - <4 RK_PB6 1 &pcfg_pull_none>, + <4 RK_PB6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_hsync */ - <4 RK_PB4 1 &pcfg_pull_none>, + <4 RK_PB4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_vsync */ - <4 RK_PB5 1 &pcfg_pull_none>; + <4 RK_PB5 1 &pcfg_pull_none_drv_level_2>; }; /omit-if-no-ref/ rgb3x8_pins_m1: rgb3x8-pins-m1 { rockchip,pins = /* vo_lcdc_clk */ - <4 RK_PB7 1 &pcfg_pull_none>, + <4 RK_PB7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d13 */ - <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d14 */ - <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d15 */ - <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d19 */ - <3 RK_PD7 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d20 */ - <4 RK_PA0 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d21 */ - <4 RK_PA1 1 &pcfg_pull_none>, + <4 RK_PA1 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d22 */ - <4 RK_PA2 1 &pcfg_pull_none>, + <4 RK_PA2 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d23 */ - <4 RK_PA3 1 &pcfg_pull_none>, + <4 RK_PA3 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_den */ - <4 RK_PB6 1 &pcfg_pull_none>, + <4 RK_PB6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_hsync */ - <4 RK_PB4 1 &pcfg_pull_none>, + <4 RK_PB4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_vsync */ - <4 RK_PB5 1 &pcfg_pull_none>; + <4 RK_PB5 1 &pcfg_pull_none_drv_level_2>; }; /omit-if-no-ref/ rgb565_pins: rgb565-pins { rockchip,pins = /* vo_lcdc_clk */ - <4 RK_PB7 1 &pcfg_pull_none>, + <4 RK_PB7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d3 */ - <3 RK_PC4 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d4 */ - <3 RK_PC5 1 &pcfg_pull_none>, + <3 RK_PC5 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d5 */ - <3 RK_PC6 1 &pcfg_pull_none>, + <3 RK_PC6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d6 */ - <3 RK_PC7 1 &pcfg_pull_none>, + <3 RK_PC7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d7 */ - <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD0 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d10 */ - <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d11 */ - <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d12 */ - <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d13 */ - <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d14 */ - <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d15 */ - <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d19 */ - <3 RK_PD7 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d20 */ - <4 RK_PA0 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d21 */ - <4 RK_PA1 1 &pcfg_pull_none>, + <4 RK_PA1 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d22 */ - <4 RK_PA2 1 &pcfg_pull_none>, + <4 RK_PA2 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d23 */ - <4 RK_PA3 1 &pcfg_pull_none>, + <4 RK_PA3 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_den */ - <4 RK_PB6 1 &pcfg_pull_none>, + <4 RK_PB6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_hsync */ - <4 RK_PB4 1 &pcfg_pull_none>, + <4 RK_PB4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_vsync */ - <4 RK_PB5 1 &pcfg_pull_none>; + <4 RK_PB5 1 &pcfg_pull_none_drv_level_2>; }; /omit-if-no-ref/ rgb666_pins: rgb666-pins { rockchip,pins = /* vo_lcdc_clk */ - <4 RK_PB7 1 &pcfg_pull_none>, + <4 RK_PB7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d2 */ - <4 RK_PB2 1 &pcfg_pull_none>, + <4 RK_PB2 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d3 */ - <3 RK_PC4 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d4 */ - <3 RK_PC5 1 &pcfg_pull_none>, + <3 RK_PC5 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d5 */ - <3 RK_PC6 1 &pcfg_pull_none>, + <3 RK_PC6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d6 */ - <3 RK_PC7 1 &pcfg_pull_none>, + <3 RK_PC7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d7 */ - <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD0 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d10 */ - <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d11 */ - <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d12 */ - <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d13 */ - <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d14 */ - <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d15 */ - <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d18 */ - <4 RK_PB3 1 &pcfg_pull_none>, + <4 RK_PB3 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d19 */ - <3 RK_PD7 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d20 */ - <4 RK_PA0 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d21 */ - <4 RK_PA1 1 &pcfg_pull_none>, + <4 RK_PA1 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d22 */ - <4 RK_PA2 1 &pcfg_pull_none>, + <4 RK_PA2 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_d23 */ - <4 RK_PA3 1 &pcfg_pull_none>, + <4 RK_PA3 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_den */ - <4 RK_PB6 1 &pcfg_pull_none>, + <4 RK_PB6 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_hsync */ - <4 RK_PB4 1 &pcfg_pull_none>, + <4 RK_PB4 1 &pcfg_pull_none_drv_level_2>, /* vo_lcdc_vsync */ - <4 RK_PB5 1 &pcfg_pull_none>; + <4 RK_PB5 1 &pcfg_pull_none_drv_level_2>; }; }; }; From 35c61f382749f711d5bfda469dbf61307838b756 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sun, 29 Jan 2023 19:18:12 +0800 Subject: [PATCH 046/258] arm64: dts: rockchip: rk3562: move rgb node to ioc_grf node In addition, add label vp0/vp1. Signed-off-by: Damon Ding Change-Id: I208e47f48c35cd615dbff0d34cd5ddd8202a89b4 --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index dd768e8d4437..3b85a6181f5c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -777,6 +777,16 @@ }; }; }; + }; + + peri_grf: syscon@ff040000 { + compatible = "rockchip,rk3562-peri-grf", "syscon"; + reg = <0x0 0xff040000 0x0 0x10000>; + }; + + ioc_grf: syscon@ff060000 { + compatible = "rockchip,rk3562-ioc-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff060000 0x0 0x30000>; rgb: rgb { compatible = "rockchip,rk3562-rgb"; @@ -809,16 +819,6 @@ }; }; - peri_grf: syscon@ff040000 { - compatible = "rockchip,rk3562-peri-grf", "syscon"; - reg = <0x0 0xff040000 0x0 0x10000>; - }; - - ioc_grf: syscon@ff060000 { - compatible = "rockchip,rk3562-ioc-grf", "syscon"; - reg = <0x0 0xff060000 0x0 0x30000>; - }; - usbphy_grf: syscon@ff090000 { compatible = "rockchip,rk3562-usbphy-grf", "syscon"; reg = <0x0 0xff090000 0x0 0x8000>; @@ -1365,7 +1365,7 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + vp0: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -1386,7 +1386,7 @@ }; }; - port@1 { + vp1: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; From 66833cf69c36a7254c3b16064d7210986b0775b7 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sun, 29 Jan 2023 19:04:17 +0800 Subject: [PATCH 047/258] arm64: dts: rockchip: rk3562-evb: add mcu display board Signed-off-by: Damon Ding Change-Id: I294420987ceddeb6f25acbb243330842ed5b3121 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts | 241 ++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 50b429240eb4..36d2f2467473 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux-amp.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-mcu-k350c4516t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts new file mode 100644 index 000000000000..93c225312cdb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + +/ { + model = "Rockchip RK3562 EVB2 DDR4 V10 Board + RK EVB MCU PANLE DISPLAY Ext Board"; + compatible = "rockchip,rk3562-evb2-ddr4-v10-mcu-k350c4516t", "rockchip,rk3562"; +}; + +&backlight { + status = "okay"; + pwms = <&pwm9 0 25000 0>; +}; + +&dsi { + status = "disabled"; +}; + +&dsi_in_vp0 { + status = "disabled"; +}; + +/* + * The pins of pcie2x1 and rgb are multiplexed + */ +&pcie2x1 { + status = "disabled"; +}; + +&pwm9 { + status = "okay"; +}; + +&rgb { + status = "okay"; + rockchip,data-sync-bypass; + pinctrl-names = "default"; + /* + * rgb3x8_pins_m0/rgb3x8_pins_m1 for serial mcu + * rgb565_pins for parallel mcu + */ + pinctrl-0 = <&rgb565_pins>; + + /* + * 320x480 RGB/MCU screen K350C4516T + */ + mcu_panel: mcu-panel { + /* + * MEDIA_BUS_FMT_RGB888_3X8 for serial mcu + * MEDIA_BUS_FMT_RGB565_1X16 for parallel mcu + */ + bus-format = ; + backlight = <&backlight>; + bl-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + reset-value = <0>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + width-mm = <217>; + height-mm = <136>; + + // type:0 is cmd, 1 is data + panel-init-sequence = [ + //type delay num val1 val2 val3 + 00 00 01 e0 + 01 00 01 00 + 01 00 01 07 + 01 00 01 0f + 01 00 01 0d + 01 00 01 1b + 01 00 01 0a + 01 00 01 3c + 01 00 01 78 + 01 00 01 4a + 01 00 01 07 + 01 00 01 0e + 01 00 01 09 + 01 00 01 1b + 01 00 01 1e + 01 00 01 0f + 00 00 01 e1 + 01 00 01 00 + 01 00 01 22 + 01 00 01 24 + 01 00 01 06 + 01 00 01 12 + 01 00 01 07 + 01 00 01 36 + 01 00 01 47 + 01 00 01 47 + 01 00 01 06 + 01 00 01 0a + 01 00 01 07 + 01 00 01 30 + 01 00 01 37 + 01 00 01 0f + + 00 00 01 c0 + 01 00 01 10 + 01 00 01 10 + + 00 00 01 c1 + 01 00 01 41 + + 00 00 01 c5 + 01 00 01 00 + 01 00 01 22 + 01 00 01 80 + + 00 00 01 36 + 01 00 01 48 + + 00 00 01 3a //interface mode control + 01 00 01 55 //spi rgb:66(r1 r4 r5) mcu parallel: 55(r2 r3 r6) + // mcu serial: 77(r1 r3 r6) + + 00 00 01 b0 //interface mode control + 01 00 01 00 + + 00 00 01 b1 //frame rate 70hz + 01 00 01 b0 + 01 00 01 11 + 00 00 01 b4 + 01 00 01 02 + 00 00 01 B6 //RGB/MCU Interface Control + 01 00 01 02 //02 mcu, 32 rgb + 01 00 01 02 + + 00 00 01 b7 + 01 00 01 c6 + + 00 00 01 be + 01 00 01 00 + 01 00 01 04 + + 00 00 01 e9 + 01 00 01 00 + + 00 00 01 f7 + 01 00 01 a9 + 01 00 01 51 + 01 00 01 2c + 01 00 01 82 + + 00 78 01 11 + 00 32 01 29 + 00 00 01 2c + ]; + + panel-exit-sequence = [ + //type delay num val1 val2 val3 + 00 0a 01 28 + 00 78 01 10 + ]; + + display-timings { + native-mode = <&kd050fwfba002_timing>; + + kd050fwfba002_timing: timing0 { + clock-frequency = <80000000>; + hactive = <320>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <10>; + vfront-porch = <5>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&rgb_in_vp1 { + status = "disabled"; +}; + +/* + * The pins of sai0 and backlight are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + mcu-timing { + mcu-pix-total = <9>; + mcu-cs-pst = <1>; + mcu-cs-pend = <8>; + mcu-rw-pst = <2>; + mcu-rw-pend = <5>; + + mcu-hold-mode = <0>; // default set to 0 + }; +}; From 49aa54ec058cb5a68ac50da34dd2c5b0430ee572 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 31 Jan 2023 15:39:47 +0800 Subject: [PATCH 048/258] MALI: bifrost: Fix building error when disable CONFIG_MALI_BIFROST_DEVFREQ Signed-off-by: Finley Xiao Change-Id: I523b4f8e547c49e2e262fe29c7252888e0694a6c --- drivers/gpu/arm/bifrost/mali_kbase_core_linux.c | 7 +++++++ drivers/gpu/arm/bifrost/mali_kbase_defs.h | 4 ++-- .../gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c | 9 ++++++++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/arm/bifrost/mali_kbase_core_linux.c b/drivers/gpu/arm/bifrost/mali_kbase_core_linux.c index 480e693f3c61..fa094ab36b1f 100644 --- a/drivers/gpu/arm/bifrost/mali_kbase_core_linux.c +++ b/drivers/gpu/arm/bifrost/mali_kbase_core_linux.c @@ -171,6 +171,13 @@ static const struct mali_kbase_capability_def kbase_caps_table[MALI_KBASE_NUM_CA static struct mutex kbase_probe_mutex; #endif +#ifndef CONFIG_MALI_BIFROST_DEVFREQ +static inline int kbase_devfreq_opp_helper(struct dev_pm_set_opp_data *data) +{ + return -EOPNOTSUPP; +} +#endif + /** * mali_kbase_supports_cap - Query whether a kbase capability is supported * diff --git a/drivers/gpu/arm/bifrost/mali_kbase_defs.h b/drivers/gpu/arm/bifrost/mali_kbase_defs.h index 1072eac6d186..15fa0d71387a 100755 --- a/drivers/gpu/arm/bifrost/mali_kbase_defs.h +++ b/drivers/gpu/arm/bifrost/mali_kbase_defs.h @@ -1104,17 +1104,17 @@ struct kbase_device { struct rockchip_opp_info opp_info; bool is_runtime_resumed; + unsigned long current_nominal_freq; + struct monitor_dev_info *mdev_info; #ifdef CONFIG_MALI_BIFROST_DEVFREQ struct devfreq_dev_profile devfreq_profile; struct devfreq *devfreq; unsigned long current_freqs[BASE_MAX_NR_CLOCKS_REGULATORS]; - unsigned long current_nominal_freq; unsigned long current_voltages[BASE_MAX_NR_CLOCKS_REGULATORS]; u64 current_core_mask; struct kbase_devfreq_opp *devfreq_table; int num_opps; struct kbasep_pm_metrics last_devfreq_metrics; - struct monitor_dev_info *mdev_info; struct ipa_power_model_data *model_data; struct kbase_devfreq_queue_info devfreq_queue; diff --git a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c index 495bcc36b1df..c32526a86275 100755 --- a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c +++ b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c @@ -57,6 +57,13 @@ */ /*---------------------------------------------------------------------------*/ +#ifndef CONFIG_MALI_BIFROST_DEVFREQ +static inline void kbase_pm_get_dvfs_metrics(struct kbase_device *kbdev, + struct kbasep_pm_metrics *last, + struct kbasep_pm_metrics *diff) +{ +} +#endif #ifdef CONFIG_REGULATOR static int rk_pm_enable_regulator(struct kbase_device *kbdev); @@ -452,7 +459,7 @@ static ssize_t utilisation_show(struct device *dev, unsigned long period_in_us = platform->utilisation_period * 1000; u32 utilisation; struct kbasep_pm_metrics metrics_when_start; - struct kbasep_pm_metrics metrics_diff; /* between start and end. */ + struct kbasep_pm_metrics metrics_diff = {}; /* between start and end. */ u32 total_time = 0; u32 busy_time = 0; From a8c4dcb234c34c88977f14f8ad07ba5a7283bc6b Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Tue, 31 Jan 2023 17:48:04 +0800 Subject: [PATCH 049/258] phy: rockchip: mipi-rx: fix compile error when CONFIG_PM is not set Signed-off-by: Jianqun Xu Change-Id: Ieb9df05a2c71c090de9ebec2d40678dd79630f55 --- drivers/phy/rockchip/phy-rockchip-mipi-rx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-mipi-rx.c b/drivers/phy/rockchip/phy-rockchip-mipi-rx.c index c78c9e96c55f..519fc4b3c77d 100644 --- a/drivers/phy/rockchip/phy-rockchip-mipi-rx.c +++ b/drivers/phy/rockchip/phy-rockchip-mipi-rx.c @@ -925,7 +925,7 @@ static int mipidphy_s_power(struct v4l2_subdev *sd, int on) return pm_runtime_put(priv->dev); } -static int mipidphy_runtime_suspend(struct device *dev) +static int __maybe_unused mipidphy_runtime_suspend(struct device *dev) { struct media_entity *me = dev_get_drvdata(dev); struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me); @@ -940,7 +940,7 @@ static int mipidphy_runtime_suspend(struct device *dev) return 0; } -static int mipidphy_runtime_resume(struct device *dev) +static int __maybe_unused mipidphy_runtime_resume(struct device *dev) { struct media_entity *me = dev_get_drvdata(dev); struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me); From 0a6fcdbf8107dc55c13131a1da04fc887a8b8488 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Tue, 31 Jan 2023 17:44:58 +0800 Subject: [PATCH 050/258] media: i2c: fix compile error when CONFIG_PM is not set Signed-off-by: Jianqun Xu Signed-off-by: Tao Huang Change-Id: I3a9d18629c20f543b2d992d9afe62d4b1b721dae --- drivers/media/i2c/cn3927v.c | 12 ++++++++++++ drivers/media/i2c/fp5510.c | 4 ++-- drivers/media/i2c/gc2053.c | 4 ++-- drivers/media/i2c/gc2093.c | 4 ++-- drivers/media/i2c/gc2385.c | 4 ++-- drivers/media/i2c/gc4c33.c | 4 ++-- drivers/media/i2c/gc8034.c | 4 ++-- drivers/media/i2c/imx415.c | 4 ++-- drivers/media/i2c/nvp6188.c | 4 ++-- drivers/media/i2c/os04a10.c | 4 ++-- drivers/media/i2c/ov02b10.c | 4 ++-- drivers/media/i2c/ov13850.c | 4 ++-- drivers/media/i2c/ov13855.c | 4 ++-- drivers/media/i2c/ov50c40.c | 4 ++-- drivers/media/i2c/ov5695.c | 4 ++-- drivers/media/i2c/ov8858.c | 4 ++-- drivers/media/i2c/s5k3l6xx.c | 4 ++-- drivers/media/i2c/s5kjn1.c | 4 ++-- drivers/media/i2c/sc3336.c | 4 ++-- drivers/media/i2c/sc4336.c | 4 ++-- drivers/media/i2c/sc530ai.c | 4 ++-- drivers/media/i2c/thcv244.c | 4 ++-- 22 files changed, 54 insertions(+), 42 deletions(-) diff --git a/drivers/media/i2c/cn3927v.c b/drivers/media/i2c/cn3927v.c index 60b73048230c..ea76b4491946 100644 --- a/drivers/media/i2c/cn3927v.c +++ b/drivers/media/i2c/cn3927v.c @@ -664,8 +664,10 @@ static int cn3927v_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) int dac = dev_vcm->start_current; struct i2c_client *client = v4l2_get_subdevdata(sd); +#ifdef CONFIG_PM v4l2_info(sd, "%s: enter, power.usage_count(%d)!\n", __func__, atomic_read(&sd->dev->power.usage_count)); +#endif rval = pm_runtime_get_sync(sd->dev); if (rval < 0) { @@ -693,8 +695,10 @@ static int cn3927v_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) cn3927v_set_dac(dev_vcm, dac); } +#ifdef CONFIG_PM v4l2_info(sd, "%s: exit, power.usage_count(%d)!\n", __func__, atomic_read(&sd->dev->power.usage_count)); +#endif return 0; } @@ -706,8 +710,10 @@ static int cn3927v_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) unsigned int move_time; struct i2c_client *client = v4l2_get_subdevdata(sd); +#ifdef CONFIG_PM v4l2_info(sd, "%s: enter, power.usage_count(%d)!\n", __func__, atomic_read(&sd->dev->power.usage_count)); +#endif v4l2_dbg(1, debug, sd, "%s: current_lens_pos %d, current_related_pos %d\n", __func__, dev_vcm->current_lens_pos, dev_vcm->current_related_pos); @@ -734,8 +740,10 @@ static int cn3927v_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) pm_runtime_put(sd->dev); +#ifdef CONFIG_PM v4l2_info(sd, "%s: exit, power.usage_count(%d)!\n", __func__, atomic_read(&sd->dev->power.usage_count)); +#endif return 0; } @@ -1449,8 +1457,10 @@ static int __maybe_unused cn3927v_vcm_suspend(struct device *dev) struct v4l2_subdev *sd = i2c_get_clientdata(client); struct cn3927v_device *dev_vcm = sd_to_cn3927v_vcm(sd); +#ifdef CONFIG_PM v4l2_dbg(1, debug, sd, "%s: enter, power.usage_count(%d)!\n", __func__, atomic_read(&sd->dev->power.usage_count)); +#endif __cn3927v_set_power(dev_vcm, false); return 0; @@ -1462,8 +1472,10 @@ static int __maybe_unused cn3927v_vcm_resume(struct device *dev) struct v4l2_subdev *sd = i2c_get_clientdata(client); struct cn3927v_device *dev_vcm = sd_to_cn3927v_vcm(sd); +#ifdef CONFIG_PM v4l2_dbg(1, debug, sd, "%s: enter, power.usage_count(%d)!\n", __func__, atomic_read(&sd->dev->power.usage_count)); +#endif __cn3927v_set_power(dev_vcm, true); return 0; diff --git a/drivers/media/i2c/fp5510.c b/drivers/media/i2c/fp5510.c index 1f720b120eb2..5411a3e06b54 100644 --- a/drivers/media/i2c/fp5510.c +++ b/drivers/media/i2c/fp5510.c @@ -818,7 +818,7 @@ static int fp5510_remove(struct i2c_client *client) return 0; } -static int fp5510_vcm_resume(struct device *dev) +static int __maybe_unused fp5510_vcm_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -830,7 +830,7 @@ static int fp5510_vcm_resume(struct device *dev) return 0; } -static int fp5510_vcm_suspend(struct device *dev) +static int __maybe_unused fp5510_vcm_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/gc2053.c b/drivers/media/i2c/gc2053.c index d7fe4e871f98..44fa3826c79b 100644 --- a/drivers/media/i2c/gc2053.c +++ b/drivers/media/i2c/gc2053.c @@ -1283,7 +1283,7 @@ static const struct v4l2_subdev_ops gc2053_subdev_ops = { .pad = &gc2053_pad_ops, }; -static int gc2053_runtime_resume(struct device *dev) +static int __maybe_unused gc2053_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1293,7 +1293,7 @@ static int gc2053_runtime_resume(struct device *dev) return 0; } -static int gc2053_runtime_suspend(struct device *dev) +static int __maybe_unused gc2053_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/gc2093.c b/drivers/media/i2c/gc2093.c index a85a2a696bab..8082afcc91cd 100644 --- a/drivers/media/i2c/gc2093.c +++ b/drivers/media/i2c/gc2093.c @@ -1379,7 +1379,7 @@ static const struct v4l2_subdev_ops gc2093_subdev_ops = { .pad = &gc2093_pad_ops, }; -static int gc2093_runtime_resume(struct device *dev) +static int __maybe_unused gc2093_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1389,7 +1389,7 @@ static int gc2093_runtime_resume(struct device *dev) return 0; } -static int gc2093_runtime_suspend(struct device *dev) +static int __maybe_unused gc2093_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/gc2385.c b/drivers/media/i2c/gc2385.c index dffedcb55f08..1e51b346c979 100644 --- a/drivers/media/i2c/gc2385.c +++ b/drivers/media/i2c/gc2385.c @@ -729,7 +729,7 @@ static void __gc2385_power_off(struct gc2385 *gc2385) regulator_bulk_disable(GC2385_NUM_SUPPLIES, gc2385->supplies); } -static int gc2385_runtime_resume(struct device *dev) +static int __maybe_unused gc2385_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -738,7 +738,7 @@ static int gc2385_runtime_resume(struct device *dev) return __gc2385_power_on(gc2385); } -static int gc2385_runtime_suspend(struct device *dev) +static int __maybe_unused gc2385_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/gc4c33.c b/drivers/media/i2c/gc4c33.c index bd199bbfaae7..2b1563194b33 100644 --- a/drivers/media/i2c/gc4c33.c +++ b/drivers/media/i2c/gc4c33.c @@ -2084,7 +2084,7 @@ static void __gc4c33_power_off(struct gc4c33 *gc4c33) gpiod_set_value_cansleep(gc4c33->pwren_gpio, 0); } -static int gc4c33_runtime_resume(struct device *dev) +static int __maybe_unused gc4c33_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -2093,7 +2093,7 @@ static int gc4c33_runtime_resume(struct device *dev) return __gc4c33_power_on(gc4c33); } -static int gc4c33_runtime_suspend(struct device *dev) +static int __maybe_unused gc4c33_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/gc8034.c b/drivers/media/i2c/gc8034.c index b21c591110bc..63f46d152699 100644 --- a/drivers/media/i2c/gc8034.c +++ b/drivers/media/i2c/gc8034.c @@ -2611,7 +2611,7 @@ static void __gc8034_power_off(struct gc8034 *gc8034) regulator_bulk_disable(GC8034_NUM_SUPPLIES, gc8034->supplies); } -static int gc8034_runtime_resume(struct device *dev) +static int __maybe_unused gc8034_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -2620,7 +2620,7 @@ static int gc8034_runtime_resume(struct device *dev) return __gc8034_power_on(gc8034); } -static int gc8034_runtime_suspend(struct device *dev) +static int __maybe_unused gc8034_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c index f0276b812713..af500917c8ef 100644 --- a/drivers/media/i2c/imx415.c +++ b/drivers/media/i2c/imx415.c @@ -2131,7 +2131,7 @@ static void __imx415_power_off(struct imx415 *imx415) regulator_bulk_disable(IMX415_NUM_SUPPLIES, imx415->supplies); } -static int imx415_runtime_resume(struct device *dev) +static int __maybe_unused imx415_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -2140,7 +2140,7 @@ static int imx415_runtime_resume(struct device *dev) return __imx415_power_on(imx415); } -static int imx415_runtime_suspend(struct device *dev) +static int __maybe_unused imx415_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/nvp6188.c b/drivers/media/i2c/nvp6188.c index bb58c9aab72b..6bd0316101c1 100644 --- a/drivers/media/i2c/nvp6188.c +++ b/drivers/media/i2c/nvp6188.c @@ -1929,7 +1929,7 @@ err_free_handler: return ret; } -static int nvp6188_runtime_resume(struct device *dev) +static int __maybe_unused nvp6188_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1938,7 +1938,7 @@ static int nvp6188_runtime_resume(struct device *dev) return __nvp6188_power_on(nvp6188); } -static int nvp6188_runtime_suspend(struct device *dev) +static int __maybe_unused nvp6188_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/os04a10.c b/drivers/media/i2c/os04a10.c index 8eb9d961684d..5bd509f8e025 100644 --- a/drivers/media/i2c/os04a10.c +++ b/drivers/media/i2c/os04a10.c @@ -2300,7 +2300,7 @@ static void __os04a10_power_off(struct os04a10 *os04a10) usleep_range(30000, 31000); } -static int os04a10_runtime_resume(struct device *dev) +static int __maybe_unused os04a10_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -2309,7 +2309,7 @@ static int os04a10_runtime_resume(struct device *dev) return __os04a10_power_on(os04a10); } -static int os04a10_runtime_suspend(struct device *dev) +static int __maybe_unused os04a10_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/ov02b10.c b/drivers/media/i2c/ov02b10.c index 7a68a647b864..d13e34c429e0 100644 --- a/drivers/media/i2c/ov02b10.c +++ b/drivers/media/i2c/ov02b10.c @@ -923,7 +923,7 @@ static void __ov02b10_power_off(struct ov02b10 *ov02b10) regulator_bulk_disable(OV02B10_NUM_SUPPLIES, ov02b10->supplies); } -static int ov02b10_runtime_resume(struct device *dev) +static int __maybe_unused ov02b10_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -932,7 +932,7 @@ static int ov02b10_runtime_resume(struct device *dev) return __ov02b10_power_on(ov02b10); } -static int ov02b10_runtime_suspend(struct device *dev) +static int __maybe_unused ov02b10_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/ov13850.c b/drivers/media/i2c/ov13850.c index 8c5c8209e68b..f541f0a7a50a 100644 --- a/drivers/media/i2c/ov13850.c +++ b/drivers/media/i2c/ov13850.c @@ -1189,7 +1189,7 @@ static void __ov13850_power_off(struct ov13850 *ov13850) regulator_bulk_disable(OV13850_NUM_SUPPLIES, ov13850->supplies); } -static int ov13850_runtime_resume(struct device *dev) +static int __maybe_unused ov13850_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1198,7 +1198,7 @@ static int ov13850_runtime_resume(struct device *dev) return __ov13850_power_on(ov13850); } -static int ov13850_runtime_suspend(struct device *dev) +static int __maybe_unused ov13850_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/ov13855.c b/drivers/media/i2c/ov13855.c index c05c5cea46f1..5af63dca8bcc 100644 --- a/drivers/media/i2c/ov13855.c +++ b/drivers/media/i2c/ov13855.c @@ -1512,7 +1512,7 @@ static void __ov13855_power_off(struct ov13855 *ov13855) regulator_bulk_disable(OV13855_NUM_SUPPLIES, ov13855->supplies); } -static int ov13855_runtime_resume(struct device *dev) +static int __maybe_unused ov13855_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1521,7 +1521,7 @@ static int ov13855_runtime_resume(struct device *dev) return __ov13855_power_on(ov13855); } -static int ov13855_runtime_suspend(struct device *dev) +static int __maybe_unused ov13855_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/ov50c40.c b/drivers/media/i2c/ov50c40.c index 55d74c6faa75..964459796058 100644 --- a/drivers/media/i2c/ov50c40.c +++ b/drivers/media/i2c/ov50c40.c @@ -6671,7 +6671,7 @@ static void __ov50c40_power_off(struct ov50c40 *ov50c40) regulator_bulk_disable(OV50C40_NUM_SUPPLIES, ov50c40->supplies); } -static int ov50c40_runtime_resume(struct device *dev) +static int __maybe_unused ov50c40_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -6680,7 +6680,7 @@ static int ov50c40_runtime_resume(struct device *dev) return __ov50c40_power_on(ov50c40); } -static int ov50c40_runtime_suspend(struct device *dev) +static int __maybe_unused ov50c40_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/ov5695.c b/drivers/media/i2c/ov5695.c index a8e9d589bab7..f4b1409f8cf7 100644 --- a/drivers/media/i2c/ov5695.c +++ b/drivers/media/i2c/ov5695.c @@ -1105,7 +1105,7 @@ static void __ov5695_power_off(struct ov5695 *ov5695) regulator_bulk_disable(OV5695_NUM_SUPPLIES, ov5695->supplies); } -static int ov5695_runtime_resume(struct device *dev) +static int __maybe_unused ov5695_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1114,7 +1114,7 @@ static int ov5695_runtime_resume(struct device *dev) return __ov5695_power_on(ov5695); } -static int ov5695_runtime_suspend(struct device *dev) +static int __maybe_unused ov5695_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/ov8858.c b/drivers/media/i2c/ov8858.c index 1453f22a6a07..82926805f14e 100644 --- a/drivers/media/i2c/ov8858.c +++ b/drivers/media/i2c/ov8858.c @@ -2803,7 +2803,7 @@ static void __ov8858_power_off(struct ov8858 *ov8858) regulator_bulk_disable(OV8858_NUM_SUPPLIES, ov8858->supplies); } -static int ov8858_runtime_resume(struct device *dev) +static int __maybe_unused ov8858_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -2812,7 +2812,7 @@ static int ov8858_runtime_resume(struct device *dev) return __ov8858_power_on(ov8858); } -static int ov8858_runtime_suspend(struct device *dev) +static int __maybe_unused ov8858_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/s5k3l6xx.c b/drivers/media/i2c/s5k3l6xx.c index c1cb2020520a..118b93550c18 100644 --- a/drivers/media/i2c/s5k3l6xx.c +++ b/drivers/media/i2c/s5k3l6xx.c @@ -1015,7 +1015,7 @@ static void __s5k3l6xx_power_off(struct s5k3l6xx *s5k3l6xx) regulator_bulk_disable(S5K3L6XX_NUM_SUPPLIES, s5k3l6xx->supplies); } -static int s5k3l6xx_runtime_resume(struct device *dev) +static int __maybe_unused s5k3l6xx_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1024,7 +1024,7 @@ static int s5k3l6xx_runtime_resume(struct device *dev) return __s5k3l6xx_power_on(s5k3l6xx); } -static int s5k3l6xx_runtime_suspend(struct device *dev) +static int __maybe_unused s5k3l6xx_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/s5kjn1.c b/drivers/media/i2c/s5kjn1.c index 0fcc9d27017d..8f61020a1f77 100644 --- a/drivers/media/i2c/s5kjn1.c +++ b/drivers/media/i2c/s5kjn1.c @@ -1764,7 +1764,7 @@ static void __s5kjn1_power_off(struct s5kjn1 *s5kjn1) regulator_bulk_disable(S5KJN1_NUM_SUPPLIES, s5kjn1->supplies); } -static int s5kjn1_runtime_resume(struct device *dev) +static int __maybe_unused s5kjn1_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1773,7 +1773,7 @@ static int s5kjn1_runtime_resume(struct device *dev) return __s5kjn1_power_on(s5kjn1); } -static int s5kjn1_runtime_suspend(struct device *dev) +static int __maybe_unused s5kjn1_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/sc3336.c b/drivers/media/i2c/sc3336.c index afaa543bbce2..dfa19cf941ea 100644 --- a/drivers/media/i2c/sc3336.c +++ b/drivers/media/i2c/sc3336.c @@ -1216,7 +1216,7 @@ static void __sc3336_power_off(struct sc3336 *sc3336) regulator_bulk_disable(SC3336_NUM_SUPPLIES, sc3336->supplies); } -static int sc3336_runtime_resume(struct device *dev) +static int __maybe_unused sc3336_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1225,7 +1225,7 @@ static int sc3336_runtime_resume(struct device *dev) return __sc3336_power_on(sc3336); } -static int sc3336_runtime_suspend(struct device *dev) +static int __maybe_unused sc3336_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/sc4336.c b/drivers/media/i2c/sc4336.c index 6b38b190d40f..31aeebdffb3a 100644 --- a/drivers/media/i2c/sc4336.c +++ b/drivers/media/i2c/sc4336.c @@ -1033,7 +1033,7 @@ static void __sc4336_power_off(struct sc4336 *sc4336) regulator_bulk_disable(SC4336_NUM_SUPPLIES, sc4336->supplies); } -static int sc4336_runtime_resume(struct device *dev) +static int __maybe_unused sc4336_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1042,7 +1042,7 @@ static int sc4336_runtime_resume(struct device *dev) return __sc4336_power_on(sc4336); } -static int sc4336_runtime_suspend(struct device *dev) +static int __maybe_unused sc4336_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/sc530ai.c b/drivers/media/i2c/sc530ai.c index 7c92587c518d..6725245e6f13 100644 --- a/drivers/media/i2c/sc530ai.c +++ b/drivers/media/i2c/sc530ai.c @@ -1507,7 +1507,7 @@ static void __sc530ai_power_off(struct sc530ai *sc530ai) regulator_bulk_disable(sc530ai_NUM_SUPPLIES, sc530ai->supplies); } -static int sc530ai_runtime_resume(struct device *dev) +static int __maybe_unused sc530ai_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -1516,7 +1516,7 @@ static int sc530ai_runtime_resume(struct device *dev) return __sc530ai_power_on(sc530ai); } -static int sc530ai_runtime_suspend(struct device *dev) +static int __maybe_unused sc530ai_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); diff --git a/drivers/media/i2c/thcv244.c b/drivers/media/i2c/thcv244.c index 35703c32109a..8837d274c620 100644 --- a/drivers/media/i2c/thcv244.c +++ b/drivers/media/i2c/thcv244.c @@ -953,7 +953,7 @@ static void __thcv244_power_off(struct thcv244 *thcv244) regulator_bulk_disable(THCV244_NUM_SUPPLIES, thcv244->supplies); } -static int thcv244_runtime_resume(struct device *dev) +static int __maybe_unused thcv244_runtime_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); @@ -962,7 +962,7 @@ static int thcv244_runtime_resume(struct device *dev) return __thcv244_power_on(thcv244); } -static int thcv244_runtime_suspend(struct device *dev) +static int __maybe_unused thcv244_runtime_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); From 7bb1ff6ff38779ac4757e96fc7b9f9760a4578ef Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 30 Jan 2023 17:15:30 +0800 Subject: [PATCH 051/258] mtd: spi-nor: gigadevice: Support New devices gd55b01ge Change-Id: I3e7242fcb4433bcfd0ed6769ad939dda6078fe8f Signed-off-by: Jon Lin --- drivers/mtd/spi-nor/gigadevice.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c index 3f1c7f5007e0..11cb942f6941 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -56,14 +56,17 @@ static const struct flash_info gigadevice_parts[] = { SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6) .fixups = &gd25q256_fixups }, { "gd25lq255", INFO(0xc86019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) }, { "gd25lb512m", INFO(0xc8671a, 0, 64 * 1024, 1024, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) }, { "gd25b512m", INFO(0xc8471a, 0, 64 * 1024, 1024, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) }, + { "gd55b01ge", INFO(0xc8471b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) }, }; const struct spi_nor_manufacturer spi_nor_gigadevice = { From c67c8fc5b3cc15dc31d7a20ac9ddb439c4a1f7a0 Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Wed, 1 Feb 2023 17:52:02 +0800 Subject: [PATCH 052/258] crypto: rockchip: Kconfig: select crypto v3 if RK3562 Change-Id: I3d22fa8a12d77c77b32f65e249300817d4fc862b Signed-off-by: Nickey Yang --- drivers/crypto/rockchip/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/rockchip/Kconfig b/drivers/crypto/rockchip/Kconfig index 94824c8b7ec4..b7402e8a5e60 100644 --- a/drivers/crypto/rockchip/Kconfig +++ b/drivers/crypto/rockchip/Kconfig @@ -10,8 +10,8 @@ config CRYPTO_DEV_ROCKCHIP_V2 default y if CPU_RV1126 || CPU_RK1808 || CPU_RK3308 || CPU_PX30 || CPU_RK3568 || CPU_RK3588 config CRYPTO_DEV_ROCKCHIP_V3 - bool "crypto v3/v4 for RV1106/RK3528" - default y if CPU_RV1106 || CPU_RK3528 + bool "crypto v3/v4 for RV1106/RK3528/RK3562" + default y if CPU_RV1106 || CPU_RK3528 || CPU_RK3562 endif From 49979286c471ed15fbdb237862dfa326fd005cc4 Mon Sep 17 00:00:00 2001 From: Zain Wang Date: Mon, 6 Feb 2023 10:42:12 +0800 Subject: [PATCH 053/258] arm64: configs: rockchip_linux_defconfig: enable CONFIG_CPU_RK3562 Signed-off-by: Zain Wang Change-Id: I226a1d123d550c95c414c7fa1b84480ccfa8644f --- arch/arm64/configs/rockchip_linux_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig index 42b28a655c87..e618733f409b 100644 --- a/arch/arm64/configs/rockchip_linux_defconfig +++ b/arch/arm64/configs/rockchip_linux_defconfig @@ -504,6 +504,7 @@ CONFIG_CPU_PX30=y CONFIG_CPU_RK1808=y CONFIG_CPU_RK3328=y CONFIG_CPU_RK3399=y +CONFIG_CPU_RK3562=y CONFIG_CPU_RK3568=y CONFIG_CPU_RK3588=y CONFIG_ROCKCHIP_AMP=y From 3d9af6480a3da0c902953d8f44c394d277fc0715 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 3 Feb 2023 10:00:27 +0800 Subject: [PATCH 054/258] PCI: Mark Micron 2100AI NVMe to avoid using ASPM From test, 2100AI NVMe randomly reject TLP access when ASPM is enabled. Especially after powering cycle it, it immediately enters lower power mode but refuse to ack TLP. Signed-off-by: Shawn Lin Change-Id: I2ce3e857014296195d91cd89c8185810a271b4af --- drivers/pci/quirks.c | 7 +++++++ include/linux/pci_ids.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1be2894ada70..0ad6bf1807b2 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2357,6 +2357,13 @@ static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) */ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); +/* + * Micron 2100AI NVMe doesn't work reliably when ASPM is enabled. Disable + * ASPM support for it now. + */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICRON, PCI_DEVICE_ID_MICRON_2100AI, + quirk_disable_aspm_l0s_l1); + /* * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain * Link bit cleared after starting the link retrain process to allow this diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 2efb6a1c823f..cf4e50e87cb5 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -1912,6 +1912,9 @@ #define PCI_DEVICE_ID_MICRO_MEMORY_5425CN 0x5425 #define PCI_DEVICE_ID_MICRO_MEMORY_6155 0x6155 +#define PCI_VENDOR_ID_MICRON 0x1344 +#define PCI_DEVICE_ID_MICRON_2100AI 0x6001 + #define PCI_VENDOR_ID_DOMEX 0x134a #define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 From 2780ba1dc584f19619235173eff65438fdb198be Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sun, 29 Jan 2023 19:59:33 +0800 Subject: [PATCH 055/258] drm/rockchip: vop3: add support for rk3562 mcu interface Signed-off-by: Damon Ding Change-Id: I5f9a0676bb048bfffcf413fa50029eafd0ce625a --- drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 9 ++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 9 -- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 136 ++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 - 4 files changed, 143 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index 3739d5cb4657..224c0f346c65 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -273,6 +273,15 @@ struct rockchip_logo { int count; }; +struct rockchip_mcu_timing { + int mcu_pix_total; + int mcu_cs_pst; + int mcu_cs_pend; + int mcu_rw_pst; + int mcu_rw_pend; + int mcu_hold_mode; +}; + struct loader_cubic_lut { bool enable; u32 offset; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 96099755633f..9eac7826f337 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -186,15 +186,6 @@ struct vop_plane_state { struct vop_dump_list *planlist; }; -struct rockchip_mcu_timing { - int mcu_pix_total; - int mcu_cs_pst; - int mcu_cs_pend; - int mcu_rw_pst; - int mcu_rw_pend; - int mcu_hold_mode; -}; - struct vop_win { struct vop_win *parent; struct drm_plane base; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index d3fb68b94705..e2b66130055e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -562,6 +562,7 @@ struct vop2_wb_connector_state { struct vop2_video_port { struct rockchip_crtc rockchip_crtc; + struct rockchip_mcu_timing mcu_timing; struct vop2 *vop2; struct reset_control *dclk_rst; struct clk *dclk; @@ -5635,17 +5636,98 @@ static void vop2_crtc_line_flag_irq_disable(struct vop2_video_port *vp) spin_unlock_irqrestore(&vop2->irq_lock, flags); } -static void vop3_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value) +static void vop3_mcu_mode_setup(struct drm_crtc *crtc) { + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct vop2 *vop2 = vp->vop2; + + VOP_MODULE_SET(vop2, vp, mcu_type, 1); + VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1); + VOP_MODULE_SET(vop2, vp, mcu_pix_total, vp->mcu_timing.mcu_pix_total); + VOP_MODULE_SET(vop2, vp, mcu_cs_pst, vp->mcu_timing.mcu_cs_pst); + VOP_MODULE_SET(vop2, vp, mcu_cs_pend, vp->mcu_timing.mcu_cs_pend); + VOP_MODULE_SET(vop2, vp, mcu_rw_pst, vp->mcu_timing.mcu_rw_pst); + VOP_MODULE_SET(vop2, vp, mcu_rw_pend, vp->mcu_timing.mcu_rw_pend); +} + +static void vop3_mcu_bypass_mode_setup(struct drm_crtc *crtc) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct vop2 *vop2 = vp->vop2; + + VOP_MODULE_SET(vop2, vp, mcu_type, 1); + VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1); + VOP_MODULE_SET(vop2, vp, mcu_pix_total, 53); + VOP_MODULE_SET(vop2, vp, mcu_cs_pst, 6); + VOP_MODULE_SET(vop2, vp, mcu_cs_pend, 48); + VOP_MODULE_SET(vop2, vp, mcu_rw_pst, 12); + VOP_MODULE_SET(vop2, vp, mcu_rw_pend, 30); +} + +static u32 vop3_mode_done(struct vop2_video_port *vp) +{ + return VOP_MODULE_GET(vp->vop2, vp, out_mode); +} + +static void vop3_set_out_mode(struct drm_crtc *crtc, u32 out_mode) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct vop2 *vop2 = vp->vop2; + int ret; + u32 val; + + VOP_MODULE_SET(vop2, vp, out_mode, out_mode); + vop2_cfg_done(crtc); + ret = readx_poll_timeout(vop3_mode_done, vp, val, val == out_mode, + 1000, 500 * 1000); + if (ret) + dev_err(vop2->dev, "wait mode 0x%x timeout\n", out_mode); +} + +static void vop3_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value) +{ + struct drm_crtc_state *crtc_state; + struct drm_display_mode *adjusted_mode; + struct rockchip_crtc_state *vcstate; struct vop2_video_port *vp; struct vop2 *vop2; if (!crtc) return; + crtc_state = crtc->state; + adjusted_mode = &crtc_state->adjusted_mode; + vcstate = to_rockchip_crtc_state(crtc->state); vp = to_vop2_video_port(crtc); vop2 = vp->vop2; + switch (vcstate->output_mode) { + case ROCKCHIP_OUT_MODE_P565: + case ROCKCHIP_OUT_MODE_S888: + /* + * Send cmds for both rgb3x8_m0 and rgb3x8_m1. + */ + value = (((value & 0x1f) << 3) | ((value & 0xe0) << 5)) | + (((value & 0x7) << 13) | ((value & 0xf8) << 16)); + break; + case ROCKCHIP_OUT_MODE_P666: + value = ((value & 0x3f) << 2) | ((value & 0xc0) << 4); + break; + default: + break; + } + + /* + * 1.set output mode to AAAA when start sending cmds. + * 2.set mcu bypass mode timing. + * 3.set dclk rate to 150M. + */ + if ((type == MCU_SETBYPASS) && value) { + vop3_set_out_mode(crtc, ROCKCHIP_OUT_MODE_AAAA); + vop3_mcu_bypass_mode_setup(crtc); + clk_set_rate(vp->dclk, 150000000); + } + mutex_lock(&vop2->vop2_lock); if (vop2 && vop2->is_enabled) { switch (type) { @@ -5666,6 +5748,17 @@ static void vop3_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value) } } mutex_unlock(&vop2->vop2_lock); + + /* + * 1.restore output mode at the end. + * 2.restore mcu data mode timing. + * 3.restore dclk rate to crtc_clock. + */ + if ((type == MCU_SETBYPASS) && !value) { + vop3_set_out_mode(crtc, vcstate->output_mode); + vop3_mcu_mode_setup(crtc); + clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000); + } } static int vop2_crtc_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) @@ -6394,6 +6487,13 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656) adj_mode->crtc_clock *= 2; + if (vp->mcu_timing.mcu_pix_total) { + if (vcstate->output_mode == ROCKCHIP_OUT_MODE_S888) + adj_mode->crtc_clock *= 3; + else if (vcstate->output_mode == ROCKCHIP_OUT_MODE_S888_DUMMY) + adj_mode->crtc_clock *= 4; + } + drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) && @@ -7243,6 +7343,14 @@ static void vop3_setup_pipe_dly(struct vop2_video_port *vp, const struct vop2_zp } } +static int vop2_get_vrefresh(struct vop2_video_port *vp, const struct drm_display_mode *mode) +{ + if (vp->mcu_timing.mcu_pix_total) + return drm_mode_vrefresh(mode) / vp->mcu_timing.mcu_pix_total; + else + return drm_mode_vrefresh(mode); +} + static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { struct vop2_video_port *vp = to_vop2_video_port(crtc); @@ -7291,7 +7399,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state vop2_lock(vop2); DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x) for vp%d dclk: %d\n", hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p", - drm_mode_vrefresh(adjusted_mode), vcstate->output_type, vcstate->output_if, + vop2_get_vrefresh(vp, adjusted_mode), vcstate->output_type, vcstate->output_if, vp->id, adjusted_mode->crtc_clock * 1000); if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) { @@ -7325,6 +7433,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state if (vcstate->mode_update) vop2_disable_all_planes_for_crtc(crtc); + if (vp->mcu_timing.mcu_pix_total) + vop3_mcu_mode_setup(crtc); + dclk_inv = (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0; val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); @@ -9471,6 +9582,9 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state vop2_wb_commit(crtc); vop2_cfg_done(crtc); + if (vp->mcu_timing.mcu_pix_total) + VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 0); + spin_unlock_irqrestore(&vop2->irq_lock, flags); /* @@ -11134,6 +11248,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) int num_wins = 0; int registered_num_crtcs; struct device_node *vop_out_node; + struct device_node *mcu_timing_node; vop2_data = of_device_get_match_data(dev); if (!vop2_data) @@ -11264,6 +11379,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) u32 plane_mask = 0; u32 primary_plane_phy_id = 0; u32 vp_id = 0; + u32 val = 0; of_property_read_u32(child, "rockchip,plane-mask", &plane_mask); of_property_read_u32(child, "rockchip,primary-plane", &primary_plane_phy_id); @@ -11283,6 +11399,22 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return ret; } + mcu_timing_node = of_get_child_by_name(child, "mcu-timing"); + if (mcu_timing_node) { + if (!of_property_read_u32(mcu_timing_node, "mcu-pix-total", &val)) + vop2->vps[vp_id].mcu_timing.mcu_pix_total = val; + if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pst", &val)) + vop2->vps[vp_id].mcu_timing.mcu_cs_pst = val; + if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pend", &val)) + vop2->vps[vp_id].mcu_timing.mcu_cs_pend = val; + if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pst", &val)) + vop2->vps[vp_id].mcu_timing.mcu_rw_pst = val; + if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pend", &val)) + vop2->vps[vp_id].mcu_timing.mcu_rw_pend = val; + if (!of_property_read_u32(mcu_timing_node, "mcu-hold-mode", &val)) + vop2->vps[vp_id].mcu_timing.mcu_hold_mode = val; + } + DRM_DEV_INFO(dev, "vp%d assign plane mask: 0x%x, primary plane phy id: %d\n", vp_id, vop2->vps[vp_id].plane_mask, vop2->vps[vp_id].primary_plane_phy_id); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 724072eb33fa..55d6107604e2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1017,7 +1017,6 @@ static const struct vop2_video_port_regs rk3562_vop_vp0_regs = { .mcu_cs_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 10), .mcu_rw_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 16), .mcu_rw_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 20), - .mcu_clk_sel = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 26), .mcu_hold_mode = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 27), .mcu_frame_st = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 28), .mcu_rs = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 29), @@ -1081,7 +1080,6 @@ static const struct vop2_video_port_regs rk3562_vop_vp1_regs = { .mcu_cs_pend = VOP_REG(RK3562_VP1_MCU_CTRL, 0x3f, 10), .mcu_rw_pst = VOP_REG(RK3562_VP1_MCU_CTRL, 0xf, 16), .mcu_rw_pend = VOP_REG(RK3562_VP1_MCU_CTRL, 0x3f, 20), - .mcu_clk_sel = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 26), .mcu_hold_mode = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 27), .mcu_frame_st = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 28), .mcu_rs = VOP_REG(RK3562_VP1_MCU_CTRL, 0x1, 29), From 4e71f3e843f3af521e81b5b48b21de98f8b71c1c Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sun, 29 Jan 2023 20:22:40 +0800 Subject: [PATCH 056/258] drm/rockchip: rgb: add support for vop3 in mcu cmds sending Signed-off-by: Damon Ding Change-Id: If3e4d23d83fafc16faba88a3b1f7e441090bbde5 --- drivers/gpu/drm/rockchip/rockchip_rgb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index 8797a5eb0437..1bf943d76c93 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -54,7 +54,7 @@ #define RK3288_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 8, 8) #define RK3288_LVDS_CON_TTL_EN(x) HIWORD_UPDATE(x, 6, 6) -#define RK3562_GRF_IOC_VO_IO_CON 0x500 +#define RK3562_GRF_IOC_VO_IO_CON 0x10500 #define RK3562_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6) #define RK3568_GRF_VO_CON1 0X0364 @@ -542,8 +542,15 @@ static void rockchip_drm_crtc_send_mcu_cmd(struct drm_device *drm_dev, struct rockchip_drm_private *priv; drm_for_each_crtc(crtc, drm_dev) { - if (of_get_parent(crtc->port) == np_crtc) + /* + * Support to find crtc device for both vop and vop3: + * vop -> rgb out + * vop3 -> vp -> rgb out + */ + if (of_get_parent(of_get_parent(crtc->port)) == np_crtc || + of_get_parent(crtc->port) == np_crtc) { break; + } } pipe = drm_crtc_index(crtc); From ea6df1a5bbdb2c0283324621ac5295c5db1e0e00 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Fri, 3 Feb 2023 18:32:02 +0800 Subject: [PATCH 057/258] ASoC: codecs: rv1106_codec: fixes and clean up DAC steps based on vendor DS_V1P8 Signed-off-by: Xing Zheng Change-Id: Ifeaec747dda09c6445309e15e43cdb8c30686959 --- sound/soc/codecs/rv1106_codec.c | 78 ++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 36 deletions(-) diff --git a/sound/soc/codecs/rv1106_codec.c b/sound/soc/codecs/rv1106_codec.c index 7c767e7ece8a..f239b3319ac1 100644 --- a/sound/soc/codecs/rv1106_codec.c +++ b/sound/soc/codecs/rv1106_codec.c @@ -1051,87 +1051,96 @@ static int rv1106_mute_stream(struct snd_soc_dai *dai, int mute, int stream) static int rv1106_codec_dac_enable(struct rv1106_codec_priv *rv1106) { - /* vendor step 1 */ + /* Step 01 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_IBIAS_MSK, ACODEC_DAC_IBIAS_EN); - udelay(20); - /* vendor step 2 */ + /* Step 02 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_L_REF_VOL_BUF_MSK, ACODEC_DAC_L_REF_VOL_BUF_EN); - /* Waiting the stable reference voltage */ - mdelay(1); + usleep_range(1000, 2000); - /* vendor step 7 */ + /* Step 03 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1, ACODEC_DAC_L_LINEOUT_MSK, ACODEC_DAC_L_LINEOUT_EN); - udelay(20); - /* vendor step 8 */ + /* Step 04 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1, ACODEC_DAC_L_LINEOUT_SIGNAL_MSK, ACODEC_DAC_L_LINEOUT_SIGNAL_WORK); - udelay(20); - /* vendor step 11 */ + /* Step 05 */ + regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL, + ACODEC_DAC_HPMIX_MSK, + ACODEC_DAC_HPMIX_EN); + udelay(20); + + /* Step 06 */ + regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL, + ACODEC_DAC_HPMIX_MDL_MSK, + ACODEC_DAC_HPMIX_MDL_WORK); + udelay(20); + + /* Step 07 */ + regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL, + ACODEC_DAC_HPMIX_SEL_MSK, + ACODEC_DAC_HPMIX_I2S); + /* Waiting HPMIX be stable */ + usleep_range(18000, 20000); + + /* Step 08 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_L_REF_VOL_MSK, ACODEC_DAC_L_REF_VOL_EN); - udelay(20); - /* vendor step 12 */ + /* Step 09 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_L_CLK_MSK, ACODEC_DAC_L_CLK_EN); - udelay(20); - /* vendor step 13 */ + /* Step 10 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_SRC_SIGNAL_MSK, ACODEC_DAC_SRC_SIGNAL_EN); - udelay(20); - /* vendor step 14 */ + /* Step 11 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_L_SIGNAL_MSK, ACODEC_DAC_L_SIGNAL_WORK); - udelay(20); - /* vendor step 15 */ + /* Step 12 */ + regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL, + ACODEC_DAC_HPMIX_MUTE_MSK, + ACODEC_DAC_HPMIX_WORK); + udelay(20); + + /* Step 13 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1, ACODEC_DAC_L_LINEOUT_MUTE_MSK, ACODEC_DAC_L_LINEOUT_WORK); - udelay(20); - - regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL, - ACODEC_DAC_HPMIX_MSK | - ACODEC_DAC_HPMIX_MDL_MSK | - ACODEC_DAC_HPMIX_MUTE_MSK | - ACODEC_DAC_HPMIX_SEL_MSK, - ACODEC_DAC_HPMIX_EN | - ACODEC_DAC_HPMIX_MDL_WORK | - ACODEC_DAC_HPMIX_WORK | - ACODEC_DAC_HPMIX_I2S); + /* Skip setting gains that Step 14/15 */ rv1106->dac_enable = true; - return 0; } static int rv1106_codec_dac_disable(struct rv1106_codec_priv *rv1106) { + /* Step 01 */ + /* Skip cleaning the gain to GAIN_LINEOUTL */ + /* Step 02 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1, ACODEC_DAC_L_LINEOUT_MUTE_MSK, @@ -1170,20 +1179,17 @@ static int rv1106_codec_dac_disable(struct rv1106_codec_priv *rv1106) regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_L_REF_VOL_MSK, ACODEC_DAC_L_REF_VOL_DIS); - - /* Step 11, note: skip handing POP Sound */ - - /* Step 12 */ + /* Step 11 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_L_REF_VOL_BUF_MSK, ACODEC_DAC_L_REF_VOL_BUF_DIS); - /* Step 13 */ + /* Step 12 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_IBIAS_MSK, ACODEC_DAC_IBIAS_DIS); - /* Step 14 */ + /* Step 13 */ regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0, ACODEC_DAC_L_SIGNAL_MSK, ACODEC_DAC_L_SIGNAL_INIT); From 8a071e9fe8903f7b89ccf7b3195622f24853f0e3 Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Wed, 1 Feb 2023 17:57:01 +0800 Subject: [PATCH 058/258] clk: rockchip: Kconfig: select clk link if rk3562 Change-Id: I311ca6f1b22fb32ccb2dbf685b659a9f738f5faa Signed-off-by: Nickey Yang --- drivers/clk/rockchip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 191515a53c13..e711ba005825 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -142,7 +142,7 @@ config ROCKCHIP_CLK_COMPENSATION config ROCKCHIP_CLK_LINK tristate "Rockchip clock link support" - default CLK_RK3588 + default CLK_RK3562 || CLK_RK3588 help Say y here to enable clock link for Rockchip. From 1e3b2519b053d53cefd18430bf8694c26551ac95 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Fri, 18 Nov 2022 11:36:45 +0800 Subject: [PATCH 059/258] ARM: dts: rockchip: add rk3036-evb1-ddr3-v10.dts Change-Id: Iee527cf67b8ddcb4ec5a38807f657357f4ee3b55 Signed-off-by: Hongming Zou --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts | 632 +++++++++++++++++++++ 2 files changed, 633 insertions(+) create mode 100644 arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 24e96d78a7a7..7a7f487f8e61 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1008,6 +1008,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1126-evb-ddr3-v12-spi-nor.dtb \ rv1126-evb-ddr3-v13.dtb \ rk3036-evb.dtb \ + rk3036-evb1-ddr3-v10.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ rk3066a-marsboard.dtb \ diff --git a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts new file mode 100644 index 000000000000..18a5a06e6a2a --- /dev/null +++ b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; + +#include "rk3036.dtsi" +#include + +/ { + model = "Rockchip RK3036 EVB1 DDR3 V10 Board"; + compatible = "rockchip,rk3036-evb1-ddr3-v10", "rockchip,rk3036"; + + chosen { + bootargs = "console=uart8250,mmio32,0x20068000 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x20000000>; + }; + + multi_sound: multi-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,hdmi-codec"; + rockchip,cpu = <&i2s>; + rockchip,codec = <&acodec>, <&hdmi>; + }; + + vdd_arm: vdd-arm-regulator { + compatible = "pwm-regulator"; + rockchip,pwm_id = <2>; + pwms = <&pwm2 0 25000 0>; + regulator-name = "vdd_arm"; + regulator-init-microvolt = <1100000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_host"; + gpio = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + enable-active-high; + regulator-boot-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + + wifi_chip_type = "rk915"; + WIFI,poweren_gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&acodec { + spk_ctl_io = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu0_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-1200000000; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>; + phy = <&phy0>; + phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ + phy-reset-duration = <10>; /* millisecond */ + + + /* If you're going to use Ethernet, you need an external clock + * This is just a test(e.g: the accurate 50MHz what mac_ref need) + * so cpu The frequency should be set to 600M + */ + assigned-clock-parents = <&cru PLL_APLL>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&emmc { + rockchip,default-sample-phase = <0>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_arm>; +}; + +&hdmi { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + es8311: es8311@18 { + compatible = "everest,es8311"; + reg = <0x18>; + //clocks = <&cru SCLK_I2S_OUT>; + clock-names = "mclk"; + adc-pga-gain = <8>; + adc-volume = <0xdf>; + dac-volume = <0xbf>; + aec-mode = "dac left, adc right"; + //pinctrl-names = "default"; + //pinctrl-0 = <&i2s_mclk>; + + /* + * in rk3036-evb-v10,es8311 is not actually connected + * to PA,so we don't need spk-ctl-gpios + */ + /*spk-ctl-gpios = ;*/ + + #sound-dai-cells = <0>; + }; + + rk628: rk628@50 { + compatible = "rockchip,rk628"; + reg = <0x50>; + interrupt-parent = <&gpio0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + plugin-det-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + status = "okay"; + rk628,hdmi-in; + rk628-dsi { + //rockchip,dual-channel; + dsi,eotp; + dsi,video-mode; + dsi,format = "rgb888"; + dsi,lanes = <4>; + status = "okay"; + + rk628-panel { + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 55 7b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 32 + 15 00 02 b2 00 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + }; + }; + + display-timings { + + src-timing { + clock-frequency = <65000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <48>; + hsync-len = <8>; + hback-porch = <52>; + vfront-porch = <16>; + vsync-len = <6>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + dst-timing { + clock-frequency = <65000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <48>; + hsync-len = <8>; + hback-porch = <52>; + vfront-porch = <16>; + vsync-len = <6>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&i2s { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&sdio { + bus-width = <4>; + max_frequency = <50000000>; + cap-sd-highspeed; + supports-sdio; + ignore-pm-notify; + keep-power-in-suspend; + supports-rk912; + /delete-property/ non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; + + //status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + supports-sd; + status = "disabled"; +}; + +&sfc { + status = "okay"; +}; + +&tve { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_xfer>, <&uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + From b5795e81ec077d43a5c78ac85f98d53956dd0011 Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Fri, 2 Sep 2022 17:18:05 +0800 Subject: [PATCH 060/258] rpmsg: rockchip: add Rockchip RPMsg Platform Support Support Rockchip Platform to use mailbox for rpmsg communication and provide hardware interface for inter-core communication. Signed-off-by: Steven Liu Change-Id: Ibf81167f173d25de03de3b9bf25e53479cb557ac --- drivers/rpmsg/Kconfig | 11 + drivers/rpmsg/Makefile | 1 + drivers/rpmsg/rockchip_rpmsg.c | 421 +++++++++++++++++++++++++++ include/linux/rpmsg/rockchip_rpmsg.h | 43 +++ 4 files changed, 476 insertions(+) create mode 100644 drivers/rpmsg/rockchip_rpmsg.c create mode 100644 include/linux/rpmsg/rockchip_rpmsg.h diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig index f96716893c2a..eade7d1bb127 100644 --- a/drivers/rpmsg/Kconfig +++ b/drivers/rpmsg/Kconfig @@ -58,6 +58,17 @@ config RPMSG_QCOM_SMD providing communication channels to remote processors in Qualcomm platforms. +config RPMSG_ROCKCHIP + tristate "Rockchip Platform RPMsg Support" + depends on ARCH_ROCKCHIP + depends on MAILBOX + depends on ROCKCHIP_MBOX + select RPMSG + select VIRTIO + help + Say y here to enable support for The Remote Processors Messasing + in Rockchip Platform. + config RPMSG_VIRTIO tristate "Virtio RPMSG bus driver" depends on HAS_DMA diff --git a/drivers/rpmsg/Makefile b/drivers/rpmsg/Makefile index ffe932ef6050..4547e31c8e4b 100644 --- a/drivers/rpmsg/Makefile +++ b/drivers/rpmsg/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_RPMSG_QCOM_GLINK) += qcom_glink.o obj-$(CONFIG_RPMSG_QCOM_GLINK_RPM) += qcom_glink_rpm.o obj-$(CONFIG_RPMSG_QCOM_GLINK_SMEM) += qcom_glink_smem.o obj-$(CONFIG_RPMSG_QCOM_SMD) += qcom_smd.o +obj-$(CONFIG_RPMSG_ROCKCHIP) += rockchip_rpmsg.o obj-$(CONFIG_RPMSG_VIRTIO) += virtio_rpmsg_bus.o diff --git a/drivers/rpmsg/rockchip_rpmsg.c b/drivers/rpmsg/rockchip_rpmsg.c new file mode 100644 index 000000000000..c335aa4bad65 --- /dev/null +++ b/drivers/rpmsg/rockchip_rpmsg.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Remote Processors Messaging Platform Support. + * + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Author: Steven Liu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rpmsg_internal.h" + +enum rk_rpmsg_chip { + RK3568, +}; + +struct rk_virtio_dev { + struct virtio_device vdev; + unsigned int vring[2]; + struct virtqueue *vq[2]; + unsigned int base_queue_id; + int num_of_vqs; + struct rk_rpmsg_dev *rpdev; +}; + +#define to_rk_rpvdev(vd) container_of(vd, struct rk_virtio_dev, vdev) + +struct rk_rpmsg_dev { + struct platform_device *pdev; + enum rk_rpmsg_chip chip; + int vdev_nums; + unsigned int link_id; + int first_notify; + u32 flags; + struct mbox_client mbox_cl; + struct mbox_chan *mbox_rx_chan; + struct mbox_chan *mbox_tx_chan; + struct rk_virtio_dev *rpvdev[RPMSG_MAX_INSTANCE_NUM]; +}; + +struct rk_rpmsg_vq_info { + u32 queue_id; + void *vring_addr; + struct rk_rpmsg_dev *rpdev; +}; + +static void rk_rpmsg_rx_callback(struct mbox_client *client, void *message) +{ + u32 link_id; + struct rk_virtio_dev *rpvdev; + struct rk_rpmsg_dev *rpdev = container_of(client, struct rk_rpmsg_dev, mbox_cl); + struct platform_device *pdev = rpdev->pdev; + struct device *dev = &pdev->dev; + struct rockchip_mbox_msg *rx_msg; + + rx_msg = message; + dev_dbg(dev, "rpmsg master: receive cmd=0x%x data=0x%x\n", + rx_msg->cmd, rx_msg->data); + if (rx_msg->data != RPMSG_MBOX_MAGIC) + dev_err(dev, "rpmsg master: mailbox data error!\n"); + link_id = rx_msg->cmd & 0xFFU; + /* TODO: only support one remote core now */ + rpvdev = rpdev->rpvdev[0]; + rpdev->flags |= RPMSG_REMOTE_IS_READY; + dev_dbg(dev, "rpmsg master: rx link_id=0x%x flag=0x%x\n", link_id, rpdev->flags); + vring_interrupt(0, rpvdev->vq[0]); +} + +static bool rk_rpmsg_notify(struct virtqueue *vq) +{ + struct rk_rpmsg_vq_info *rpvq = vq->priv; + struct rk_rpmsg_dev *rpdev = rpvq->rpdev; + struct platform_device *pdev = rpdev->pdev; + struct device *dev = &pdev->dev; + u32 link_id; + int ret; + struct rockchip_mbox_msg tx_msg; + + memset(&tx_msg, 0, sizeof(tx_msg)); + dev_dbg(dev, "queue_id-0x%x virt_vring_addr 0x%p\n", + rpvq->queue_id, rpvq->vring_addr); + + link_id = rpdev->link_id; + tx_msg.cmd = link_id & 0xFFU; + tx_msg.data = RPMSG_MBOX_MAGIC; + + if ((rpdev->first_notify == 0) && (rpvq->queue_id % 2 == 0)) { + /* first_notify is used in the master init handshake phase. */ + dev_dbg(dev, "rpmsg first_notify\n"); + rpdev->first_notify++; + } else if (rpvq->queue_id % 2 == 0) { + /* tx done is not supported, so ignored */ + return true; + } + ret = mbox_send_message(rpdev->mbox_tx_chan, &tx_msg); + if (ret < 0) { + dev_err(dev, "mbox send failed!\n"); + return false; + } + mbox_chan_txdone(rpdev->mbox_tx_chan, 0); + + return true; +} + +static struct virtqueue *rk_rpmsg_find_vq(struct virtio_device *vdev, + unsigned int index, + void (*callback)(struct virtqueue *vq), + const char *name, + bool ctx) +{ + struct rk_virtio_dev *rpvdev = to_rk_rpvdev(vdev); + struct rk_rpmsg_dev *rpdev = rpvdev->rpdev; + struct platform_device *pdev = rpdev->pdev; + struct device *dev = &pdev->dev; + struct rk_rpmsg_vq_info *rpvq; + struct virtqueue *vq; + int ret; + + rpvq = kmalloc(sizeof(*rpvq), GFP_KERNEL); + if (!rpvq) + return ERR_PTR(-ENOMEM); + + rpdev->flags &= (~RPMSG_CACHED_VRING); + rpvq->vring_addr = (__force void *) ioremap(rpvdev->vring[index], RPMSG_VRING_SIZE); + if (!rpvq->vring_addr) { + ret = -ENOMEM; + goto free_rpvq; + } + dev_dbg(dev, "vring%d: phys 0x%x, virt 0x%p\n", index, + rpvdev->vring[index], rpvq->vring_addr); + + memset_io(rpvq->vring_addr, 0, RPMSG_VRING_SIZE); + + vq = vring_new_virtqueue(index, RPMSG_BUF_COUNT, RPMSG_VRING_ALIGN, vdev, true, ctx, + rpvq->vring_addr, rk_rpmsg_notify, callback, name); + if (!vq) { + dev_err(dev, "vring_new_virtqueue failed\n"); + ret = -ENOMEM; + goto unmap_vring; + } + + rpvdev->vq[index] = vq; + vq->priv = rpvq; + + rpvq->queue_id = rpvdev->base_queue_id + index; + rpvq->rpdev = rpdev; + + return vq; + +unmap_vring: + iounmap((__force void __iomem *) rpvq->vring_addr); +free_rpvq: + kfree(rpvq); + return ERR_PTR(ret); +} + +static u8 rk_rpmsg_get_status(struct virtio_device *vdev) +{ + /* TODO: */ + return 0; +} + +static void rk_rpmsg_set_status(struct virtio_device *vdev, u8 status) +{ + /* TODO: */ +} + +static void rk_rpmsg_reset(struct virtio_device *vdev) +{ + /* TODO: */ +} + +static void rk_rpmsg_del_vqs(struct virtio_device *vdev) +{ + struct virtqueue *vq, *n; + + list_for_each_entry_safe(vq, n, &vdev->vqs, list) { + struct rk_rpmsg_vq_info *rpvq = vq->priv; + + iounmap(rpvq->vring_addr); + vring_del_virtqueue(vq); + kfree(rpvq); + } +} + +static int rk_rpmsg_find_vqs(struct virtio_device *vdev, unsigned int nvqs, + struct virtqueue *vqs[], + vq_callback_t *callbacks[], + const char * const names[], + const bool *ctx, + struct irq_affinity *desc) +{ + struct rk_virtio_dev *rpvdev = to_rk_rpvdev(vdev); + int i, ret; + + /* Each rpmsg instance has two virtqueues. vqs[0] is rvq and vqs[1] is tvq */ + if (nvqs != 2) + return -EINVAL; + + for (i = 0; i < nvqs; ++i) { + vqs[i] = rk_rpmsg_find_vq(vdev, i, callbacks[i], names[i], + ctx ? ctx[i] : false); + if (IS_ERR(vqs[i])) { + ret = PTR_ERR(vqs[i]); + goto error; + } + } + + rpvdev->num_of_vqs = nvqs; + + return 0; + +error: + rk_rpmsg_del_vqs(vdev); + + return ret; +} + +static u64 rk_rpmsg_get_features(struct virtio_device *vdev) +{ + return RPMSG_VIRTIO_RPMSG_F_NS; +} + +static int rk_rpmsg_finalize_features(struct virtio_device *vdev) +{ + vring_transport_features(vdev); + + return 0; +} + +static void rk_rpmsg_vdev_release(struct device *dev) +{ +} + +static struct virtio_config_ops rk_rpmsg_config_ops = { + .get_status = rk_rpmsg_get_status, + .set_status = rk_rpmsg_set_status, + .reset = rk_rpmsg_reset, + .find_vqs = rk_rpmsg_find_vqs, + .del_vqs = rk_rpmsg_del_vqs, + .get_features = rk_rpmsg_get_features, + .finalize_features = rk_rpmsg_finalize_features, +}; + +static int rk_set_vring_phy_buf(struct platform_device *pdev, + struct rk_rpmsg_dev *rpdev, int vdev_nums) +{ + struct device *dev = &pdev->dev; + struct resource *res; + resource_size_t size; + unsigned int start, end; + int i, ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res) { + size = resource_size(res); + start = res->start; + end = res->start + size; + for (i = 0; i < vdev_nums; i++) { + rpdev->rpvdev[i] = devm_kzalloc(dev, sizeof(struct rk_virtio_dev), + GFP_KERNEL); + if (!rpdev->rpvdev[i]) + return -ENOMEM; + + rpdev->rpvdev[i]->vring[0] = start; + rpdev->rpvdev[i]->vring[1] = start + RPMSG_VRING_SIZE; + start += RPMSG_VRING_OVERHEAD; + if (start > end) { + dev_err(dev, "Too small memory size %x!\n", (u32)size); + ret = -EINVAL; + break; + } + } + } else { + return -ENOMEM; + } + + return ret; +} + +static int rockchip_rpmsg_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rk_rpmsg_dev *rpdev = NULL; + struct mbox_client *cl; + int i, ret = 0; + + rpdev = devm_kzalloc(dev, sizeof(*rpdev), GFP_KERNEL); + if (!rpdev) + return -ENOMEM; + + dev_info(dev, "rockchip rpmsg platform probe.\n"); + rpdev->pdev = pdev; + rpdev->chip = (enum rk_rpmsg_chip)device_get_match_data(dev); + rpdev->first_notify = 0; + + cl = &rpdev->mbox_cl; + cl->dev = dev; + cl->rx_callback = rk_rpmsg_rx_callback; + + rpdev->mbox_rx_chan = mbox_request_channel_byname(cl, "rpmsg-rx"); + if (IS_ERR(rpdev->mbox_rx_chan)) { + ret = PTR_ERR(rpdev->mbox_rx_chan); + dev_err(dev, "failed to request mbox rx chan, ret %d\n", ret); + return ret; + } + rpdev->mbox_tx_chan = mbox_request_channel_byname(cl, "rpmsg-tx"); + if (IS_ERR(rpdev->mbox_tx_chan)) { + ret = PTR_ERR(rpdev->mbox_tx_chan); + dev_err(dev, "failed to request mbox tx chan, ret %d\n", ret); + return ret; + } + + ret = device_property_read_u32(dev, "rockchip,link-id", &rpdev->link_id); + if (ret) { + dev_err(dev, "failed to get link_id, ret %d\n", ret); + goto free_channel; + } + ret = device_property_read_u32(dev, "rockchip,vdev-nums", &rpdev->vdev_nums); + if (ret) { + dev_info(dev, "vdev-nums default 1\n"); + rpdev->vdev_nums = 1; + } + if (rpdev->vdev_nums > RPMSG_MAX_INSTANCE_NUM) { + dev_err(dev, "vdev-nums exceed the max %d\n", RPMSG_MAX_INSTANCE_NUM); + ret = -EINVAL; + goto free_channel; + } + + ret = rk_set_vring_phy_buf(pdev, rpdev, rpdev->vdev_nums); + if (ret) { + dev_err(dev, "No vring buffer.\n"); + ret = -ENOMEM; + goto free_channel; + } + if (of_reserved_mem_device_init(dev)) { + dev_info(dev, "No shared DMA pool.\n"); + rpdev->flags &= (~RPMSG_SHARED_DMA_POOL); + } else { + rpdev->flags |= RPMSG_SHARED_DMA_POOL; + } + + for (i = 0; i < rpdev->vdev_nums; i++) { + dev_info(dev, "rpdev vdev%d: vring0 0x%x, vring1 0x%x\n", + i, rpdev->rpvdev[i]->vring[0], rpdev->rpvdev[i]->vring[1]); + rpdev->rpvdev[i]->vdev.id.device = VIRTIO_ID_RPMSG; + rpdev->rpvdev[i]->vdev.config = &rk_rpmsg_config_ops; + rpdev->rpvdev[i]->vdev.dev.parent = dev; + rpdev->rpvdev[i]->vdev.dev.release = rk_rpmsg_vdev_release; + rpdev->rpvdev[i]->base_queue_id = i * 2; + rpdev->rpvdev[i]->rpdev = rpdev; + + ret = register_virtio_device(&rpdev->rpvdev[i]->vdev); + if (ret) { + dev_err(dev, "fail to register rpvdev: %d\n", ret); + goto free_reserved_mem; + } + } + + platform_set_drvdata(pdev, rpdev); + + return ret; + +free_reserved_mem: + if (rpdev->flags & RPMSG_SHARED_DMA_POOL) + of_reserved_mem_device_release(dev); + +free_channel: + mbox_free_channel(rpdev->mbox_rx_chan); + mbox_free_channel(rpdev->mbox_tx_chan); + + return ret; +} + +static int rockchip_rpmsg_remove(struct platform_device *pdev) +{ + struct rk_rpmsg_dev *rpdev = platform_get_drvdata(pdev); + + mbox_free_channel(rpdev->mbox_rx_chan); + mbox_free_channel(rpdev->mbox_tx_chan); + + return 0; +} + +static const struct of_device_id rockchip_rpmsg_match[] = { + { .compatible = "rockchip,rk3568-rpmsg", .data = (void *)RK3568, }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, rockchip_rpmsg_match); + +static struct platform_driver rockchip_rpmsg_driver = { + .probe = rockchip_rpmsg_probe, + .remove = rockchip_rpmsg_remove, + .driver = { + .name = "rockchip-rpmsg", + .of_match_table = rockchip_rpmsg_match, + }, +}; +module_platform_driver(rockchip_rpmsg_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Rockchip Remote Processors Messaging Platform Support"); +MODULE_AUTHOR("Steven Liu "); + diff --git a/include/linux/rpmsg/rockchip_rpmsg.h b/include/linux/rpmsg/rockchip_rpmsg.h new file mode 100644 index 000000000000..6d253faea8e7 --- /dev/null +++ b/include/linux/rpmsg/rockchip_rpmsg.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ +#ifndef ROCKCHIP_RPMSG_H +#define ROCKCHIP_RPMSG_H + +/* rpmsg flag bit definition + * bit 0: Set 1 to indicate remote processor is ready + * bit 1: Set 1 to use reserved memory region as shared DMA pool + * bit 2: Set 1 to use cached share memory as vring buffer + */ +#define RPMSG_REMOTE_IS_READY BIT(0) +#define RPMSG_SHARED_DMA_POOL BIT(1) +#define RPMSG_CACHED_VRING BIT(2) + +#define RPMSG_VIRTIO_RPMSG_F_NS BIT(0) + +#define RPMSG_BUF_PAYLOAD_SIZE (496UL) +/* rpmsg buffer size is formed by payload size and struct rpmsg_hdr */ +#define RPMSG_BUF_SIZE (RPMSG_BUF_PAYLOAD_SIZE + 16UL) +/* rpmsg buffer count for each direction */ +#define RPMSG_BUF_COUNT (64UL) +/* rpmsg endpoint size is equal to rpmsg buffer size */ +#define RPMSG_EPT_SIZE RPMSG_BUF_SIZE + +#define RPMSG_MAX_INSTANCE_NUM (12U) +#define RPMSG_MAX_LINK_ID (0xFFU) + +#define RPMSG_MBOX_MAGIC (0x524D5347U) + +/* Linux requires the ALIGN to 0x1000(4KB) */ +#define RPMSG_VRING_ALIGN (0x1000UL) +/* contains pool of descriptors and two circular buffers */ +#define RPMSG_VRING_SIZE (0x8000UL) +/* size of 2 * RPMSG_VRING_SIZE */ +#define RPMSG_VRING_OVERHEAD (2UL * RPMSG_VRING_SIZE) + +/* link_id: 4 bit master cpu_id and 4 bit remote_id */ +#define RPMSG_GET_M_CPU_ID(link_id) (((link_id) & 0xF0U) >> 4U) +#define RPMSG_GET_R_CPU_ID(link_id) ((link_id) & 0xFU) + +#endif /* ROCKCHIP_RPMSG_H */ From 4e6ff4aaacbe1af05fef6dfd4bd54bffd1ae6727 Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Sun, 9 Oct 2022 10:31:32 +0800 Subject: [PATCH 061/258] dt-bindings: rpmsg: rpmsg-rockchip: add description for rpmsg-rockchip Signed-off-by: Steven Liu Change-Id: I1a114f460ba751e4f348aa134410cbf86eab2503 --- .../bindings/rpmsg/rpmsg-rockchip.txt | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/rpmsg/rpmsg-rockchip.txt diff --git a/Documentation/devicetree/bindings/rpmsg/rpmsg-rockchip.txt b/Documentation/devicetree/bindings/rpmsg/rpmsg-rockchip.txt new file mode 100644 index 000000000000..0aa80c52b2a8 --- /dev/null +++ b/Documentation/devicetree/bindings/rpmsg/rpmsg-rockchip.txt @@ -0,0 +1,46 @@ +* Rockchip RPMsg Platform Driver + +The Rockchip RPMsg Platform Driver is used for Remote Processors Messaging. + +Required Properties: + +- compatible: should be one of the following. + "rockchip,rk3568-rpmsg" for rk3568 SoCs. +- mbox-names: mailbox name for "rpmsg-rx" or "rpmsg-tx". +- mboxes: mailbox channel for rpmsg. +- rockchip,vdev-nums: number of rpmsg instance. +- rockchip,link-id: link_id of rpmsg instance. 4bit for master cpu_id and 4bit + for remote cpu_id. + +Optional Properties: + +Example: + + rpmsg: rpmsg { + compatible = "rockchip,rk3568-rpmsg"; + mbox-names = "rpmsg-rx", "rpmsg-tx"; + mboxes = <&mailbox 0 &mailbox 3>; + rockchip,vdev-nums = <1>; + rockchip,link-id = <0x03>; + reg = <0x0 0x7c00000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rpmsg_reserved: rpmsg@7c00000 { + reg = <0x0 0x7c00000 0x0 0x400000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x8000000 0x0 0x100000>; + no-map; + }; + }; From 8ad4a5a8f2a684dae4744106aa52501ad0531d3b Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Mon, 10 Oct 2022 11:32:58 +0800 Subject: [PATCH 062/258] rpmsg: rockchip: add rockchip rpmsg test Signed-off-by: Hongming Zou Change-Id: Ibdecd0d26e258af0b687c44f1aa94833c7101627 --- drivers/rpmsg/Kconfig | 6 ++ drivers/rpmsg/Makefile | 1 + drivers/rpmsg/rockchip_rpmsg_test.c | 116 ++++++++++++++++++++++++++++ 3 files changed, 123 insertions(+) create mode 100644 drivers/rpmsg/rockchip_rpmsg_test.c diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig index eade7d1bb127..3b547a718bfc 100644 --- a/drivers/rpmsg/Kconfig +++ b/drivers/rpmsg/Kconfig @@ -69,6 +69,12 @@ config RPMSG_ROCKCHIP Say y here to enable support for The Remote Processors Messasing in Rockchip Platform. +config RPMSG_ROCKCHIP_TEST + tristate "Rockchip RPMsg Test" + depends on RPMSG_ROCKCHIP + help + Say y here to enable Rockchip RPMsg Test. + config RPMSG_VIRTIO tristate "Virtio RPMSG bus driver" depends on HAS_DMA diff --git a/drivers/rpmsg/Makefile b/drivers/rpmsg/Makefile index 4547e31c8e4b..bb767a423785 100644 --- a/drivers/rpmsg/Makefile +++ b/drivers/rpmsg/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_RPMSG_QCOM_GLINK_RPM) += qcom_glink_rpm.o obj-$(CONFIG_RPMSG_QCOM_GLINK_SMEM) += qcom_glink_smem.o obj-$(CONFIG_RPMSG_QCOM_SMD) += qcom_smd.o obj-$(CONFIG_RPMSG_ROCKCHIP) += rockchip_rpmsg.o +obj-$(CONFIG_RPMSG_ROCKCHIP_TEST) += rockchip_rpmsg_test.o obj-$(CONFIG_RPMSG_VIRTIO) += virtio_rpmsg_bus.o diff --git a/drivers/rpmsg/rockchip_rpmsg_test.c b/drivers/rpmsg/rockchip_rpmsg_test.c new file mode 100644 index 000000000000..08677d6975b0 --- /dev/null +++ b/drivers/rpmsg/rockchip_rpmsg_test.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Remote Processors Messaging Test. + * + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Author: Hongming Zou + */ + +#include +#include +#include +#include +#include + +#define LINUX_TEST_MSG_1 "Announce master ept id!" +#define LINUX_TEST_MSG_2 "Rockchip rpmsg linux test pingpong!" +#define MSG_LIMIT 100 + +struct instance_data { + int rx_count; +}; + +static int rockchip_rpmsg_test_cb(struct rpmsg_device *rp, void *payload, + int payload_len, void *priv, u32 src) +{ + int ret; + uint32_t remote_ept_id; + struct instance_data *idata = dev_get_drvdata(&rp->dev); + + remote_ept_id = src; + dev_info(&rp->dev, "rx msg %s rx_count %d(remote_ept_id: 0x%x)\n", + (char *)payload, ++idata->rx_count, remote_ept_id); + + /* test should not live forever */ + if (idata->rx_count >= MSG_LIMIT) { + dev_info(&rp->dev, "Rockchip rpmsg test exit!\n"); + return 0; + } + + /* send a new message now */ + ret = rpmsg_sendto(rp->ept, LINUX_TEST_MSG_2, strlen(LINUX_TEST_MSG_2), remote_ept_id); + if (ret) + dev_err(&rp->dev, "rpmsg_send failed: %d\n", ret); + return ret; +} + +static int rockchip_rpmsg_test_probe(struct rpmsg_device *rp) +{ + int ret; + uint32_t master_ept_id, remote_ept_id; + struct instance_data *idata; + + master_ept_id = rp->src; + remote_ept_id = rp->dst; + dev_info(&rp->dev, "new channel: 0x%x -> 0x%x!\n", master_ept_id, remote_ept_id); + + idata = devm_kzalloc(&rp->dev, sizeof(*idata), GFP_KERNEL); + if (!idata) + return -ENOMEM; + + dev_set_drvdata(&rp->dev, idata); + + /* + * send a message to our remote processor, and tell remote + * processor about this channel + */ + ret = rpmsg_send(rp->ept, LINUX_TEST_MSG_1, strlen(LINUX_TEST_MSG_1)); + if (ret) { + dev_err(&rp->dev, "rpmsg_send failed: %d\n", ret); + return ret; + } + + ret = rpmsg_sendto(rp->ept, LINUX_TEST_MSG_2, strlen(LINUX_TEST_MSG_2), remote_ept_id); + if (ret) { + dev_err(&rp->dev, "rpmsg_send failed: %d\n", ret); + return ret; + } + + return 0; +} + +static void rockchip_rpmsg_test_remove(struct rpmsg_device *rp) +{ + dev_info(&rp->dev, "rockchip rpmsg test is removed\n"); +} + +static struct rpmsg_device_id rockchip_rpmsg_test_id_table[] = { + { .name = "rpmsg-ap3-ch0" }, + { /* sentinel */ }, +}; + +static struct rpmsg_driver rockchip_rpmsg_test = { + .drv.name = KBUILD_MODNAME, + .drv.owner = THIS_MODULE, + .id_table = rockchip_rpmsg_test_id_table, + .probe = rockchip_rpmsg_test_probe, + .callback = rockchip_rpmsg_test_cb, + .remove = rockchip_rpmsg_test_remove, +}; + +static int __init init(void) +{ + return register_rpmsg_driver(&rockchip_rpmsg_test); +} + +static void __exit fini(void) +{ + unregister_rpmsg_driver(&rockchip_rpmsg_test); +} +module_init(init); +module_exit(fini); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Rockchip Remote Processors Messaging Test"); +MODULE_AUTHOR("Hongming Zou "); + From aff83a4a82a3bfe45f123a57323a28e5e9adbe46 Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Mon, 6 Feb 2023 15:09:59 +0800 Subject: [PATCH 063/258] arm64: rockchip_linux_defconfig: enable Rockchip RPMsg Enable the following macros for AMP system: CONFIG_ROCKCHIP_MBOX=y CONFIG_RPMSG_ROCKCHIP=y CONFIG_RPMSG_VIRTIO=y Signed-off-by: Steven Liu Change-Id: I4d82954a441e543627536b9d207e7203c5ab8f7d --- arch/arm64/configs/rockchip_linux_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig index e618733f409b..188f351b7155 100644 --- a/arch/arm64/configs/rockchip_linux_defconfig +++ b/arch/arm64/configs/rockchip_linux_defconfig @@ -496,10 +496,13 @@ CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_PWM=y CONFIG_MAILBOX=y +CONFIG_ROCKCHIP_MBOX=y CONFIG_IOMMU_LIMIT_IOVA_ALIGNMENT=y CONFIG_IOMMU_IOVA_ALIGNMENT=4 CONFIG_ROCKCHIP_IOMMU=y CONFIG_ARM_SMMU_V3=y +CONFIG_RPMSG_ROCKCHIP=y +CONFIG_RPMSG_VIRTIO=y CONFIG_CPU_PX30=y CONFIG_CPU_RK1808=y CONFIG_CPU_RK3328=y From 238571a1011900d1db3103dbcc227d55d8df33af Mon Sep 17 00:00:00 2001 From: Dingxian Wen Date: Fri, 3 Feb 2023 19:51:36 +0800 Subject: [PATCH 064/258] media: rockchip: hdmirx: modify the enum definition of hdmirx color space Signed-off-by: Dingxian Wen Change-Id: I23070858c0c7ea573af2bdf34652639bac551e68 --- include/uapi/linux/rk_hdmirx_config.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/uapi/linux/rk_hdmirx_config.h b/include/uapi/linux/rk_hdmirx_config.h index 3e158f941af2..a0b7e436aed9 100644 --- a/include/uapi/linux/rk_hdmirx_config.h +++ b/include/uapi/linux/rk_hdmirx_config.h @@ -34,14 +34,14 @@ enum hdmirx_color_range { HDMIRX_FULL_RANGE = 2, }; -enum hdmirx_video_standard { +enum hdmirx_color_space { HDMIRX_XVYCC601 = 0, HDMIRX_XVYCC709 = 1, HDMIRX_SYCC601 = 2, HDMIRX_ADOBE_YCC601 = 3, HDMIRX_ADOBE_RGB = 4, - HDMIRX_BT2020 = 5, - HDMIRX_BT2020_RGB = 6, + HDMIRX_BT2020_YCC_CONST_LUM = 5, + HDMIRX_BT2020_RGB_OR_YCC = 6, }; /* Private v4l2 ioctl */ From 659435873d08adcf394d3758576510becc45e9dd Mon Sep 17 00:00:00 2001 From: Dingxian Wen Date: Fri, 3 Feb 2023 20:12:18 +0800 Subject: [PATCH 065/258] media: rockchip: hdmirx: fill colorspace and quantification to v4l2_format Signed-off-by: Dingxian Wen Change-Id: Iaeea507ea5e81ae5dada265598678ccb8188d48d --- .../platform/rockchip/hdmirx/rk_hdmirx.c | 60 ++++++++++++++++++- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c index 9018d26ddd1e..b828cec04bc0 100644 --- a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c +++ b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c @@ -341,7 +341,7 @@ static u8 edid_init_data_600M[] = { static char *hdmirx_color_space[8] = { "xvYCC601", "xvYCC709", "sYCC601", "Adobe_YCC601", - "Adobe_RGB", "BT2020_YcCbcCrc", "BT2020_RGB" + "Adobe_RGB", "BT2020_YcCbcCrc", "BT2020_RGB_OR_YCbCr" }; static const struct v4l2_dv_timings_cap hdmirx_timings_cap = { @@ -1666,7 +1666,63 @@ static void hdmirx_set_fmt(struct hdmirx_stream *stream, pixm->height = bt->height; pixm->num_planes = fmt->mplanes; pixm->field = V4L2_FIELD_NONE; - pixm->quantization = V4L2_QUANTIZATION_DEFAULT; + + switch (hdmirx_dev->cur_color_range) { + case HDMIRX_DEFAULT_RANGE: + pixm->quantization = V4L2_QUANTIZATION_DEFAULT; + break; + case HDMIRX_LIMIT_RANGE: + pixm->quantization = V4L2_QUANTIZATION_LIM_RANGE; + break; + case HDMIRX_FULL_RANGE: + pixm->quantization = V4L2_QUANTIZATION_FULL_RANGE; + break; + + default: + pixm->quantization = V4L2_QUANTIZATION_DEFAULT; + break; + } + + if (hdmirx_dev->pix_fmt == HDMIRX_RGB888) { + if (hdmirx_dev->cur_color_space == HDMIRX_BT2020_RGB_OR_YCC) + pixm->colorspace = V4L2_COLORSPACE_BT2020; + else if (hdmirx_dev->cur_color_space == HDMIRX_ADOBE_RGB) + pixm->colorspace = V4L2_COLORSPACE_OPRGB; + else + pixm->colorspace = V4L2_COLORSPACE_SRGB; + } else { + switch (hdmirx_dev->cur_color_space) { + case HDMIRX_XVYCC601: + pixm->colorspace = V4L2_COLORSPACE_DEFAULT; + pixm->ycbcr_enc = V4L2_YCBCR_ENC_XV601; + break; + case HDMIRX_XVYCC709: + pixm->colorspace = V4L2_COLORSPACE_REC709; + pixm->ycbcr_enc = V4L2_YCBCR_ENC_XV709; + break; + case HDMIRX_SYCC601: + pixm->colorspace = V4L2_COLORSPACE_DEFAULT; + pixm->ycbcr_enc = V4L2_YCBCR_ENC_601; + break; + case HDMIRX_ADOBE_YCC601: + pixm->colorspace = V4L2_COLORSPACE_DEFAULT; + pixm->ycbcr_enc = V4L2_YCBCR_ENC_601; + break; + case HDMIRX_BT2020_YCC_CONST_LUM: + pixm->colorspace = V4L2_COLORSPACE_BT2020; + pixm->ycbcr_enc = V4L2_YCBCR_ENC_BT2020_CONST_LUM; + break; + case HDMIRX_BT2020_RGB_OR_YCC: + pixm->colorspace = V4L2_COLORSPACE_BT2020; + pixm->ycbcr_enc = V4L2_YCBCR_ENC_BT2020; + break; + + default: + pixm->colorspace = V4L2_COLORSPACE_DEFAULT; + pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + break; + } + } /* calculate plane size and image size */ fcc_xysubs(fmt->fourcc, &xsubs, &ysubs); From 558bea71757ca6808fba72d8fd603f45a3305993 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 10 Jan 2023 11:33:51 +0800 Subject: [PATCH 066/258] Revert "arm64: dts: rockchip: document explicit px30 cru dependencies" This reverts commit 45cb61b4f3bf991ac2011dbc4a155bd5f3b29ebe. For GKI, cru init is deferred_probe_work_func,which make system crash: [ 8.930765][ T6] Unable to handle kernel paging request at virtual address ffffffc8098270e0 [ 8.931691][ T6] Mem abort info: [ 8.932102][ T6] ESR = 0x96000007 [ 8.932541][ T6] EC = 0x25: DABT (current EL), IL = 32 bits [ 8.933192][ T6] SET = 0, FnV = 0 [ 8.933625][ T6] EA = 0, S1PTW = 0 [ 8.934061][ T6] Data abort info: [ 8.934566][ T6] ISV = 0, ISS = 0x00000007 [ 8.935080][ T6] CM = 0, WnR = 0 [ 8.935516][ T6] swapper pgtable: 4k pages, 39-bit VAs, pgdp=000000000297f000 [ 8.936301][ T6] [ffffffc8098270e0] pgd=000000007ffff003, p4d=000000007ffff003, pud=000000007ffff003, pmd=0000000003de9003, pte=0000000000000000 [ 8.937821][ T6] Internal error: Oops: 96000007 [#1] PREEMPT SMP [ 8.938493][ T6] Modules linked in: clk_px30(E) rockchip_cpuinfo(E) clk_rockchip(E) rockchip_sip(E) [ 8.939677][ T6] CPU: 0 PID: 6 Comm: kworker/u8:0 Tainted: G E 5.10.107 #35 [ 8.940574][ T6] Hardware name: Rockchip PX30 evb ddr3 board (DT) [ 8.941305][ T6] Workqueue: events_unbound deferred_probe_work_func [ 8.942062][ T6] pstate: 60400005 (nZCv daif +PAN -UAO -TCO BTYPE=--) [ 8.943125][ T6] pc : rockchip_clk_register_plls+0x164/0x1b8 [clk_rockchip] [ 8.944225][ T6] lr : rockchip_clk_register_plls+0x160/0x1b8 [clk_rockchip] [ 8.944991][ T6] sp : ffffffc812c07980 [ 8.945453][ T6] x29: ffffffc812c079f0 x28: 0000000000000006 [ 8.946173][ T6] x27: 00000000000000a0 x26: ffffffc8098270e0 [ 8.946890][ T6] x25: 0000000000000840 x24: c8ffff800530d100 [ 8.947607][ T6] x23: 00000000000000d8 x22: 0000000000000004 [ 8.948323][ T6] x21: 0000000000000060 x20: 0000000000000001 [ 8.949040][ T6] x19: 0000000000000001 x18: ffffffc812b8d078 [ 8.949760][ T6] x17: 0000000014d453dc x16: 00000000024a8ec8 [ 8.950476][ T6] x15: 0000000000000000 x14: 0000000000000000 [ 8.951193][ T6] x13: 0000000000000000 x12: ffffffc810010644 [ 8.951912][ T6] x11: 0000000000000082 x10: ff800048097f86dc [ 8.952630][ T6] x9 : 0000000000000027 x8 : 00000000000000ff [ 8.953347][ T6] x7 : ffffffffffffffff x6 : 0000000000000000 [ 8.954061][ T6] x5 : 0000000000000000 x4 : a3ffff80048dfc60 [ 8.954778][ T6] x3 : ffffffc8097f86dc x2 : 0000000000000001 [ 8.955493][ T6] x1 : 0000000000000008 x0 : 70ffff8004165308 [ 8.956204][ T6] Call trace: [ 8.956923][ T6] rockchip_clk_register_plls+0x164/0x1b8 [clk_rockchip] [ 8.957665][ T6] 0xffffffc809825168 [ 8.958262][ T6] clk_px30_probe+0x68/0x88 [clk_px30] [ 8.958866][ T6] platform_drv_probe+0xc0/0xe0 [ 8.959421][ T6] really_probe+0x304/0x72c [ 8.959943][ T6] driver_probe_device+0xa4/0xf0 [ 8.960509][ T6] __device_attach_driver+0x1a8/0x1d0 [ 8.961108][ T6] bus_for_each_drv+0xb0/0x10c [ 8.961653][ T6] __device_attach+0x164/0x1d4 [ 8.962201][ T6] device_initial_probe+0x18/0x28 [ 8.962768][ T6] bus_probe_device+0x58/0xf8 [ 8.963308][ T6] deferred_probe_work_func+0xc0/0x164 [ 8.963920][ T6] process_one_work+0x358/0x700 [ 8.964471][ T6] worker_thread+0x52c/0x918 [ 8.964991][ T6] kthread+0x1f8/0x210 [ 8.965466][ T6] ret_from_fork+0x10/0x30 Signed-off-by: Elaine Zhang Change-Id: I255fb5c008077c0c0b430e6922a2ae414cfd422a --- .../bindings/clock/rockchip,px30-cru.txt | 5 ---- arch/arm64/boot/dts/rockchip/px30.dtsi | 25 ++++++++----------- 2 files changed, 10 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt index 55e78cddec8c..39f0c1ac84ee 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt @@ -10,11 +10,6 @@ Required Properties: - compatible: CRU should be "rockchip,px30-cru" - reg: physical base address of the controller and length of memory mapped region. -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names -- clock-names: Should contain the following: - - "xin24m" for both PMUCRU and CRU - - "gpll" for CRU (sourced from PMUCRU) - #clock-cells: should be 1. - #reset-cells: should be 1. diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 5a43a617a30f..b0d79064403d 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1215,38 +1215,33 @@ cru: clock-controller@ff2b0000 { compatible = "rockchip,px30-cru"; reg = <0x0 0xff2b0000 0x0 0x1000>; - clocks = <&xin24m>, <&pmucru PLL_GPLL>; - clock-names = "xin24m", "gpll"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>; + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1188000000>; }; pmucru: clock-controller@ff2bc000 { compatible = "rockchip,px30-pmucru"; reg = <0x0 0xff2bc000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, - <&pmucru SCLK_WIFI_PMU>; + <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; assigned-clock-rates = <1200000000>, <100000000>, - <26000000>; + <26000000>, <600000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>; }; usb2phy_grf: syscon@ff2c0000 { From bb0ed863d88d8a3cec260c4d05275d8843af3495 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Mon, 6 Feb 2023 11:29:33 +0800 Subject: [PATCH 067/258] drm/rockchip: vop2: filter VP vcnt status VP vcnt update and read are driven by two asynchronous dclk and hclk, so add this filtering process, otherwise may read the wrong vcnt value. Signed-off-by: Sandy Huang Change-Id: Ibe933c3b507933720222544ac695e06ad6b957dd --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index e2b66130055e..14cb1c3f5201 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1286,8 +1286,23 @@ static bool vop2_fs_irq_is_pending(struct vop2_video_port *vp) static uint32_t vop2_read_vcnt(struct vop2_video_port *vp) { uint32_t offset = RK3568_SYS_STATUS0 + (vp->id << 2); + uint32_t vcnt0, vcnt1; + int i = 0; - return vop2_readl(vp->vop2, offset) >> 16; + for (i = 0; i < 10; i++) { + vcnt0 = vop2_readl(vp->vop2, offset) >> 16; + vcnt1 = vop2_readl(vp->vop2, offset) >> 16; + + if ((vcnt1 - vcnt0) <= 1) + break; + } + + if (i == 10) { + DRM_DEV_ERROR(vp->vop2->dev, "read VP%d vcnt error: %d %d\n", vp->id, vcnt0, vcnt1); + vcnt1 = vop2_readl(vp->vop2, offset) >> 16; + } + + return vcnt1; } static void vop2_wait_for_irq_handler(struct drm_crtc *crtc) From ae525c9f3af0a212cc8ff9663a23792411cf41bf Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 3 Jan 2023 14:42:48 +0800 Subject: [PATCH 068/258] arm64: dts: rockchip: add rk3562-evb1-lp4x-v10-rgb2lvds Signed-off-by: Sandy Huang Signed-off-by: Damon Ding Change-Id: Ie7d61f0df22bc3ccdaa9bab98c91ce951ea9c5b1 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rk3562-evb1-lp4x-v10-rgb2lvds.dts | 121 ++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb2lvds.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 36d2f2467473..99c82c781a10 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux-amp.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-mcu-k350c4516t.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb2lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb2lvds.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb2lvds.dts new file mode 100644 index 000000000000..5dca5a2cb880 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb2lvds.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + + +/ { + panel-rgb { + compatible = "simple-panel"; + status = "okay"; + backlight = <&backlight>; + enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + reset-delay-ms = <20>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <164>; + height-mm = <100>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <140>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + pwms = <&pwm9 0 25000 0>; + status = "okay"; +}; + +&dsi { + status = "disabled"; +}; + +/* + * The pins of gmac0 and rgb are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&rgb { + status = "okay"; + pinctrl-0 = <&rgb666_pins>; + + ports { + port@1 { + reg = <1>; + + rgb_out_panel: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&rgb_in_vp1 { + status = "disabled"; +}; + +&pwm9 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + status = "okay"; +}; + +&route_rgb { + status = "okay"; + connect = <&vp0_out_rgb>; +}; + +/* + * The pins of sai0 and backlight are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; From 5ac9874dfd8e21a6c21c1f8f55810ea35b317c37 Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Thu, 2 Feb 2023 21:27:53 +0800 Subject: [PATCH 069/258] arm64: configs: add rk3562_linux_dictpen_defconfig add config for rk3562 linux dictionary pen product vs rockchip_linux_defconfig: 1.size of arch/arm64/boot/Image: 33MiB -> 10.5MiB 2.boot time from DDR to Run /sbin/init: 2.25s -> 1.51s (CPU:1008M DDR:780M) Change-Id: I57e6a0109a403f6d87960c032d6e1c1ab06ffef1 Signed-off-by: Nickey Yang --- .../configs/rk3562_linux_dictpen_defconfig | 318 ++++++++++++++++++ 1 file changed, 318 insertions(+) create mode 100644 arch/arm64/configs/rk3562_linux_dictpen_defconfig diff --git a/arch/arm64/configs/rk3562_linux_dictpen_defconfig b/arch/arm64/configs/rk3562_linux_dictpen_defconfig new file mode 100644 index 000000000000..3aa1b7d6fde1 --- /dev/null +++ b/arch/arm64/configs/rk3562_linux_dictpen_defconfig @@ -0,0 +1,318 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="localhost" +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +# CONFIG_BASE_FULL is not set +# CONFIG_IO_URING is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_SYSFS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_ZONE_DMA is not set +CONFIG_ARCH_ROCKCHIP=y +# CONFIG_ARM64_ERRATUM_826319 is not set +# CONFIG_ARM64_ERRATUM_827319 is not set +# CONFIG_ARM64_ERRATUM_824069 is not set +# CONFIG_ARM64_ERRATUM_819472 is not set +# CONFIG_ARM64_ERRATUM_832075 is not set +# CONFIG_ARM64_ERRATUM_1418040 is not set +# CONFIG_ARM64_ERRATUM_1165522 is not set +# CONFIG_ARM64_ERRATUM_1319367 is not set +# CONFIG_ARM64_ERRATUM_1530923 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_ERRATUM_1508412 is not set +# CONFIG_ARM64_ERRATUM_2054223 is not set +# CONFIG_ARM64_ERRATUM_2067961 is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=4 +CONFIG_HZ_300=y +CONFIG_COMPAT=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +# CONFIG_ARM64_PTR_AUTH is not set +# CONFIG_ARM64_AMU_EXTN is not set +# CONFIG_ARM64_TLB_RANGE is not set +# CONFIG_ARM64_BTI is not set +# CONFIG_ARM64_E0PD is not set +# CONFIG_ARCH_RANDOM is not set +# CONFIG_ARM64_MTE is not set +# CONFIG_ARM64_SVE is not set +CONFIG_ARM64_PSEUDO_NMI=y +# CONFIG_EFI is not set +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ENERGY_MODEL=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_ROCKCHIP_CPUFREQ=y +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ROCKCHIP_SIP=y +# CONFIG_SECCOMP is not set +# CONFIG_STACKPROTECTOR_STRONG is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEBUG_FS is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_MSDOS_PARTITION is not set +# CONFIG_COMPACTION is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_HS=y +CONFIG_CFG80211_WEXT=y +CONFIG_RFKILL=y +CONFIG_RFKILL_RK=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_SRAM=y +CONFIG_NETDEVICES=y +# CONFIG_ETHERNET is not set +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_WL_ROCKCHIP=y +CONFIG_WIFI_BUILD_MODULE=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_RK805_PWRKEY=y +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=5 +CONFIG_SERIAL_8250_RUNTIME_UARTS=5 +CONFIG_SERIAL_8250_DW=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_RK3X=y +CONFIG_PINCTRL_RK805=y +CONFIG_GPIO_SYSFS=y +# CONFIG_GPIO_CDEV is not set +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_RK817=y +CONFIG_CHARGER_RK817=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_ROCKCHIP_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_MFD_RK808=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK808=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_MEDIA_TEST_SUPPORT is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_ROCKCHIP_CIF=y +CONFIG_VIDEO_ROCKCHIP_ISP=y +CONFIG_VIDEO_OV7251=y +CONFIG_VIDEO_SC031GS=y +CONFIG_DRM=y +CONFIG_DRM_IGNORE_IOTCL_PERMIT=y +# CONFIG_DRM_FBDEV_EMULATION is not set +CONFIG_DRM_ROCKCHIP=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_MALI_BIFROST=y +CONFIG_MALI_PLATFORM_NAME="rk" +CONFIG_MALI_BIFROST_EXPERT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_ROCKCHIP_MULTI_RGA=y +CONFIG_ROCKCHIP_RGA_PROC_FS=y +# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set +CONFIG_ROCKCHIP_MPP_SERVICE=y +CONFIG_ROCKCHIP_MPP_RKVDEC2=y +CONFIG_ROCKCHIP_MPP_VDPU2=y +CONFIG_ROCKCHIP_MPP_JPGDEC=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_PCM_TIMER is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_PROC_FS is not set +CONFIG_SND_ALOOP=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_ROCKCHIP=y +CONFIG_SND_SOC_ROCKCHIP_SAI=y +CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y +CONFIG_SND_SOC_RK817=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_HUSB311=y +CONFIG_TYPEC_FUSB302=y +CONFIG_TYPEC_DP_ALTMODE=y +CONFIG_MMC=y +# CONFIG_PWRSEQ_EMMC is not set +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_RK808=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_STAGING=y +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_NO_SLEEP=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_RK_CONSOLE_THREAD=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCMI=y +# CONFIG_ROCKCHIP_CLK_PVTM is not set +# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set +CONFIG_IOMMU_LIMIT_IOVA_ALIGNMENT=y +CONFIG_IOMMU_IOVA_ALIGNMENT=4 +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_CPU_RK3562=y +CONFIG_ROCKCHIP_CPUINFO=y +CONFIG_ROCKCHIP_GRF=y +CONFIG_ROCKCHIP_OPP=y +CONFIG_ROCKCHIP_PERFORMANCE=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +CONFIG_ROCKCHIP_SUSPEND_MODE=y +CONFIG_ROCKCHIP_SYSTEM_MONITOR=y +CONFIG_ROCKCHIP_VENDOR_STORAGE=y +CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE=y +CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y +CONFIG_ROCKCHIP_DEBUG=y +CONFIG_ROCKCHIP_MINI_KERNEL=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=y +CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y +CONFIG_EXTCON=y +CONFIG_IIO=y +CONFIG_ROCKCHIP_SARADC=y +CONFIG_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y +CONFIG_ANDROID=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_RK_HEADSET=y +CONFIG_ROCKCHIP_RKNPU=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_HW is not set +CONFIG_DMA_CMA=y +CONFIG_PRINTK_TIME=y +CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_MISC is not set +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_TIMEOUT=5 +# CONFIG_SCHED_DEBUG is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_RUNTIME_TESTING_MENU is not set From 08546dd843f810246326617bd924adcaed102162 Mon Sep 17 00:00:00 2001 From: Jianlong Wang Date: Fri, 6 Jan 2023 15:10:11 +0800 Subject: [PATCH 070/258] arm64: dts: rockchip: rk3358-evb-ddr3.dtsi: rk809 compatible to rockchip,multicodecs-card Signed-off-by: Jianlong Wang Change-Id: I0cad1068489027d1bfac80d240cbb24ca7cd3e9e --- .../boot/dts/rockchip/rk3358-evb-ddr3.dtsi | 43 ++++++++----------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3.dtsi b/arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3.dtsi index 4abca9c2fc55..104af907f4a0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3.dtsi @@ -97,33 +97,26 @@ status = "okay"; }; - rk809-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rk809-codec"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - simple-audio-card,cpu { - sound-dai = <&i2s1_2ch>; - }; - simple-audio-card,codec { - sound-dai = <&rk809_codec>; - }; - }; - - rk_headset: rk-headset { - compatible = "rockchip_headset"; - headset_gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 1>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_2ch>; + rockchip,codec = <&rk809_codec>; pinctrl-names = "default"; pinctrl-0 = <&hp_det>; - io-channels = <&saradc 1>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; }; sdio_pwrseq: sdio-pwrseq { From 270801db590fb59d0781bad1fd50a23d89c54b1e Mon Sep 17 00:00:00 2001 From: Jianlong Wang Date: Mon, 6 Feb 2023 17:55:52 +0800 Subject: [PATCH 071/258] arm64: dts: rockchip: rk3358-linux.dtsi: add ramoops device node Signed-off-by: Jianlong Wang Change-Id: If2497b36f984348467948f15a97c62bd8fe6668d --- arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi b/arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi index cdaecbc7c1e9..97d6434a869d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3358-linux.dtsi @@ -33,6 +33,15 @@ compatible = "rockchip,drm-logo"; reg = <0x0 0x0 0x0 0x0>; }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; }; }; From d6c491185ea0d54608131615b9e8c3dd27f96fb1 Mon Sep 17 00:00:00 2001 From: Jianlong Wang Date: Tue, 7 Feb 2023 15:11:34 +0800 Subject: [PATCH 072/258] arm64: configs: px30_linux_defconfig: enable CONFIG_PSTORE Signed-off-by: Jianlong Wang Change-Id: I00d69aefef747372dcbb42d85638db6189646f05 --- arch/arm64/configs/px30_linux_defconfig | 5 +++++ arch/arm64/configs/rk3326_linux.config | 21 --------------------- 2 files changed, 5 insertions(+), 21 deletions(-) diff --git a/arch/arm64/configs/px30_linux_defconfig b/arch/arm64/configs/px30_linux_defconfig index 22a47364ae84..a15667bbad88 100644 --- a/arch/arm64/configs/px30_linux_defconfig +++ b/arch/arm64/configs/px30_linux_defconfig @@ -374,6 +374,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="utf8" CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_SQUASHFS=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_FTRACE=y +CONFIG_PSTORE_RAM=y CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y diff --git a/arch/arm64/configs/rk3326_linux.config b/arch/arm64/configs/rk3326_linux.config index 28f7539ce7c9..19968f6a6ce8 100644 --- a/arch/arm64/configs/rk3326_linux.config +++ b/arch/arm64/configs/rk3326_linux.config @@ -1,34 +1,13 @@ -CONFIG_CRYPTO_DEFLATE=y # CONFIG_ETHERNET is not set CONFIG_MD=y -CONFIG_PSTORE=y CONFIG_SND_SOC_ROCKCHIP_PDM=y CONFIG_VIDEO_ROCKCHIP_CIF=y # CONFIG_BCACHE is not set # CONFIG_BLK_DEV_DM is not set # CONFIG_BLK_DEV_MD is not set -# CONFIG_DPM_WATCHDOG is not set -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_BOOT_LOG is not set -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -# CONFIG_PSTORE_FTRACE is not set -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_PMSG is not set -CONFIG_PSTORE_RAM=y -# CONFIG_PSTORE_ZSTD_COMPRESS is not set -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y CONFIG_ROCKCHIP_CIF_USE_DUMMY_BUF=y # CONFIG_ROCKCHIP_CIF_USE_MONITOR is not set # CONFIG_ROCKCHIP_CIF_USE_NONE_DUMMY_BUF is not set # CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y CONFIG_VIDEOBUF2_CMA_SG=y -CONFIG_ZLIB_DEFLATE=y From 9f908ad29d8d8eecfe6b48703e7bc05d0bd48e77 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Fri, 3 Feb 2023 09:36:53 +0800 Subject: [PATCH 073/258] media: rockchip: isp: stats buf add application params frame id Change-Id: Ib343caba3c4e378661d83f0485a9e0a2940367f3 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/isp_params.h | 2 +- drivers/media/platform/rockchip/isp/isp_params_v21.c | 1 + drivers/media/platform/rockchip/isp/isp_params_v32.c | 1 + drivers/media/platform/rockchip/isp/isp_params_v3x.c | 1 + drivers/media/platform/rockchip/isp/isp_stats_v21.c | 2 ++ drivers/media/platform/rockchip/isp/isp_stats_v32.c | 3 +++ drivers/media/platform/rockchip/isp/isp_stats_v3x.c | 2 ++ include/uapi/linux/rkisp21-config.h | 1 + include/uapi/linux/rkisp3-config.h | 1 + include/uapi/linux/rkisp32-config.h | 1 + 10 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/rockchip/isp/isp_params.h b/drivers/media/platform/rockchip/isp/isp_params.h index 1d6f3591f7c5..9555e234ece6 100644 --- a/drivers/media/platform/rockchip/isp/isp_params.h +++ b/drivers/media/platform/rockchip/isp/isp_params.h @@ -76,7 +76,7 @@ struct rkisp_isp_params_vdev { enum v4l2_quantization quantization; enum rkisp_fmt_raw_pat_type raw_type; u32 in_mbus_code; - + u32 cur_frame_id; struct preisp_hdrae_para_s hdrae_para; struct rkisp_isp_params_ops *ops; diff --git a/drivers/media/platform/rockchip/isp/isp_params_v21.c b/drivers/media/platform/rockchip/isp/isp_params_v21.c index 44dd7a945b92..9b42f6a4ba92 100644 --- a/drivers/media/platform/rockchip/isp/isp_params_v21.c +++ b/drivers/media/platform/rockchip/isp/isp_params_v21.c @@ -3648,6 +3648,7 @@ void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops; u64 module_cfg_update = new_params->module_cfg_update; + params_vdev->cur_frame_id = new_params->frame_id; if (type == RKISP_PARAMS_SHD) return; diff --git a/drivers/media/platform/rockchip/isp/isp_params_v32.c b/drivers/media/platform/rockchip/isp/isp_params_v32.c index 6d1c9430082b..bd136d73a3cb 100644 --- a/drivers/media/platform/rockchip/isp/isp_params_v32.c +++ b/drivers/media/platform/rockchip/isp/isp_params_v32.c @@ -3961,6 +3961,7 @@ void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; u64 module_cfg_update = new_params->module_cfg_update; + params_vdev->cur_frame_id = new_params->frame_id; if (type == RKISP_PARAMS_SHD) return; diff --git a/drivers/media/platform/rockchip/isp/isp_params_v3x.c b/drivers/media/platform/rockchip/isp/isp_params_v3x.c index d5952bfcd8fb..e31c2500903e 100644 --- a/drivers/media/platform/rockchip/isp/isp_params_v3x.c +++ b/drivers/media/platform/rockchip/isp/isp_params_v3x.c @@ -4016,6 +4016,7 @@ void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops; u64 module_cfg_update = new_params->module_cfg_update; + params_vdev->cur_frame_id = new_params->frame_id; if (type == RKISP_PARAMS_SHD) return; diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v21.c b/drivers/media/platform/rockchip/isp/isp_stats_v21.c index 065d2dbd08ab..cb835eee69cb 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats_v21.c +++ b/drivers/media/platform/rockchip/isp/isp_stats_v21.c @@ -948,6 +948,7 @@ rkisp_stats_send_meas_v21(struct rkisp_isp_stats_vdev *stats_vdev, struct rkisp_isp21_stat_buffer *cur_stat_buf = NULL; struct rkisp_stats_v21_ops *ops = (struct rkisp_stats_v21_ops *)stats_vdev->priv_ops; + struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev; int ret = 0; cur_frame_id = meas_work->frame_id; @@ -966,6 +967,7 @@ rkisp_stats_send_meas_v21(struct rkisp_isp_stats_vdev *stats_vdev, cur_stat_buf = (struct rkisp_isp21_stat_buffer *)(cur_buf->vaddr[0]); cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; } if (meas_work->isp_ris & ISP2X_AFM_SUM_OF) diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v32.c b/drivers/media/platform/rockchip/isp/isp_stats_v32.c index b66d0caf4715..fb6a9bb0c723 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats_v32.c +++ b/drivers/media/platform/rockchip/isp/isp_stats_v32.c @@ -509,6 +509,7 @@ rkisp_stats_send_meas_v32(struct rkisp_isp_stats_vdev *stats_vdev, struct rkisp32_isp_stat_buffer *cur_stat_buf = NULL; struct rkisp_stats_ops_v32 *ops = (struct rkisp_stats_ops_v32 *)stats_vdev->priv_ops; + struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev; u32 size = sizeof(struct rkisp32_isp_stat_buffer); int ret = 0; bool is_dummy = false; @@ -600,6 +601,7 @@ rkisp_stats_send_meas_v32(struct rkisp_isp_stats_vdev *stats_vdev, list_del(&cur_buf->queue); } else { cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; } spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); if (cur_buf) { @@ -609,6 +611,7 @@ rkisp_stats_send_meas_v32(struct rkisp_isp_stats_vdev *stats_vdev, } if (cur_buf && cur_stat_buf) { cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; cur_stat_buf->params.info2ddr.buf_fd = -1; cur_stat_buf->params.info2ddr.owner = 0; rkisp_stats_info2ddr(stats_vdev, cur_stat_buf); diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v3x.c b/drivers/media/platform/rockchip/isp/isp_stats_v3x.c index 43aeb618b6f9..3b72a1c339f0 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats_v3x.c +++ b/drivers/media/platform/rockchip/isp/isp_stats_v3x.c @@ -970,6 +970,7 @@ rkisp_stats_send_meas_v3x(struct rkisp_isp_stats_vdev *stats_vdev, struct rkisp3x_isp_stat_buffer *cur_stat_buf = NULL; struct rkisp_stats_ops_v3x *ops = (struct rkisp_stats_ops_v3x *)stats_vdev->priv_ops; + struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev; int ret = 0; u32 size = sizeof(struct rkisp3x_isp_stat_buffer); @@ -989,6 +990,7 @@ rkisp_stats_send_meas_v3x(struct rkisp_isp_stats_vdev *stats_vdev, cur_stat_buf = (struct rkisp3x_isp_stat_buffer *)(cur_buf->vaddr[0]); cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; } if (meas_work->isp_ris & ISP3X_AFM_SUM_OF) diff --git a/include/uapi/linux/rkisp21-config.h b/include/uapi/linux/rkisp21-config.h index fc72ef94159b..3e83014823f7 100644 --- a/include/uapi/linux/rkisp21-config.h +++ b/include/uapi/linux/rkisp21-config.h @@ -805,6 +805,7 @@ struct isp21_stat { struct rkisp_isp21_stat_buffer { unsigned int meas_type; unsigned int frame_id; + unsigned int params_id; struct isp21_stat params; } __attribute__ ((packed)); diff --git a/include/uapi/linux/rkisp3-config.h b/include/uapi/linux/rkisp3-config.h index 1ea2a910385c..06cb06807b7e 100644 --- a/include/uapi/linux/rkisp3-config.h +++ b/include/uapi/linux/rkisp3-config.h @@ -1070,6 +1070,7 @@ struct isp3x_stat { struct rkisp3x_isp_stat_buffer { u32 meas_type; u32 frame_id; + u32 params_id; struct isp3x_stat params; } __attribute__ ((packed)); diff --git a/include/uapi/linux/rkisp32-config.h b/include/uapi/linux/rkisp32-config.h index c2ad9123a3d7..a967b3aad751 100644 --- a/include/uapi/linux/rkisp32-config.h +++ b/include/uapi/linux/rkisp32-config.h @@ -1398,6 +1398,7 @@ struct rkisp32_isp_stat_buffer { struct isp32_stat params; u32 meas_type; u32 frame_id; + u32 params_id; } __attribute__ ((packed)); struct rkisp32_thunderboot_resmem_head { From c38ee7a65d9578a422a3de4330075cbf23a86bdc Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Tue, 7 Feb 2023 15:48:01 +0800 Subject: [PATCH 074/258] media: rockchip: isp: version v2.1.0 Change-Id: Ie02dfdad44f9f67a765fe577b609346552a35a59 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/version.h | 47 +++++++++++++++++++ include/uapi/linux/rkisp2-config.h | 2 +- 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/rockchip/isp/version.h b/drivers/media/platform/rockchip/isp/version.h index 01bd28330c38..ff76f199011e 100644 --- a/drivers/media/platform/rockchip/isp/version.h +++ b/drivers/media/platform/rockchip/isp/version.h @@ -357,6 +357,53 @@ * 79.fix isp32 stream force to update enable * 80.fix mi no disable for multi sensor unite mode * 81.fix size for multi isp composite mode + * + * v2.1.0 + * 1.fix mipi error for isp2x with multi sensor + * 2.default reg config after reset + * 3.fix isp20 mi no work + * 4.fix stream off just close isp + * 5.remove the judgment that gain turn off if ldch is enabled + * 6.drop first output for fast case + * 7.fix scl for unite mode + * 8.no wait if shutdown + * 9.fix stream no output for multi senso + * 10.fix hdr config for unite multi sensor + * 11.make sure to free buf after isp stop + * 12.improve thunder boot process + * 13.second frame first run for fast + * 14.multi sensor for fast case + * 15.fix fbc output for isp30 multi sensor + * 16.frame start to update buf for isp30 + * 17.fix stream switch when readback mode + * 18.remove unsupported formats + * 19.fix stats buf update for multi sensor + * 20.fix self update config for isp30 + * 21.fix dmatx loss first buf + * 22.fix rockit stream pause if readback mode + * 23.fix isp32 cmsk feature + * 24.online rx add memory compact or no + * 25.remove cif/isp/ispp hw SYSTEM_SLEEP_PM_OPS + * 26.api to force enum multi isp resolution + * 27.isp30 3a to ddr for readback mode + * 28.sync stop to dmarx for isp stop + * 29.fix mulit isp x3 mode + * 30.fix lsc table read by isp for multi sensor + * 31.merge dual dhaz config chang to user for unite mode + * 32.no support rgb8888 for isp30 + * 33.fix iommu err for stream stop + * 34.fix 3a to ddr iommu err for isp30 two readback mode + * 35.400ms timeout for rtt complete + * 36.add mosaic block size for cmsk + * 37.wrap width and height config by user + * 38.fix ldch err + * 39.fix isp32 vflip config + * 40.dump two isp reg for unite mode + * 41.fix output stream sync for readback mode + * 42.wait isp0 end for unite mode + * 43.fix first frame loss + * 44.fix rgb range for selfpath + * 45.stats buf add application params frame id */ #define RKISP_DRIVER_VERSION RKISP_API_VERSION diff --git a/include/uapi/linux/rkisp2-config.h b/include/uapi/linux/rkisp2-config.h index b97846c879ad..667aad1f4d1a 100644 --- a/include/uapi/linux/rkisp2-config.h +++ b/include/uapi/linux/rkisp2-config.h @@ -10,7 +10,7 @@ #include #include -#define RKISP_API_VERSION KERNEL_VERSION(2, 0, 0) +#define RKISP_API_VERSION KERNEL_VERSION(2, 1, 0) /****************ISP SUBDEV IOCTL*****************************/ From 717debc7f2c836050141d85f96329ad3c199591c Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Fri, 3 Feb 2023 07:44:24 +0000 Subject: [PATCH 075/258] drm/rockchip: vop2: Use devm_clk_get_optional() in vop2_extend_clk_init() Silence warning print if didn't have a clock reference in the DT. Signed-off-by: Wyon Bi Change-Id: I1e6276950e6e582a424daec5b46e51d08d5fe05a --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 14cb1c3f5201..686835c160be 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -3993,13 +3993,16 @@ static int vop2_extend_clk_init(struct vop2 *vop2) return 0; for (i = 0; i < ARRAY_SIZE(extend_clk_name); i++) { - clk = devm_clk_get(drm_dev->dev, extend_clk_name[i]); + clk = devm_clk_get_optional(drm_dev->dev, extend_clk_name[i]); if (IS_ERR(clk)) { dev_warn(drm_dev->dev, "failed to get %s: %ld\n", extend_clk_name[i], PTR_ERR(clk)); continue; } + if (!clk) + continue; + extend_pll = devm_kzalloc(drm_dev->dev, sizeof(*extend_pll), GFP_KERNEL); if (!extend_pll) return -ENOMEM; From 72baf7945d56aaffc679d1b2e6de4450d503980a Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Fri, 6 Jan 2023 15:24:23 +0800 Subject: [PATCH 076/258] arm64: dts: rockchip: rk3308: Sync with upstream Signed-off-by: Tao Huang Change-Id: I632c4ff0b86275d3d11969377185d48c64dec76c --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 108 ++++++++++++----------- 1 file changed, 58 insertions(+), 50 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index d74ef9812c99..2526a05ef890 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -464,37 +464,36 @@ }; usb2phy_grf: syscon@ff008000 { - compatible = "rockchip,rk3308-usb2phy-grf", "syscon", - "simple-mfd"; + compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xff008000 0x0 0x4000>; #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,rk3308-usb2phy"; reg = <0x100 0x10>; - clocks = <&cru SCLK_USBPHY_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; assigned-clocks = <&cru USB480M>; assigned-clock-parents = <&u2phy>; + clocks = <&cru SCLK_USBPHY_REF>; + clock-names = "phyclk"; clock-output-names = "usb480m_phy"; + #clock-cells = <0>; status = "disabled"; u2phy_otg: otg-port { - #phy-cells = <0>; interrupts = , , ; interrupt-names = "otg-bvalid", "otg-id", "linestate"; + #phy-cells = <0>; status = "disabled"; }; u2phy_host: host-port { - #phy-cells = <0>; interrupts = ; interrupt-names = "linestate"; + #phy-cells = <0>; status = "disabled"; }; }; @@ -573,7 +572,7 @@ }; wdt: watchdog@ff080000 { - compatible = "snps,dw-wdt"; + compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; reg = <0x0 0xff080000 0x0 0x100>; clocks = <&cru PCLK_WDT>; interrupts = ; @@ -950,33 +949,26 @@ }; }; - amba: bus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + dmac0: dma-controller@ff2c0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2c0000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; - dmac0: dma-controller@ff2c0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2c0000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@ff2d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2d0000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; + dmac1: dma-controller@ff2d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2d0000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; }; vop: vop@ff2e0000 { @@ -1212,7 +1204,8 @@ }; usb20_otg: usb@ff400000 { - compatible = "rockchip,rk3066-usb", "snps,dwc2"; + compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", + "snps,dwc2"; reg = <0x0 0xff400000 0x0 0x40000>; interrupts = ; clocks = <&cru HCLK_OTG>; @@ -1291,6 +1284,21 @@ status = "disabled"; }; + nfc: nand-controller@ff4b0000 { + compatible = "rockchip,rk3308-nfc", + "rockchip,rv1108-nfc"; + reg = <0x0 0xff4b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 + &flash_rdn &flash_rdy &flash_wrn>; + pinctrl-names = "default"; + status = "disabled"; + }; + nandc: nandc@ff4b0000 { compatible = "rockchip,rk-nandc"; reg = <0x0 0xff4b0000 0x0 0x4000>; @@ -1301,21 +1309,9 @@ status = "disabled"; }; - sfc: sfc@ff4c0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xff4c0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - assigned-clocks = <&cru SCLK_SFC>; - assigned-clock-rates = <100000000>; - status = "disabled"; - }; - mac: ethernet@ff4e0000 { compatible = "rockchip,rk3308-mac"; reg = <0x0 0xff4e0000 0x0 0x10000>; - rockchip,grf = <&grf>; interrupts = ; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, @@ -1331,16 +1327,28 @@ pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; resets = <&cru SRST_MAC_A>; reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + sfc: spi@ff4c0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff4c0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; status = "disabled"; }; cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; rockchip,grf = <&grf>; rockchip,boost = <&cpu_boost>; + #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&cru SCLK_RTC32K>; assigned-clock-rates = <32768>; }; From 479b4d68510d8ecfa80b6357de9307309953ef1d Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Tue, 7 Feb 2023 19:58:15 +0800 Subject: [PATCH 077/258] arm64: dts: rockchip: pinconf: Sync with upstream Signed-off-by: Tao Huang Change-Id: I7cd9c2d2c61ce008efef6781eb59bcaaf7e0164d --- arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi index a836e12f2105..72d644575cf9 100644 --- a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi +++ b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi @@ -1,10 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2020~2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. */ &pinctrl { - /omit-if-no-ref/ pcfg_pull_up: pcfg-pull-up { bias-pull-up; @@ -414,4 +413,3 @@ bias-disable; }; }; - From 721af6e07935d81eb6c7669a2d74d9227efdcfe5 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 2 Feb 2023 20:11:52 +0800 Subject: [PATCH 078/258] arm64: dts: rockchip: rk3562-rk817-tablet-v10: Enable tsadc Signed-off-by: Finley Xiao Change-Id: I07edce95737941f071e108e12db2fde6cc05bf3e --- arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts index 4702884fc428..38c916ccb47a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts @@ -1010,6 +1010,10 @@ status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy { status = "okay"; }; From 40b48438999fd6b45cb9bc5607b9ddf63eeba4b4 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Tue, 7 Feb 2023 20:16:36 +0800 Subject: [PATCH 079/258] spi: rockchip: Sync with upstream Signed-off-by: Tao Huang Change-Id: Ia25e81a1ac5dca491ff31bd3557eac61bbd0962e --- drivers/spi/spi-rockchip.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 03ae4ab93fc8..3e2de189d371 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -601,9 +601,9 @@ static int rockchip_spi_config(struct rockchip_spi *rs, enum rockchip_spi_xfer_mode xfer_mode, bool slave_mode) { u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET - | CR0_BHT_8BIT << CR0_BHT_OFFSET - | CR0_SSD_ONE << CR0_SSD_OFFSET - | CR0_EM_BIG << CR0_EM_OFFSET; + | CR0_BHT_8BIT << CR0_BHT_OFFSET + | CR0_SSD_ONE << CR0_SSD_OFFSET + | CR0_EM_BIG << CR0_EM_OFFSET; u32 cr1; u32 dmacr = 0; @@ -761,7 +761,6 @@ static int rockchip_spi_slave_abort(struct spi_controller *ctlr) *(u16 *)rs->rx = (u16)rxw; rs->rx += rs->n_bytes; } - rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf); } From 25a24f5d20f7b410bf139c0b443ef8b607e5ead9 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 7 Feb 2023 20:26:32 +0800 Subject: [PATCH 080/258] clk: rockchip: rk3562: Remove CLK_IGNORE_UNUSED for pclk_intc Signed-off-by: Finley Xiao Change-Id: I211d7d8680f73438818b712bc274b51a2c445038 --- drivers/clk/rockchip/clk-rk3562.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c index b1080fb1f652..a9f9129a7b87 100644 --- a/drivers/clk/rockchip/clk-rk3562.c +++ b/drivers/clk/rockchip/clk-rk3562.c @@ -391,7 +391,7 @@ static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = { RK3562_CLKGATE_CON(22), 3, GFLAGS), GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3562_CLKGATE_CON(22), 4, GFLAGS), - GATE(PCLK_INTC, "pclk_intc", "pclk_bus", CLK_IGNORE_UNUSED, + GATE(PCLK_INTC, "pclk_intc", "pclk_bus", 0, RK3562_CLKGATE_CON(22), 5, GFLAGS), GATE(ACLK_BUS_GIC400, "aclk_bus_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3562_CLKGATE_CON(22), 6, GFLAGS), From 7c9551becd596acb38528cb067f2828ddf5f75d1 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 10 Aug 2021 09:10:07 +0800 Subject: [PATCH 081/258] BACKPORT: iio: adc: rockchip_saradc: add voltage notifier so get referenced voltage once at probe Add voltage notifier, no need to query regulator voltage for every saradc read, just get regulator voltage once at probe. Signed-off-by: David Wu Signed-off-by: Simon Xue Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20210810011007.54066-1-xxm@rock-chips.com Signed-off-by: Jonathan Cameron (cherry picked from commit cabd6e9cf22dc80544c3eb09c4169a05e94a6d3f) Change-Id: I5723398bac6e1349b60f36c0088a49884f0106bb --- drivers/iio/adc/rockchip_saradc.c | 39 ++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index a923fb0b2410..273110713bcb 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -73,6 +73,7 @@ struct rockchip_saradc { const struct rockchip_saradc_data *data; u16 last_val; const struct iio_chan_spec *last_chan; + struct notifier_block nb; bool suspended; #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN bool test; @@ -499,6 +500,26 @@ out: return IRQ_HANDLED; } +static int rockchip_saradc_volt_notify(struct notifier_block *nb, + unsigned long event, + void *data) +{ + struct rockchip_saradc *info = + container_of(nb, struct rockchip_saradc, nb); + + if (event & REGULATOR_EVENT_VOLTAGE_CHANGE) + info->uv_vref = (unsigned long)data; + + return NOTIFY_OK; +} + +static void rockchip_saradc_regulator_unreg_notifier(void *data) +{ + struct rockchip_saradc *info = data; + + regulator_unregister_notifier(info->vref, &info->nb); +} + #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN static ssize_t saradc_test_chn_store(struct device *dev, struct device_attribute *attr, @@ -680,13 +701,14 @@ static int rockchip_saradc_probe(struct platform_device *pdev) return ret; } - info->uv_vref = regulator_get_voltage(info->vref); - if (info->uv_vref < 0) { + ret = regulator_get_voltage(info->vref); + if (ret < 0) { dev_err(&pdev->dev, "failed to get voltage\n"); - ret = info->uv_vref; return ret; } + info->uv_vref = ret; + ret = clk_prepare_enable(info->pclk); if (ret < 0) { dev_err(&pdev->dev, "failed to enable pclk\n"); @@ -727,6 +749,17 @@ static int rockchip_saradc_probe(struct platform_device *pdev) if (ret) return ret; + info->nb.notifier_call = rockchip_saradc_volt_notify; + ret = regulator_register_notifier(info->vref, &info->nb); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&pdev->dev, + rockchip_saradc_regulator_unreg_notifier, + info); + if (ret) + return ret; + #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN info->wq = create_singlethread_workqueue("adc_wq"); INIT_DELAYED_WORK(&info->work, rockchip_saradc_test_work); From f8652ea55ef10ec71ed221eae943d622ec3c268c Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Mon, 6 Feb 2023 15:15:39 +0800 Subject: [PATCH 082/258] rpmsg: rockchip: add rk3562 support Signed-off-by: Steven Liu Change-Id: I99b0f06ea787376fe0e2c1098d3d193e2a19859b --- drivers/rpmsg/rockchip_rpmsg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/rpmsg/rockchip_rpmsg.c b/drivers/rpmsg/rockchip_rpmsg.c index c335aa4bad65..be1b202a156b 100644 --- a/drivers/rpmsg/rockchip_rpmsg.c +++ b/drivers/rpmsg/rockchip_rpmsg.c @@ -27,6 +27,7 @@ #include "rpmsg_internal.h" enum rk_rpmsg_chip { + RK3562, RK3568, }; @@ -399,6 +400,7 @@ static int rockchip_rpmsg_remove(struct platform_device *pdev) } static const struct of_device_id rockchip_rpmsg_match[] = { + { .compatible = "rockchip,rk3562-rpmsg", .data = (void *)RK3562, }, { .compatible = "rockchip,rk3568-rpmsg", .data = (void *)RK3568, }, { /* sentinel */ }, }; From c115ee06bc96c85a8dee9be9a1d2b2e8cc386487 Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Mon, 6 Feb 2023 15:23:38 +0800 Subject: [PATCH 083/258] arm64: dts: rockchip: rk3562-amp: add rpmsg node Signed-off-by: Steven Liu Change-Id: I4a1b1842414042c91a3365161f3baea236f7dc7d --- arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi index 80e194e2bcec..66ece0360c78 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi @@ -7,9 +7,11 @@ rockchip_amp: rockchip-amp { compatible = "rockchip,mcu-amp"; clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>, + <&cru PCLK_MAILBOX>, <&cru PCLK_INTC>, <&cru SCLK_UART5>, <&cru PCLK_UART5>, <&cru PCLK_TIMER>, <&cru CLK_TIMER5>; clock-names = "fclk_bus_cm0_core", "clk_bus_cm0_rtc", + "pclk_maikbox", "pclk_intc", "baudclk", "apb_pclk", "pclk", "timer"; pinctrl-names = "default"; @@ -18,6 +20,18 @@ status = "okay"; }; + rpmsg: rpmsg@a0000000 { + compatible = "rockchip,rk3562-rpmsg"; + mbox-names = "rpmsg-rx", "rpmsg-tx"; + mboxes = <&mailbox 0 &mailbox 3>; + rockchip,vdev-nums = <1>; + rockchip,link-id = <0x04>; + reg = <0x0 0xa0000000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -28,6 +42,20 @@ reg = <0x0 0x8200000 0x0 0x100000>; no-map; }; + + rpmsg_reserved: rpmsg@a0000000 { + reg = <0x0 0xa0000000 0x0 0x400000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@a0400000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xa0400000 0x0 0x100000>; + no-map; + }; }; }; +&mailbox { + status = "okay"; +}; From a0881c07c2a29794327d79c1b6eed9eede4a007b Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Tue, 31 Jan 2023 10:22:20 +0800 Subject: [PATCH 084/258] ASoC: codecs: support rk dsm Support rockchip Delta-sigma Digital Converter. And it only has DAC which is a reduced version of rk_codec_digital. Signed-off-by: Jason Zhu Change-Id: I0444ac99b12ed4d8cfb6df4034392dbd844e2bca --- sound/soc/codecs/Kconfig | 3 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rk_dsm.c | 645 ++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/rk_dsm.h | 176 +++++++++++ 4 files changed, 826 insertions(+) create mode 100644 sound/soc/codecs/rk_dsm.c create mode 100644 sound/soc/codecs/rk_dsm.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 38c79e21630e..9a9173ff39c0 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1119,6 +1119,9 @@ config SND_SOC_RK817 config SND_SOC_RK_CODEC_DIGITAL tristate "Rockchip Codec Digital Interface" +config SND_SOC_RK_DSM + tristate "Rockchip Delta-sigma Digital Converter Interface" + config SND_SOC_RL6231 tristate default y if SND_SOC_RT5514=y diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 204868b9c308..20ee39074e71 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -172,6 +172,7 @@ snd-soc-rk3528-objs := rk3528_codec.o snd-soc-rk730-objs := rk730.o snd-soc-rk817-objs := rk817_codec.o snd-soc-rk-codec-digital-objs := rk_codec_digital.o +snd-soc-rk-dsm-objs := rk_dsm.o snd-soc-rl6231-objs := rl6231.o snd-soc-rl6347a-objs := rl6347a.o snd-soc-rt1011-objs := rt1011.o @@ -498,6 +499,7 @@ obj-$(CONFIG_SND_SOC_RK3528) += snd-soc-rk3528.o obj-$(CONFIG_SND_SOC_RK730) += snd-soc-rk730.o obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o obj-$(CONFIG_SND_SOC_RK_CODEC_DIGITAL) += snd-soc-rk-codec-digital.o +obj-$(CONFIG_SND_SOC_RK_DSM) += snd-soc-rk-dsm.o obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o obj-$(CONFIG_SND_SOC_RT1011) += snd-soc-rt1011.o diff --git a/sound/soc/codecs/rk_dsm.c b/sound/soc/codecs/rk_dsm.c new file mode 100644 index 000000000000..616014a7322f --- /dev/null +++ b/sound/soc/codecs/rk_dsm.c @@ -0,0 +1,645 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Rockchip Audio Delta-sigma Digital Converter Interface + * + * Copyright (C) 2023 Rockchip Electronics Co.,Ltd + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk_dsm.h" + +#define RK3562_GRF_PERI_AUDIO_CON (0x0070) + +struct rk_dsm_soc_data { + int (*init)(struct device *dev); + void (*deinit)(struct device *dev); +}; + +struct rk_dsm_priv { + struct regmap *grf; + struct regmap *regmap; + struct clk *clk_dac; + struct clk *pclk; + unsigned int pa_ctl_delay_ms; + struct gpio_desc *pa_ctl; + struct reset_control *rc; + const struct rk_dsm_soc_data *data; +}; + +/* DAC digital gain */ +static const DECLARE_TLV_DB_SCALE(dac_tlv, -95625, 375, 0); + +/* DAC Cutoff for High Pass Filter */ +static const char * const dac_hpf_cutoff_text[] = { + "80Hz", "100Hz", "120Hz", "140Hz", +}; + +static SOC_ENUM_SINGLE_DECL(dac_hpf_cutoff_enum, DACHPF, 4, + dac_hpf_cutoff_text); + +static const char * const pa_ctl[] = {"Off", "On"}; + +static const struct soc_enum pa_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(pa_ctl), pa_ctl); + +static int rk_dsm_dac_vol_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int val = snd_soc_component_read(component, mc->reg); + unsigned int sign = snd_soc_component_read(component, DACVOGP); + unsigned int mask = (1 << fls(mc->max)) - 1; + unsigned int shift = mc->shift; + int mid = mc->max / 2; + int uv; + + uv = (val >> shift) & mask; + if (sign) + uv = mid + uv; + else + uv = mid - uv; + + ucontrol->value.integer.value[0] = uv; + ucontrol->value.integer.value[1] = uv; + + return 0; +} + +static int rk_dsm_dac_vol_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int reg = mc->reg; + unsigned int rreg = mc->rreg; + unsigned int shift = mc->shift; + unsigned int mask = (1 << fls(mc->max)) - 1; + unsigned int val, val_mask, sign; + int uv = ucontrol->value.integer.value[0]; + int min = mc->min; + int mid = mc->max / 2; + + if (uv > mid) { + sign = DSM_DACVOGP_VOLGPL0_POS | DSM_DACVOGP_VOLGPR0_POS; + uv = uv - mid; + } else { + sign = DSM_DACVOGP_VOLGPL0_NEG | DSM_DACVOGP_VOLGPR0_NEG; + uv = mid - uv; + } + + val = ((uv + min) & mask); + val_mask = mask << shift; + val = val << shift; + + snd_soc_component_update_bits(component, reg, val_mask, val); + snd_soc_component_update_bits(component, rreg, val_mask, val); + snd_soc_component_write(component, DACVOGP, sign); + + return 0; +} + +static int rk_dsm_dac_pa_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rk_dsm_priv *rd = snd_soc_component_get_drvdata(component); + + if (!rd->pa_ctl) + return -EINVAL; + + ucontrol->value.enumerated.item[0] = gpiod_get_value(rd->pa_ctl); + + return 0; +} + +static int rk_dsm_dac_pa_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rk_dsm_priv *rd = snd_soc_component_get_drvdata(component); + + if (!rd->pa_ctl) + return -EINVAL; + + gpiod_set_value(rd->pa_ctl, ucontrol->value.enumerated.item[0]); + + return 0; +} + +static const struct snd_kcontrol_new rk_dsm_snd_controls[] = { + SOC_DOUBLE_R_EXT_TLV("DAC Digital Volume", + DACVOLL0, DACVOLR0, 0, 0x1fe, 0, + rk_dsm_dac_vol_get, + rk_dsm_dac_vol_put, + dac_tlv), + + SOC_ENUM("DAC HPF Cutoff", dac_hpf_cutoff_enum), + SOC_SINGLE("DAC HPF Switch", DACHPF, 0, 1, 0), + SOC_ENUM_EXT("Power Amplifier", pa_enum, + rk_dsm_dac_pa_get, + rk_dsm_dac_pa_put), +}; + +/* + * ACDC_CLK D2A_CLK D2A_SYNC Sample rates supported + * 49.152MHz 49.152MHz 6.144MHz 12/24/48/96/192kHz + * 45.154MHz 45.154MHz 5.644MHz 11.025/22.05/44.1/88.2/176.4kHz + * 32.768MHz 32.768MHz 4.096MHz 8/16/32/64/128kHz + */ +static void rk_dsm_get_clk(unsigned int samplerate, + unsigned int *mclk, + unsigned int *sclk) +{ + switch (samplerate) { + case 12000: + case 24000: + case 48000: + case 96000: + case 192000: + *mclk = 49152000; + *sclk = 6144000; + break; + case 11025: + case 22050: + case 44100: + case 88200: + case 176400: + *mclk = 45158400; + *sclk = 5644800; + break; + case 8000: + case 16000: + case 32000: + case 64000: + case 128000: + *mclk = 32768000; + *sclk = 4096000; + break; + default: + *mclk = 0; + *sclk = 0; + break; + } +} + +static void rk_dsm_enable_clk_dac(struct rk_dsm_priv *rd) +{ + regmap_update_bits(rd->regmap, DACCLKCTRL, + DSM_DACCLKCTRL_DAC_CKE_MASK | + DSM_DACCLKCTRL_I2SRX_CKE_MASK | + DSM_DACCLKCTRL_CKE_BCLKRX_MASK | + DSM_DACCLKCTRL_DAC_SYNC_ENA_MASK | + DSM_DACCLKCTRL_DAC_MODE_ATTENU_MASK, + DSM_DACCLKCTRL_DAC_CKE_EN | + DSM_DACCLKCTRL_I2SRX_CKE_EN | + DSM_DACCLKCTRL_CKE_BCLKRX_EN | + DSM_DACCLKCTRL_DAC_SYNC_ENA_EN | + DSM_DACCLKCTRL_DAC_MODE_ATTENU_EN); +} + +static int rk_dsm_set_clk(struct rk_dsm_priv *rd, + struct snd_pcm_substream *substream, + unsigned int samplerate) +{ + unsigned int mclk, sclk, bclk; + unsigned int div_bclk; + + rk_dsm_get_clk(samplerate, &mclk, &sclk); + if (!mclk || !sclk) + return -EINVAL; + + bclk = 64 * samplerate; + div_bclk = DIV_ROUND_CLOSEST(mclk, bclk); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + clk_set_rate(rd->clk_dac, mclk); + + rk_dsm_enable_clk_dac(rd); + + regmap_update_bits(rd->regmap, DACSCLKRXINT_DIV, + DSM_DACSCLKRXINT_DIV_SCKRXDIV_MASK, + DSM_DACSCLKRXINT_DIV_SCKRXDIV(div_bclk)); + regmap_update_bits(rd->regmap, I2S_CKR0, + DSM_I2S_CKR0_RSD_MASK, + DSM_I2S_CKR0_RSD(64)); + } + + return 0; +} + +static int rk_dsm_set_dai_fmt(struct snd_soc_dai *dai, + unsigned int fmt) +{ + struct rk_dsm_priv *rd = + snd_soc_component_get_drvdata(dai->component); + unsigned int mask = 0, val = 0; + + /* master mode only */ + regmap_update_bits(rd->regmap, I2S_CKR1, + DSM_I2S_CKR1_MSS_MASK, + DSM_I2S_CKR1_MSS_MASTER); + + mask = DSM_I2S_CKR1_CKP_MASK | + DSM_I2S_CKR1_RLP_MASK | + DSM_I2S_CKR1_TLP_MASK; + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + val = DSM_I2S_CKR1_CKP_NORMAL | + DSM_I2S_CKR1_RLP_NORMAL | + DSM_I2S_CKR1_TLP_NORMAL; + break; + case SND_SOC_DAIFMT_IB_IF: + val = DSM_I2S_CKR1_CKP_INVERTED | + DSM_I2S_CKR1_RLP_INVERTED | + DSM_I2S_CKR1_TLP_INVERTED; + break; + case SND_SOC_DAIFMT_IB_NF: + val = DSM_I2S_CKR1_CKP_INVERTED | + DSM_I2S_CKR1_RLP_NORMAL | + DSM_I2S_CKR1_TLP_NORMAL; + break; + case SND_SOC_DAIFMT_NB_IF: + val = DSM_I2S_CKR1_CKP_NORMAL | + DSM_I2S_CKR1_RLP_INVERTED | + DSM_I2S_CKR1_TLP_INVERTED; + break; + default: + return -EINVAL; + } + + regmap_update_bits(rd->regmap, I2S_CKR1, mask, val); + + return 0; +} + +static int rk_dsm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct rk_dsm_priv *rd = + snd_soc_component_get_drvdata(dai->component); + unsigned int srt = 0, val = 0; + + rk_dsm_set_clk(rd, substream, params_rate(params)); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + switch (params_rate(params)) { + case 8000: + case 11025: + case 12000: + srt = 0; + break; + case 16000: + case 22050: + case 24000: + srt = 1; + break; + case 32000: + case 44100: + case 48000: + srt = 2; + break; + case 64000: + case 88200: + case 96000: + srt = 3; + break; + case 128000: + case 176400: + case 192000: + srt = 4; + break; + default: + return -EINVAL; + } + + regmap_update_bits(rd->regmap, DACCFG1, + DSM_DACCFG1_DACSRT_MASK, + DSM_DACCFG1_DACSRT(srt)); + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + val = 16; + break; + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S32_LE: + val = 24; + break; + default: + return -EINVAL; + } + + regmap_update_bits(rd->regmap, I2S_RXCR0, + DSM_I2S_RXCR0_VDW_MASK, + DSM_I2S_RXCR0_VDW(val)); + regmap_update_bits(rd->regmap, DACPWM_CTRL, + DSM_DACPWM_CTRL_PWM_MODE_CKE_MASK | + DSM_DACPWM_CTRL_PWM_EN_MASK, + DSM_DACPWM_CTRL_PWM_MODE_CKE_EN | + DSM_DACPWM_CTRL_PWM_EN); + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + regmap_update_bits(rd->regmap, I2S_XFER, + DSM_I2S_XFER_RXS_MASK, + DSM_I2S_XFER_RXS_START); + regmap_update_bits(rd->regmap, DACDIGEN, + DSM_DACDIGEN_DAC_GLBEN_MASK | + DSM_DACDIGEN_DACEN_L0R1_MASK, + DSM_DACDIGEN_DAC_GLBEN_EN | + DSM_DACDIGEN_DACEN_L0R1_EN); + } + + return 0; +} + +static int rk_dsm_pcm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct rk_dsm_priv *rd = + snd_soc_component_get_drvdata(dai->component); + + gpiod_set_value(rd->pa_ctl, 1); + if (rd->pa_ctl_delay_ms) + msleep(rd->pa_ctl_delay_ms); + + return 0; +} + +static void rk_dsm_pcm_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct rk_dsm_priv *rd = + snd_soc_component_get_drvdata(dai->component); + + gpiod_set_value(rd->pa_ctl, 0); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + regmap_update_bits(rd->regmap, DACPWM_CTRL, + DSM_DACPWM_CTRL_PWM_MODE_CKE_MASK | + DSM_DACPWM_CTRL_PWM_EN_MASK, + DSM_DACPWM_CTRL_PWM_MODE_CKE_DIS | + DSM_DACPWM_CTRL_PWM_DIS); + regmap_update_bits(rd->regmap, I2S_XFER, + DSM_I2S_XFER_RXS_MASK, + DSM_I2S_XFER_RXS_STOP); + regmap_update_bits(rd->regmap, I2S_CLR, + DSM_I2S_CLR_RXC_MASK, + DSM_I2S_CLR_RXC_CLR); + regmap_update_bits(rd->regmap, DACDIGEN, + DSM_DACDIGEN_DAC_GLBEN_MASK | + DSM_DACDIGEN_DACEN_L0R1_MASK, + DSM_DACDIGEN_DAC_GLBEN_DIS | + DSM_DACDIGEN_DACEN_L0R1_DIS); + } +} + +static const struct snd_soc_dai_ops rd_dai_ops = { + .hw_params = rk_dsm_hw_params, + .set_fmt = rk_dsm_set_dai_fmt, + .startup = rk_dsm_pcm_startup, + .shutdown = rk_dsm_pcm_shutdown, +}; + +static struct snd_soc_dai_driver rd_dai[] = { + { + .name = "rk_dsm", + .id = 0, + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = (SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE), + }, + .ops = &rd_dai_ops, + }, +}; + +static const struct snd_soc_component_driver soc_codec_dev_rd = { + .controls = rk_dsm_snd_controls, + .num_controls = ARRAY_SIZE(rk_dsm_snd_controls), +}; + +static const struct regmap_config rd_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = VERSION, + .cache_type = REGCACHE_FLAT, +}; + +static int rk3562_soc_init(struct device *dev) +{ + struct rk_dsm_priv *rd = dev_get_drvdata(dev); + + if (IS_ERR(rd->grf)) + return PTR_ERR(rd->grf); + + /* enable internal codec to i2s1 */ + return regmap_write(rd->grf, RK3562_GRF_PERI_AUDIO_CON, + (BIT(14) << 16 | BIT(14) | 0x0a100a10)); +} + +static void rk3562_soc_deinit(struct device *dev) +{ + struct rk_dsm_priv *rd = dev_get_drvdata(dev); + + if (IS_ERR(rd->grf)) + return; + + regmap_write(rd->grf, RK3562_GRF_PERI_AUDIO_CON, (BIT(14) << 16) | 0x0a100a10); +} + +static const struct rk_dsm_soc_data rk3562_data = { + .init = rk3562_soc_init, + .deinit = rk3562_soc_deinit, +}; + +#ifdef CONFIG_OF +static const struct of_device_id rd_of_match[] = { + { .compatible = "rockchip,rk3562-dsm", .data = &rk3562_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, rd_of_match); +#endif + +#ifdef CONFIG_PM +static int rk_dsm_runtime_resume(struct device *dev) +{ + struct rk_dsm_priv *rd = dev_get_drvdata(dev); + int ret = 0; + + ret = clk_prepare_enable(rd->pclk); + if (ret) + return ret; + + regcache_cache_only(rd->regmap, false); + regcache_mark_dirty(rd->regmap); + + ret = clk_prepare_enable(rd->clk_dac); + if (ret) + goto err; + + return 0; +err: + clk_disable_unprepare(rd->pclk); + + return ret; +} + +static int rk_dsm_runtime_suspend(struct device *dev) +{ + struct rk_dsm_priv *rd = dev_get_drvdata(dev); + + regcache_cache_only(rd->regmap, true); + clk_disable_unprepare(rd->clk_dac); + clk_disable_unprepare(rd->pclk); + + return 0; +} +#endif + +static int rk_dsm_platform_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct rk_dsm_priv *rd; + void __iomem *base; + int ret = 0; + + rd = devm_kzalloc(&pdev->dev, sizeof(*rd), GFP_KERNEL); + if (!rd) + return -ENOMEM; + + rd->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); + if (IS_ERR(rd->grf)) + return PTR_ERR(rd->grf); + + if (device_property_read_u32(&pdev->dev, "rockchip,pa-ctl-delay-ms", + &rd->pa_ctl_delay_ms)) + rd->pa_ctl_delay_ms = 0; + + rd->rc = devm_reset_control_get(&pdev->dev, "reset"); + + rd->clk_dac = devm_clk_get(&pdev->dev, "dac"); + if (IS_ERR(rd->clk_dac)) + return PTR_ERR(rd->clk_dac); + + rd->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(rd->pclk)) + return PTR_ERR(rd->pclk); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + rd->regmap = + devm_regmap_init_mmio(&pdev->dev, base, &rd_regmap_config); + if (IS_ERR(rd->regmap)) + return PTR_ERR(rd->regmap); + + platform_set_drvdata(pdev, rd); + + rd->data = device_get_match_data(&pdev->dev); + if (rd->data && rd->data->init) { + ret = rd->data->init(&pdev->dev); + if (ret) + return ret; + } + + pm_runtime_enable(&pdev->dev); + if (!pm_runtime_enabled(&pdev->dev)) { + ret = rk_dsm_runtime_resume(&pdev->dev); + if (ret) + goto err_pm_disable; + } + + regmap_update_bits(rd->regmap, DACPWM_CTRL, + DSM_DACPWM_CTRL_PWM_MODE_MASK, + DSM_DACPWM_CTRL_PWM_MODE_0); + + rd->pa_ctl = devm_gpiod_get_optional(&pdev->dev, "pa-ctl", + GPIOD_OUT_LOW); + + if (!rd->pa_ctl) { + dev_info(&pdev->dev, "no need pa-ctl gpio\n"); + } else if (IS_ERR(rd->pa_ctl)) { + ret = PTR_ERR(rd->pa_ctl); + dev_err(&pdev->dev, "fail to request gpio pa-ctl\n"); + goto err_suspend; + } + + ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rd, + rd_dai, ARRAY_SIZE(rd_dai)); + + if (ret) + goto err_suspend; + + return 0; + +err_suspend: + if (!pm_runtime_status_suspended(&pdev->dev)) + rk_dsm_runtime_suspend(&pdev->dev); +err_pm_disable: + pm_runtime_disable(&pdev->dev); + + if (rd->data && rd->data->deinit) + rd->data->deinit(&pdev->dev); + + return ret; +} + +static int rk_dsm_platform_remove(struct platform_device *pdev) +{ + struct rk_dsm_priv *rd = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + if (!pm_runtime_status_suspended(&pdev->dev)) + rk_dsm_runtime_suspend(&pdev->dev); + + if (rd->data && rd->data->deinit) + rd->data->deinit(&pdev->dev); + + return 0; +} + +static const struct dev_pm_ops rd_pm = { + SET_RUNTIME_PM_OPS(rk_dsm_runtime_suspend, + rk_dsm_runtime_resume, NULL) +}; + +static struct platform_driver rk_dsm_driver = { + .driver = { + .name = "rk_dsm", + .of_match_table = of_match_ptr(rd_of_match), + .pm = &rd_pm, + }, + .probe = rk_dsm_platform_probe, + .remove = rk_dsm_platform_remove, +}; +module_platform_driver(rk_dsm_driver); + +MODULE_AUTHOR("Jason Zhu "); +MODULE_DESCRIPTION("ASoC Rockchip Delta-sigma Digital Converter Driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/rk_dsm.h b/sound/soc/codecs/rk_dsm.h new file mode 100644 index 000000000000..70b8e700da9e --- /dev/null +++ b/sound/soc/codecs/rk_dsm.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Rockchip Audio Delta-sigma Digital Converter driver + * + * Copyright (C) 2023 Rockchip Electronics Co., Ltd + * + */ + +#ifndef _RK_DSM_H +#define _RK_DSM_H + +#define DACVUCTL 0x0000 +#define DACVUCTIME 0x0004 +#define DACDIGEN 0x0008 +#define DACCLKCTRL 0x000c +#define DACINT_DIV 0x0014 +#define DACSCLKRXINT_DIV 0x0020 +#define DACPWM_DIV 0x0024 +#define DACPWM_CTRL 0x0028 +#define DACCFG1 0x0044 +#define DACMUTE 0x0048 +#define DACMUTEST 0x004c +#define DACVOLL0 0x0050 +#define DACVOLL1 0x0054 +#define DACVOLL2 0x0058 +#define DACVOLL3 0x005c +#define DACVOLR0 0x0060 +#define DACVOLR1 0x0064 +#define DACVOLR2 0x0068 +#define DACVOLR3 0x006c +#define DACVOGP 0x0070 +#define DACRVOLL0 0x0074 +#define DACRVOLL1 0x0078 +#define DACRVOLL2 0x007c +#define DACRVOLL3 0x0080 +#define DACRVOLR0 0x0084 +#define DACRVOLR1 0x0088 +#define DACRVOLR2 0x008c +#define DACRVOLR3 0x0090 +#define DACLMT0 0x0094 +#define DACLMT1 0x0098 +#define DACLMT2 0x009c +#define DACMIXCTRLL 0x00a0 +#define DACMIXCTRLR 0x00a4 +#define DACHPF 0x00a8 +#define I2S_RXCR0 0x010c +#define I2S_RXCR1 0x0110 +#define I2S_CKR0 0x0114 +#define I2S_CKR1 0x0118 +#define I2S_XFER 0x011c +#define I2S_CLR 0x0120 +#define VERSION 0x0140 + +/* DACDIGEN */ +#define DSM_DACDIGEN_DACEN_L0R1_MASK BIT(0) +#define DSM_DACDIGEN_DACEN_L0R1_EN BIT(0) +#define DSM_DACDIGEN_DACEN_L0R1_DIS 0 +#define DSM_DACDIGEN_DAC_GLBEN_MASK BIT(4) +#define DSM_DACDIGEN_DAC_GLBEN_EN BIT(4) +#define DSM_DACDIGEN_DAC_GLBEN_DIS 0 +/* DACCLKCTRL */ +#define DSM_DACCLKCTRL_DAC_MODE_ATTENU_MASK BIT(0) +#define DSM_DACCLKCTRL_DAC_MODE_ATTENU_EN BIT(0) +#define DSM_DACCLKCTRL_DAC_MODE_ATTENU_DIS 0 +#define DSM_DACCLKCTRL_DAC_SYNC_STATUS_MASK BIT(1) +#define DSM_DACCLKCTRL_DAC_SYNC_STATUS_DONE 0 +#define DSM_DACCLKCTRL_DAC_SYNC_ENA_MASK BIT(2) +#define DSM_DACCLKCTRL_DAC_SYNC_ENA_EN BIT(2) +#define DSM_DACCLKCTRL_DAC_SYNC_ENA_DIS 0 +#define DSM_DACCLKCTRL_CKE_BCLKRX_MASK BIT(3) +#define DSM_DACCLKCTRL_CKE_BCLKRX_EN BIT(3) +#define DSM_DACCLKCTRL_CKE_BCLKRX_DIS 0 +#define DSM_DACCLKCTRL_I2SRX_CKE_MASK BIT(4) +#define DSM_DACCLKCTRL_I2SRX_CKE_EN BIT(4) +#define DSM_DACCLKCTRL_I2SRX_CKE_DIS 0 +#define DSM_DACCLKCTRL_DAC_CKE_MASK BIT(5) +#define DSM_DACCLKCTRL_DAC_CKE_EN BIT(5) +#define DSM_DACCLKCTRL_DAC_CKE_DIS 0 +/* DACINT_DIV */ +#define DSM_DACINT_DIV_INT_DIV_CON_MASK GENMASK(7, 0) +#define DSM_DACINT_DIV_INT_DIV_CON(x) ((x) - 1) +/* DACSCLKRXINT_DIV */ +#define DSM_DACSCLKRXINT_DIV_SCKRXDIV_MASK GENMASK(7, 0) +#define DSM_DACSCLKRXINT_DIV_SCKRXDIV(x) ((x) - 1) +/* DACPWM_DIV */ +#define DSM_DACPWM_DIV_AUDIO_PWM_DIV_MASK GENMASK(7, 0) +#define DSM_DACPWM_DIV_AUDIO_PWM_DIV(x) ((x) - 1) +/* DACPWM_CTRL */ +#define DSM_DACPWM_CTRL_DITH_SEL_MASK GENMASK(2, 0) +#define DSM_DACPWM_CTRL_DITH_SEL(x) (x) +#define DSM_DACPWM_CTRL_PWM_EN_MASK BIT(3) +#define DSM_DACPWM_CTRL_PWM_EN BIT(3) +#define DSM_DACPWM_CTRL_PWM_DIS 0 +#define DSM_DACPWM_CTRL_PWM_MODE_MASK GENMASK(5, 4) +#define DSM_DACPWM_CTRL_PWM_MODE_1 (0x2 << 4) +#define DSM_DACPWM_CTRL_PWM_MODE_0 (0x1 << 4) +#define DSM_DACPWM_CTRL_PWM_MODE_DAC (0x0 << 4) +#define DSM_DACPWM_CTRL_PWM_MODE_CKE_MASK BIT(6) +#define DSM_DACPWM_CTRL_PWM_MODE_CKE_EN BIT(6) +#define DSM_DACPWM_CTRL_PWM_MODE_CKE_DIS 0 +/* DACCFG1 */ +#define DSM_DACCFG1_DACSRT_MASK GENMASK(4, 2) +#define DSM_DACCFG1_DACSRT(x) ((x) << 2) +/* DACMUTE */ +#define DSM_DACMUTE_DACMT_MASK BIT(0) +#define DSM_DACMUTE_DACUNMT_MASK BIT(1) +/* DACVOLL0 */ +#define DSM_DACVOLL0_DACLV0_MASK GENMASK(7, 0) +#define DSM_DACVOLL0_DACLV0(x) (x) +/* DACVOLR0 */ +#define DSM_DACVOLR0_DACRV0_MASK GENMASK(7, 0) +#define DSM_DACVOLR0_DACRV0(x) (x) +/* DACVOGP */ +#define DSM_DACVOGP_VOLGPL0_MASK BIT(0) +#define DSM_DACVOGP_VOLGPL0_POS BIT(0) +#define DSM_DACVOGP_VOLGPL0_NEG 0 +#define DSM_DACVOGP_VOLGPR0_MASK BIT(1) +#define DSM_DACVOGP_VOLGPR0_POS BIT(1) +#define DSM_DACVOGP_VOLGPR0_NEG 0 +/* DACMIXCTRLL */ +#define DSM_DACMIXCTRLL_MIXMODE_L0_MASK GENMASK(1, 0) +#define DSM_DACMIXCTRLL_MIXMODE_L0_LR 2 +#define DSM_DACMIXCTRLL_MIXMODE_L0_R 1 +#define DSM_DACMIXCTRLL_MIXMODE_L0_L 0 +/* DACMIXCTRLR */ +#define DSM_DACMIXCTRLR_MIXMODE_R0_MASK GENMASK(1, 0) +#define DSM_DACMIXCTRLR_MIXMODE_R0_LR 2 +#define DSM_DACMIXCTRLR_MIXMODE_R0_L 1 +#define DSM_DACMIXCTRLR_MIXMODE_R0_R 0 +/* DACHPF */ +#define DSM_DACHPF_HPFEN_L0R0_MASK BIT(0) +#define DSM_DACHPF_HPFEN_L0R0_EN BIT(0) +#define DSM_DACHPF_HPFCF_MASK GENMASK(5, 4) +#define DSM_DACHPF_HPFCF_140HZ (0x3 << 4) +#define DSM_DACHPF_HPFCF_120HZ (0x2 << 4) +#define DSM_DACHPF_HPFCF_100HZ (0x1 << 4) +#define DSM_DACHPF_HPFCF_80HZ (0x0 << 4) +/* I2S_RXCR0 */ +#define DSM_I2S_RXCR0_VDW_MASK GENMASK(4, 0) +#define DSM_I2S_RXCR0_VDW(x) ((x) - 1) +/* I2S_RXCR1 */ +#define DSM_I2S_RXCR1_CEX_MASK BIT(4) +#define DSM_I2S_RXCR1_CEX_EXCHANGE BIT(4) +#define DSM_I2S_RXCR1_RCSR_MASK GENMASK(7, 6) +#define DSM_I2S_RXCR1_RCSR_2CH (0x0 << 6) +/* I2S_CKR0 */ +#define DSM_I2S_CKR0_TSD_MASK GENMASK(1, 0) +#define DSM_I2S_CKR0_TSD(x) ((x) << 0) +#define DSM_I2S_CKR0_RSD_MASK GENMASK(3, 2) +#define DSM_I2S_CKR0_RSD(x) ((x) << 2) +/* I2S_CKR1 */ +#define DSM_I2S_CKR1_TLP_MASK BIT(0) +#define DSM_I2S_CKR1_TLP_INVERTED BIT(0) +#define DSM_I2S_CKR1_TLP_NORMAL 0 +#define DSM_I2S_CKR1_RLP_MASK BIT(1) +#define DSM_I2S_CKR1_RLP_INVERTED BIT(1) +#define DSM_I2S_CKR1_RLP_NORMAL 0 +#define DSM_I2S_CKR1_CKP_MASK BIT(2) +#define DSM_I2S_CKR1_CKP_INVERTED BIT(2) +#define DSM_I2S_CKR1_CKP_NORMAL 0 +#define DSM_I2S_CKR1_MSS_MASK BIT(3) +#define DSM_I2S_CKR1_MSS_MASTER 0 +/* I2S_XFER */ +#define DSM_I2S_XFER_TXS_MASK BIT(0) +#define DSM_I2S_XFER_TXS_START BIT(0) +#define DSM_I2S_XFER_TXS_STOP 0 +#define DSM_I2S_XFER_RXS_MASK BIT(1) +#define DSM_I2S_XFER_RXS_START BIT(1) +#define DSM_I2S_XFER_RXS_STOP 0 +/* I2S_CLR */ +#define DSM_I2S_CLR_TXC_MASK BIT(0) +#define DSM_I2S_CLR_TXC_CLR BIT(0) +#define DSM_I2S_CLR_RXC_MASK BIT(1) +#define DSM_I2S_CLR_RXC_CLR BIT(1) + +#endif From 52dfec02ca99056b49ea8190384add4273bc7032 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Thu, 2 Feb 2023 15:19:58 +0800 Subject: [PATCH 085/258] arm64: configs: rockchip_defconfig: enable CONFIG_SND_SOC_RK_DSM Signed-off-by: Jason Zhu Change-Id: I6e69cd59e64af922ee8608fbbd9454fcf3960e0a --- arch/arm64/configs/rockchip_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index c518d4a58a95..00157fd9c756 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -707,6 +707,7 @@ CONFIG_SND_SOC_RK3328=y CONFIG_SND_SOC_RK3528=y CONFIG_SND_SOC_RK817=y CONFIG_SND_SOC_RK_CODEC_DIGITAL=y +CONFIG_SND_SOC_RK_DSM=y CONFIG_SND_SOC_RT5640=y CONFIG_SND_SOC_SPDIF=y CONFIG_SND_SOC_AW883XX=y From a8617a287084a11266aff4cf9786728f360efda7 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Thu, 2 Feb 2023 15:22:20 +0800 Subject: [PATCH 086/258] arm64: rockchip_linux_defconfig: enable CONFIG_SND_SOC_RK_DSM Signed-off-by: Jason Zhu Change-Id: Id95110bd1b6a95c89f82432e352fd538303b0896 --- arch/arm64/configs/rockchip_linux_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig index 188f351b7155..b0e9a4098d6e 100644 --- a/arch/arm64/configs/rockchip_linux_defconfig +++ b/arch/arm64/configs/rockchip_linux_defconfig @@ -407,6 +407,7 @@ CONFIG_SND_SOC_RK3328=y CONFIG_SND_SOC_RK3528=y CONFIG_SND_SOC_RK817=y CONFIG_SND_SOC_RK_CODEC_DIGITAL=y +CONFIG_SND_SOC_RK_DSM=y CONFIG_SND_SOC_RT5616=y CONFIG_SND_SOC_RT5640=y CONFIG_SND_SOC_RT5651=y From 1d55fcb01ff1c16b48d9cf18c7e72e6ef9f8629e Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Thu, 2 Feb 2023 15:21:34 +0800 Subject: [PATCH 087/258] arm64: configs: rockchip_gki: enable CONFIG_SND_SOC_RK_DSM Signed-off-by: Jason Zhu Change-Id: I586e7cd2c142b0b6245039a5177676b765afa1ca --- arch/arm64/configs/rockchip_gki.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rockchip_gki.config b/arch/arm64/configs/rockchip_gki.config index 5381930f94e4..a8634841707b 100644 --- a/arch/arm64/configs/rockchip_gki.config +++ b/arch/arm64/configs/rockchip_gki.config @@ -275,6 +275,7 @@ CONFIG_SND_SOC_ES8396=m CONFIG_SND_SOC_RK3328=m CONFIG_SND_SOC_RK817=m CONFIG_SND_SOC_RK_CODEC_DIGITAL=m +CONFIG_SND_SOC_RK_DSM=m CONFIG_SND_SOC_ROCKCHIP=m CONFIG_SND_SOC_ROCKCHIP_HDMI=m CONFIG_SND_SOC_ROCKCHIP_I2S=m From 22c0fc4c7d65e56ac2ff17fbcc30523ecd5be886 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Tue, 31 Jan 2023 10:30:30 +0800 Subject: [PATCH 088/258] arm64: dts: rockchip: rk3562: change the dsm info Change the IP name according to the TRM. Delete unused info and correct the grf base address. Signed-off-by: Jason Zhu Change-Id: Ic562db95e504372ace137eaebb679697230a0a6c --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 3b85a6181f5c..3a2e53c46859 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -1958,15 +1958,14 @@ status = "disabled"; }; - acdcdig_dsm: codec-digital@ff850000 { - compatible = "rockchip,rk3562-codec-digital", "rockchip,codec-digital-v1"; + dsm: dsm@ff850000 { + compatible = "rockchip,rk3562-dsm"; reg = <0x0 0xff850000 0x0 0x1000>; clocks = <&cru CLK_DSM>, <&cru HCLK_DSM>; clock-names = "dac", "pclk"; resets = <&cru SRST_DSM>; reset-names = "reset" ; - rockchip,grf = <&sys_grf>; - rockchip,pwm-output-mode; + rockchip,grf = <&peri_grf>; pinctrl-names = "default"; pinctrl-0 = <&dsm_pins>; #sound-dai-cells = <0>; From 12609f92269c8947752360e2df04b31cea5544a7 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Tue, 31 Jan 2023 10:51:42 +0800 Subject: [PATCH 089/258] arm64: dts: rockchip: rk3562-iotest: support rk dsm sound Signed-off-by: Jason Zhu Change-Id: I25ad0e77f03a69ae19e085a20d5cb5ccdee78af4 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3562-iotest-lp3-v10-dsm.dts | 23 +++++++++++++++++++ .../dts/rockchip/rk3562-iotest-lp3-v10.dts | 16 +++++++++++++ 3 files changed, 40 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10-dsm.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 99c82c781a10..42ea1ce9871d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-pdm-mic-array.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10-dsm.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-rk817-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test2-ddr4-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10-dsm.dts b/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10-dsm.dts new file mode 100644 index 000000000000..403924de3674 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10-dsm.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + + #include "rk3562-iotest-lp3-v10.dts" + +&dsm { + status = "okay"; +}; + +&dsm_sound { + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sdmmc0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts index 528741967486..48f3ad7eefe8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts @@ -41,6 +41,22 @@ regulator-max-microvolt = <3300000>; vin-supply = <&dc_12v>; }; + + dsm_sound: dsm-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,dsm-sound"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + sndcodec: simple-audio-card,codec { + sound-dai = <&dsm>; + }; + }; }; #include "rk3562-rk809.dtsi" From b21ba4394dc19be1ca1969c0b89cce1ecda2bdb7 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Tue, 7 Feb 2023 02:34:38 +0000 Subject: [PATCH 090/258] arm64: dts: rockchip: rk3562: move display route to innermost dtsi Change-Id: I34471e644d6a2e070cc031e7699489c6fc8632d4 Signed-off-by: Guochun Huang --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 3a2e53c46859..7a0c8d93adc2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -289,6 +289,37 @@ compatible = "rockchip,display-subsystem"; ports = <&vop_out>; status = "disabled"; + + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_dsi>; + }; + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_lvds>; + }; + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_rgb>; + }; + }; }; firmware { @@ -318,6 +349,34 @@ method = "smc"; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; + rkcif_mipi_lvds: rkcif-mipi-lvds { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; From 411e86fa317607555369c0f28531896f4792034d Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 8 Feb 2023 15:35:54 +0800 Subject: [PATCH 091/258] arm64: dts: rockchip: rk3562-android/linux: move display route to innermost dtsi Signed-off-by: Guochun Huang Change-Id: Ibb68db2daab5ded86019a607efde554250d0559b --- .../boot/dts/rockchip/rk3562-android.dtsi | 61 ------------------- .../arm64/boot/dts/rockchip/rk3562-linux.dtsi | 61 ------------------- 2 files changed, 122 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-android.dtsi index cf0728c8fbb7..6ec686977bc7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-android.dtsi @@ -28,67 +28,6 @@ method = "smc"; }; }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - drm_logo: drm-logo@00000000 { - compatible = "rockchip,drm-logo"; - reg = <0x0 0x0 0x0 0x0>; - }; - - drm_cubic_lut: drm-cubic-lut@00000000 { - compatible = "rockchip,drm-cubic-lut"; - reg = <0x0 0x0 0x0 0x0>; - }; - - ramoops: ramoops@110000 { - compatible = "ramoops"; - /* 0x110000 to 0x1f0000 is for ramoops */ - reg = <0x0 0x110000 0x0 0xe0000>; - boot-log-size = <0x8000>; /* do not change */ - boot-log-count = <0x1>; /* do not change */ - console-size = <0x80000>; - pmsg-size = <0x30000>; - ftrace-size = <0x00000>; - record-size = <0x14000>; - }; - }; -}; - -&display_subsystem { - memory-region = <&drm_logo>, <&drm_cubic_lut>; - memory-region-names = "drm-logo", "drm-cubic-lut"; - /* devfreq = <&dmc>; */ - - route { - route_dsi: route-dsi { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp0_out_dsi>; - }; - route_lvds: route-lvds { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp0_out_lvds>; - }; - route_rgb: route-rgb { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp1_out_rgb>; - }; - }; }; &vop { diff --git a/arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi index a8ead0c9270c..a39728c1719d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi @@ -21,67 +21,6 @@ pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - drm_logo: drm-logo@00000000 { - compatible = "rockchip,drm-logo"; - reg = <0x0 0x0 0x0 0x0>; - }; - - drm_cubic_lut: drm-cubic-lut@00000000 { - compatible = "rockchip,drm-cubic-lut"; - reg = <0x0 0x0 0x0 0x0>; - }; - - ramoops: ramoops@110000 { - compatible = "ramoops"; - /* 0x110000 to 0x1f0000 is for ramoops */ - reg = <0x0 0x110000 0x0 0xe0000>; - boot-log-size = <0x8000>; /* do not change */ - boot-log-count = <0x1>; /* do not change */ - console-size = <0x80000>; - pmsg-size = <0x30000>; - ftrace-size = <0x00000>; - record-size = <0x14000>; - }; - }; -}; - -&display_subsystem { - memory-region = <&drm_logo>, <&drm_cubic_lut>; - memory-region-names = "drm-logo", "drm-cubic-lut"; - /* devfreq = <&dmc>; */ - - route { - route_dsi: route-dsi { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp0_out_dsi>; - }; - route_lvds: route-lvds { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp0_out_lvds>; - }; - route_rgb: route-rgb { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp1_out_rgb>; - }; - }; }; &rng { From 81dbadea25d0c5d9b0b9b0ccbb86956e2dc6a96c Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Tue, 7 Feb 2023 02:39:25 +0000 Subject: [PATCH 092/258] arm64: dts: rockchip: rk3562-evb: enable dsi display logo Change-Id: I52d558e9f3d2a857acd461f67bc11152acd0f27e Signed-off-by: Guochun Huang --- arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi index b2eb35ad17c8..c910ed867442 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi @@ -305,6 +305,10 @@ status = "okay"; }; +&route_dsi { + status = "okay"; +}; + &vcc3v3_lcd_n { gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; enable-active-high; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi index bb29df29d92d..8ed465c2b6fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi @@ -313,6 +313,10 @@ status = "okay"; }; +&route_dsi { + status = "okay"; +}; + &sai0 { status = "okay"; pinctrl-names = "default"; From b6de31a0225481b3eb3a8d0b232e5d46c8de83f6 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 8 Feb 2023 03:00:53 +0000 Subject: [PATCH 093/258] phy/rockchip: inno-dsidphy: add support px30s Change-Id: I275d589f56e5963649aee9397eba3a9994e5901d Signed-off-by: Guochun Huang --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 133 +++++++++++++----- 1 file changed, 100 insertions(+), 33 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 22ed6e0c87ea..04007a04f61c 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -19,6 +19,7 @@ #include #include #include +#include #define PSEC_PER_SEC 1000000000000LL @@ -196,6 +197,16 @@ #define DSI_PHY_STATUS 0xb0 #define PHY_LOCK BIT(0) +enum soc_type { + PX30, + PX30S, + RK3128, + RK3368, + RK3562, + RK3568, + RV1126, +}; + enum phy_max_rate { MAX_1GHZ, MAX_2_5GHZ, @@ -232,6 +243,7 @@ struct inno_dsidphy { }; struct inno_dsidphy_plat_data { + enum soc_type soc_type; const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; const unsigned int num_timings; enum phy_max_rate max_rate; @@ -601,6 +613,11 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, MODE_ENABLE_MASK, MIPI_MODE_ENABLE); + /* set pin_txclkesc_0 pin_txbyteclk invert disable */ + if (inno->pdata->soc_type == PX30S) + phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01, + INVERT_TXCLKESC_MASK, INVERT_TXCLKESC_DISABLE); + if (inno->pdata->max_rate == MAX_2_5GHZ) inno_mipi_dphy_max_2_5GHz_pll_enable(inno); else @@ -623,6 +640,15 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) SAMPLE_CLOCK_DIRECTION_REVERSE | PLL_OUTPUT_FREQUENCY_DIV_BY_1); + /* Reset LVDS digital logic */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, + LVDS_DIGITAL_INTERNAL_RESET_MASK, + LVDS_DIGITAL_INTERNAL_RESET_ENABLE); + udelay(1); + phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, + LVDS_DIGITAL_INTERNAL_RESET_MASK, + LVDS_DIGITAL_INTERNAL_RESET_DISABLE); + /* Select LVDS mode */ phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, MODE_ENABLE_MASK, LVDS_MODE_ENABLE); @@ -645,14 +671,6 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e, PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE); - /* Reset LVDS digital logic */ - phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, - LVDS_DIGITAL_INTERNAL_RESET_MASK, - LVDS_DIGITAL_INTERNAL_RESET_ENABLE); - udelay(1); - phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, - LVDS_DIGITAL_INTERNAL_RESET_MASK, - LVDS_DIGITAL_INTERNAL_RESET_DISABLE); /* Enable LVDS digital logic */ phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, LVDS_DIGITAL_INTERNAL_ENABLE_MASK, @@ -666,9 +684,6 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) static void inno_dsidphy_phy_ttl_mode_enable(struct inno_dsidphy *inno) { - /* Select TTL mode */ - phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, - MODE_ENABLE_MASK, TTL_MODE_ENABLE); /* Reset digital logic */ phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, LVDS_DIGITAL_INTERNAL_RESET_MASK, @@ -677,6 +692,11 @@ static void inno_dsidphy_phy_ttl_mode_enable(struct inno_dsidphy *inno) phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, LVDS_DIGITAL_INTERNAL_RESET_MASK, LVDS_DIGITAL_INTERNAL_RESET_DISABLE); + + /* Select TTL mode */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, + MODE_ENABLE_MASK, TTL_MODE_ENABLE); + /* Enable digital logic */ phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, LVDS_DIGITAL_INTERNAL_ENABLE_MASK, @@ -810,6 +830,55 @@ static const struct phy_ops inno_dsidphy_ops = { .owner = THIS_MODULE, }; +static const struct inno_dsidphy_plat_data px30_video_phy_plat_data = { + .soc_type = PX30, + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz), + .max_rate = MAX_1GHZ, +}; + +static const struct inno_dsidphy_plat_data px30s_video_phy_plat_data = { + .soc_type = PX30S, + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz), + .max_rate = MAX_2_5GHZ, +}; + +static const struct inno_dsidphy_plat_data rk3128_video_phy_plat_data = { + .soc_type = RK3128, + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz), + .max_rate = MAX_1GHZ, +}; + +static const struct inno_dsidphy_plat_data rk3368_video_phy_plat_data = { + .soc_type = RK3368, + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz), + .max_rate = MAX_1GHZ, +}; + +static const struct inno_dsidphy_plat_data rk3562_video_phy_plat_data = { + .soc_type = RK3562, + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz), + .max_rate = MAX_2_5GHZ, +}; + +static const struct inno_dsidphy_plat_data rk3568_video_phy_plat_data = { + .soc_type = RK3568, + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz), + .max_rate = MAX_2_5GHZ, +}; + +static const struct inno_dsidphy_plat_data rv1126_video_phy_plat_data = { + .soc_type = RV1126, + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz), + .max_rate = MAX_2_5GHZ, +}; + static int inno_dsidphy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -825,6 +894,9 @@ static int inno_dsidphy_probe(struct platform_device *pdev) inno->dev = dev; inno->pdata = of_device_get_match_data(inno->dev); + if (soc_is_px30s()) + inno->pdata = &px30s_video_phy_plat_data; + platform_set_drvdata(pdev, inno); inno->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy"); @@ -893,18 +965,6 @@ static int inno_dsidphy_probe(struct platform_device *pdev) return 0; } -static const struct inno_dsidphy_plat_data px30_plat_data = { - .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz, - .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz), - .max_rate = MAX_1GHZ, -}; - -static const struct inno_dsidphy_plat_data rk3568_plat_data = { - .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz, - .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz), - .max_rate = MAX_2_5GHZ, -}; - static int inno_dsidphy_remove(struct platform_device *pdev) { struct inno_dsidphy *inno = platform_get_drvdata(pdev); @@ -915,20 +975,27 @@ static int inno_dsidphy_remove(struct platform_device *pdev) } static const struct of_device_id inno_dsidphy_of_match[] = { - { .compatible = "rockchip,px30-dsi-dphy", - .data = &px30_plat_data, + { + .compatible = "rockchip,px30-dsi-dphy", + .data = &px30_video_phy_plat_data, }, { - .compatible = "rockchip,rk3128-dsi-dphy", - .data = &px30_plat_data, + .compatible = "rockchip,px30s-dsi-dphy", + .data = &px30s_video_phy_plat_data, }, { - .compatible = "rockchip,rk3368-dsi-dphy", - .data = &px30_plat_data, + .compatible = "rockchip,rk3128-dsi-dphy", + .data = &rk3128_video_phy_plat_data, }, { - .compatible = "rockchip,rk3568-dsi-dphy", - .data = &rk3568_plat_data, + .compatible = "rockchip,rk3368-dsi-dphy", + .data = &rk3368_video_phy_plat_data, }, { - .compatible = "rockchip,rv1126-mipi-dphy", - .data = &rk3568_plat_data, + .compatible = "rockchip,rk3562-dsi-dphy", + .data = &rk3562_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3568-dsi-dphy", + .data = &rk3568_video_phy_plat_data, + }, { + .compatible = "rockchip,rv1126-mipi-dphy", + .data = &rv1126_video_phy_plat_data, }, {} }; From c1770bf251bbcae99d2095ddac2f7fcf6a8f94f5 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 8 Feb 2023 15:20:29 +0800 Subject: [PATCH 094/258] ASoC: rockchip: sai: Handle HCLK with runtime PM This patch handle HCLK with runtime PM to save a little bit of power consumption. Signed-off-by: Sugar Zhang Change-Id: I4ab16fd21d592245a0d0eb2240740f0a90403f0a --- sound/soc/rockchip/rockchip_sai.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/sound/soc/rockchip/rockchip_sai.c b/sound/soc/rockchip/rockchip_sai.c index a77686dce4e0..7906919bba39 100644 --- a/sound/soc/rockchip/rockchip_sai.c +++ b/sound/soc/rockchip/rockchip_sai.c @@ -72,6 +72,7 @@ static int sai_runtime_suspend(struct device *dev) regcache_cache_only(sai->regmap, true); clk_disable_unprepare(sai->mclk); + clk_disable_unprepare(sai->hclk); return 0; } @@ -81,6 +82,10 @@ static int sai_runtime_resume(struct device *dev) struct rk_sai_dev *sai = dev_get_drvdata(dev); int ret; + ret = clk_prepare_enable(sai->hclk); + if (ret) + goto err_hclk; + ret = clk_prepare_enable(sai->mclk); if (ret) goto err_mclk; @@ -103,6 +108,8 @@ static int sai_runtime_resume(struct device *dev) err_regmap: clk_disable_unprepare(sai->mclk); err_mclk: + clk_disable_unprepare(sai->hclk); +err_hclk: return ret; } @@ -1110,10 +1117,6 @@ static int rockchip_sai_probe(struct platform_device *pdev) return PTR_ERR(sai->hclk); } - ret = clk_prepare_enable(sai->hclk); - if (ret) - return ret; - pm_runtime_enable(&pdev->dev); if (!pm_runtime_enabled(&pdev->dev)) { ret = sai_runtime_resume(&pdev->dev); @@ -1142,21 +1145,16 @@ err_runtime_suspend: sai_runtime_suspend(&pdev->dev); err_runtime_disable: pm_runtime_disable(&pdev->dev); - clk_disable_unprepare(sai->hclk); return ret; } static int rockchip_sai_remove(struct platform_device *pdev) { - struct rk_sai_dev *sai = dev_get_drvdata(&pdev->dev); - pm_runtime_disable(&pdev->dev); if (!pm_runtime_status_suspended(&pdev->dev)) sai_runtime_suspend(&pdev->dev); - clk_disable_unprepare(sai->hclk); - return 0; } From 5e0fa7cfeff255eb4fe4512055d0a091845cb887 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 8 Feb 2023 17:24:25 +0800 Subject: [PATCH 095/258] pinctrl/rockchip: Sync with upstream Signed-off-by: Tao Huang Change-Id: I752b6433b1682930eb0e080759334a5a876a5d23 --- drivers/pinctrl/pinctrl-rockchip.c | 188 ++++++++++++++--------------- drivers/pinctrl/pinctrl-rockchip.h | 3 +- 2 files changed, 95 insertions(+), 96 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index a6756048aadd..1d993f9ac98b 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2673,108 +2673,108 @@ static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } -#define RK3588_PMU1_IOC_REG 0x0000 -#define RK3588_PMU2_IOC_REG 0x4000 -#define RK3588_BUS_IOC_REG 0x8000 -#define RK3588_VCCIO1_4_IOC_REG 0x9000 -#define RK3588_VCCIO3_5_IOC_REG 0xA000 -#define RK3588_VCCIO2_IOC_REG 0xB000 -#define RK3588_VCCIO6_IOC_REG 0xC000 -#define RK3588_EMMC_IOC_REG 0xD000 +#define RK3588_PMU1_IOC_REG (0x0000) +#define RK3588_PMU2_IOC_REG (0x4000) +#define RK3588_BUS_IOC_REG (0x8000) +#define RK3588_VCCIO1_4_IOC_REG (0x9000) +#define RK3588_VCCIO3_5_IOC_REG (0xA000) +#define RK3588_VCCIO2_IOC_REG (0xB000) +#define RK3588_VCCIO6_IOC_REG (0xC000) +#define RK3588_EMMC_IOC_REG (0xD000) static const u32 rk3588_ds_regs[][2] = { - { RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010 }, - { RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014 }, - { RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018 }, - { RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014 }, - { RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018 }, - { RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C }, - { RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020 }, - { RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024 }, - { RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020 }, - { RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024 }, - { RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028 }, - { RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C }, - { RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030 }, - { RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034 }, - { RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038 }, - { RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C }, - { RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040 }, - { RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044 }, - { RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048 }, - { RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C }, - { RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050 }, - { RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054 }, - { RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058 }, - { RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C }, - { RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060 }, - { RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064 }, - { RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068 }, - { RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C }, - { RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070 }, - { RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074 }, - { RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078 }, - { RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C }, - { RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080 }, - { RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084 }, - { RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088 }, - { RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C }, - { RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090 }, - { RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090 }, - { RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094 }, - { RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098 }, + {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010}, + {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014}, + {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018}, + {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014}, + {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018}, + {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C}, + {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020}, + {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024}, + {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020}, + {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024}, + {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028}, + {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C}, + {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030}, + {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034}, + {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038}, + {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C}, + {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040}, + {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044}, + {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048}, + {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C}, + {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050}, + {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054}, + {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058}, + {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C}, + {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060}, + {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064}, + {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068}, + {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C}, + {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070}, + {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074}, + {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078}, + {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C}, + {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080}, + {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084}, + {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088}, + {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C}, + {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090}, + {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090}, + {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094}, + {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098}, }; static const u32 rk3588_p_regs[][2] = { - { RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020 }, - { RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024 }, - { RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028 }, - { RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C }, - { RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030 }, - { RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110 }, - { RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114 }, - { RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118 }, - { RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C }, - { RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120 }, - { RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120 }, - { RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124 }, - { RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128 }, - { RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C }, - { RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130 }, - { RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134 }, - { RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138 }, - { RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C }, - { RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140 }, - { RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144 }, - { RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148 }, - { RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148 }, - { RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C }, + {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020}, + {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024}, + {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028}, + {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C}, + {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030}, + {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110}, + {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114}, + {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118}, + {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C}, + {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120}, + {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0120}, + {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124}, + {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128}, + {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C}, + {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130}, + {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134}, + {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138}, + {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C}, + {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140}, + {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144}, + {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148}, + {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148}, + {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C}, }; static const u32 rk3588_smt_regs[][2] = { - { RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030 }, - { RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034 }, - { RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040 }, - { RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044 }, - { RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048 }, - { RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210 }, - { RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214 }, - { RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218 }, - { RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C }, - { RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220 }, - { RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220 }, - { RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224 }, - { RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228 }, - { RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C }, - { RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230 }, - { RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234 }, - { RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238 }, - { RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C }, - { RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240 }, - { RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244 }, - { RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248 }, - { RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248 }, - { RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C }, + {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030}, + {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034}, + {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040}, + {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044}, + {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048}, + {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210}, + {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214}, + {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218}, + {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C}, + {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220}, + {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0220}, + {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224}, + {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228}, + {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C}, + {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230}, + {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234}, + {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238}, + {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C}, + {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240}, + {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244}, + {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248}, + {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248}, + {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C}, }; #define RK3588_PULL_BITS_PER_PIN 2 diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 0566b8b7c8ef..80b5552fd8d0 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -18,8 +18,6 @@ #ifndef _PINCTRL_ROCKCHIP_H #define _PINCTRL_ROCKCHIP_H -#include - #define RK_GPIO0_A0 0 #define RK_GPIO0_A1 1 #define RK_GPIO0_A2 2 @@ -403,6 +401,7 @@ struct rockchip_pin_ctrl { u32 niomux_recalced; struct rockchip_mux_route_data *iomux_routes; u32 niomux_routes; + int (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); From 9cce7d5ac893e4ce3eb16addefde473aabdb3adb Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 3 Feb 2023 15:11:14 +0800 Subject: [PATCH 096/258] phy: rockchip: inno-usb2: fix incorrect perip_connected The U2PHY sent "peripheral connected" extcon message to DWC3 even if there is no USB cable pluuged when the otg_sm_work is scheduled first time, this would be resumed DWC3 unexpectedly and cause the DWC3 gadget to incorrect state. So initialize the perip_connected to false before send the extcon message to fix it. This can fix the ADB can not be enumerated when plug the USB cable in the first time after the system boot up and the below messages may find in the Kernel log on RK3562-EVB2 board. [ 7.218101] read descriptors [ 7.218191] read strings [ 7.306784] dwc3 fe500000.usb: failed to enable ep0out Fixes: 00168bb5b5aa ("phy: rockchip: inno-usb2: fix otg port with vbus always on") Signed-off-by: Frank Wang Change-Id: I90209f15605d16ca746dd6c44fbaf6d9c1684eaa --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 0536c08e216e..4f545a9db14a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -1291,6 +1291,7 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) } else { rphy->chg_state = USB_CHG_STATE_UNDEFINED; rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; + rport->perip_connected = false; mutex_unlock(&rport->mutex); if (!rport->dis_u2_susphy) rockchip_usb2phy_power_off(rport->phy); From c8436595e4a945d8644302ddfc2fbb1516dbcec0 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Wed, 8 Feb 2023 15:43:05 +0800 Subject: [PATCH 097/258] ARM: dts: rockchip: rk3288 fix thermal node name to 'soc-thermal' Fixes: 043ddfca3f2e ("ARM: dts: rockchip: rk3288: add operating-points-v2 for cpu nodes") The pvtm driver will find a thermal by name of the thermal node. This patch fixes a issue as following: [ 5.215126] cpu cpu0: failed to read out thermal zone (-22) [ 5.221562] thermal thermal_zone1: binding zone cpu_thermal with cdev thermal-cpufreq-0 failed:-17 Signed-off-by: Jianqun Xu Change-Id: I475e4035ab797f9d374feaddce8fda68af0d522c --- arch/arm/boot/dts/rk3288.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 2ed45b0d03d2..e764a7e6ae9a 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -154,7 +154,7 @@ rockchip,pvtm-error = <1000>; rockchip,pvtm-ref-temp = <35>; rockchip,pvtm-temp-prop = <(-18) (-18)>; - rockchip,thermal-zone = "soc-thermal"; + rockchip,thermal-zone = "cpu-thermal"; opp-126000000 { opp-hz = /bits/ 64 <126000000>; @@ -611,7 +611,7 @@ thermal-sensors = <&tsadc 0>; }; - cpu_thermal: cpu_thermal { + cpu_thermal: cpu-thermal { polling-delay-passive = <100>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ From bb15bb91c3b0399a8dcdcca559b1243ef85dcb8a Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Wed, 8 Feb 2023 15:56:42 +0800 Subject: [PATCH 098/258] Revert "ARM: dts: rockchip: rk3288: Fix reg size for ehci" This reverts commit 0fce242c0177650a84f61f3c7b68a33a4cce2384. Signed-off-by: Jianqun Xu Change-Id: I34edb1a073fb977bcd78300fc14ac5d0040d3de6 --- arch/arm/boot/dts/rk3288.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index e764a7e6ae9a..c925562f587e 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -725,7 +725,7 @@ usb_host0_ehci: usb@ff500000 { compatible = "generic-ehci"; - reg = <0x0 0xff500000 0x0 0x20000>; + reg = <0x0 0xff500000 0x0 0x100>; interrupts = ; clocks = <&cru HCLK_USBHOST0>, <&usbphy1>; clock-names = "usbhost", "utmi"; From 9c22724d164588556c9cfeb1d30e6e6041a4dafe Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Wed, 8 Feb 2023 17:31:45 +0800 Subject: [PATCH 099/258] ARM: dts: rockchip: default to disable the rga for rk3288 Set the rga node to be "disabled" defaultly for rk3288. Signed-off-by: Jianqun Xu Change-Id: Idccb5dfd79e7bfd5005307f5fba576df1ff03a0d --- arch/arm/boot/dts/rk3288.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index c925562f587e..ab2c22ea8b64 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1341,6 +1341,7 @@ power-domains = <&power RK3288_PD_VIO>; resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; reset-names = "core", "axi", "ahb"; + status = "disabled"; }; vopb: vop@ff930000 { From a74fc5b70d808aee44a75d3f2237f6017a3d0046 Mon Sep 17 00:00:00 2001 From: Korneliusz Osmenda Date: Tue, 7 Feb 2023 10:59:16 +0800 Subject: [PATCH 100/258] BACKPORT: FROMLIST: PCI: sysfs: Guard pci_create_sysfs_dev_files with atomic value There is a race contition seen in rockchip platform which seems expose a long existing bug in PCI sysfs code. 1. pci_bus_add_device() called pcibios_bus_add_device() or pci_fixup_device() but have not called pci_create_sysfs_dev_files() yet. Meanwhile pci_sysfs_init() is running and pci_create_sysfs_dev_files() was called for newly registered device. In this case function pci_create_sysfs_dev_files() is called two times, ones from pci_bus_add_device() and once from pci_sysfs_init(). 2. pci_sysfs_init() is called. It first sets sysfs_initialized to 1 which unblock calling pci_create_sysfs_dev_files(). Then another bus registers new PCI device and calls pci_bus_add_device() which calls pci_create_sysfs_dev_files() and registers sysfs files. Function pci_sysfs_init() continues execution and calls function pci_create_sysfs_dev_files() also for this newly registered device. So pci_create_sysfs_dev_files() is again called two times. The call trace looks like: [ 2.822232] [ T143] sysfs: cannot create duplicate filename '/devices/platform/fe170000.pcie/pci0002:20/0002:20:00.0/0002:21:00.0/config' [ 2.822240] [ T143] CPU: 1 PID: 143 Comm: rk-pcie Not tainted 5.10.66 #56 [ 2.822245] [ T143] Hardware name: Telpo RK3588 F206 Board (DT) [ 2.822251] [ T143] Call trace: [ 2.822262] [ T143] dump_backtrace+0x0/0x1c8 [ 2.822269] [ T143] show_stack+0x1c/0x2c [ 2.822276] [ T143] dump_stack_lvl+0xdc/0x12c [ 2.822282] [ T143] dump_stack+0x1c/0x64 [ 2.822289] [ T143] sysfs_warn_dup+0x6c/0x8c [ 2.822296] [ T143] sysfs_create_bin_file+0xe4/0x130 [ 2.822303] [ T143] pci_create_sysfs_dev_files+0x50/0x210 [ 2.822310] [ T143] pci_bus_add_device+0x30/0xac [ 2.822316] [ T143] pci_bus_add_devices+0x44/0x88 [ 2.822321] [ T143] pci_bus_add_devices+0x70/0x88 [ 2.822327] [ T143] pci_host_probe+0x78/0xb0 [ 2.822335] [ T143] dw_pcie_host_init+0x308/0x3f8 [ 2.822340] [ T143] rk_pcie_really_probe+0x954/0xe04 [ 2.822347] [ T143] kthread+0x13c/0x344 [ 2.822353] [ T143] ret_from_fork+0x10/0x30 There are continuous reporting about this bug[1] can be found here[1]. The above link leads me to the fix[2]. Upstream kernel has contained the fix: 0ad52e381d85eb86906749e2b8073cdc2265844b ("Convert "config" to static attribute") However there are still corner bugs around directory create. So Bijorn created a Bugzilla item[3] for it. After a long time, Korneliusz Osmenda pushed a new patch to fix it. Then we wait for another long period of time without any update. IMO, [4] is better than other proposes. So just backport the better fix into vendor tree. [1] https: //lore.kernel.org/all/m3eebg9puj.fsf@t19.piap.pl/ [2] https: //patchwork.kernel.org/project/linux-pci/patch/20210416205856.3234481-2-kw@linux.com/ [3] Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215515 [4] https: //patchwork.kernel.org/project/linux-pci/patch/4469eba2-188b-aab7-07d1-5c77313fc42f@gmail.com/ Signed-off-by: Korneliusz Osmenda Signed-off-by: Shawn Lin [Shawn: backport and reword to explain what happened] Change-Id: Ib0a54bc2204afa7d9136e8d3156b00ec6aa4d8b3 (cherry-picked from https: //patchwork.kernel.org/project/linux-pci/patch/4469eba2-188b-aab7-07d1-5c77313fc42f@gmail.com/) --- drivers/pci/pci-sysfs.c | 10 ++++++++++ include/linux/pci.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index d15c881e2e7e..8f845b8ad2c7 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1338,6 +1338,11 @@ int __must_check pci_create_sysfs_dev_files(struct pci_dev *pdev) if (!sysfs_initialized) return -EACCES; +#ifdef CONFIG_NO_GKI + if (atomic_cmpxchg(&pdev->sysfs_init_cnt, 0, 1) == 1) + return 0; /* already added */ +#endif + if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) retval = sysfs_create_bin_file(&pdev->dev.kobj, &pcie_config_attr); else @@ -1417,6 +1422,11 @@ void pci_remove_sysfs_dev_files(struct pci_dev *pdev) if (!sysfs_initialized) return; +#ifdef CONFIG_NO_GKI + if (atomic_cmpxchg(&pdev->sysfs_init_cnt, 1, 0) == 0) + return; /* already removed */ +#endif + pci_remove_capabilities_sysfs(pdev); if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) diff --git a/include/linux/pci.h b/include/linux/pci.h index 9d9c198be7d0..95fd50c28e18 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -453,6 +453,9 @@ struct pci_dev { pci_dev_flags_t dev_flags; atomic_t enable_cnt; /* pci_enable_device has been called */ +#ifdef CONFIG_NO_GKI + atomic_t sysfs_init_cnt; /* pci_create_sysfs_dev_files has been called */ +#endif u32 saved_config_space[16]; /* Config space saved at suspend time */ struct hlist_head saved_cap_space; struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ From bc249ee6f7579d574d29130c9125d885f46a92bd Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 8 Feb 2023 19:20:08 +0800 Subject: [PATCH 101/258] soc: rockchip: power-domain: Sync with upstream Signed-off-by: Tao Huang Change-Id: Ice950e43affea12912acf5f96d51c52b0c132bfb --- drivers/soc/rockchip/pm_domains.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 9e630d8e8349..4941d533990d 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -1705,17 +1705,6 @@ static const struct rockchip_pmu_info px30_pmu = { .domain_info = px30_pm_domains, }; -static const struct rockchip_pmu_info rv1126_pmu = { - .pwr_offset = 0x110, - .status_offset = 0x108, - .req_offset = 0xc0, - .idle_offset = 0xd8, - .ack_offset = 0xd0, - - .num_domains = ARRAY_SIZE(rv1126_pm_domains), - .domain_info = rv1126_pm_domains, -}; - static const struct rockchip_pmu_info rk1808_pmu = { .pwr_offset = 0x18, .status_offset = 0x20, @@ -1901,15 +1890,22 @@ static const struct rockchip_pmu_info rk3588_pmu = { .domain_info = rk3588_pm_domains, }; +static const struct rockchip_pmu_info rv1126_pmu = { + .pwr_offset = 0x110, + .status_offset = 0x108, + .req_offset = 0xc0, + .idle_offset = 0xd8, + .ack_offset = 0xd0, + + .num_domains = ARRAY_SIZE(rv1126_pm_domains), + .domain_info = rv1126_pm_domains, +}; + static const struct of_device_id rockchip_pm_domain_dt_match[] = { { .compatible = "rockchip,px30-power-controller", .data = (void *)&px30_pmu, }, - { - .compatible = "rockchip,rv1126-power-controller", - .data = (void *)&rv1126_pmu, - }, { .compatible = "rockchip,rk1808-power-controller", .data = (void *)&rk1808_pmu, @@ -1972,6 +1968,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3588-power-controller", .data = (void *)&rk3588_pmu, }, + { + .compatible = "rockchip,rv1126-power-controller", + .data = (void *)&rv1126_pmu, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, rockchip_pm_domain_dt_match); From 7558c3e9357e4c8cc8fedddfcbbe5d747ee30300 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 8 Feb 2023 19:32:41 +0800 Subject: [PATCH 102/258] gpio: rockchip: Sync with upstream Signed-off-by: Tao Huang Change-Id: I49a33907327f3c08d613d9c463cd9abaac8dcd92 --- drivers/gpio/gpio-rockchip.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index e4e16ba551be..b9327a33ec1d 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -16,8 +17,8 @@ #include #include #include -#include #include +#include #include #include @@ -274,10 +275,10 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, { enum pin_config_param param = pinconf_to_config_param(config); unsigned int debounce = pinconf_to_config_argument(config); - int ret = 0; switch (param) { case PIN_CONFIG_INPUT_DEBOUNCE: + rockchip_gpio_set_debounce(gc, offset, debounce); /* * Rockchip's gpio could only support up to one period * of the debounce clock(pclk), which is far away from @@ -289,15 +290,10 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, * still return -ENOTSUPP as before, to make sure the caller * of gpiod_set_debounce won't change its behaviour. */ - rockchip_gpio_set_debounce(gc, offset, debounce); - ret = -ENOTSUPP; - break; + return -ENOTSUPP; default: - ret = -ENOTSUPP; - break; + return -ENOTSUPP; } - - return ret; } /* From 9cd7abdb02afa6e9e5c9fbbb673fae4a61f43981 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 8 Feb 2023 19:45:37 +0800 Subject: [PATCH 103/258] net: wireless: rockchip_wlan: bcmdhd: No include stdarg.h from 5.15 Signed-off-by: Tao Huang Change-Id: If5a6ca39f8fcdc0854a34049f08f90c636b2044c --- drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmutils.c | 4 ++-- drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmxtlv.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmutils.c b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmutils.c index 63d237e7e648..6d9e4a80fa63 100755 --- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmutils.c +++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmutils.c @@ -23,9 +23,9 @@ #include #include -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) #include -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0) */ +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0) */ #ifdef BCMDRIVER #include #include diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmxtlv.c b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmxtlv.c index 91d5747f8581..70bb74e7c074 100755 --- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmxtlv.c +++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmxtlv.c @@ -24,9 +24,9 @@ #include #include -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) #include -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0) */ +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0) */ #ifdef BCMDRIVER #include From d1de5fc48f362bd859ca98531baca6b38bce1422 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Thu, 9 Feb 2023 11:32:58 +0800 Subject: [PATCH 104/258] soc: rockchip: bring all rockchip drivers into a submenu As the number of Rockchip drivers increase, entries in SoC menu looks scattered with other SoC drivers. Make a submenu for Rockchip drivers to make it visibly clear while selecting Rockchip SoC specific drivers. Signed-off-by: Tao Huang Change-Id: Ia657e184a32c9b28f6ddd585838890ba5ec814cf --- drivers/soc/rockchip/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig index 0773f56a9dc4..5b43df7b8516 100644 --- a/drivers/soc/rockchip/Kconfig +++ b/drivers/soc/rockchip/Kconfig @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only if ARCH_ROCKCHIP || COMPILE_TEST +menu "Rockchip SoC drivers" + source "drivers/soc/rockchip/Kconfig.cpu" # @@ -268,4 +270,6 @@ config RK_MEMBLOCK_PROCFS Extend memblock procfs to show size of each memblock, and shows the result of total size by KiB format. +endmenu + endif From 0a51d4a592e3501fa10186775eacc4d1bc99bfbe Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 8 Feb 2023 18:31:08 +0800 Subject: [PATCH 105/258] soc: rockchip: io-domain: Sync with upstream Change-Id: I3aa990729e988f08f384a10606cc2cf26d091b8a Signed-off-by: Tao Huang --- drivers/soc/rockchip/io-domain.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c index ae8ed0f3cfd0..f5ec81667ef3 100644 --- a/drivers/soc/rockchip/io-domain.c +++ b/drivers/soc/rockchip/io-domain.c @@ -68,15 +68,6 @@ struct rockchip_iodomain; -/** - * @supplies: voltage settings matching the register bits. - */ -struct rockchip_iodomain_soc_data { - int grf_offset; - const char *supply_names[MAX_SUPPLIES]; - void (*init)(struct rockchip_iodomain *iod); -}; - struct rockchip_iodomain_supply { struct rockchip_iodomain *iod; struct regulator *reg; @@ -84,6 +75,13 @@ struct rockchip_iodomain_supply { int idx; }; +struct rockchip_iodomain_soc_data { + int grf_offset; + const char *supply_names[MAX_SUPPLIES]; + void (*init)(struct rockchip_iodomain *iod); + int (*write)(struct rockchip_iodomain_supply *supply, int uV); +}; + struct rockchip_iodomain { struct device *dev; struct regmap *grf; @@ -92,8 +90,7 @@ struct rockchip_iodomain { int (*write)(struct rockchip_iodomain_supply *supply, int uV); }; -static int rk3568_pmu_iodomain_write(struct rockchip_iodomain_supply *supply, - int uV) +static int rk3568_iodomain_write(struct rockchip_iodomain_supply *supply, int uV) { struct rockchip_iodomain *iod = supply->iod; u32 is_3v3 = uV > MAX_VOLTAGE_1_8; @@ -504,6 +501,7 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = { "vccio6", "vccio7", }, + .write = rk3568_iodomain_write, }; static const struct rockchip_iodomain_soc_data soc_data_rv1108 = { @@ -788,8 +786,8 @@ static int rockchip_iodomain_probe(struct platform_device *pdev) match = of_match_node(rockchip_iodomain_match, np); iod->soc_data = match->data; - if (IS_ENABLED(CONFIG_CPU_RK3568) && match->data == &soc_data_rk3568_pmu) - iod->write = rk3568_pmu_iodomain_write; + if (iod->soc_data->write) + iod->write = iod->soc_data->write; else iod->write = rockchip_iodomain_write; From 0513facbab34e4376942a350efcabf3d289e599a Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Thu, 9 Feb 2023 10:45:57 +0800 Subject: [PATCH 106/258] dma-buf: Rename CONFIG_DMABUF_DEBUG to CONFIG_RK_DMABUF_DEBUG To avoid conflicts with upstream config. Signed-off-by: Tao Huang Change-Id: Ib24fc9dbd07604a934de53d3b2402ab747bbcadf --- drivers/dma-buf/Kconfig | 6 +++--- drivers/dma-buf/dma-buf.c | 8 ++++---- include/linux/dma-buf.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/dma-buf/Kconfig b/drivers/dma-buf/Kconfig index 5dc97ec0993d..0a173b70149b 100644 --- a/drivers/dma-buf/Kconfig +++ b/drivers/dma-buf/Kconfig @@ -9,8 +9,8 @@ config DMABUF_CACHE This option support to store attachments in a list and destroy them by set to a callback list in the dtor of dma-buf. -config DMABUF_DEBUG - bool "DMABUF debug option" +config RK_DMABUF_DEBUG + bool "Rockchip DMABUF debug option" depends on NO_GKI select RK_DMABUF_PROCFS help @@ -19,7 +19,7 @@ config DMABUF_DEBUG config DMABUF_DEBUG_ADVANCED bool "DMABUF debug advanced option" - depends on DMABUF_DEBUG + depends on RK_DMABUF_DEBUG help This option support to debug all the dmabuf on db_list, allows to attach and map a dmabuf who has no attachment. If not sure, say N diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 0891d5994a30..b077fe78b756 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -63,7 +63,7 @@ int get_each_dmabuf(int (*callback)(const struct dma_buf *dmabuf, } EXPORT_SYMBOL_GPL(get_each_dmabuf); -#if IS_ENABLED(CONFIG_DMABUF_DEBUG) +#if IS_ENABLED(CONFIG_RK_DMABUF_DEBUG) static size_t db_total_size; static size_t db_peak_size; @@ -167,7 +167,7 @@ static int dma_buf_file_release(struct inode *inode, struct file *file) dmabuf = file->private_data; mutex_lock(&db_list.lock); -#if IS_ENABLED(CONFIG_DMABUF_DEBUG) +#if IS_ENABLED(CONFIG_RK_DMABUF_DEBUG) db_total_size -= dmabuf->size; #endif list_del(&dmabuf->list_node); @@ -726,7 +726,7 @@ struct dma_buf *dma_buf_export(const struct dma_buf_export_info *exp_info) mutex_lock(&db_list.lock); list_add(&dmabuf->list_node, &db_list.head); -#if IS_ENABLED(CONFIG_DMABUF_DEBUG) +#if IS_ENABLED(CONFIG_RK_DMABUF_DEBUG) db_total_size += dmabuf->size; db_peak_size = max(db_total_size, db_peak_size); #endif @@ -736,7 +736,7 @@ struct dma_buf *dma_buf_export(const struct dma_buf_export_info *exp_info) if (ret) goto err_sysfs; - if (IS_ENABLED(CONFIG_DMABUF_DEBUG)) + if (IS_ENABLED(CONFIG_RK_DMABUF_DEBUG)) dma_buf_set_default_name(dmabuf); return dmabuf; diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h index f87ebbdf945b..485b3d526e66 100644 --- a/include/linux/dma-buf.h +++ b/include/linux/dma-buf.h @@ -661,7 +661,7 @@ static inline void dma_buf_set_destructor(struct dma_buf *dmabuf, } #endif -#if IS_ENABLED(CONFIG_DMABUF_DEBUG) +#if IS_ENABLED(CONFIG_RK_DMABUF_DEBUG) void dma_buf_reset_peak_size(void); size_t dma_buf_get_peak_size(void); size_t dma_buf_get_total_size(void); From 4f0ec7c431be467b4421a739db0666b0fff147a7 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Thu, 9 Feb 2023 10:51:31 +0800 Subject: [PATCH 107/258] arm64: configs: Renmae CONFIG_DMABUF_DEBUG to CONFIG_RK_DMABUF_DEBUG Signed-off-by: Tao Huang Change-Id: Ie808ed8bd8d47e2fbd5734a20ab979a5c240b2e9 --- arch/arm64/configs/rockchip_defconfig | 2 +- arch/arm64/configs/rockchip_linux_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index 00157fd9c756..5672f6ee1f47 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -854,7 +854,7 @@ CONFIG_RTC_DRV_HYM8563=y CONFIG_RTC_DRV_RK808=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y -CONFIG_DMABUF_DEBUG=y +CONFIG_RK_DMABUF_DEBUG=y CONFIG_SW_SYNC=y CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_SYSFS_STATS=y diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig index b0e9a4098d6e..5ccb0bcac1fd 100644 --- a/arch/arm64/configs/rockchip_linux_defconfig +++ b/arch/arm64/configs/rockchip_linux_defconfig @@ -478,7 +478,7 @@ CONFIG_RTC_DRV_HYM8563=y CONFIG_RTC_DRV_RK808=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y -CONFIG_DMABUF_DEBUG=y +CONFIG_RK_DMABUF_DEBUG=y CONFIG_SW_SYNC=y CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_SYSFS_STATS=y From 50ae3938ef3eb3a2307f710a0792c279986157f3 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Thu, 9 Feb 2023 11:27:47 +0800 Subject: [PATCH 108/258] dma-buf: Rename CONFIG_DMABUF_DEBUG_ADVANCED to CONFIG_RK_DMABUF_DEBUG_ADVANCED Signed-off-by: Tao Huang Change-Id: I7752359d34e1fb579471d915c2e2039229a2defc --- drivers/dma-buf/Kconfig | 4 ++-- drivers/soc/rockchip/rk_dmabuf_procfs.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma-buf/Kconfig b/drivers/dma-buf/Kconfig index 0a173b70149b..f46fe574bb1e 100644 --- a/drivers/dma-buf/Kconfig +++ b/drivers/dma-buf/Kconfig @@ -17,8 +17,8 @@ config RK_DMABUF_DEBUG This option support to debug all the dmabuf on db_list, allows to set a name for dmabuf. If not sure, say N -config DMABUF_DEBUG_ADVANCED - bool "DMABUF debug advanced option" +config RK_DMABUF_DEBUG_ADVANCED + bool "Rockchip DMABUF debug advanced option" depends on RK_DMABUF_DEBUG help This option support to debug all the dmabuf on db_list, allows to attach diff --git a/drivers/soc/rockchip/rk_dmabuf_procfs.c b/drivers/soc/rockchip/rk_dmabuf_procfs.c index a4d4273a1d3c..943b196e2b9c 100644 --- a/drivers/soc/rockchip/rk_dmabuf_procfs.c +++ b/drivers/soc/rockchip/rk_dmabuf_procfs.c @@ -79,7 +79,7 @@ static void rk_dmabuf_dump_sgt(const struct dma_buf *dmabuf, void *private) return; } /* Try to attach and map the dmabufs without sgt. */ - if (IS_ENABLED(CONFIG_DMABUF_DEBUG_ADVANCED)) { + if (IS_ENABLED(CONFIG_RK_DMABUF_DEBUG_ADVANCED)) { struct dma_buf *dbuf = (struct dma_buf *)dmabuf; get_dma_buf(dbuf); From 8abf8eba33021f6e4546a4b6604686913c74b238 Mon Sep 17 00:00:00 2001 From: Wangqiang Guo Date: Fri, 3 Feb 2023 07:28:37 +0000 Subject: [PATCH 109/258] media: rockchip: hdmirx: add aviif_chg_irq. Use aviif_chg_irq interrupts to monitor scenarios where the TMDS signal is not disconnected but the resolution, frame rate, color range or image format changes. Change-Id: I2f6e3d0d734de1c5a8033b00d3b6b14d1815f6ca Signed-off-by: Wangqiang Guo --- .../platform/rockchip/hdmirx/rk_hdmirx.c | 39 ++++++++++++++++--- .../platform/rockchip/hdmirx/rk_hdmirx.h | 5 +++ 2 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c index b828cec04bc0..ef185a77b8db 100644 --- a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c +++ b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c @@ -668,7 +668,7 @@ static void hdmirx_get_color_space(struct rk_hdmirx_dev *hdmirx_dev) struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; /* - * Note: PKTDEC_ACR_PB3_0 contents only updated after + * Note: PKTDEC_AVIIF_PB3_0 contents only updated after * reading pktdec_aviif_ph2_1 unless snapshot feature * is disabled using pktdec_snapshot_bypass */ @@ -687,7 +687,7 @@ static void hdmirx_get_color_range(struct rk_hdmirx_dev *hdmirx_dev) struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; /* - * Note: PKTDEC_ACR_PB3_0 contents only updated after + * Note: PKTDEC_AVIIF_PB3_0 contents only updated after * reading pktdec_aviif_ph2_1 unless snapshot feature * is disabled using pktdec_snapshot_bypass */ @@ -2375,6 +2375,7 @@ static void avpunit_1_int_handler(struct rk_hdmirx_dev *hdmirx_dev, hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff); hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_FORCE, 0x0); } + static void mainunit_0_int_handler(struct rk_hdmirx_dev *hdmirx_dev, int status, bool *handled) { @@ -2434,6 +2435,22 @@ static void mainunit_2_int_handler(struct rk_hdmirx_dev *hdmirx_dev, hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_FORCE, 0x0); } +static void pkt_0_int_handler(struct rk_hdmirx_dev *hdmirx_dev, + int status, bool *handled) +{ + struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; + + if ((status & PKTDEC_AVIIF_CHG_IRQ)) { + process_signal_change(hdmirx_dev); + v4l2_dbg(2, debug, v4l2_dev, "%s: ptk0_st:%#x\n", + __func__, status); + *handled = true; + } + + hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff); + hdmirx_writel(hdmirx_dev, PKT_0_INT_FORCE, 0x0); +} + static void pkt_2_int_handler(struct rk_hdmirx_dev *hdmirx_dev, int status, bool *handled) { @@ -2470,15 +2487,17 @@ static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id) struct rk_hdmirx_dev *hdmirx_dev = dev_id; struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev; bool handled = false; - u32 mu0_st, mu2_st, pk2_st, scdc_st, avp1_st, avp0_st; - u32 mu0_mask, mu2_mask, pk2_mask, scdc_mask, avp1_msk, avp0_msk; + u32 mu0_st, mu2_st, pk2_st, scdc_st, avp1_st, avp0_st, pk0_st; + u32 mu0_mask, mu2_mask, pk2_mask, scdc_mask, avp1_msk, avp0_msk, pk0_mask; mu0_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_MASK_N); mu2_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_MASK_N); + pk0_mask = hdmirx_readl(hdmirx_dev, PKT_0_INT_MASK_N); pk2_mask = hdmirx_readl(hdmirx_dev, PKT_2_INT_MASK_N); scdc_mask = hdmirx_readl(hdmirx_dev, SCDC_INT_MASK_N); mu0_st = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_STATUS); mu2_st = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_STATUS); + pk0_st = hdmirx_readl(hdmirx_dev, PKT_0_INT_STATUS); pk2_st = hdmirx_readl(hdmirx_dev, PKT_2_INT_STATUS); scdc_st = hdmirx_readl(hdmirx_dev, SCDC_INT_STATUS); avp0_st = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_STATUS); @@ -2487,6 +2506,7 @@ static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id) avp1_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_MASK_N); mu0_st &= mu0_mask; mu2_st &= mu2_mask; + pk0_st &= pk0_mask; pk2_st &= pk2_mask; avp1_st &= avp1_msk; avp0_st &= avp0_msk; @@ -2500,6 +2520,8 @@ static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id) mainunit_0_int_handler(hdmirx_dev, mu0_st, &handled); if (mu2_st) mainunit_2_int_handler(hdmirx_dev, mu2_st, &handled); + if (pk0_st) + pkt_0_int_handler(hdmirx_dev, pk0_st, &handled); if (pk2_st) pkt_2_int_handler(hdmirx_dev, pk2_st, &handled); if (scdc_st) @@ -2508,8 +2530,8 @@ static irqreturn_t hdmirx_hdmi_irq_handler(int irq, void *dev_id) if (!handled) { v4l2_dbg(2, debug, v4l2_dev, "%s: hdmi irq not handled!", __func__); v4l2_dbg(2, debug, v4l2_dev, - "avp0:%#x, avp1:%#x, mu0:%#x, mu2:%#x, pk2:%#x, scdc:%#x\n", - avp0_st, avp1_st, mu0_st, mu2_st, pk2_st, scdc_st); + "avp0:%#x, avp1:%#x, mu0:%#x, mu2:%#x, pk0: %#x, pk2:%#x, scdc:%#x\n", + avp0_st, avp1_st, mu0_st, mu2_st, pk0_st, pk2_st, scdc_st); } v4l2_dbg(2, debug, v4l2_dev, "%s: en_fiq", __func__); @@ -2732,6 +2754,7 @@ static void hdmirx_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en) hdmirx_clear_interrupt(hdmirx_dev, MAINUNIT_2_INT_CLEAR, 0xffffffff); hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_0_INT_CLEAR, 0xffffffff); hdmirx_clear_interrupt(hdmirx_dev, AVPUNIT_1_INT_CLEAR, 0xffffffff); + hdmirx_clear_interrupt(hdmirx_dev, PKT_0_INT_CLEAR, 0xffffffff); if (en) { hdmirx_update_bits(hdmirx_dev, MAINUNIT_0_INT_MASK_N, @@ -2742,11 +2765,15 @@ static void hdmirx_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en) hdmirx_update_bits(hdmirx_dev, AVPUNIT_1_INT_MASK_N, VMON_VMEAS_IRQ | VMON_HMEAS_IRQ, VMON_VMEAS_IRQ | VMON_HMEAS_IRQ); + hdmirx_update_bits(hdmirx_dev, PKT_0_INT_MASK_N, + PKTDEC_AVIIF_CHG_MASK_N, + PKTDEC_AVIIF_CHG_MASK_N); } else { hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0); hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0); hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0); hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_MASK_N, 0); + hdmirx_writel(hdmirx_dev, PKT_0_INT_MASK_N, 0); } sip_hdmirx_config(HDMIRX_REG_PRE_FETCH, 0, MAINUNIT_0_INT_MASK_N, 0); diff --git a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.h b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.h index 87f64999fd13..a1af89eea681 100644 --- a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.h +++ b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.h @@ -423,10 +423,15 @@ #define AVPUNIT_1_INT_FORCE 0x505C #define PKT_0_INT_STATUS 0x5080 #define PKTDEC_AUDIF_CHG_IRQ BIT(13) +#define PKTDEC_AVIIF_CHG_IRQ BIT(11) +#define PKTDEV_VSIF_CHG_IRQ BIT(10) #define PKTDEC_ACR_CHG_IRQ BIT(3) #define PKT_0_INT_MASK_N 0x5084 +#define PKTDEC_AVIIF_CHG_MASK_N BIT(11) +#define PKTDEV_VSIF_CHG_MASK_N BIT(10) #define PKTDEC_ACR_CHG_MASK_N BIT(3) #define PKT_0_INT_CLEAR 0x5088 +#define PKT_0_INT_FORCE 0x508c #define PKT_1_INT_STATUS 0x5090 #define PKT_1_INT_MASK_N 0x5094 #define PKT_1_INT_CLEAR 0x5098 From 408861dc073d551066069e12860e5e233626d509 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Wed, 8 Feb 2023 17:16:12 +0800 Subject: [PATCH 110/258] Revert "ARM: dts: rockchip: delete gpu 100MHz for rk3288" This reverts commit 25e9b5b53a5cca05e224824d16d29e69939d3e3d. Signed-off-by: Jianqun Xu Change-Id: Ifabc3f04113c0b8ebf054df2cbc58c57d4c3925b --- arch/arm/boot/dts/rk3288.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ab2c22ea8b64..c5b3c01ad56e 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1787,6 +1787,10 @@ 3 61 >; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <950000>; From c44d1ff0abf32e7dfa0a3d7368587044c2c66536 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 8 Feb 2023 18:52:50 +0800 Subject: [PATCH 111/258] clk: rockchip: rk3562: Add clock ids for secure crypto Signed-off-by: Finley Xiao Change-Id: Ic2614c5ff312e6a2b69b481eb5d794c97e6f711e --- include/dt-bindings/clock/rk3562-cru.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/rk3562-cru.h b/include/dt-bindings/clock/rk3562-cru.h index bee65dbf450c..3bdbed5a8c7e 100644 --- a/include/dt-bindings/clock/rk3562-cru.h +++ b/include/dt-bindings/clock/rk3562-cru.h @@ -369,8 +369,12 @@ #define HCLK_VOP 359 #define DCLK_VOP 360 #define DCLK_VOP1 361 +#define ACLK_CRYPTO_S 362 +#define PCLK_CRYPTO_S 363 +#define CLK_CORE_CRYPTO_S 364 +#define CLK_PKA_CRYPTO_S 365 -#define CLK_NR_CLKS (DCLK_VOP1 + 1) +#define CLK_NR_CLKS (CLK_PKA_CRYPTO_S + 1) /* soft-reset indices */ From 001bea88b9f1ad0c8d74734b84ba8607aba47bf3 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 8 Feb 2023 11:40:02 +0800 Subject: [PATCH 112/258] arm64: dts: rockchip: rk3562: Crypto and rng use scmi clock Signed-off-by: Finley Xiao Change-Id: Ia34b1caf94aaa964c71a303130f81ee0d1f5253f --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 7a0c8d93adc2..a1279e8e29ee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -2096,10 +2096,11 @@ compatible = "rockchip,crypto-v4"; reg = <0x0 0xff8a0000 0x0 0x2000>; interrupts = ; - clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, - <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; - clock-names = "aclk", "hclk", "sclk", "pka"; - assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; + clocks = <&scmi_clk ACLK_CRYPTO>, <&scmi_clk HCLK_CRYPTO>, + <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>, + <&scmi_clk PCLK_CRYPTO>; + clock-names = "aclk", "hclk", "sclk", "pka", "pclk"; + assigned-clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>; assigned-clock-rates = <200000000>, <300000000>; resets = <&cru SRST_CORE_CRYPTO>; reset-names = "crypto-rst"; @@ -2110,7 +2111,7 @@ compatible = "rockchip,rkrng"; reg = <0x0 0xff8e0000 0x0 0x200>; interrupts = ; - clocks = <&cru HCLK_RK_RNG_NS>; + clocks = <&scmi_clk HCLK_RK_RNG_NS>; clock-names = "hclk_trng"; resets = <&cru SRST_H_RK_RNG_NS>; reset-names = "reset"; From b46525b95177a93253577eb140f02d75b24321ff Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Wed, 21 Dec 2022 10:48:07 +0800 Subject: [PATCH 113/258] dt-bindings: devfreq: rockchip_dfi: Add rk3562 support Signed-off-by: YouMin Chen Change-Id: Ia10308583f88909a2efeb76922ca635f63d6016e --- Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt index eee2a7f7cb92..8534c99d9f00 100644 --- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt @@ -10,6 +10,7 @@ Required properties: - "rockchip,rk3328-dfi" - for RK3328 SoCs. - "rockchip,rk3368-dfi" - for RK3368 SoCs. - "rockchip,rk3399-dfi" - for RK3399 SoCs. + - "rockchip,rk3562-dfi" - for RK3562 SoCs. - "rockchip,rk3568-dfi" - for RK3568 SoCs. - "rockchip,rv1126-dfi" - for RV1126 SoCs. From 1af50cdeaf64784b24675e5d0411ee531d4ed0d0 Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Wed, 21 Dec 2022 11:24:52 +0800 Subject: [PATCH 114/258] PM / devfreq: rockchip-dfi: Add support for rk3562 dfi Signed-off-by: YouMin Chen Change-Id: Idf016a7ad082771277e6de6a7412d9a7a8e226eb --- drivers/devfreq/event/rockchip-dfi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 0708535bda18..4aa090e78b0a 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -745,6 +745,9 @@ static const struct of_device_id rockchip_dfi_id_match[] = { #ifdef CONFIG_CPU_RK3399 { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, #endif +#ifdef CONFIG_CPU_RK3562 + { .compatible = "rockchip,rk3562-dfi", .data = px30_dfi_init }, +#endif #ifdef CONFIG_CPU_RK3568 { .compatible = "rockchip,rk3568-dfi", .data = px30_dfi_init }, #endif From 65a05dcbab33344840e175db07a4d5fc465949a8 Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Wed, 21 Dec 2022 14:23:31 +0800 Subject: [PATCH 115/258] dt-bindings: devfreq: rockchip_dmc: Add rk3562 support Signed-off-by: YouMin Chen Change-Id: I00e209a30918bc69d43d93306a812e10805fe32c --- Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt b/Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt index 6c9b927a1ab0..cc8964697434 100644 --- a/Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt @@ -11,6 +11,7 @@ Required properties: - "rockchip,rk3328-dmc" - for RK3328 SoCs. - "rockchip,rk3368-dmc" - for RK3368 SoCs. - "rockchip,rk3399-dmc" - for RK3399 SoCs. + - "rockchip,rk3562-dmc" - for RK3562 SoCs. - "rockchip,rk3568-dmc" - for RK3568 SoCs. - "rockchip,rk3588-dmc" - for RK3588 SoCs. - "rockchip,rv1126-dmc" - for RV1126 SoCs. From c7cb4c1ef83bfe9861b54854cb4811612a994182 Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Wed, 21 Dec 2022 14:29:58 +0800 Subject: [PATCH 116/258] PM / devfreq: rockchip_dmc: Add support for rk3562 Signed-off-by: YouMin Chen Change-Id: I839d731812df29a05f339a0ff5d63bf2056a88f2 --- drivers/devfreq/rockchip_dmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/devfreq/rockchip_dmc.c b/drivers/devfreq/rockchip_dmc.c index 92d7e5794cf7..dc6364894b39 100644 --- a/drivers/devfreq/rockchip_dmc.c +++ b/drivers/devfreq/rockchip_dmc.c @@ -2181,6 +2181,9 @@ static const struct of_device_id rockchip_dmcfreq_of_match[] = { #if IS_ENABLED(CONFIG_CPU_RK3399) { .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init }, #endif +#if IS_ENABLED(CONFIG_CPU_RK3562) + { .compatible = "rockchip,rk3562-dmc", .data = rk3568_dmc_init }, +#endif #if IS_ENABLED(CONFIG_CPU_RK3568) { .compatible = "rockchip,rk3568-dmc", .data = rk3568_dmc_init }, #endif From d5089114110c1db2e34592fef0527a66c8ec43cb Mon Sep 17 00:00:00 2001 From: YouMin Chen Date: Wed, 21 Dec 2022 15:45:59 +0800 Subject: [PATCH 117/258] arm64: dts: rockchip: Add rk3562 ddr relate node Signed-off-by: YouMin Chen Change-Id: Icd2ba1ef071259e50ff4495fb1b78caf02d82cd9 --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index a1279e8e29ee..a673b441821a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -322,6 +322,42 @@ }; }; + dmc: dmc { + compatible = "rockchip,rk3562-dmc"; + interrupts = ; + interrupt-names = "complete"; + devfreq-events = <&dfi>; + clocks = <&scmi_clk CLK_DDR>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + upthreshold = <40>; + downdifferential = <20>; + system-status-level = < + /*system status freq level*/ + SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH + SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW + SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH + SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH + SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH + SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH + >; + auto-min-freq = <324000>; + auto-freq-en = <1>; + #cooling-cells = <2>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + opp-1560000000 { + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <900000>; + }; + }; + firmware { scmi: scmi { compatible = "arm,scmi-smc"; @@ -1534,6 +1570,13 @@ status = "disabled"; }; + dfi: dfi@ff4c0000 { + reg = <0x00 0xff4c0000 0x00 0x400>; + compatible = "rockchip,rk3562-dfi"; + rockchip,pmugrf = <&pmu_grf>; + status = "disabled"; + }; + pcie2x1: pcie@ff500000 { compatible = "rockchip,rk3562-pcie", "snps,dw-pcie"; #address-cells = <3>; From 52c9c71ccbf1a4d7afd9e642ea56f279728a0b42 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 8 Feb 2023 11:08:49 +0800 Subject: [PATCH 118/258] clk: rockchip: rk3562: Remove CRYPTO RNG and KLAD clocks Signed-off-by: Finley Xiao Change-Id: I35d432561605227b35a1c3b953bfa6c926b1adb8 --- drivers/clk/rockchip/clk-rk3562.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c index a9f9129a7b87..ae80763a6d84 100644 --- a/drivers/clk/rockchip/clk-rk3562.c +++ b/drivers/clk/rockchip/clk-rk3562.c @@ -169,8 +169,6 @@ PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" }; PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" }; PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" }; PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; -PNAME(mux_200m_100m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "xin24m" }; -PNAME(mux_300m_200m_100m_xin24m_p) = { "clk_matrix_300m_src", "clk_matrix_200m_src", "clk_matrix_100m_src", "xin24m" }; PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_io" }; PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" }; PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_io" }; @@ -788,32 +786,6 @@ static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = { COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, RK3562_PERI_CLKSEL_CON(41), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3562_PERI_CLKGATE_CON(11), 3, GFLAGS), - GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_peri", 0, - RK3562_PERI_CLKGATE_CON(12), 0, GFLAGS), - GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_peri", 0, - RK3562_PERI_CLKGATE_CON(12), 1, GFLAGS), - GATE(PCLK_CRYPTO, "pclk_crypto", "pclk_peri", 0, - RK3562_PERI_CLKGATE_CON(12), 2, GFLAGS), - COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_200m_100m_xin24m_p, 0, - RK3562_PERI_CLKSEL_CON(43), 0, 2, MFLAGS, - RK3562_PERI_CLKGATE_CON(12), 3, GFLAGS), - COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_xin24m_p, 0, - RK3562_PERI_CLKSEL_CON(43), 6, 2, MFLAGS, - RK3562_PERI_CLKGATE_CON(12), 4, GFLAGS), - GATE(HCLK_KLAD, "hclk_klad", "hclk_peri", CLK_IGNORE_UNUSED, - RK3562_PERI_CLKGATE_CON(12), 5, GFLAGS), - GATE(PCLK_KEY_READER, "pclk_key_reader", "pclk_peri", CLK_IGNORE_UNUSED, - RK3562_PERI_CLKGATE_CON(12), 6, GFLAGS), - GATE(HCLK_RK_RNG_NS, "hclk_rk_rng_ns", "hclk_peri", CLK_IGNORE_UNUSED, - RK3562_PERI_CLKGATE_CON(12), 7, GFLAGS), - GATE(HCLK_RK_RNG_S, "hclk_rk_rng_s", "hclk_peri", CLK_IGNORE_UNUSED, - RK3562_PERI_CLKGATE_CON(12), 8, GFLAGS), - GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_peri", CLK_IGNORE_UNUSED, - RK3562_PERI_CLKGATE_CON(12), 9, GFLAGS), - GATE(HCLK_TRNG_S, "hclk_trng_s", "hclk_peri", CLK_IGNORE_UNUSED, - RK3562_PERI_CLKGATE_CON(12), 10, GFLAGS), - GATE(HCLK_CRYPTO_S, "hclk_crypto_s", "hclk_peri", CLK_IGNORE_UNUSED, - RK3562_PERI_CLKGATE_CON(12), 11, GFLAGS), GATE(PCLK_PERI_WDT, "pclk_peri_wdt", "pclk_peri", 0, RK3562_PERI_CLKGATE_CON(13), 0, GFLAGS), COMPOSITE_NODIV(TCLK_PERI_WDT, "tclk_peri_wdt", mux_xin24m_32k_p, 0, From 3fb264c4e2b9f952fcb7ab67f4198b1a636b946a Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 2 Feb 2023 10:48:52 +0800 Subject: [PATCH 119/258] soc: rockchip: power-domain: Fix up the dump information of panic Just dump the valid register. Signed-off-by: Elaine Zhang Change-Id: I3c35530d03463d2a5940862d866668a1f51a283c --- drivers/soc/rockchip/pm_domains.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 4941d533990d..04daba2cd212 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -1346,14 +1346,32 @@ late_initcall_sync(rockchip_pd_keepon_release); static void __iomem *pd_base; +static void dump_offset(const char *name, u32 offset) +{ + if (!offset) + return; + + pr_warn("%-9s 0x%04x: ", name, offset); + print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 4, pd_base + offset, 16, false); +} + void rockchip_dump_pmu(void) { - if (pd_base) { - pr_warn("PMU:\n"); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, - 32, 4, pd_base, - 0x100, false); - } + if (!pd_base) + return; + + pr_warn("PMU:\n"); + dump_offset("pwr", g_pmu->info->pwr_offset); + dump_offset("status", g_pmu->info->status_offset); + dump_offset("req", g_pmu->info->req_offset); + dump_offset("idle", g_pmu->info->idle_offset); + dump_offset("ack", g_pmu->info->ack_offset); + dump_offset("mem_pwr", g_pmu->info->mem_pwr_offset); + dump_offset("chain_st", g_pmu->info->chain_status_offset); + dump_offset("mem_st", g_pmu->info->mem_status_offset); + dump_offset("repair_st", g_pmu->info->repair_status_offset); + dump_offset("clkungate", g_pmu->info->clk_ungate_offset); + dump_offset("mem_sd", g_pmu->info->mem_sd_offset); } EXPORT_SYMBOL_GPL(rockchip_dump_pmu); From 89d5027fb3d2712a5a3168f0c78a6c1cd1928c06 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 2 Feb 2023 10:52:03 +0800 Subject: [PATCH 120/258] clk: rockchip: rk3588: Fix up the dump information of panic Just dump the valid register. Signed-off-by: Elaine Zhang Change-Id: I82d9ab4d0f97b93b9dcfde5a07fbd4f4afb9ab23 --- drivers/clk/rockchip/clk-rk3588.c | 46 +++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index ea8c8df593d3..28c23e962c57 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -2383,21 +2383,43 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { static void __iomem *rk3588_cru_base; +static void dump_offset(const char *name, u32 offset, u32 len) +{ + int i = 0, cnt = 0; + + if (!offset) + return; + + cnt = DIV_ROUND_UP(len, 32); + for (i = 0; i < cnt; i++) { + pr_warn("%-12s 0x%05x: ", name, offset + i * 32); + print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 32, 4, + rk3588_cru_base + offset + i * 0x10, 32, false); + } +} + static void rk3588_dump_cru(void) { if (rk3588_cru_base) { - pr_warn("DSU CRU:\n"); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, - 32, 4, rk3588_cru_base + RK3588_DSU_CRU_BASE, - 0x330, false); - pr_warn("BIGCORE0 CRU:\n"); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, - 32, 4, rk3588_cru_base + RK3588_BIGCORE0_CRU_BASE, - 0x300, false); - pr_warn("BIGCORE1 CRU:\n"); - print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, - 32, 4, rk3588_cru_base + RK3588_BIGCORE1_CRU_BASE, - 0x300, false); + pr_warn("CRU REGS:\n"); + dump_offset("LPLL", RK3588_LPLL_CON(16), 0x10); + dump_offset("B0PLL", RK3588_B0_PLL_CON(0), 0x10); + dump_offset("B1PLL", RK3588_B1_PLL_CON(8), 0x10); + dump_offset("GPLL", RK3588_PLL_CON(112), 0x10); + dump_offset("CPLL", RK3588_PLL_CON(104), 0x10); + dump_offset("V0PLL", RK3588_PLL_CON(88), 0x10); + dump_offset("AUPLL", RK3588_PLL_CON(96), 0x10); + dump_offset("PPLL", RK3588_PMU_PLL_CON(128), 0x10); + dump_offset("DSUCRU_SEL", RK3588_DSU_CLKSEL_CON(0), 0x20); + dump_offset("DSUCRU_GATE", RK3588_DSU_CLKGATE_CON(0), 0x10); + dump_offset("BIG0CRU_SEL", RK3588_BIGCORE0_CLKSEL_CON(0), 0x10); + dump_offset("BIG0CRU_GATE", RK3588_BIGCORE0_CLKGATE_CON(0), 0x10); + dump_offset("BIG1CRU_SEL", RK3588_BIGCORE1_CLKSEL_CON(0), 0x10); + dump_offset("BIG1CRU_GATE", RK3588_BIGCORE1_CLKGATE_CON(0), 0x10); + dump_offset("CRU_SEL", RK3588_CLKSEL_CON(0), 0x2d0); + dump_offset("CRU_GATE", RK3588_CLKGATE_CON(0), 0x140); + dump_offset("PMUCRU_SEL", RK3588_PMU_CLKSEL_CON(0), 0x50); + dump_offset("PMUCRU_GATE", RK3588_PMU_CLKGATE_CON(0), 0x20); } } From 10019a5beb16dbcbba11fd3fb0be0fdd021ad4db Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Fri, 10 Feb 2023 11:47:59 +0800 Subject: [PATCH 121/258] media: i2c: sensor driver remove not necessary check of fmt_code in enum_frame_interval Signed-off-by: Zefa Chen Change-Id: I2bafbe067054c30cd4e61740365a59d9ff839ae4 --- drivers/media/i2c/ar0230.c | 4 +--- drivers/media/i2c/gc0312.c | 4 +--- drivers/media/i2c/gc0329.c | 4 +--- drivers/media/i2c/gc032a.c | 4 +--- drivers/media/i2c/gc0403.c | 4 +--- drivers/media/i2c/gc08a3.c | 4 +--- drivers/media/i2c/gc2035.c | 4 +--- drivers/media/i2c/gc2145.c | 4 +--- drivers/media/i2c/gc2155.c | 4 +--- drivers/media/i2c/gc2355.c | 4 +--- drivers/media/i2c/gc2375h.c | 4 +--- drivers/media/i2c/gc2385.c | 4 +--- drivers/media/i2c/gc5024.c | 4 +--- drivers/media/i2c/gc5025.c | 4 +--- drivers/media/i2c/gc5035.c | 3 +-- drivers/media/i2c/gc8034.c | 4 +--- drivers/media/i2c/imx214.c | 4 +--- drivers/media/i2c/imx317.c | 4 +--- drivers/media/i2c/imx323.c | 4 +--- drivers/media/i2c/it6616.c | 3 +-- drivers/media/i2c/jx_h62.c | 4 +--- drivers/media/i2c/jx_h65.c | 3 +-- drivers/media/i2c/lt6911uxc.c | 3 +-- drivers/media/i2c/lt6911uxe.c | 3 +-- drivers/media/i2c/lt7911d.c | 3 +-- drivers/media/i2c/lt7911uxc.c | 3 +-- drivers/media/i2c/lt8619c.c | 3 +-- drivers/media/i2c/max96714.c | 3 +-- drivers/media/i2c/max96722.c | 3 +-- drivers/media/i2c/os08a20.c | 4 +--- drivers/media/i2c/ov13850.c | 4 +--- drivers/media/i2c/ov13855.c | 4 +--- drivers/media/i2c/ov16a10.c | 4 +--- drivers/media/i2c/ov2735.c | 4 +--- drivers/media/i2c/ov5648.c | 4 +--- drivers/media/i2c/ov5670.c | 4 +--- drivers/media/i2c/ov5695.c | 4 +--- drivers/media/i2c/ov7750.c | 4 +--- drivers/media/i2c/ov8858.c | 4 +--- drivers/media/i2c/ov9750.c | 4 +--- drivers/media/i2c/rk628/rk628_bt1120_v4l2.c | 3 +-- drivers/media/i2c/rk628/rk628_csi_v4l2.c | 3 +-- drivers/media/i2c/s5k3l6xx.c | 3 +-- drivers/media/i2c/sc031gs.c | 3 +-- drivers/media/i2c/sc2239.c | 3 +-- drivers/media/i2c/tc35874x.c | 3 +-- drivers/media/i2c/thcv244.c | 3 +-- 47 files changed, 47 insertions(+), 124 deletions(-) diff --git a/drivers/media/i2c/ar0230.c b/drivers/media/i2c/ar0230.c index 613ab85bab99..84c2432b4ff0 100644 --- a/drivers/media/i2c/ar0230.c +++ b/drivers/media/i2c/ar0230.c @@ -1309,9 +1309,7 @@ static int ar0230_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != PIX_FORMAT) - return -EINVAL; - + fie->code = PIX_FORMAT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc0312.c b/drivers/media/i2c/gc0312.c index acf52fbbfe5b..6e43407b451e 100644 --- a/drivers/media/i2c/gc0312.c +++ b/drivers/media/i2c/gc0312.c @@ -927,9 +927,7 @@ static int gc0312_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(gc0312_framesizes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_YUYV8_2X8) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_YUYV8_2X8; fie->width = gc0312_framesizes[fie->index].width; fie->height = gc0312_framesizes[fie->index].height; fie->interval = gc0312_framesizes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc0329.c b/drivers/media/i2c/gc0329.c index 266c18ae157a..bd80c67ff93d 100644 --- a/drivers/media/i2c/gc0329.c +++ b/drivers/media/i2c/gc0329.c @@ -903,9 +903,7 @@ static int gc0329_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(gc0329_framesizes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_YUYV8_2X8) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_YUYV8_2X8; fie->width = gc0329_framesizes[fie->index].width; fie->height = gc0329_framesizes[fie->index].height; fie->interval = gc0329_framesizes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc032a.c b/drivers/media/i2c/gc032a.c index 1115d3035300..3cc71568652a 100644 --- a/drivers/media/i2c/gc032a.c +++ b/drivers/media/i2c/gc032a.c @@ -944,9 +944,7 @@ static int gc032a_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(gc032a_framesizes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_YUYV8_2X8) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_YUYV8_2X8; fie->width = gc032a_framesizes[fie->index].width; fie->height = gc032a_framesizes[fie->index].height; fie->interval = gc032a_framesizes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc0403.c b/drivers/media/i2c/gc0403.c index 8e64d5dbc4e6..fa800e9aa2f8 100644 --- a/drivers/media/i2c/gc0403.c +++ b/drivers/media/i2c/gc0403.c @@ -908,9 +908,7 @@ static int gc0403_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SRGGB10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc08a3.c b/drivers/media/i2c/gc08a3.c index 6d701843954f..c98ae8f0144b 100644 --- a/drivers/media/i2c/gc08a3.c +++ b/drivers/media/i2c/gc08a3.c @@ -1700,9 +1700,7 @@ static int gc08a3_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= gc08a3->cfg_num) return -EINVAL; - if (fie->code != GC08A3_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = GC08A3_MEDIA_BUS_FMT; fie->width = gc08a3->support_modes[fie->index].width; fie->height = gc08a3->support_modes[fie->index].height; fie->interval = gc08a3->support_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc2035.c b/drivers/media/i2c/gc2035.c index 706c2ecbc5c8..db3be0d6ce73 100644 --- a/drivers/media/i2c/gc2035.c +++ b/drivers/media/i2c/gc2035.c @@ -1294,9 +1294,7 @@ static int gc2035_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(gc2035_framesizes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_UYVY8_2X8; fie->width = gc2035_framesizes[fie->index].width; fie->height = gc2035_framesizes[fie->index].height; fie->interval = gc2035_framesizes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c index 6857a16e3c33..4875ad533cd2 100644 --- a/drivers/media/i2c/gc2145.c +++ b/drivers/media/i2c/gc2145.c @@ -2672,9 +2672,7 @@ static int gc2145_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= gc2145->cfg_num) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_UYVY8_2X8; fie->width = gc2145->framesize_cfg[fie->index].width; fie->height = gc2145->framesize_cfg[fie->index].height; fie->interval = gc2145->framesize_cfg[fie->index].max_fps; diff --git a/drivers/media/i2c/gc2155.c b/drivers/media/i2c/gc2155.c index 6ede037b9af3..802b1d7821a0 100644 --- a/drivers/media/i2c/gc2155.c +++ b/drivers/media/i2c/gc2155.c @@ -1487,9 +1487,7 @@ static int gc2155_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_UYVY8_2X8; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc2355.c b/drivers/media/i2c/gc2355.c index 3715a39034a6..58bdec9591f6 100644 --- a/drivers/media/i2c/gc2355.c +++ b/drivers/media/i2c/gc2355.c @@ -817,9 +817,7 @@ static int gc2355_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SRGGB10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc2375h.c b/drivers/media/i2c/gc2375h.c index b98a3a053016..3fb7af10069f 100644 --- a/drivers/media/i2c/gc2375h.c +++ b/drivers/media/i2c/gc2375h.c @@ -1000,9 +1000,7 @@ static int gc2375h_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= gc2375h->cfg_num) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SRGGB10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc2385.c b/drivers/media/i2c/gc2385.c index 1e51b346c979..22a88e49a7e0 100644 --- a/drivers/media/i2c/gc2385.c +++ b/drivers/media/i2c/gc2385.c @@ -778,9 +778,7 @@ static int gc2385_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc5024.c b/drivers/media/i2c/gc5024.c index 528c5d6de2e7..fb384ba6e446 100644 --- a/drivers/media/i2c/gc5024.c +++ b/drivers/media/i2c/gc5024.c @@ -901,9 +901,7 @@ static int gc5024_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= gc5024->cfg_num) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc5025.c b/drivers/media/i2c/gc5025.c index be80be415f63..ecf01bab6639 100644 --- a/drivers/media/i2c/gc5025.c +++ b/drivers/media/i2c/gc5025.c @@ -1502,9 +1502,7 @@ static int gc5025_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SRGGB10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/gc5035.c b/drivers/media/i2c/gc5035.c index ee38bcdc3d08..7f97f0ca677c 100644 --- a/drivers/media/i2c/gc5035.c +++ b/drivers/media/i2c/gc5035.c @@ -993,8 +993,7 @@ static int gc5035_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= gc5035->cfg_num) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10) - return -EINVAL; + fie->code = MEDIA_BUS_FMT_SRGGB10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/gc8034.c b/drivers/media/i2c/gc8034.c index 63f46d152699..f2535ddfcddf 100644 --- a/drivers/media/i2c/gc8034.c +++ b/drivers/media/i2c/gc8034.c @@ -2662,9 +2662,7 @@ static int gc8034_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= gc8034->cfg_num) return -EINVAL; - if (fie->code != GC8034_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = GC8034_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 065ae3dfca05..5528f3f4c35b 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -1445,9 +1445,7 @@ static int imx214_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= imx214->cfg_num) return -EINVAL; - if (fie->code != IMX214_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = IMX214_MEDIA_BUS_FMT; fie->width = imx214->support_modes[fie->index].width; fie->height = imx214->support_modes[fie->index].height; fie->interval = imx214->support_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/imx317.c b/drivers/media/i2c/imx317.c index 384b171826e9..dd7ca47c776d 100644 --- a/drivers/media/i2c/imx317.c +++ b/drivers/media/i2c/imx317.c @@ -1178,9 +1178,7 @@ static int imx317_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= imx317->cfg_num) return -EINVAL; - if (fie->code != IMX317_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = IMX317_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/imx323.c b/drivers/media/i2c/imx323.c index b19eead7f828..d226ac631f66 100644 --- a/drivers/media/i2c/imx323.c +++ b/drivers/media/i2c/imx323.c @@ -723,9 +723,7 @@ static int imx323_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != PIX_FORMAT) - return -EINVAL; - + fie->code = PIX_FORMAT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/it6616.c b/drivers/media/i2c/it6616.c index 63e4a5942220..6928a11ac47c 100644 --- a/drivers/media/i2c/it6616.c +++ b/drivers/media/i2c/it6616.c @@ -3776,8 +3776,7 @@ static int it6616_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != IT6616_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = IT6616_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/jx_h62.c b/drivers/media/i2c/jx_h62.c index e108e7a9feae..864114645b6f 100644 --- a/drivers/media/i2c/jx_h62.c +++ b/drivers/media/i2c/jx_h62.c @@ -797,9 +797,7 @@ static int jx_h62_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != JX_H62_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = JX_H62_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/jx_h65.c b/drivers/media/i2c/jx_h65.c index b77e135826d2..d4258d9f4f70 100644 --- a/drivers/media/i2c/jx_h65.c +++ b/drivers/media/i2c/jx_h65.c @@ -895,8 +895,7 @@ static int jx_h65_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/lt6911uxc.c b/drivers/media/i2c/lt6911uxc.c index 07ada7454eca..02af340a4f15 100644 --- a/drivers/media/i2c/lt6911uxc.c +++ b/drivers/media/i2c/lt6911uxc.c @@ -825,8 +825,7 @@ static int lt6911uxc_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != LT6911UXC_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = LT6911UXC_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/lt6911uxe.c b/drivers/media/i2c/lt6911uxe.c index baf59ea99fff..221d96ba09fd 100644 --- a/drivers/media/i2c/lt6911uxe.c +++ b/drivers/media/i2c/lt6911uxe.c @@ -1187,8 +1187,7 @@ static int lt6911uxe_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= lt6911uxe->cfg_num) return -EINVAL; - if (fie->code != LT6911UXE_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = LT6911UXE_MEDIA_BUS_FMT; fie->width = lt6911uxe->support_modes[fie->index].width; fie->height = lt6911uxe->support_modes[fie->index].height; diff --git a/drivers/media/i2c/lt7911d.c b/drivers/media/i2c/lt7911d.c index f2a479946174..f8d3c5b75a58 100644 --- a/drivers/media/i2c/lt7911d.c +++ b/drivers/media/i2c/lt7911d.c @@ -820,8 +820,7 @@ static int lt7911d_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != LT7911D_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = LT7911D_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/lt7911uxc.c b/drivers/media/i2c/lt7911uxc.c index df91719199eb..fc9a7f45fd97 100644 --- a/drivers/media/i2c/lt7911uxc.c +++ b/drivers/media/i2c/lt7911uxc.c @@ -962,8 +962,7 @@ static int lt7911uxc_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= lt7911uxc->cfg_num) return -EINVAL; - if (fie->code != LT7911UXC_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = LT7911UXC_MEDIA_BUS_FMT; fie->width = lt7911uxc->support_modes[fie->index].width; fie->height = lt7911uxc->support_modes[fie->index].height; diff --git a/drivers/media/i2c/lt8619c.c b/drivers/media/i2c/lt8619c.c index 193a61bbeb03..8743797345ba 100644 --- a/drivers/media/i2c/lt8619c.c +++ b/drivers/media/i2c/lt8619c.c @@ -1223,8 +1223,7 @@ static int lt8619c_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8) - return -EINVAL; + fie->code = MEDIA_BUS_FMT_UYVY8_2X8; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/max96714.c b/drivers/media/i2c/max96714.c index 8c156d8d093f..8933b9aeee13 100644 --- a/drivers/media/i2c/max96714.c +++ b/drivers/media/i2c/max96714.c @@ -764,8 +764,7 @@ static int max96714_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MAX96714_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = MAX96714_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/max96722.c b/drivers/media/i2c/max96722.c index 0ad4336eb1b3..a5a054aef352 100644 --- a/drivers/media/i2c/max96722.c +++ b/drivers/media/i2c/max96722.c @@ -840,8 +840,7 @@ static int max96722_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MAX96722_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = MAX96722_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/os08a20.c b/drivers/media/i2c/os08a20.c index 38d67aa8e03c..02e3d097852a 100644 --- a/drivers/media/i2c/os08a20.c +++ b/drivers/media/i2c/os08a20.c @@ -1107,9 +1107,7 @@ static int os08a20_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= os08a20->cfg_num) return -EINVAL; - if (fie->code != OS08A20_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = OS08A20_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov13850.c b/drivers/media/i2c/ov13850.c index f541f0a7a50a..7727d7b03de4 100644 --- a/drivers/media/i2c/ov13850.c +++ b/drivers/media/i2c/ov13850.c @@ -1238,9 +1238,7 @@ static int ov13850_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov13855.c b/drivers/media/i2c/ov13855.c index 5af63dca8bcc..f087ef420e95 100644 --- a/drivers/media/i2c/ov13855.c +++ b/drivers/media/i2c/ov13855.c @@ -1561,9 +1561,7 @@ static int ov13855_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != OV13855_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = OV13855_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov16a10.c b/drivers/media/i2c/ov16a10.c index eb54a74e51a8..ad010285cd54 100644 --- a/drivers/media/i2c/ov16a10.c +++ b/drivers/media/i2c/ov16a10.c @@ -1601,9 +1601,7 @@ static int ov16a10_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != OV16A10_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = OV16A10_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov2735.c b/drivers/media/i2c/ov2735.c index c91fe0c6ff8f..0eae7fa1404f 100644 --- a/drivers/media/i2c/ov2735.c +++ b/drivers/media/i2c/ov2735.c @@ -836,9 +836,7 @@ static int ov2735_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov5648.c b/drivers/media/i2c/ov5648.c index bc2a41d9f82a..67c63f0a8375 100644 --- a/drivers/media/i2c/ov5648.c +++ b/drivers/media/i2c/ov5648.c @@ -1082,9 +1082,7 @@ static int ov5648_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ov5648->cfg_num) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov5670.c b/drivers/media/i2c/ov5670.c index 2038a766d36b..16425ffff6a0 100644 --- a/drivers/media/i2c/ov5670.c +++ b/drivers/media/i2c/ov5670.c @@ -1398,9 +1398,7 @@ static int ov5670_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ov5670->cfg_num) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov5695.c b/drivers/media/i2c/ov5695.c index f4b1409f8cf7..61bda949044a 100644 --- a/drivers/media/i2c/ov5695.c +++ b/drivers/media/i2c/ov5695.c @@ -1154,9 +1154,7 @@ static int ov5695_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov7750.c b/drivers/media/i2c/ov7750.c index 593690bcb0a7..bc7c23603363 100644 --- a/drivers/media/i2c/ov7750.c +++ b/drivers/media/i2c/ov7750.c @@ -941,9 +941,7 @@ static int ov7750_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov8858.c b/drivers/media/i2c/ov8858.c index 82926805f14e..f016f9e6af08 100644 --- a/drivers/media/i2c/ov8858.c +++ b/drivers/media/i2c/ov8858.c @@ -2854,9 +2854,7 @@ static int ov8858_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ov8858->cfg_num) return -EINVAL; - if (fie->code != OV8858_MEDIA_BUS_FMT) - return -EINVAL; - + fie->code = OV8858_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/ov9750.c b/drivers/media/i2c/ov9750.c index 922d458dfa4c..e7c5f8bf69e6 100644 --- a/drivers/media/i2c/ov9750.c +++ b/drivers/media/i2c/ov9750.c @@ -927,9 +927,7 @@ static int ov9750_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10) - return -EINVAL; - + fie->code = MEDIA_BUS_FMT_SBGGR10_1X10; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; fie->interval = supported_modes[fie->index].max_fps; diff --git a/drivers/media/i2c/rk628/rk628_bt1120_v4l2.c b/drivers/media/i2c/rk628/rk628_bt1120_v4l2.c index 1d9737740a9b..e427176a54b3 100644 --- a/drivers/media/i2c/rk628/rk628_bt1120_v4l2.c +++ b/drivers/media/i2c/rk628/rk628_bt1120_v4l2.c @@ -1290,8 +1290,7 @@ static int rk628_bt1120_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8) - return -EINVAL; + fie->code = MEDIA_BUS_FMT_UYVY8_2X8; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/rk628/rk628_csi_v4l2.c b/drivers/media/i2c/rk628/rk628_csi_v4l2.c index f21863e61553..d8a39ca5b382 100644 --- a/drivers/media/i2c/rk628/rk628_csi_v4l2.c +++ b/drivers/media/i2c/rk628/rk628_csi_v4l2.c @@ -1520,8 +1520,7 @@ static int rk628_csi_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != csi->plat_data->bus_fmt) - return -EINVAL; + fie->code = csi->plat_data->bus_fmt; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/s5k3l6xx.c b/drivers/media/i2c/s5k3l6xx.c index 118b93550c18..950d9ac2ce83 100644 --- a/drivers/media/i2c/s5k3l6xx.c +++ b/drivers/media/i2c/s5k3l6xx.c @@ -1064,8 +1064,7 @@ static int s5k3l6xx_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != S5K3L6XX_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = S5K3L6XX_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/sc031gs.c b/drivers/media/i2c/sc031gs.c index 854c2a0f9ee7..1901787d7ac2 100644 --- a/drivers/media/i2c/sc031gs.c +++ b/drivers/media/i2c/sc031gs.c @@ -945,8 +945,7 @@ static int sc031gs_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != PIX_FORMAT) - return -EINVAL; + fie->code = PIX_FORMAT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/sc2239.c b/drivers/media/i2c/sc2239.c index ddc3a90a073e..2e49ad98f942 100644 --- a/drivers/media/i2c/sc2239.c +++ b/drivers/media/i2c/sc2239.c @@ -875,8 +875,7 @@ static int sc2239_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != PIX_FORMAT) - return -EINVAL; + fie->code = PIX_FORMAT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/tc35874x.c b/drivers/media/i2c/tc35874x.c index 21da1e5c3584..692c8395db54 100644 --- a/drivers/media/i2c/tc35874x.c +++ b/drivers/media/i2c/tc35874x.c @@ -1748,8 +1748,7 @@ static int tc35874x_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8) - return -EINVAL; + fie->code = MEDIA_BUS_FMT_UYVY8_2X8; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; diff --git a/drivers/media/i2c/thcv244.c b/drivers/media/i2c/thcv244.c index 8837d274c620..e915efadccd2 100644 --- a/drivers/media/i2c/thcv244.c +++ b/drivers/media/i2c/thcv244.c @@ -1002,8 +1002,7 @@ static int thcv244_enum_frame_interval(struct v4l2_subdev *sd, if (fie->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fie->code != THCV244_MEDIA_BUS_FMT) - return -EINVAL; + fie->code = THCV244_MEDIA_BUS_FMT; fie->width = supported_modes[fie->index].width; fie->height = supported_modes[fie->index].height; From e9a0711b53a638e8a5d9f0f4bf1234a4bb61f420 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Fri, 10 Feb 2023 12:57:14 +0800 Subject: [PATCH 122/258] media: i2c: sensor driver remove mutex lock in g_frame_interval g_frame_interval may be called in interrupt function [(__mutex_lock.constprop.10) from [] (gc2053_g_frame_interval+0x13/0x2a [gc2053]) [(rkisp_rockit_ctrl_fps [video rkisp]) from [] (mi_frame_start+0x19/0xa8 [video rkisp]) [(mi_frame_start [video rkisp]) from [] (rkisp_stream_frame_start+0x31/0x3e [video rkisp]) [(rkisp_stream_frame_start [video rkisp]) from [] (rkisp_trioger_read_back+0x1bd/0x710 [video rkis]) [(rkisp_trigger_read_back [video rkisp]) from [] (rkisp_rdbk_trigger_event+0xbb/0x2a8 [video rkisp]) [(rkisp_rdbk_trigger_event [video rkisp]) from [] (tasklet_action_common.constprop.3+0x3d/0x58) [](__do_softirq) from [] (__irq_exit rcu+0x31/0x68) Signed-off-by: Zefa Chen Change-Id: I4edd1a0600fa8c6a09133c255da4a957022babdf --- drivers/media/i2c/ar0230.c | 2 -- drivers/media/i2c/gc02m2.c | 2 -- drivers/media/i2c/gc0329.c | 2 -- drivers/media/i2c/gc0403.c | 2 -- drivers/media/i2c/gc08a3.c | 2 -- drivers/media/i2c/gc1084.c | 2 -- drivers/media/i2c/gc2035.c | 2 -- drivers/media/i2c/gc2053.c | 2 -- drivers/media/i2c/gc2093.c | 2 -- drivers/media/i2c/gc2145.c | 2 -- drivers/media/i2c/gc2155.c | 2 -- drivers/media/i2c/gc2355.c | 2 -- drivers/media/i2c/gc2375h.c | 2 -- drivers/media/i2c/gc2385.c | 2 -- drivers/media/i2c/gc3003.c | 2 -- drivers/media/i2c/gc4023.c | 2 -- drivers/media/i2c/gc4653.c | 2 -- drivers/media/i2c/gc4663.c | 2 -- drivers/media/i2c/gc4c33.c | 2 -- drivers/media/i2c/gc5024.c | 2 -- drivers/media/i2c/gc5025.c | 2 -- drivers/media/i2c/gc5035.c | 2 -- drivers/media/i2c/gc8034.c | 2 -- drivers/media/i2c/imx214.c | 2 -- drivers/media/i2c/imx258.c | 2 -- drivers/media/i2c/imx307.c | 2 -- drivers/media/i2c/imx317.c | 2 -- drivers/media/i2c/imx323.c | 2 -- drivers/media/i2c/imx327.c | 2 -- drivers/media/i2c/imx334.c | 2 -- drivers/media/i2c/imx335.c | 2 -- drivers/media/i2c/imx347.c | 2 -- drivers/media/i2c/imx378.c | 2 -- drivers/media/i2c/imx415.c | 2 -- drivers/media/i2c/imx464.c | 2 -- drivers/media/i2c/imx577.c | 2 -- drivers/media/i2c/imx586.c | 2 -- drivers/media/i2c/os02g10.c | 2 -- drivers/media/i2c/os03b10.c | 2 -- drivers/media/i2c/os04a10.c | 2 -- drivers/media/i2c/os05a20.c | 2 -- drivers/media/i2c/os08a20.c | 2 -- drivers/media/i2c/ov02b10.c | 2 -- drivers/media/i2c/ov02k10.c | 2 -- drivers/media/i2c/ov12d2q.c | 2 -- drivers/media/i2c/ov13850.c | 2 -- drivers/media/i2c/ov13855.c | 2 -- drivers/media/i2c/ov16a10.c | 2 -- drivers/media/i2c/ov2718.c | 2 -- drivers/media/i2c/ov2775.c | 2 -- drivers/media/i2c/ov4686.c | 2 -- drivers/media/i2c/ov4688.c | 2 -- drivers/media/i2c/ov4689.c | 2 -- drivers/media/i2c/ov50c40.c | 2 -- drivers/media/i2c/ov5648.c | 2 -- drivers/media/i2c/ov5695.c | 2 -- drivers/media/i2c/ov7251.c | 2 -- drivers/media/i2c/ov8858.c | 2 -- drivers/media/i2c/ov9281.c | 2 -- drivers/media/i2c/ov9650.c | 2 -- drivers/media/i2c/ov9750.c | 2 -- drivers/media/i2c/s5kjn1.c | 2 -- drivers/media/i2c/sc2336.c | 2 -- 63 files changed, 126 deletions(-) diff --git a/drivers/media/i2c/ar0230.c b/drivers/media/i2c/ar0230.c index 84c2432b4ff0..2abbb46d966e 100644 --- a/drivers/media/i2c/ar0230.c +++ b/drivers/media/i2c/ar0230.c @@ -1144,9 +1144,7 @@ static int ar0230_g_frame_interval(struct v4l2_subdev *sd, struct ar0230 *ar0230 = to_ar0230(sd); const struct ar0230_mode *mode = ar0230->cur_mode; - mutex_lock(&ar0230->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ar0230->mutex); return 0; } diff --git a/drivers/media/i2c/gc02m2.c b/drivers/media/i2c/gc02m2.c index 7181832def38..ef0a135f5736 100644 --- a/drivers/media/i2c/gc02m2.c +++ b/drivers/media/i2c/gc02m2.c @@ -601,9 +601,7 @@ static int gc02m2_g_frame_interval(struct v4l2_subdev *sd, struct gc02m2 *gc02m2 = to_gc02m2(sd); const struct gc02m2_mode *mode = gc02m2->cur_mode; - mutex_lock(&gc02m2->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc02m2->mutex); return 0; } diff --git a/drivers/media/i2c/gc0329.c b/drivers/media/i2c/gc0329.c index bd80c67ff93d..edc0d424c1c2 100644 --- a/drivers/media/i2c/gc0329.c +++ b/drivers/media/i2c/gc0329.c @@ -858,9 +858,7 @@ static int gc0329_g_frame_interval(struct v4l2_subdev *sd, { struct gc0329 *gc0329 = to_gc0329(sd); - mutex_lock(&gc0329->lock); fi->interval = gc0329->frame_size->max_fps; - mutex_unlock(&gc0329->lock); return 0; } diff --git a/drivers/media/i2c/gc0403.c b/drivers/media/i2c/gc0403.c index fa800e9aa2f8..8556f70b3be4 100644 --- a/drivers/media/i2c/gc0403.c +++ b/drivers/media/i2c/gc0403.c @@ -614,9 +614,7 @@ static int gc0403_g_frame_interval(struct v4l2_subdev *sd, struct gc0403 *gc0403 = to_gc0403(sd); const struct gc0403_mode *mode = gc0403->cur_mode; - mutex_lock(&gc0403->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc0403->mutex); return 0; } diff --git a/drivers/media/i2c/gc08a3.c b/drivers/media/i2c/gc08a3.c index c98ae8f0144b..09c1996f6679 100644 --- a/drivers/media/i2c/gc08a3.c +++ b/drivers/media/i2c/gc08a3.c @@ -1303,9 +1303,7 @@ static int gc08a3_g_frame_interval(struct v4l2_subdev *sd, struct gc08a3 *gc08a3 = to_gc08a3(sd); const struct gc08a3_mode *mode = gc08a3->cur_mode; - mutex_lock(&gc08a3->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc08a3->mutex); return 0; } diff --git a/drivers/media/i2c/gc1084.c b/drivers/media/i2c/gc1084.c index d91da4fb401d..db95d1593ef4 100644 --- a/drivers/media/i2c/gc1084.c +++ b/drivers/media/i2c/gc1084.c @@ -839,9 +839,7 @@ static int gc1084_g_frame_interval(struct v4l2_subdev *sd, struct gc1084 *gc1084 = to_gc1084(sd); const struct gc1084_mode *mode = gc1084->cur_mode; - mutex_lock(&gc1084->lock); fi->interval = mode->max_fps; - mutex_unlock(&gc1084->lock); return 0; } diff --git a/drivers/media/i2c/gc2035.c b/drivers/media/i2c/gc2035.c index db3be0d6ce73..5f8e2c8c6756 100644 --- a/drivers/media/i2c/gc2035.c +++ b/drivers/media/i2c/gc2035.c @@ -1166,9 +1166,7 @@ static int gc2035_g_frame_interval(struct v4l2_subdev *sd, { struct gc2035 *gc2035 = to_gc2035(sd); - mutex_lock(&gc2035->lock); fi->interval = gc2035->frame_size->max_fps; - mutex_unlock(&gc2035->lock); return 0; } diff --git a/drivers/media/i2c/gc2053.c b/drivers/media/i2c/gc2053.c index 44fa3826c79b..a5074362277d 100644 --- a/drivers/media/i2c/gc2053.c +++ b/drivers/media/i2c/gc2053.c @@ -1059,9 +1059,7 @@ static int gc2053_g_frame_interval(struct v4l2_subdev *sd, struct gc2053 *gc2053 = to_gc2053(sd); const struct gc2053_mode *mode = gc2053->cur_mode; - mutex_lock(&gc2053->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc2053->mutex); return 0; } diff --git a/drivers/media/i2c/gc2093.c b/drivers/media/i2c/gc2093.c index 8082afcc91cd..f7b6f452edc5 100644 --- a/drivers/media/i2c/gc2093.c +++ b/drivers/media/i2c/gc2093.c @@ -1152,9 +1152,7 @@ static int gc2093_g_frame_interval(struct v4l2_subdev *sd, struct gc2093 *gc2093 = to_gc2093(sd); const struct gc2093_mode *mode = gc2093->cur_mode; - mutex_lock(&gc2093->lock); fi->interval = mode->max_fps; - mutex_unlock(&gc2093->lock); return 0; } diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c index 4875ad533cd2..9eff822d51d6 100644 --- a/drivers/media/i2c/gc2145.c +++ b/drivers/media/i2c/gc2145.c @@ -2483,9 +2483,7 @@ static int gc2145_g_frame_interval(struct v4l2_subdev *sd, { struct gc2145 *gc2145 = to_gc2145(sd); - mutex_lock(&gc2145->lock); fi->interval = gc2145->frame_size->max_fps; - mutex_unlock(&gc2145->lock); return 0; } diff --git a/drivers/media/i2c/gc2155.c b/drivers/media/i2c/gc2155.c index 802b1d7821a0..c8f8ed84cf1d 100644 --- a/drivers/media/i2c/gc2155.c +++ b/drivers/media/i2c/gc2155.c @@ -1399,9 +1399,7 @@ static int gc2155_g_frame_interval(struct v4l2_subdev *sd, { struct gc2155 *gc2155 = to_gc2155(sd); - mutex_lock(&gc2155->mutex); fi->interval = gc2155->cur_mode->max_fps; - mutex_unlock(&gc2155->mutex); return 0; } diff --git a/drivers/media/i2c/gc2355.c b/drivers/media/i2c/gc2355.c index 58bdec9591f6..1fca9ffffd90 100644 --- a/drivers/media/i2c/gc2355.c +++ b/drivers/media/i2c/gc2355.c @@ -519,9 +519,7 @@ static int gc2355_g_frame_interval(struct v4l2_subdev *sd, struct gc2355 *gc2355 = to_gc2355(sd); const struct gc2355_mode *mode = gc2355->cur_mode; - mutex_lock(&gc2355->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc2355->mutex); return 0; } diff --git a/drivers/media/i2c/gc2375h.c b/drivers/media/i2c/gc2375h.c index 3fb7af10069f..843b68a968a7 100644 --- a/drivers/media/i2c/gc2375h.c +++ b/drivers/media/i2c/gc2375h.c @@ -653,9 +653,7 @@ static int gc2375h_g_frame_interval(struct v4l2_subdev *sd, struct gc2375h *gc2375h = to_gc2375h(sd); const struct gc2375h_mode *mode = gc2375h->cur_mode; - mutex_lock(&gc2375h->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc2375h->mutex); return 0; } diff --git a/drivers/media/i2c/gc2385.c b/drivers/media/i2c/gc2385.c index 22a88e49a7e0..c5ab56f9cd46 100644 --- a/drivers/media/i2c/gc2385.c +++ b/drivers/media/i2c/gc2385.c @@ -443,9 +443,7 @@ static int gc2385_g_frame_interval(struct v4l2_subdev *sd, struct gc2385 *gc2385 = to_gc2385(sd); const struct gc2385_mode *mode = gc2385->cur_mode; - mutex_lock(&gc2385->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc2385->mutex); return 0; } diff --git a/drivers/media/i2c/gc3003.c b/drivers/media/i2c/gc3003.c index 6bfe04d5acc1..c3f46aa7537e 100644 --- a/drivers/media/i2c/gc3003.c +++ b/drivers/media/i2c/gc3003.c @@ -1055,9 +1055,7 @@ static int gc3003_g_frame_interval(struct v4l2_subdev *sd, struct gc3003 *gc3003 = to_gc3003(sd); const struct gc3003_mode *mode = gc3003->cur_mode; - mutex_lock(&gc3003->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc3003->mutex); return 0; } diff --git a/drivers/media/i2c/gc4023.c b/drivers/media/i2c/gc4023.c index c472a8ad03e5..accc8664f4cc 100644 --- a/drivers/media/i2c/gc4023.c +++ b/drivers/media/i2c/gc4023.c @@ -720,9 +720,7 @@ static int gc4023_g_frame_interval(struct v4l2_subdev *sd, struct gc4023 *gc4023 = to_gc4023(sd); const struct gc4023_mode *mode = gc4023->cur_mode; - mutex_lock(&gc4023->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc4023->mutex); return 0; } diff --git a/drivers/media/i2c/gc4653.c b/drivers/media/i2c/gc4653.c index d95b7c7077f2..64d0d7f4cd11 100644 --- a/drivers/media/i2c/gc4653.c +++ b/drivers/media/i2c/gc4653.c @@ -664,9 +664,7 @@ static int gc4653_g_frame_interval(struct v4l2_subdev *sd, struct gc4653 *gc4653 = to_gc4653(sd); const struct gc4653_mode *mode = gc4653->cur_mode; - mutex_lock(&gc4653->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc4653->mutex); return 0; } diff --git a/drivers/media/i2c/gc4663.c b/drivers/media/i2c/gc4663.c index 912a1971d880..1b60b83dd172 100644 --- a/drivers/media/i2c/gc4663.c +++ b/drivers/media/i2c/gc4663.c @@ -999,9 +999,7 @@ static int gc4663_g_frame_interval(struct v4l2_subdev *sd, struct gc4663 *gc4663 = to_gc4663(sd); const struct gc4663_mode *mode = gc4663->cur_mode; - mutex_lock(&gc4663->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc4663->mutex); return 0; } diff --git a/drivers/media/i2c/gc4c33.c b/drivers/media/i2c/gc4c33.c index 2b1563194b33..02ba9d738dd1 100644 --- a/drivers/media/i2c/gc4c33.c +++ b/drivers/media/i2c/gc4c33.c @@ -1510,9 +1510,7 @@ static int gc4c33_g_frame_interval(struct v4l2_subdev *sd, struct gc4c33 *gc4c33 = to_gc4c33(sd); const struct gc4c33_mode *mode = gc4c33->cur_mode; - mutex_lock(&gc4c33->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc4c33->mutex); return 0; } diff --git a/drivers/media/i2c/gc5024.c b/drivers/media/i2c/gc5024.c index fb384ba6e446..d0d81eda3945 100644 --- a/drivers/media/i2c/gc5024.c +++ b/drivers/media/i2c/gc5024.c @@ -541,9 +541,7 @@ static int gc5024_g_frame_interval(struct v4l2_subdev *sd, struct gc5024 *gc5024 = to_gc5024(sd); const struct gc5024_mode *mode = gc5024->cur_mode; - mutex_lock(&gc5024->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc5024->mutex); return 0; } diff --git a/drivers/media/i2c/gc5025.c b/drivers/media/i2c/gc5025.c index ecf01bab6639..1d3b4c035bdb 100644 --- a/drivers/media/i2c/gc5025.c +++ b/drivers/media/i2c/gc5025.c @@ -544,9 +544,7 @@ static int gc5025_g_frame_interval(struct v4l2_subdev *sd, struct gc5025 *gc5025 = to_gc5025(sd); const struct gc5025_mode *mode = gc5025->cur_mode; - mutex_lock(&gc5025->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc5025->mutex); return 0; } diff --git a/drivers/media/i2c/gc5035.c b/drivers/media/i2c/gc5035.c index 7f97f0ca677c..9798b3c2a484 100644 --- a/drivers/media/i2c/gc5035.c +++ b/drivers/media/i2c/gc5035.c @@ -609,9 +609,7 @@ static int gc5035_g_frame_interval(struct v4l2_subdev *sd, struct gc5035 *gc5035 = to_gc5035(sd); const struct gc5035_mode *mode = gc5035->cur_mode; - mutex_lock(&gc5035->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc5035->mutex); return 0; } diff --git a/drivers/media/i2c/gc8034.c b/drivers/media/i2c/gc8034.c index f2535ddfcddf..2c1dd377595a 100644 --- a/drivers/media/i2c/gc8034.c +++ b/drivers/media/i2c/gc8034.c @@ -1418,9 +1418,7 @@ static int gc8034_g_frame_interval(struct v4l2_subdev *sd, struct gc8034 *gc8034 = to_gc8034(sd); const struct gc8034_mode *mode = gc8034->cur_mode; - mutex_lock(&gc8034->mutex); fi->interval = mode->max_fps; - mutex_unlock(&gc8034->mutex); return 0; } diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c index 5528f3f4c35b..b64fe65d0ca3 100644 --- a/drivers/media/i2c/imx214.c +++ b/drivers/media/i2c/imx214.c @@ -872,9 +872,7 @@ static int imx214_g_frame_interval(struct v4l2_subdev *sd, struct imx214 *imx214 = to_imx214(sd); const struct imx214_mode *mode = imx214->cur_mode; - mutex_lock(&imx214->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx214->mutex); return 0; } diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c index 67c7c497649a..9ab108819ebd 100644 --- a/drivers/media/i2c/imx258.c +++ b/drivers/media/i2c/imx258.c @@ -960,9 +960,7 @@ static int imx258_g_frame_interval(struct v4l2_subdev *sd, struct imx258 *imx258 = to_imx258(sd); const struct imx258_mode *mode = imx258->cur_mode; - mutex_lock(&imx258->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx258->mutex); return 0; } diff --git a/drivers/media/i2c/imx307.c b/drivers/media/i2c/imx307.c index 1f0b7a9027fb..c0af3ad14f22 100644 --- a/drivers/media/i2c/imx307.c +++ b/drivers/media/i2c/imx307.c @@ -1187,9 +1187,7 @@ static int imx307_g_frame_interval(struct v4l2_subdev *sd, struct imx307 *imx307 = to_imx307(sd); const struct imx307_mode *mode = imx307->cur_mode; - mutex_lock(&imx307->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx307->mutex); return 0; } diff --git a/drivers/media/i2c/imx317.c b/drivers/media/i2c/imx317.c index dd7ca47c776d..a34e6a592d87 100644 --- a/drivers/media/i2c/imx317.c +++ b/drivers/media/i2c/imx317.c @@ -845,9 +845,7 @@ static int imx317_g_frame_interval(struct v4l2_subdev *sd, struct imx317 *imx317 = to_imx317(sd); const struct imx317_mode *mode = imx317->cur_mode; - mutex_lock(&imx317->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx317->mutex); return 0; } diff --git a/drivers/media/i2c/imx323.c b/drivers/media/i2c/imx323.c index d226ac631f66..7ce08567bc8b 100644 --- a/drivers/media/i2c/imx323.c +++ b/drivers/media/i2c/imx323.c @@ -558,9 +558,7 @@ static int imx323_g_frame_interval(struct v4l2_subdev *sd, struct imx323 *imx323 = to_imx323(sd); const struct imx323_mode *mode = imx323->cur_mode; - mutex_lock(&imx323->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx323->mutex); return 0; } diff --git a/drivers/media/i2c/imx327.c b/drivers/media/i2c/imx327.c index c69feba7f1ae..41875c6d2579 100644 --- a/drivers/media/i2c/imx327.c +++ b/drivers/media/i2c/imx327.c @@ -865,9 +865,7 @@ static int imx327_g_frame_interval(struct v4l2_subdev *sd, struct imx327 *imx327 = to_imx327(sd); const struct imx327_mode *mode = imx327->cur_mode; - mutex_lock(&imx327->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx327->mutex); return 0; } diff --git a/drivers/media/i2c/imx334.c b/drivers/media/i2c/imx334.c index 1e2792aef397..bcf666d54b6c 100644 --- a/drivers/media/i2c/imx334.c +++ b/drivers/media/i2c/imx334.c @@ -843,9 +843,7 @@ static int imx334_g_frame_interval(struct v4l2_subdev *sd, struct imx334 *imx334 = to_imx334(sd); const struct imx334_mode *mode = imx334->cur_mode; - mutex_lock(&imx334->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx334->mutex); return 0; } diff --git a/drivers/media/i2c/imx335.c b/drivers/media/i2c/imx335.c index e741c52b9bfd..717bce3cacda 100644 --- a/drivers/media/i2c/imx335.c +++ b/drivers/media/i2c/imx335.c @@ -808,9 +808,7 @@ static int imx335_g_frame_interval(struct v4l2_subdev *sd, struct imx335 *imx335 = to_imx335(sd); const struct imx335_mode *mode = imx335->cur_mode; - mutex_lock(&imx335->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx335->mutex); return 0; } diff --git a/drivers/media/i2c/imx347.c b/drivers/media/i2c/imx347.c index d2afb7051bbd..333e738b588c 100644 --- a/drivers/media/i2c/imx347.c +++ b/drivers/media/i2c/imx347.c @@ -1013,9 +1013,7 @@ static int imx347_g_frame_interval(struct v4l2_subdev *sd, struct imx347 *imx347 = to_imx347(sd); const struct imx347_mode *mode = imx347->cur_mode; - mutex_lock(&imx347->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx347->mutex); return 0; } diff --git a/drivers/media/i2c/imx378.c b/drivers/media/i2c/imx378.c index 967d503dbcb1..c69d38142d22 100644 --- a/drivers/media/i2c/imx378.c +++ b/drivers/media/i2c/imx378.c @@ -2083,9 +2083,7 @@ static int imx378_g_frame_interval(struct v4l2_subdev *sd, struct imx378 *imx378 = to_imx378(sd); const struct imx378_mode *mode = imx378->cur_mode; - mutex_lock(&imx378->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx378->mutex); return 0; } diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c index af500917c8ef..cda7a78b4ef4 100644 --- a/drivers/media/i2c/imx415.c +++ b/drivers/media/i2c/imx415.c @@ -1216,9 +1216,7 @@ static int imx415_g_frame_interval(struct v4l2_subdev *sd, struct imx415 *imx415 = to_imx415(sd); const struct imx415_mode *mode = imx415->cur_mode; - mutex_lock(&imx415->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx415->mutex); return 0; } diff --git a/drivers/media/i2c/imx464.c b/drivers/media/i2c/imx464.c index 8cfae0d9c9f7..10674eace047 100644 --- a/drivers/media/i2c/imx464.c +++ b/drivers/media/i2c/imx464.c @@ -1686,9 +1686,7 @@ static int IMX464_g_frame_interval(struct v4l2_subdev *sd, struct IMX464 *IMX464 = to_IMX464(sd); const struct IMX464_mode *mode = IMX464->cur_mode; - mutex_lock(&IMX464->mutex); fi->interval = mode->max_fps; - mutex_unlock(&IMX464->mutex); return 0; } diff --git a/drivers/media/i2c/imx577.c b/drivers/media/i2c/imx577.c index 3fc6e38443a9..0d4eca4ef866 100644 --- a/drivers/media/i2c/imx577.c +++ b/drivers/media/i2c/imx577.c @@ -1268,9 +1268,7 @@ static int imx577_g_frame_interval(struct v4l2_subdev *sd, struct imx577 *imx577 = to_imx577(sd); const struct imx577_mode *mode = imx577->cur_mode; - mutex_lock(&imx577->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx577->mutex); return 0; } diff --git a/drivers/media/i2c/imx586.c b/drivers/media/i2c/imx586.c index 594eee0b6836..c0808d0c5962 100644 --- a/drivers/media/i2c/imx586.c +++ b/drivers/media/i2c/imx586.c @@ -1133,9 +1133,7 @@ static int imx586_g_frame_interval(struct v4l2_subdev *sd, struct imx586 *imx586 = to_imx586(sd); const struct imx586_mode *mode = imx586->cur_mode; - mutex_lock(&imx586->mutex); fi->interval = mode->max_fps; - mutex_unlock(&imx586->mutex); return 0; } diff --git a/drivers/media/i2c/os02g10.c b/drivers/media/i2c/os02g10.c index 21af8928f665..f7dbb7905cda 100644 --- a/drivers/media/i2c/os02g10.c +++ b/drivers/media/i2c/os02g10.c @@ -525,9 +525,7 @@ static int os02g10_g_frame_interval(struct v4l2_subdev *sd, struct os02g10 *os02g10 = to_os02g10(sd); const struct os02g10_mode *mode = os02g10->cur_mode; - mutex_lock(&os02g10->mutex); fi->interval = mode->max_fps; - mutex_unlock(&os02g10->mutex); return 0; } diff --git a/drivers/media/i2c/os03b10.c b/drivers/media/i2c/os03b10.c index a851a1519f2d..6edf07372b5f 100644 --- a/drivers/media/i2c/os03b10.c +++ b/drivers/media/i2c/os03b10.c @@ -533,9 +533,7 @@ static int os03b10_g_frame_interval(struct v4l2_subdev *sd, struct os03b10 *os03b10 = to_os03b10(sd); const struct os03b10_mode *mode = os03b10->cur_mode; - mutex_lock(&os03b10->mutex); fi->interval = mode->max_fps; - mutex_unlock(&os03b10->mutex); return 0; } diff --git a/drivers/media/i2c/os04a10.c b/drivers/media/i2c/os04a10.c index 5bd509f8e025..19662b3b94cb 100644 --- a/drivers/media/i2c/os04a10.c +++ b/drivers/media/i2c/os04a10.c @@ -1567,9 +1567,7 @@ static int os04a10_g_frame_interval(struct v4l2_subdev *sd, struct os04a10 *os04a10 = to_os04a10(sd); const struct os04a10_mode *mode = os04a10->cur_mode; - mutex_lock(&os04a10->mutex); fi->interval = mode->max_fps; - mutex_unlock(&os04a10->mutex); return 0; } diff --git a/drivers/media/i2c/os05a20.c b/drivers/media/i2c/os05a20.c index b47a0fb8a4fc..f39981400c9f 100644 --- a/drivers/media/i2c/os05a20.c +++ b/drivers/media/i2c/os05a20.c @@ -920,9 +920,7 @@ static int os05a20_g_frame_interval(struct v4l2_subdev *sd, struct os05a20 *os05a20 = to_os05a20(sd); const struct os05a20_mode *mode = os05a20->cur_mode; - mutex_lock(&os05a20->mutex); fi->interval = mode->max_fps; - mutex_unlock(&os05a20->mutex); return 0; } diff --git a/drivers/media/i2c/os08a20.c b/drivers/media/i2c/os08a20.c index 02e3d097852a..3194a613a1ad 100644 --- a/drivers/media/i2c/os08a20.c +++ b/drivers/media/i2c/os08a20.c @@ -684,9 +684,7 @@ static int os08a20_g_frame_interval(struct v4l2_subdev *sd, struct os08a20 *os08a20 = to_os08a20(sd); const struct os08a20_mode *mode = os08a20->cur_mode; - mutex_lock(&os08a20->mutex); fi->interval = mode->max_fps; - mutex_unlock(&os08a20->mutex); return 0; } diff --git a/drivers/media/i2c/ov02b10.c b/drivers/media/i2c/ov02b10.c index d13e34c429e0..94d5d7f38835 100644 --- a/drivers/media/i2c/ov02b10.c +++ b/drivers/media/i2c/ov02b10.c @@ -526,9 +526,7 @@ static int ov02b10_g_frame_interval(struct v4l2_subdev *sd, struct ov02b10 *ov02b10 = to_ov02b10(sd); const struct ov02b10_mode *mode = ov02b10->cur_mode; - mutex_lock(&ov02b10->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov02b10->mutex); return 0; } diff --git a/drivers/media/i2c/ov02k10.c b/drivers/media/i2c/ov02k10.c index a57cc643d806..db5dcbe8c32c 100644 --- a/drivers/media/i2c/ov02k10.c +++ b/drivers/media/i2c/ov02k10.c @@ -829,9 +829,7 @@ static int ov02k10_g_frame_interval(struct v4l2_subdev *sd, struct ov02k10 *ov02k10 = to_ov02k10(sd); const struct ov02k10_mode *mode = ov02k10->cur_mode; - mutex_lock(&ov02k10->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov02k10->mutex); return 0; } diff --git a/drivers/media/i2c/ov12d2q.c b/drivers/media/i2c/ov12d2q.c index 0d92a446b0cc..f7d6a904d4e4 100644 --- a/drivers/media/i2c/ov12d2q.c +++ b/drivers/media/i2c/ov12d2q.c @@ -2216,9 +2216,7 @@ static int ov12d2q_g_frame_interval(struct v4l2_subdev *sd, struct ov12d2q *ov12d2q = to_ov12d2q(sd); const struct ov12d2q_mode *mode = ov12d2q->cur_mode; - mutex_lock(&ov12d2q->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov12d2q->mutex); return 0; } diff --git a/drivers/media/i2c/ov13850.c b/drivers/media/i2c/ov13850.c index 7727d7b03de4..d060c6e3f4aa 100644 --- a/drivers/media/i2c/ov13850.c +++ b/drivers/media/i2c/ov13850.c @@ -902,9 +902,7 @@ static int ov13850_g_frame_interval(struct v4l2_subdev *sd, struct ov13850 *ov13850 = to_ov13850(sd); const struct ov13850_mode *mode = ov13850->cur_mode; - mutex_lock(&ov13850->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov13850->mutex); return 0; } diff --git a/drivers/media/i2c/ov13855.c b/drivers/media/i2c/ov13855.c index f087ef420e95..1bac15fc1864 100644 --- a/drivers/media/i2c/ov13855.c +++ b/drivers/media/i2c/ov13855.c @@ -1212,9 +1212,7 @@ static int ov13855_g_frame_interval(struct v4l2_subdev *sd, struct ov13855 *ov13855 = to_ov13855(sd); const struct ov13855_mode *mode = ov13855->cur_mode; - mutex_lock(&ov13855->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov13855->mutex); return 0; } diff --git a/drivers/media/i2c/ov16a10.c b/drivers/media/i2c/ov16a10.c index ad010285cd54..0cbcc3f16abf 100644 --- a/drivers/media/i2c/ov16a10.c +++ b/drivers/media/i2c/ov16a10.c @@ -1185,9 +1185,7 @@ static int ov16a10_g_frame_interval(struct v4l2_subdev *sd, struct ov16a10 *ov16a10 = to_ov16a10(sd); const struct ov16a10_mode *mode = ov16a10->cur_mode; - mutex_lock(&ov16a10->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov16a10->mutex); return 0; } diff --git a/drivers/media/i2c/ov2718.c b/drivers/media/i2c/ov2718.c index 0eb234c0f9cc..ecfa53375e10 100644 --- a/drivers/media/i2c/ov2718.c +++ b/drivers/media/i2c/ov2718.c @@ -7913,9 +7913,7 @@ static int ov2718_g_frame_interval(struct v4l2_subdev *sd, struct ov2718 *ov2718 = to_ov2718(sd); const struct ov2718_mode *mode = ov2718->cur_mode; - mutex_lock(&ov2718->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov2718->mutex); return 0; } diff --git a/drivers/media/i2c/ov2775.c b/drivers/media/i2c/ov2775.c index da438d47e2f2..7c010f3d2fd6 100644 --- a/drivers/media/i2c/ov2775.c +++ b/drivers/media/i2c/ov2775.c @@ -4103,9 +4103,7 @@ static int ov2775_g_frame_interval(struct v4l2_subdev *sd, struct ov2775 *ov2775 = to_ov2775(sd); const struct ov2775_mode *mode = ov2775->cur_mode; - mutex_lock(&ov2775->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov2775->mutex); return 0; } diff --git a/drivers/media/i2c/ov4686.c b/drivers/media/i2c/ov4686.c index e587b68de24b..f04849cd3d09 100644 --- a/drivers/media/i2c/ov4686.c +++ b/drivers/media/i2c/ov4686.c @@ -718,9 +718,7 @@ static int OV4686_g_frame_interval(struct v4l2_subdev *sd, struct OV4686 *OV4686 = to_OV4686(sd); const struct OV4686_mode *mode = OV4686->cur_mode; - mutex_lock(&OV4686->mutex); fi->interval = mode->max_fps; - mutex_unlock(&OV4686->mutex); return 0; } diff --git a/drivers/media/i2c/ov4688.c b/drivers/media/i2c/ov4688.c index 5923ca002bbd..366877ced1e0 100644 --- a/drivers/media/i2c/ov4688.c +++ b/drivers/media/i2c/ov4688.c @@ -976,9 +976,7 @@ static int ov4688_g_frame_interval(struct v4l2_subdev *sd, struct ov4688 *ov4688 = to_ov4688(sd); const struct ov4688_mode *mode = ov4688->cur_mode; - mutex_lock(&ov4688->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov4688->mutex); return 0; } diff --git a/drivers/media/i2c/ov4689.c b/drivers/media/i2c/ov4689.c index 9f5623d052f5..fd1f1774d540 100644 --- a/drivers/media/i2c/ov4689.c +++ b/drivers/media/i2c/ov4689.c @@ -755,9 +755,7 @@ static int ov4689_g_frame_interval(struct v4l2_subdev *sd, struct ov4689 *ov4689 = to_ov4689(sd); const struct ov4689_mode *mode = ov4689->cur_mode; - mutex_lock(&ov4689->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov4689->mutex); return 0; } diff --git a/drivers/media/i2c/ov50c40.c b/drivers/media/i2c/ov50c40.c index 964459796058..55f5b8284836 100644 --- a/drivers/media/i2c/ov50c40.c +++ b/drivers/media/i2c/ov50c40.c @@ -6137,9 +6137,7 @@ static int ov50c40_g_frame_interval(struct v4l2_subdev *sd, struct ov50c40 *ov50c40 = to_ov50c40(sd); const struct ov50c40_mode *mode = ov50c40->cur_mode; - mutex_lock(&ov50c40->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov50c40->mutex); return 0; } diff --git a/drivers/media/i2c/ov5648.c b/drivers/media/i2c/ov5648.c index 67c63f0a8375..c37df9c21239 100644 --- a/drivers/media/i2c/ov5648.c +++ b/drivers/media/i2c/ov5648.c @@ -736,9 +736,7 @@ static int ov5648_g_frame_interval(struct v4l2_subdev *sd, struct ov5648 *ov5648 = to_ov5648(sd); const struct ov5648_mode *mode = ov5648->cur_mode; - mutex_lock(&ov5648->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov5648->mutex); return 0; } diff --git a/drivers/media/i2c/ov5695.c b/drivers/media/i2c/ov5695.c index 61bda949044a..32cdf5e6e650 100644 --- a/drivers/media/i2c/ov5695.c +++ b/drivers/media/i2c/ov5695.c @@ -841,9 +841,7 @@ static int ov5695_g_frame_interval(struct v4l2_subdev *sd, struct ov5695 *ov5695 = to_ov5695(sd); const struct ov5695_mode *mode = ov5695->cur_mode; - mutex_lock(&ov5695->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov5695->mutex); return 0; } diff --git a/drivers/media/i2c/ov7251.c b/drivers/media/i2c/ov7251.c index 462b5aa38de2..c144428486a6 100644 --- a/drivers/media/i2c/ov7251.c +++ b/drivers/media/i2c/ov7251.c @@ -973,12 +973,10 @@ static int ov7251_g_frame_interval(struct v4l2_subdev *sd, struct ov7251 *ov7251 = to_ov7251(sd); const struct ov7251_mode *mode = ov7251->cur_mode; - mutex_lock(&ov7251->mutex); if (ov7251->streaming) fi->interval = ov7251->cur_fps; else fi->interval = mode->max_fps; - mutex_unlock(&ov7251->mutex); return 0; } diff --git a/drivers/media/i2c/ov8858.c b/drivers/media/i2c/ov8858.c index f016f9e6af08..966b8dae3e51 100644 --- a/drivers/media/i2c/ov8858.c +++ b/drivers/media/i2c/ov8858.c @@ -2131,9 +2131,7 @@ static int ov8858_g_frame_interval(struct v4l2_subdev *sd, struct ov8858 *ov8858 = to_ov8858(sd); const struct ov8858_mode *mode = ov8858->cur_mode; - mutex_lock(&ov8858->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov8858->mutex); return 0; } diff --git a/drivers/media/i2c/ov9281.c b/drivers/media/i2c/ov9281.c index 69d62cb0db63..a8521603da9e 100644 --- a/drivers/media/i2c/ov9281.c +++ b/drivers/media/i2c/ov9281.c @@ -667,9 +667,7 @@ static int ov9281_g_frame_interval(struct v4l2_subdev *sd, struct ov9281 *ov9281 = to_ov9281(sd); const struct ov9281_mode *mode = ov9281->cur_mode; - mutex_lock(&ov9281->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov9281->mutex); return 0; } diff --git a/drivers/media/i2c/ov9650.c b/drivers/media/i2c/ov9650.c index 4fe68aa55789..fccd94af86a7 100644 --- a/drivers/media/i2c/ov9650.c +++ b/drivers/media/i2c/ov9650.c @@ -1108,9 +1108,7 @@ static int ov965x_g_frame_interval(struct v4l2_subdev *sd, { struct ov965x *ov965x = to_ov965x(sd); - mutex_lock(&ov965x->lock); fi->interval = ov965x->fiv->interval; - mutex_unlock(&ov965x->lock); return 0; } diff --git a/drivers/media/i2c/ov9750.c b/drivers/media/i2c/ov9750.c index e7c5f8bf69e6..4b88ae132217 100644 --- a/drivers/media/i2c/ov9750.c +++ b/drivers/media/i2c/ov9750.c @@ -623,9 +623,7 @@ static int ov9750_g_frame_interval(struct v4l2_subdev *sd, struct ov9750 *ov9750 = to_ov9750(sd); const struct ov9750_mode *mode = ov9750->cur_mode; - mutex_lock(&ov9750->mutex); fi->interval = mode->max_fps; - mutex_unlock(&ov9750->mutex); return 0; } diff --git a/drivers/media/i2c/s5kjn1.c b/drivers/media/i2c/s5kjn1.c index 8f61020a1f77..29621d3f43ca 100644 --- a/drivers/media/i2c/s5kjn1.c +++ b/drivers/media/i2c/s5kjn1.c @@ -1199,9 +1199,7 @@ static int s5kjn1_g_frame_interval(struct v4l2_subdev *sd, struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); const struct s5kjn1_mode *mode = s5kjn1->cur_mode; - mutex_lock(&s5kjn1->mutex); fi->interval = mode->max_fps; - mutex_unlock(&s5kjn1->mutex); return 0; } diff --git a/drivers/media/i2c/sc2336.c b/drivers/media/i2c/sc2336.c index dde243a43200..ca948d69ac8b 100644 --- a/drivers/media/i2c/sc2336.c +++ b/drivers/media/i2c/sc2336.c @@ -660,9 +660,7 @@ static int sc2336_g_frame_interval(struct v4l2_subdev *sd, struct sc2336 *sc2336 = to_sc2336(sd); const struct sc2336_mode *mode = sc2336->cur_mode; - mutex_lock(&sc2336->mutex); fi->interval = mode->max_fps; - mutex_unlock(&sc2336->mutex); return 0; } From b99d30ed2a5e0cc337352c59cf3c50d02e576c42 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Fri, 10 Feb 2023 17:16:07 +0800 Subject: [PATCH 123/258] ARM: dts: rockchip: rk3036: fix i2s pinctrl Change-Id: I4e8ddc326c95694ba648545049f56b8804a89ac5 Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3036.dtsi | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index b2853011e5ec..447218d5d74b 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -488,7 +488,12 @@ resets = <&cru SRST_I2S>; reset-names = "reset-m"; pinctrl-names = "default"; - pinctrl-0 = <&i2s_bus>; + pinctrl-0 = <&i2s_mclk + &i2s_sclk + &i2s_lrclkrx + &i2s_lrclktx + &i2s_sdo + &i2s_sdi>; #sound-dai-cells = <0>; status = "disabled"; }; @@ -937,13 +942,23 @@ }; i2s { - i2s_bus: i2s-bus { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, - <1 RK_PA1 1 &pcfg_pull_default>, - <1 RK_PA2 1 &pcfg_pull_default>, - <1 RK_PA3 1 &pcfg_pull_default>, - <1 RK_PA4 1 &pcfg_pull_default>, - <1 RK_PA5 1 &pcfg_pull_default>; + i2s_mclk: i2s-mclk { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>; + }; + i2s_sclk: i2s-sclk { + rockchip,pins = <1 RK_PA1 1 &pcfg_pull_default>; + }; + i2s_lrclkrx: i2s-lrclkrx { + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; + }; + i2s_lrclktx: i2s-lrclktx { + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; + }; + i2s_sdo: i2s-sdo { + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>; + }; + i2s_sdi: i2s-sdi { + rockchip,pins = <1 RK_PA5 1 &pcfg_pull_default>; }; }; From b3e140c597d43e761c86bd4be58755215c16f339 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Fri, 10 Feb 2023 17:30:10 +0800 Subject: [PATCH 124/258] ARM: dts: rockchip: rk3036-evb1: update es8311 node and i2s node Change-Id: Ic50c3c5f75bee2dea72a133a600c707875e17d4b Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts index 18a5a06e6a2a..9884deec143a 100644 --- a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts +++ b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts @@ -151,14 +151,14 @@ es8311: es8311@18 { compatible = "everest,es8311"; reg = <0x18>; - //clocks = <&cru SCLK_I2S_OUT>; + clocks = <&cru SCLK_I2S_OUT>; clock-names = "mclk"; adc-pga-gain = <8>; adc-volume = <0xdf>; dac-volume = <0xbf>; aec-mode = "dac left, adc right"; - //pinctrl-names = "default"; - //pinctrl-0 = <&i2s_mclk>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_mclk>; /* * in rk3036-evb-v10,es8311 is not actually connected @@ -425,8 +425,12 @@ }; &i2s { - #sound-dai-cells = <0>; status = "okay"; + #sound-dai-cells = <0>; + pinctrl-0 = <&i2s_sclk + &i2s_lrclktx + &i2s_sdo + &i2s_sdi>; }; &mpp_srv { From 311bd445fb0b9e6bb1be24fc3f6916a172e76162 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Wed, 8 Feb 2023 09:57:05 +0800 Subject: [PATCH 125/258] ARM: dts: rockchip: rk3036-echo/kylin use new i2s node Change-Id: I46677e361788f58738e216593277cee390392e51 Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3036-echo.dts | 4 ++++ arch/arm/boot/dts/rk3036-kylin.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-echo.dts b/arch/arm/boot/dts/rk3036-echo.dts index 140c93c6c444..a072eacf78b7 100644 --- a/arch/arm/boot/dts/rk3036-echo.dts +++ b/arch/arm/boot/dts/rk3036-echo.dts @@ -645,6 +645,10 @@ &i2s { #sound-dai-cells = <0>; + pinctrl-0 = <&i2s_sclk + &i2s_lrclktx + &i2s_sdo + &i2s_sdi>; status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 41480890bb6a..a4ed6b0ff158 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -374,6 +374,10 @@ &i2s { status = "okay"; + pinctrl-0 = <&i2s_sclk + &i2s_lrclktx + &i2s_sdo + &i2s_sdi>; }; &mpp_srv { From 9b71d6a08065fb15d86913e659df1219b253e519 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Thu, 9 Feb 2023 10:29:24 +0800 Subject: [PATCH 126/258] drm/rockchip: inno_hdmi: add support hdmi audio Change-Id: I4df13c5ed17516cf820dc425c17368c1fbb9c6be Signed-off-by: Hongming Zou --- drivers/gpu/drm/rockchip/inno_hdmi.c | 201 ++++++++++++++++++++++++++- drivers/gpu/drm/rockchip/inno_hdmi.h | 2 + 2 files changed, 201 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index 9e8d0ade9dbe..995d1f5ecbe3 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -21,6 +21,8 @@ #include #include +#include + #include "rockchip_drm_drv.h" #include "rockchip_drm_vop.h" @@ -28,6 +30,12 @@ #define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x) +struct audio_info { + int sample_rate; + int channels; + int sample_width; +}; + struct hdmi_data_info { int vic; bool sink_is_hdmi; @@ -79,6 +87,8 @@ struct inno_hdmi { struct i2c_adapter *ddc; unsigned int tmds_rate; + struct platform_device *audio_pdev; + bool audio_enable; const struct inno_hdmi_plat_data *plat_data; struct hdmi_data_info hdmi_data; @@ -307,6 +317,21 @@ static int inno_hdmi_config_video_vsi(struct inno_hdmi *hdmi, m_PACKET_VSI_EN, v_PACKET_VSI_EN(0), v_PACKET_VSI_EN(1)); } +static int inno_hdmi_config_audio_aai(struct inno_hdmi *hdmi, + struct audio_info *audio) +{ + struct hdmi_audio_infoframe *faudio; + union hdmi_infoframe frame; + int rc; + + rc = hdmi_audio_infoframe_init(&frame.audio); + faudio = (struct hdmi_audio_infoframe *)&frame; + + faudio->channels = audio->channels; + + return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_AAI, 0, 0, 0); +} + static int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi, struct drm_display_mode *mode) { @@ -505,8 +530,9 @@ static int inno_hdmi_setup(struct inno_hdmi *hdmi, inno_hdmi_i2c_init(hdmi); /* Unmute video and audio output */ - hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, - v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0)); + hdmi_modb(hdmi, HDMI_AV_MUTE, m_VIDEO_BLACK, v_VIDEO_MUTE(0)); + if (hdmi->audio_enable) + hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE, v_AUDIO_MUTE(0)); return 0; } @@ -629,6 +655,176 @@ static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = { .mode_valid = inno_hdmi_connector_mode_valid, }; +static int +inno_hdmi_audio_config_set(struct inno_hdmi *hdmi, struct audio_info *audio) +{ + int rate, N, channel; + + if (audio->channels < 3) + channel = I2S_CHANNEL_1_2; + else if (audio->channels < 5) + channel = I2S_CHANNEL_3_4; + else if (audio->channels < 7) + channel = I2S_CHANNEL_5_6; + else + channel = I2S_CHANNEL_7_8; + + switch (audio->sample_rate) { + case 32000: + rate = AUDIO_32K; + N = N_32K; + break; + case 44100: + rate = AUDIO_441K; + N = N_441K; + break; + case 48000: + rate = AUDIO_48K; + N = N_48K; + break; + case 88200: + rate = AUDIO_882K; + N = N_882K; + break; + case 96000: + rate = AUDIO_96K; + N = N_96K; + break; + case 176400: + rate = AUDIO_1764K; + N = N_1764K; + break; + case 192000: + rate = AUDIO_192K; + N = N_192K; + break; + default: + dev_err(hdmi->dev, "[%s] not support such sample rate %d\n", + __func__, audio->sample_rate); + return -ENOENT; + } + + /* Set_audio source I2S */ + hdmi_writeb(hdmi, HDMI_AUDIO_CTRL1, 0x01); + hdmi_writeb(hdmi, AUDIO_SAMPLE_RATE, rate); + hdmi_writeb(hdmi, AUDIO_I2S_MODE, v_I2S_MODE(I2S_STANDARD) | + v_I2S_CHANNEL(channel)); + + hdmi_writeb(hdmi, AUDIO_I2S_MAP, 0x00); + hdmi_writeb(hdmi, AUDIO_I2S_SWAPS_SPDIF, 0); + + /* Set N value */ + hdmi_writeb(hdmi, AUDIO_N_H, (N >> 16) & 0x0F); + hdmi_writeb(hdmi, AUDIO_N_M, (N >> 8) & 0xFF); + hdmi_writeb(hdmi, AUDIO_N_L, N & 0xFF); + + /* Set hdmi nlpcm mode to support hdmi bitstream */ + hdmi_writeb(hdmi, HDMI_AUDIO_CHANNEL_STATUS, v_AUDIO_STATUS_NLPCM(0)); + + return inno_hdmi_config_audio_aai(hdmi, audio); +} + +static int inno_hdmi_audio_hw_params(struct device *dev, void *d, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct inno_hdmi *hdmi = dev_get_drvdata(dev); + struct audio_info audio = { + .sample_width = params->sample_width, + .sample_rate = params->sample_rate, + .channels = params->channels, + }; + + if (!hdmi->hdmi_data.sink_has_audio) { + dev_err(hdmi->dev, "Sink do not support audio!\n"); + return -ENODEV; + } + + if (!hdmi->encoder.crtc) + return -ENODEV; + + switch (daifmt->fmt) { + case HDMI_I2S: + break; + default: + dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); + return -EINVAL; + } + + return inno_hdmi_audio_config_set(hdmi, &audio); +} + +static void inno_hdmi_audio_shutdown(struct device *dev, void *d) +{ + /* do nothing */ +} + +static int inno_hdmi_audio_mute(struct device *dev, void *data, bool mute, int direction) +{ + struct inno_hdmi *hdmi = dev_get_drvdata(dev); + + if (!hdmi->hdmi_data.sink_has_audio) { + dev_err(hdmi->dev, "Sink do not support audio!\n"); + return -ENODEV; + } + + hdmi->audio_enable = !mute; + + if (mute) + hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_AUDIO_PD, + v_AUDIO_MUTE(1) | v_AUDIO_PD(1)); + else + hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_AUDIO_PD, + v_AUDIO_MUTE(0) | v_AUDIO_PD(0)); + + return 0; +} + +static int inno_hdmi_audio_get_eld(struct device *dev, void *d, + uint8_t *buf, size_t len) +{ + struct inno_hdmi *hdmi = dev_get_drvdata(dev); + struct drm_mode_config *config = &hdmi->encoder.dev->mode_config; + struct drm_connector *connector; + int ret = -ENODEV; + + mutex_lock(&config->mutex); + list_for_each_entry(connector, &config->connector_list, head) { + if (&hdmi->encoder == connector->encoder) { + memcpy(buf, connector->eld, + min(sizeof(connector->eld), len)); + ret = 0; + } + } + mutex_unlock(&config->mutex); + + return ret; +} + +static const struct hdmi_codec_ops audio_codec_ops = { + .hw_params = inno_hdmi_audio_hw_params, + .audio_shutdown = inno_hdmi_audio_shutdown, + .mute_stream = inno_hdmi_audio_mute, + .get_eld = inno_hdmi_audio_get_eld, +}; + +static int inno_hdmi_audio_codec_init(struct inno_hdmi *hdmi, + struct device *dev) +{ + struct hdmi_codec_pdata codec_data = { + .i2s = 1, + .ops = &audio_codec_ops, + .max_i2s_channels = 8, + }; + + hdmi->audio_enable = false; + hdmi->audio_pdev = platform_device_register_data( + dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_NONE, + &codec_data, sizeof(codec_data)); + + return PTR_ERR_OR_ZERO(hdmi->audio_pdev); +} + static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) { struct drm_encoder *encoder = &hdmi->encoder; @@ -658,6 +854,7 @@ static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) hdmi->ddc); drm_connector_attach_encoder(&hdmi->connector, encoder); + inno_hdmi_audio_codec_init(hdmi, dev); return 0; } diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.h b/drivers/gpu/drm/rockchip/inno_hdmi.h index 93245b55f967..b722afc4e41f 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.h +++ b/drivers/gpu/drm/rockchip/inno_hdmi.h @@ -96,11 +96,13 @@ enum { #define HDMI_AV_MUTE 0x05 #define m_AVMUTE_CLEAR (1 << 7) #define m_AVMUTE_ENABLE (1 << 6) +#define m_AUDIO_PD (1 << 2) #define m_AUDIO_MUTE (1 << 1) #define m_VIDEO_BLACK (1 << 0) #define v_AVMUTE_CLEAR(n) (n << 7) #define v_AVMUTE_ENABLE(n) (n << 6) #define v_AUDIO_MUTE(n) (n << 1) +#define v_AUDIO_PD(n) (n << 2) #define v_VIDEO_MUTE(n) (n << 0) #define HDMI_VIDEO_TIMING_CTL 0x08 From be6124d1991030bf1e7b63b848d92e9036343200 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Tue, 7 Feb 2023 20:19:44 +0800 Subject: [PATCH 127/258] ARM: configs: rockchip_linux_defconfig: add two codec configs for the rk3036 evb1 board CONFIG_SND_SOC_INNO_RK3036=y CONFIG_SND_SOC_ES8311=y Change-Id: Id90f81974cf045b3534031d5b504f6cac080a3f1 Signed-off-by: Hongming Zou --- arch/arm/configs/rockchip_linux_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rockchip_linux_defconfig b/arch/arm/configs/rockchip_linux_defconfig index 6e356c7533a3..dd119051d270 100644 --- a/arch/arm/configs/rockchip_linux_defconfig +++ b/arch/arm/configs/rockchip_linux_defconfig @@ -334,8 +334,10 @@ CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_SPDIF=y CONFIG_SND_SOC_ROCKCHIP_MAX98090=y CONFIG_SND_SOC_ROCKCHIP_RT5645=y +CONFIG_SND_SOC_ES8311=y CONFIG_SND_SOC_ES8323=y CONFIG_SND_SOC_ES8396=y +CONFIG_SND_SOC_INNO_RK3036=y CONFIG_SND_SOC_RK312X=y CONFIG_SND_SOC_RT5616=y CONFIG_SND_SOC_RT5640=y From 116e21f4fdc536bd54f2d8f8d9a1763a65da9064 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Mon, 13 Feb 2023 03:20:35 +0000 Subject: [PATCH 128/258] arm64: dts: rockchip: rk3562: Use GRF_PMU_OS_REG8 as reboot-mode register GRF_PMU_OS_REG8 can't be reset by NPOR. Signed-off-by: Joseph Chen Change-Id: Ie1dee8c0744b00b3cba23637cadcc382ba529207 --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index a673b441821a..019358146f82 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -826,7 +826,7 @@ reboot_mode: reboot-mode { compatible = "syscon-reboot-mode"; - offset = <0x200>; + offset = <0x220>; mode-bootloader = ; mode-charge = ; mode-fastboot = ; From f23955ad2cbc2ad4d47fcad3c4eb8a308e2eefa5 Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Tue, 7 Feb 2023 09:29:22 +0000 Subject: [PATCH 129/258] media: i2c: add vcm dw9763 driver Change-Id: Ib7b903f508e002d9bd41d842a01f406925ee48f5 Signed-off-by: Jianwei Fan --- drivers/media/i2c/Kconfig | 12 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/dw9763.c | 949 +++++++++++++++++++++++++++++++++++++ 3 files changed, 962 insertions(+) create mode 100644 drivers/media/i2c/dw9763.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index f0d19df43ff3..15598a3ccb17 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -2241,6 +2241,18 @@ config VIDEO_DW9714 capability. This is designed for linear control of voice coil motors, controlled via I2C serial interface. +config VIDEO_DW9763 + tristate "DW9763 lens voice coil support" + depends on I2C && VIDEO_V4L2 + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a driver for the DW9763 camera lens voice coil. + DW9763 is a 10 bit DAC with 120mA output current sink + capability. This is designed for linear control of + voice coil motors, controlled via I2C serial interface. + config VIDEO_DW9768 tristate "DW9768 lens voice coil support" depends on I2C && VIDEO_V4L2 diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 6ebe2d59a708..327052fc174a 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_VIDEO_AK7375) += ak7375.o obj-$(CONFIG_VIDEO_AW8601) += aw8601.o obj-$(CONFIG_VIDEO_CN3927V) += cn3927v.o obj-$(CONFIG_VIDEO_DW9714) += dw9714.o +obj-$(CONFIG_VIDEO_DW9763) += dw9763.o obj-$(CONFIG_VIDEO_DW9768) += dw9768.o obj-$(CONFIG_VIDEO_DW9800W) += dw9800w.o obj-$(CONFIG_VIDEO_DW9807_VCM) += dw9807-vcm.o diff --git a/drivers/media/i2c/dw9763.c b/drivers/media/i2c/dw9763.c new file mode 100644 index 000000000000..907b5434c187 --- /dev/null +++ b/drivers/media/i2c/dw9763.c @@ -0,0 +1,949 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dw9763 vcm driver + * + * Copyright (C) 2022 Rockchip Electronics Co., Ltd. + */ +// #define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x0) +#define DW9763_NAME "dw9763" + +#define DW9763_MAX_CURRENT 120U +#define DW9763_MAX_REG 1023U + +#define DW9763_DEFAULT_START_CURRENT 20 +#define DW9763_DEFAULT_RATED_CURRENT 90 +#define DW9763_DEFAULT_STEP_MODE 0x3 +#define DW9763_DEFAULT_T_SACT 0x20 +#define DW9763_DEFAULT_T_DIV 0x1 +#define REG_NULL 0xFF + +#define DW9763_CHIP_ID 0xF9 +#define DW9763_REG_CHIP_ID 0x00 + +enum mode_e { + SAC1_MODE, + SAC2_MODE, + SAC2_5_MODE, + SAC3_MODE, + SAC4_MODE = 5, + DIRECT_MODE, +}; + +/* dw9763 device structure */ +struct dw9763_device { + struct v4l2_ctrl_handler ctrls_vcm; + struct i2c_client *client; + struct v4l2_subdev sd; + struct v4l2_device vdev; + u16 current_val; + + struct gpio_desc *power_gpio; + unsigned short current_related_pos; + unsigned short current_lens_pos; + unsigned int start_current; + unsigned int rated_current; + unsigned int step; + unsigned int step_mode; + unsigned int vcm_movefull_t; + unsigned int t_src; + unsigned int t_div; + + struct __kernel_old_timeval start_move_tv; + struct __kernel_old_timeval end_move_tv; + unsigned long move_us; + + u32 module_index; + const char *module_facing; + struct rk_cam_vcm_cfg vcm_cfg; + int max_ma; + struct mutex lock; +}; + +static inline struct dw9763_device *to_dw9763_vcm(struct v4l2_ctrl *ctrl) +{ + return container_of(ctrl->handler, struct dw9763_device, ctrls_vcm); +} + +static inline struct dw9763_device *sd_to_dw9763_vcm(struct v4l2_subdev *subdev) +{ + return container_of(subdev, struct dw9763_device, sd); +} + +static int dw9763_write_reg(struct i2c_client *client, u8 reg, + u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[5]; + u8 *val_p; + __be32 val_be; + + if (len > 4) + return -EINVAL; + + buf[0] = reg; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 1; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 1) != len + 1) { + dev_err(&client->dev, "Failed to write 0x%04x,0x%x\n", reg, val); + return -EIO; + } + dev_dbg(&client->dev, "succeed to write 0x%04x,0x%x\n", reg, val); + + return 0; +} + +static int dw9763_read_reg(struct i2c_client *client, + u8 reg, + unsigned int len, + u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 1; + msgs[0].buf = (u8 *)® + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +static unsigned int dw9763_move_time_div(struct dw9763_device *dev_vcm, + unsigned int move_time_us) +{ + struct i2c_client *client = dev_vcm->client; + unsigned int move_time = 0; + + switch (dev_vcm->t_div) { + case 0: + move_time = move_time_us * 2; + break; + case 1: + move_time = move_time_us; + break; + case 2: + move_time = move_time_us / 2; + break; + case 3: + move_time = move_time_us / 4; + break; + case 4: + move_time = move_time_us * 8; + break; + case 5: + move_time = move_time_us * 4; + break; + default: + dev_err(&client->dev, "%s: t_div parameter err %d\n", __func__, dev_vcm->t_div); + move_time = move_time_us; + break; + } + return move_time; +} + +static unsigned int dw9763_move_time(struct dw9763_device *dev_vcm, + unsigned int move_pos) +{ + struct i2c_client *client = dev_vcm->client; + unsigned int move_time_us = 0; + + switch (dev_vcm->step_mode) { + case SAC1_MODE: + case SAC2_MODE: + case SAC2_5_MODE: + case SAC3_MODE: + case SAC4_MODE: + move_time_us = 6300 + dev_vcm->t_src * 100; + move_time_us = dw9763_move_time_div(dev_vcm, move_time_us); + break; + case DIRECT_MODE: + move_time_us = 30000; + break; + default: + dev_err(&client->dev, + "%s: step_mode is error %d\n", + __func__, dev_vcm->step_mode); + break; + } + + dev_dbg(&client->dev, + "%s: vcm_movefull_t is: %d us\n", + __func__, move_time_us); + + return move_time_us; +} + +static int dw9763_set_dac(struct dw9763_device *dev_vcm, + unsigned int dest_dac) +{ + struct i2c_client *client = v4l2_get_subdevdata(&dev_vcm->sd); + int ret; + u32 is_busy, i; + + for (i = 0; i < 10; i++) { + ret = dw9763_read_reg(client, 0x05, 1, &is_busy); + if (!ret && !(is_busy & 0x01)) + break; + usleep_range(100, 200); + } + + ret = dw9763_write_reg(client, 0x03, 2, dest_dac); + if (ret != 0) + goto err; + dev_dbg(&client->dev, + "%s: set reg val %d\n", __func__, dest_dac); + + return ret; +err: + dev_err(&client->dev, + "%s: failed with error %d\n", __func__, ret); + return ret; +} + +static int dw9763_get_dac(struct dw9763_device *dev_vcm, unsigned int *cur_dac) +{ + struct i2c_client *client = v4l2_get_subdevdata(&dev_vcm->sd); + int ret; + unsigned int abs_step; + + ret = dw9763_read_reg(client, 0x03, 2, &abs_step); + if (ret != 0) + goto err; + + *cur_dac = abs_step; + dev_dbg(&client->dev, "%s: get dac %d\n", __func__, *cur_dac); + + return 0; + +err: + dev_err(&client->dev, + "%s: failed with error %d\n", __func__, ret); + return ret; +} + +static int dw9763_get_pos(struct dw9763_device *dev_vcm, + unsigned int *cur_pos) +{ + struct i2c_client *client = dev_vcm->client; + int ret; + unsigned int abs_step; + + ret = dw9763_read_reg(client, 0x03, 2, &abs_step); + if (ret != 0) + goto err; + + if (abs_step <= dev_vcm->start_current) + abs_step = VCMDRV_MAX_LOG; + else if ((abs_step > dev_vcm->start_current) && + (abs_step <= dev_vcm->rated_current)) + abs_step = (dev_vcm->rated_current - abs_step) / dev_vcm->step; + else + abs_step = 0; + + *cur_pos = abs_step; + dev_dbg(&client->dev, "%s: get position %d\n", __func__, *cur_pos); + return 0; + +err: + dev_err(&client->dev, + "%s: failed with error %d\n", __func__, ret); + return ret; +} + +static int dw9763_set_pos(struct dw9763_device *dev_vcm, + unsigned int dest_pos) +{ + int ret; + unsigned int position = 0; + struct i2c_client *client = dev_vcm->client; + + if (dest_pos >= VCMDRV_MAX_LOG) + position = dev_vcm->start_current; + else + position = dev_vcm->start_current + + (dev_vcm->step * (VCMDRV_MAX_LOG - dest_pos)); + + if (position > DW9763_MAX_REG) + position = DW9763_MAX_REG; + + dev_vcm->current_lens_pos = position; + dev_vcm->current_related_pos = dest_pos; + + ret = dw9763_set_dac(dev_vcm, position); + dev_dbg(&client->dev, "%s: set position %d, dac %d\n", __func__, dest_pos, position); + + return ret; +} + +static int dw9763_get_ctrl(struct v4l2_ctrl *ctrl) +{ + struct dw9763_device *dev_vcm = to_dw9763_vcm(ctrl); + + if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE) + return dw9763_get_pos(dev_vcm, &ctrl->val); + + return -EINVAL; +} + +static int dw9763_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct dw9763_device *dev_vcm = to_dw9763_vcm(ctrl); + struct i2c_client *client = dev_vcm->client; + unsigned int dest_pos = ctrl->val; + long mv_us; + int ret = 0; + + dev_dbg(&client->dev, "ctrl->id: 0x%x, ctrl->val: 0x%x\n", + ctrl->id, ctrl->val); + + if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE) { + + if (dest_pos > VCMDRV_MAX_LOG) { + dev_info(&client->dev, + "%s dest_pos is error. %d > %d\n", + __func__, dest_pos, VCMDRV_MAX_LOG); + return -EINVAL; + } + + ret = dw9763_set_pos(dev_vcm, dest_pos); + + dev_vcm->move_us = dev_vcm->vcm_movefull_t; + + dev_dbg(&client->dev, + "dest_pos %d, move_us %ld\n", + dest_pos, dev_vcm->move_us); + + dev_vcm->start_move_tv = ns_to_kernel_old_timeval(ktime_get_ns()); + mv_us = dev_vcm->start_move_tv.tv_usec + + dev_vcm->move_us; + if (mv_us >= 1000000) { + dev_vcm->end_move_tv.tv_sec = + dev_vcm->start_move_tv.tv_sec + 1; + dev_vcm->end_move_tv.tv_usec = mv_us - 1000000; + } else { + dev_vcm->end_move_tv.tv_sec = + dev_vcm->start_move_tv.tv_sec; + dev_vcm->end_move_tv.tv_usec = mv_us; + } + } + + return ret; +} + +static const struct v4l2_ctrl_ops dw9763_vcm_ctrl_ops = { + .g_volatile_ctrl = dw9763_get_ctrl, + .s_ctrl = dw9763_set_ctrl, +}; + +static int dw9763_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + int rval; + + rval = pm_runtime_get_sync(sd->dev); + if (rval < 0) { + pm_runtime_put_noidle(sd->dev); + return rval; + } + + return 0; +} + +static int dw9763_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + pm_runtime_put(sd->dev); + + return 0; +} + +static const struct v4l2_subdev_internal_ops dw9763_int_ops = { + .open = dw9763_open, + .close = dw9763_close, +}; + +static void dw9763_update_vcm_cfg(struct dw9763_device *dev_vcm) +{ + struct i2c_client *client = dev_vcm->client; + int cur_dist; + + if (dev_vcm->max_ma == 0) { + dev_err(&client->dev, "max current is zero"); + return; + } + + cur_dist = dev_vcm->vcm_cfg.rated_ma - dev_vcm->vcm_cfg.start_ma; + cur_dist = cur_dist * DW9763_MAX_REG / dev_vcm->max_ma; + dev_vcm->step = (cur_dist + (VCMDRV_MAX_LOG - 1)) / VCMDRV_MAX_LOG; + dev_vcm->start_current = dev_vcm->vcm_cfg.start_ma * + DW9763_MAX_REG / dev_vcm->max_ma; + dev_vcm->rated_current = dev_vcm->vcm_cfg.rated_ma * + DW9763_MAX_REG / dev_vcm->max_ma; + dev_vcm->step_mode = dev_vcm->vcm_cfg.step_mode; + + dev_info(&client->dev, + "vcm_cfg: %d, %d, %d, max_ma %d\n", + dev_vcm->vcm_cfg.start_ma, + dev_vcm->vcm_cfg.rated_ma, + dev_vcm->vcm_cfg.step_mode, + dev_vcm->max_ma); +} + +static long dw9763_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct dw9763_device *dev_vcm = sd_to_dw9763_vcm(sd); + struct i2c_client *client = dev_vcm->client; + struct rk_cam_vcm_tim *vcm_tim; + struct rk_cam_vcm_cfg *vcm_cfg; + int ret = 0; + + if (cmd == RK_VIDIOC_VCM_TIMEINFO) { + vcm_tim = (struct rk_cam_vcm_tim *)arg; + + vcm_tim->vcm_start_t.tv_sec = dev_vcm->start_move_tv.tv_sec; + vcm_tim->vcm_start_t.tv_usec = + dev_vcm->start_move_tv.tv_usec; + vcm_tim->vcm_end_t.tv_sec = dev_vcm->end_move_tv.tv_sec; + vcm_tim->vcm_end_t.tv_usec = dev_vcm->end_move_tv.tv_usec; + + dev_dbg(&client->dev, "dw9763_get_move_res 0x%lx, 0x%lx, 0x%lx, 0x%lx\n", + vcm_tim->vcm_start_t.tv_sec, + vcm_tim->vcm_start_t.tv_usec, + vcm_tim->vcm_end_t.tv_sec, + vcm_tim->vcm_end_t.tv_usec); + } else if (cmd == RK_VIDIOC_GET_VCM_CFG) { + vcm_cfg = (struct rk_cam_vcm_cfg *)arg; + + vcm_cfg->start_ma = dev_vcm->vcm_cfg.start_ma; + vcm_cfg->rated_ma = dev_vcm->vcm_cfg.rated_ma; + vcm_cfg->step_mode = dev_vcm->vcm_cfg.step_mode; + } else if (cmd == RK_VIDIOC_SET_VCM_CFG) { + vcm_cfg = (struct rk_cam_vcm_cfg *)arg; + + if (vcm_cfg->start_ma == 0 && vcm_cfg->rated_ma == 0) { + dev_err(&client->dev, + "vcm_cfg err, start_ma %d, rated_ma %d\n", + vcm_cfg->start_ma, vcm_cfg->rated_ma); + return -EINVAL; + } + dev_vcm->vcm_cfg.start_ma = vcm_cfg->start_ma; + dev_vcm->vcm_cfg.rated_ma = vcm_cfg->rated_ma; + dev_vcm->vcm_cfg.step_mode = vcm_cfg->step_mode; + dw9763_update_vcm_cfg(dev_vcm); + } else { + dev_err(&client->dev, + "cmd 0x%x not supported\n", cmd); + return -EINVAL; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long dw9763_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + struct dw9763_device *dev_vcm = sd_to_dw9763_vcm(sd); + struct i2c_client *client = dev_vcm->client; + void __user *up = compat_ptr(arg); + struct rk_cam_compat_vcm_tim compat_vcm_tim; + struct rk_cam_vcm_tim vcm_tim; + struct rk_cam_vcm_cfg vcm_cfg; + long ret; + + if (cmd == RK_VIDIOC_COMPAT_VCM_TIMEINFO) { + struct rk_cam_compat_vcm_tim __user *p32 = up; + + ret = dw9763_ioctl(sd, RK_VIDIOC_VCM_TIMEINFO, &vcm_tim); + compat_vcm_tim.vcm_start_t.tv_sec = vcm_tim.vcm_start_t.tv_sec; + compat_vcm_tim.vcm_start_t.tv_usec = vcm_tim.vcm_start_t.tv_usec; + compat_vcm_tim.vcm_end_t.tv_sec = vcm_tim.vcm_end_t.tv_sec; + compat_vcm_tim.vcm_end_t.tv_usec = vcm_tim.vcm_end_t.tv_usec; + + put_user(compat_vcm_tim.vcm_start_t.tv_sec, + &p32->vcm_start_t.tv_sec); + put_user(compat_vcm_tim.vcm_start_t.tv_usec, + &p32->vcm_start_t.tv_usec); + put_user(compat_vcm_tim.vcm_end_t.tv_sec, + &p32->vcm_end_t.tv_sec); + put_user(compat_vcm_tim.vcm_end_t.tv_usec, + &p32->vcm_end_t.tv_usec); + } else if (cmd == RK_VIDIOC_GET_VCM_CFG) { + ret = dw9763_ioctl(sd, RK_VIDIOC_GET_VCM_CFG, &vcm_cfg); + if (!ret) { + ret = copy_to_user(up, &vcm_cfg, sizeof(vcm_cfg)); + if (ret) + ret = -EFAULT; + } + } else if (cmd == RK_VIDIOC_SET_VCM_CFG) { + ret = copy_from_user(&vcm_cfg, up, sizeof(vcm_cfg)); + if (!ret) + ret = dw9763_ioctl(sd, cmd, &vcm_cfg); + else + ret = -EFAULT; + } else { + dev_err(&client->dev, + "cmd 0x%x not supported\n", cmd); + return -EINVAL; + } + + return ret; +} +#endif + +static const struct v4l2_subdev_core_ops dw9763_core_ops = { + .ioctl = dw9763_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = dw9763_compat_ioctl32 +#endif +}; + +static const struct v4l2_subdev_ops dw9763_ops = { + .core = &dw9763_core_ops, +}; + +static void dw9763_subdev_cleanup(struct dw9763_device *dw9763_dev) +{ + v4l2_device_unregister_subdev(&dw9763_dev->sd); + v4l2_device_unregister(&dw9763_dev->vdev); + v4l2_ctrl_handler_free(&dw9763_dev->ctrls_vcm); + media_entity_cleanup(&dw9763_dev->sd.entity); +} + +static int dw9763_init_controls(struct dw9763_device *dev_vcm) +{ + struct v4l2_ctrl_handler *hdl = &dev_vcm->ctrls_vcm; + const struct v4l2_ctrl_ops *ops = &dw9763_vcm_ctrl_ops; + + v4l2_ctrl_handler_init(hdl, 1); + + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE, + 0, VCMDRV_MAX_LOG, 1, 32); + + if (hdl->error) + dev_err(dev_vcm->sd.dev, "%s fail error: 0x%x\n", + __func__, hdl->error); + dev_vcm->sd.ctrl_handler = hdl; + return hdl->error; +} + +#define USED_SYS_DEBUG +#ifdef USED_SYS_DEBUG +static ssize_t set_dacval(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct dw9763_device *dev_vcm = sd_to_dw9763_vcm(sd); + int val = 0; + int ret = 0; + + ret = kstrtoint(buf, 0, &val); + if (!ret) + dw9763_set_dac(dev_vcm, val); + + return count; +} + +static ssize_t get_dacval(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct dw9763_device *dev_vcm = sd_to_dw9763_vcm(sd); + unsigned int dac = 0; + + dw9763_get_dac(dev_vcm, &dac); + return sprintf(buf, "%u\n", dac); +} + +static struct device_attribute attributes[] = { + __ATTR(dacval, 0600, get_dacval, set_dacval), +}; + +static int add_sysfs_interfaces(struct device *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(attributes); i++) + if (device_create_file(dev, attributes + i)) + goto undo; + return 0; +undo: + for (i--; i >= 0 ; i--) + device_remove_file(dev, attributes + i); + dev_err(dev, "%s: failed to create sysfs interface\n", __func__); + return -ENODEV; +} + +static int remove_sysfs_interfaces(struct device *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(attributes); i++) + device_remove_file(dev, attributes + i); + return 0; +} +#else +static inline int add_sysfs_interfaces(struct device *dev) +{ + return 0; +} + +static inline int remove_sysfs_interfaces(struct device *dev) +{ + return 0; +} +#endif + +static int __dw9763_set_power(struct dw9763_device *dw9763_dev, bool on) +{ + if (dw9763_dev->power_gpio) + gpiod_direction_output(dw9763_dev->power_gpio, on); + usleep_range(10000, 11000); + + return 0; +} + +static int __maybe_unused dw9763_check_id(struct dw9763_device *dw9763_dev) +{ + int ret = 0; + unsigned int pid = 0x00; + struct i2c_client *client = dw9763_dev->client; + struct device *dev = &client->dev; + + __dw9763_set_power(dw9763_dev, true); + ret = dw9763_read_reg(client, DW9763_REG_CHIP_ID, 1, &pid); + + if (pid != DW9763_CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", pid, ret); + return -ENODEV; + } + + dev_info(&dw9763_dev->client->dev, + "Detected dw9763 vcm id:0x%x\n", DW9763_CHIP_ID); + return 0; +} +static int dw9763_probe_init(struct i2c_client *client) +{ + int ret = 0; + + /* Default goto power down mode when finished probe */ + ret = dw9763_write_reg(client, 0x02, 1, 0x01); + if (ret) + goto err; + + return 0; +err: + dev_err(&client->dev, "probe init failed with error %d\n", ret); + return -1; +} + +static int dw9763_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device_node *np = of_node_get(client->dev.of_node); + struct dw9763_device *dw9763_dev; + unsigned int max_ma, start_ma, rated_ma, step_mode; + unsigned int t_src, t_div; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + + dev_info(&client->dev, "probing...\n"); + if (of_property_read_u32(np, + OF_CAMERA_VCMDRV_MAX_CURRENT, + (unsigned int *)&max_ma)) { + max_ma = DW9763_MAX_CURRENT; + dev_info(&client->dev, + "could not get module %s from dts!\n", + OF_CAMERA_VCMDRV_MAX_CURRENT); + } + if (max_ma == 0) + max_ma = DW9763_MAX_CURRENT; + + if (of_property_read_u32(np, + OF_CAMERA_VCMDRV_START_CURRENT, + (unsigned int *)&start_ma)) { + start_ma = DW9763_DEFAULT_START_CURRENT; + dev_info(&client->dev, + "could not get module %s from dts!\n", + OF_CAMERA_VCMDRV_START_CURRENT); + } + if (of_property_read_u32(np, + OF_CAMERA_VCMDRV_RATED_CURRENT, + (unsigned int *)&rated_ma)) { + rated_ma = DW9763_DEFAULT_RATED_CURRENT; + dev_info(&client->dev, + "could not get module %s from dts!\n", + OF_CAMERA_VCMDRV_RATED_CURRENT); + } + if (of_property_read_u32(np, + OF_CAMERA_VCMDRV_STEP_MODE, + (unsigned int *)&step_mode)) { + step_mode = DW9763_DEFAULT_STEP_MODE; + dev_info(&client->dev, + "could not get module %s from dts!\n", + OF_CAMERA_VCMDRV_STEP_MODE); + } + + if (of_property_read_u32(np, + OF_CAMERA_VCMDRV_T_SRC, + (unsigned int *)&t_src)) { + t_src = DW9763_DEFAULT_T_SACT; + dev_info(&client->dev, + "could not get module %s from dts!\n", + OF_CAMERA_VCMDRV_T_SRC); + } + + if (of_property_read_u32(np, + OF_CAMERA_VCMDRV_T_DIV, + (unsigned int *)&t_div)) { + t_div = DW9763_DEFAULT_T_DIV; + dev_info(&client->dev, + "could not get module %s from dts!\n", + OF_CAMERA_VCMDRV_T_DIV); + } + + dw9763_dev = devm_kzalloc(&client->dev, sizeof(*dw9763_dev), + GFP_KERNEL); + if (dw9763_dev == NULL) + return -ENOMEM; + + ret = of_property_read_u32(np, RKMODULE_CAMERA_MODULE_INDEX, + &dw9763_dev->module_index); + ret |= of_property_read_string(np, RKMODULE_CAMERA_MODULE_FACING, + &dw9763_dev->module_facing); + if (ret) { + dev_err(&client->dev, + "could not get module information!\n"); + return -EINVAL; + } + dw9763_dev->client = client; + dw9763_dev->power_gpio = devm_gpiod_get(&client->dev, + "power", GPIOD_OUT_LOW); + if (IS_ERR(dw9763_dev->power_gpio)) { + dw9763_dev->power_gpio = NULL; + dev_warn(&client->dev, + "Failed to get power-gpios, maybe no use\n"); + } + + /* enter power down mode */ + dw9763_probe_init(client); + + v4l2_i2c_subdev_init(&dw9763_dev->sd, client, &dw9763_ops); + dw9763_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dw9763_dev->sd.internal_ops = &dw9763_int_ops; + + ret = dw9763_init_controls(dw9763_dev); + if (ret) + goto err_cleanup; + + ret = media_entity_pads_init(&dw9763_dev->sd.entity, 0, NULL); + if (ret < 0) + goto err_cleanup; + + sd = &dw9763_dev->sd; + sd->entity.function = MEDIA_ENT_F_LENS; + + memset(facing, 0, sizeof(facing)); + if (strcmp(dw9763_dev->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + dw9763_dev->module_index, facing, + DW9763_NAME, dev_name(sd->dev)); + ret = v4l2_async_register_subdev(sd); + if (ret) + dev_err(&client->dev, "v4l2 async register subdev failed\n"); + + dw9763_dev->max_ma = max_ma; + dw9763_dev->vcm_cfg.start_ma = start_ma; + dw9763_dev->vcm_cfg.rated_ma = rated_ma; + dw9763_dev->vcm_cfg.step_mode = step_mode; + dw9763_update_vcm_cfg(dw9763_dev); + dw9763_dev->move_us = 0; + dw9763_dev->current_related_pos = VCMDRV_MAX_LOG; + dw9763_dev->start_move_tv = ns_to_kernel_old_timeval(ktime_get_ns()); + dw9763_dev->end_move_tv = ns_to_kernel_old_timeval(ktime_get_ns()); + + dw9763_dev->t_src = t_src; + dw9763_dev->t_div = t_div; + + i2c_set_clientdata(client, dw9763_dev); + mutex_init(&dw9763_dev->lock); + + dw9763_dev->vcm_movefull_t = + dw9763_move_time(dw9763_dev, DW9763_MAX_REG); + pm_runtime_set_active(&client->dev); + pm_runtime_enable(&client->dev); + pm_runtime_idle(&client->dev); + + add_sysfs_interfaces(&client->dev); + dev_info(&client->dev, "probing successful\n"); + + return 0; +err_cleanup: + dw9763_subdev_cleanup(dw9763_dev); + + dev_err(&client->dev, "Probe failed: %d\n", ret); + + return ret; +} + +static int dw9763_remove(struct i2c_client *client) +{ + struct dw9763_device *dw9763_dev = i2c_get_clientdata(client); + + remove_sysfs_interfaces(&client->dev); + mutex_destroy(&dw9763_dev->lock); + pm_runtime_disable(&client->dev); + dw9763_subdev_cleanup(dw9763_dev); + + return 0; +} + +static int dw9763_init(struct i2c_client *client) +{ + struct dw9763_device *dev_vcm = i2c_get_clientdata(client); + int ret = 0; + u32 ring = 0; + u32 mode_val = 0; + u32 algo_time = 0; + + + /* Delay 200us~300us */ + usleep_range(200, 300); + ret = dw9763_write_reg(client, 0x02, 1, 0x00); + if (ret) + goto err; + usleep_range(100, 200); + + if (dev_vcm->step_mode != DIRECT_MODE) + ring = 0x02; + ret = dw9763_write_reg(client, 0x02, 1, ring); + if (ret) + goto err; + switch (dev_vcm->step_mode) { + case SAC1_MODE: + case SAC2_MODE: + case SAC2_5_MODE: + case SAC3_MODE: + case SAC4_MODE: + mode_val |= dev_vcm->step_mode << 5; + break; + default: + break; + } + + mode_val |= (dev_vcm->t_div & 0x07); + algo_time = dev_vcm->t_src; + ret = dw9763_write_reg(client, 0x06, 1, mode_val); + if (ret) + goto err; + ret = dw9763_write_reg(client, 0x07, 1, algo_time); + if (ret) + goto err; + usleep_range(100, 200); + + return 0; +err: + dev_err(&client->dev, "init failed with error %d\n", ret); + return -1; +} + +static int __maybe_unused dw9763_vcm_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + int ret = 0; + + /* set to power down mode */ + ret = dw9763_write_reg(client, 0x02, 1, 0x01); + if (ret) + dev_err(&client->dev, "failed to set power down mode!\n"); + + return 0; +} + +static int __maybe_unused dw9763_vcm_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct dw9763_device *dev_vcm = i2c_get_clientdata(client); + + dw9763_init(client); + dw9763_set_pos(dev_vcm, dev_vcm->current_related_pos); + return 0; +} + +static const struct i2c_device_id dw9763_id_table[] = { + { DW9763_NAME, 0 }, + { { 0 } } +}; +MODULE_DEVICE_TABLE(i2c, dw9763_id_table); + +static const struct of_device_id dw9763_of_table[] = { + { .compatible = "dongwoon,dw9763" }, + { { 0 } } +}; +MODULE_DEVICE_TABLE(of, dw9763_of_table); + +static const struct dev_pm_ops dw9763_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dw9763_vcm_suspend, dw9763_vcm_resume) + SET_RUNTIME_PM_OPS(dw9763_vcm_suspend, dw9763_vcm_resume, NULL) +}; + +static struct i2c_driver dw9763_i2c_driver = { + .driver = { + .name = DW9763_NAME, + .pm = &dw9763_pm_ops, + .of_match_table = dw9763_of_table, + }, + .probe = &dw9763_probe, + .remove = &dw9763_remove, + .id_table = dw9763_id_table, +}; + +module_i2c_driver(dw9763_i2c_driver); + +MODULE_DESCRIPTION("DW9763 VCM driver"); +MODULE_LICENSE("GPL"); From 58a093602185b301c3ac043612af8bcf99d9ce2f Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Tue, 7 Feb 2023 09:30:02 +0000 Subject: [PATCH 130/258] arm64: rockchip_defconfig: enable dw9763 for rk3562-rk817-tablet Change-Id: I47ce770ebb4fd40ef7222c7b1861b80f8c83571c Signed-off-by: Jianwei Fan --- arch/arm64/configs/rockchip_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index 5672f6ee1f47..9ae06bf3b982 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -606,6 +606,7 @@ CONFIG_VIDEO_S5KJN1=y CONFIG_VIDEO_AW8601=y CONFIG_VIDEO_CN3927V=y CONFIG_VIDEO_DW9714=y +CONFIG_VIDEO_DW9763=y CONFIG_VIDEO_FP5510=y CONFIG_VIDEO_AW36518=y CONFIG_VIDEO_SGM3784=y From cc646fcd140eeef3e4f8a6f4dcfc8737911cc20a Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 10 Feb 2023 09:50:53 +0800 Subject: [PATCH 131/258] Revert "video: rockchip: rga3: disable memory when RGA power off to save power" This reverts commit 0a7cd35e38a4e9449e6037757a85b59e46d521ed. Signed-off-by: Yu Qiaowei Change-Id: I3d2c7a40ee3e0bc18fe802ce0b7a7e089ab58f3d --- drivers/video/rockchip/rga3/include/rga_drv.h | 8 -- drivers/video/rockchip/rga3/rga_drv.c | 74 +------------------ 2 files changed, 3 insertions(+), 79 deletions(-) diff --git a/drivers/video/rockchip/rga3/include/rga_drv.h b/drivers/video/rockchip/rga3/include/rga_drv.h index 9cd097a7cd2a..bfca12afc061 100644 --- a/drivers/video/rockchip/rga3/include/rga_drv.h +++ b/drivers/video/rockchip/rga3/include/rga_drv.h @@ -319,18 +319,10 @@ struct rga_timer { u32 busy_time_record; }; -struct rga_grf_info { - uint32_t offset; - uint32_t open_val; - uint32_t close_val; - struct regmap *grf; -}; - struct rga_scheduler_t { struct device *dev; void __iomem *rga_base; struct rga_iommu_info *iommu_info; - struct rga_grf_info grf_info; struct clk *clks[RGA_MAX_BUS_CLK]; int num_clks; diff --git a/drivers/video/rockchip/rga3/rga_drv.c b/drivers/video/rockchip/rga3/rga_drv.c index ae3b379a4e73..226fb773760d 100644 --- a/drivers/video/rockchip/rga3/rga_drv.c +++ b/drivers/video/rockchip/rga3/rga_drv.c @@ -7,9 +7,6 @@ #define pr_fmt(fmt) "rga: " fmt -#include -#include - #include "rga2_reg_info.h" #include "rga3_reg_info.h" #include "rga_dma_buf.h" @@ -375,62 +372,6 @@ static void rga_cancel_timer(void) } #ifndef RGA_DISABLE_PM -static int rga_grf_open(struct rga_scheduler_t *scheduler) -{ - if (scheduler->grf_info.grf && scheduler->grf_info.open_val) - regmap_write(scheduler->grf_info.grf, - scheduler->grf_info.offset, - scheduler->grf_info.open_val); - - return 0; -} - -static int rga_grf_close(struct rga_scheduler_t *scheduler) -{ - if (scheduler->grf_info.grf && scheduler->grf_info.close_val) - regmap_write(scheduler->grf_info.grf, - scheduler->grf_info.offset, - scheduler->grf_info.close_val); - - return 0; -} - -static int rga_grf_init(struct rga_scheduler_t *scheduler) -{ - int ret; - uint32_t grf_offset = 0; - uint32_t grf_open_value = 0, grf_close_value = 0; - struct device_node *np = scheduler->dev->of_node; - struct regmap *grf; - - grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); - if (IS_ERR_OR_NULL(grf)) - return -EINVAL; - - ret = of_property_read_u32(np, "rockchip,grf-offset", &grf_offset); - if (ret) - return -ENODATA; - - ret = of_property_read_u32_index(np, "rockchip,grf-values", - 0, &grf_open_value); - if (ret) - return -ENODATA; - - ret = of_property_read_u32_index(np, "rockchip,grf-values", - 1, &grf_close_value); - if (ret) - return -ENODATA; - - scheduler->grf_info.grf = grf; - scheduler->grf_info.offset = grf_offset; - scheduler->grf_info.open_val = grf_open_value; - scheduler->grf_info.close_val = grf_close_value; - - pr_info("%s grf init successfully.\n", dev_driver_string(scheduler->dev)); - - return 0; -} - int rga_power_enable(struct rga_scheduler_t *scheduler) { int ret = -EINVAL; @@ -451,10 +392,8 @@ int rga_power_enable(struct rga_scheduler_t *scheduler) spin_lock_irqsave(&scheduler->irq_lock, flags); scheduler->pd_refcount++; - if (scheduler->status == RGA_SCHEDULER_IDLE) { + if (scheduler->status == RGA_SCHEDULER_IDLE) scheduler->status = RGA_SCHEDULER_WORKING; - rga_grf_open(scheduler); - } spin_unlock_irqrestore(&scheduler->irq_lock, flags); @@ -486,10 +425,8 @@ int rga_power_disable(struct rga_scheduler_t *scheduler) } scheduler->pd_refcount--; - if (scheduler->pd_refcount == 0) { + if (scheduler->pd_refcount == 0) scheduler->status = RGA_SCHEDULER_IDLE; - rga_grf_close(scheduler); - } spin_unlock_irqrestore(&scheduler->irq_lock, flags); @@ -1425,9 +1362,8 @@ static int rga_drv_probe(struct platform_device *pdev) return ret; } -#ifndef RGA_DISABLE_PM - rga_grf_init(scheduler); +#ifndef RGA_DISABLE_PM /* clk init */ for (i = 0; i < match_data->num_clks; i++) { struct clk *clk = devm_clk_get(dev, match_data->clks[i]); @@ -1458,8 +1394,6 @@ static int rga_drv_probe(struct platform_device *pdev) } } } - - rga_grf_open(scheduler); #endif /* #ifndef RGA_DISABLE_PM */ scheduler->ops->get_version(scheduler); @@ -1485,8 +1419,6 @@ static int rga_drv_probe(struct platform_device *pdev) data->num_of_scheduler++; #ifndef RGA_DISABLE_PM - rga_grf_close(scheduler); - for (i = scheduler->num_clks - 1; i >= 0; i--) if (!IS_ERR(scheduler->clks[i])) clk_disable_unprepare(scheduler->clks[i]); From 707da1d0cb1011cfac8c802efa4e05f2711ec6a5 Mon Sep 17 00:00:00 2001 From: Jake Wu Date: Sun, 15 Jan 2023 08:48:48 +0000 Subject: [PATCH 132/258] arm64: dts: rockchip: rk3562-test2: enable usb nodes This enable usb20-otg. Signed-off-by: Jake Wu Signed-off-by: William Wu Change-Id: I82a8e1417a7e4318e77d19504365bdd5908cbf3e --- .../dts/rockchip/rk3562-test2-ddr4-v10.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi index 312abc96ca57..d638ac0103eb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi @@ -89,3 +89,27 @@ &pwm6 { status = "okay"; }; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + From 390dee5bd8014d2ee27ad80c846c00427373869d Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 31 Jan 2023 10:38:54 +0800 Subject: [PATCH 133/258] drm/rockchip: vop3: add xmirror register define Signed-off-by: Sandy Huang Change-Id: I3e6653efb208b53f7a858904b7babaf092a6841f --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 55d6107604e2..5e7f3bc64e85 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -783,6 +783,7 @@ static const struct vop2_video_port_regs rk3528_vop_vp0_regs = { .dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6), .dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7), .dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8), + .dsp_x_mir_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 13), .post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15), .pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16), .dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17), @@ -856,6 +857,7 @@ static const struct vop2_video_port_regs rk3528_vop_vp1_regs = { .dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6), .dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7), .dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8), + .dsp_x_mir_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 13), .post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15), .pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16), .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17), @@ -969,6 +971,7 @@ static const struct vop2_video_port_regs rk3562_vop_vp0_regs = { .dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6), .dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7), .dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8), + .dsp_x_mir_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 13), .post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15), .pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16), .dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17), @@ -1036,6 +1039,7 @@ static const struct vop2_video_port_regs rk3562_vop_vp1_regs = { .dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6), .dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7), .dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8), + .dsp_x_mir_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 13), .post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15), .pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16), .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17), From cb9f78f78e39fbaf7dfd0196ef15ba2f3793cc98 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Fri, 10 Feb 2023 17:03:27 +0800 Subject: [PATCH 134/258] drm/rockchip: vop3: alloc hdr gem object when first use it the vop is binded before iommu init, if alloc hdr gem object in vop bind stage, which may get the wrong dma address. To fix this issue, alloc hdr gem object when first used it. Signed-off-by: Zhang Yubing Change-Id: I99359cc345cb49aee1ce34ff6d5ee33d04ac2283 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 686835c160be..3f95763a57c3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -7911,6 +7911,7 @@ static void vop3_setup_hdrvivid(struct vop2_video_port *vp, uint8_t win_phys_id) int phys_id; struct hdrvivid_regs *hdrvivid_data; struct hdr_extend *hdr_data; + struct rockchip_gem_object *lut_gem_obj; bool have_sdr_layer = false; uint32_t hdr_mode; int i; @@ -8025,6 +8026,16 @@ static void vop3_setup_hdrvivid(struct vop2_video_port *vp, uint8_t win_phys_id) vop2_writel(vop2, RK3528_HDR_CSC_COE20_21, hdrvivid_data->hdr_csc_coe20_21); vop2_writel(vop2, RK3528_HDR_CSC_COE22, hdrvivid_data->hdr_csc_coe22); + if (!vp->hdr_lut_gem_obj) { + lut_gem_obj = rockchip_gem_create_object(vop2->drm_dev, + RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH * 4, true, 0); + if (IS_ERR(lut_gem_obj)) { + DRM_ERROR("create hdr lut obj failed\n"); + return; + } + vp->hdr_lut_gem_obj = lut_gem_obj; + } + tone_lut_kvaddr = (u32 *)vp->hdr_lut_gem_obj->kvaddr; tone_lut_mst = vp->hdr_lut_gem_obj->dma_addr; @@ -10948,15 +10959,8 @@ static int vop2_create_crtc(struct vop2 *vop2) "Failed to init %s with SR helpers %d, ignoring\n", crtc->name, ret); - if (vp_data->feature & VOP_FEATURE_VIVID_HDR) { + if (vp_data->feature & VOP_FEATURE_VIVID_HDR) vop2_crtc_create_hdr_property(vop2, crtc); - vp->hdr_lut_gem_obj = rockchip_gem_create_object(vop2->drm_dev, - RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH * 4, true, 0); - if (IS_ERR(vp->hdr_lut_gem_obj)) { - DRM_ERROR("create hdr lut obj failed\n"); - return -ENOMEM; - } - } if (vp_data->feature & VOP_FEATURE_POST_ACM) vop2_crtc_create_post_acm_property(vop2, crtc); if (vp_data->feature & VOP_FEATURE_POST_CSC) From c6165d6923e0554f068cf809fd1469c74b0fb245 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Thu, 9 Feb 2023 19:35:51 +0800 Subject: [PATCH 135/258] drm/rockchip: vop3: implement get property function for hdr, csc, acm Signed-off-by: Zhang Yubing Change-Id: Ia89c70387a6e3093f327ff71c61886066935b7bc --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 3f95763a57c3..574172068dae 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -9842,14 +9842,20 @@ static int vop2_crtc_atomic_get_property(struct drm_crtc *crtc, return 0; } - if (property == vp->hdr_ext_data_prop) + if (property == vp->hdr_ext_data_prop) { + *val = vcstate->hdr_ext_data ? vcstate->hdr_ext_data->base.id : 0; return 0; + } - if (property == vp->acm_lut_data_prop) + if (property == vp->acm_lut_data_prop) { + *val = vcstate->acm_lut_data ? vcstate->acm_lut_data->base.id : 0; return 0; + } - if (property == vp->post_csc_data_prop) + if (property == vp->post_csc_data_prop) { + *val = vcstate->post_csc_data ? vcstate->post_csc_data->base.id : 0; return 0; + } DRM_ERROR("failed to get vop2 crtc property: %s\n", property->name); From ed46f27f29c172387659910d149495239921d41f Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Mon, 13 Feb 2023 15:59:46 +0800 Subject: [PATCH 136/258] arm64: dts: rockchip: rk3562: fix pinctrl cam m0/m1 clk0/clk1 Signed-off-by: Steven Liu Change-Id: Iebf5c036af34478a44047ec55f71bb67f0f7e11e --- .../boot/dts/rockchip/rk3562-pinctrl.dtsi | 27 +++++++++++++------ 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi index dcf7feb3f554..a2c9f208d6dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi @@ -13,20 +13,30 @@ &pinctrl { cam { /omit-if-no-ref/ - camm0_pins: camm0-pins { + camm0_clk0_out: camm0-clk0-out { rockchip,pins = - /* cam_clk0_out_m0 */ - <3 RK_PB2 2 &pcfg_pull_none>, - /* cam_clk1_out_m0 */ + /* camm0_clk0_out */ + <3 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm0_clk1_out: camm0-clk1-out { + rockchip,pins = + /* camm0_clk1_out */ <3 RK_PB3 2 &pcfg_pull_none>; }; /omit-if-no-ref/ - camm1_pins: camm1-pins { + camm1_clk0_out: camm1-clk0-out { rockchip,pins = - /* cam_clk0_out_m1 */ - <4 RK_PB1 3 &pcfg_pull_none>, - /* cam_clk1_out_m1 */ + /* camm1_clk0_out */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk1_out: camm1-clk1-out { + rockchip,pins = + /* camm1_clk1_out */ <4 RK_PB7 3 &pcfg_pull_none>; }; @@ -36,6 +46,7 @@ /* cam_clk2_out */ <3 RK_PB4 2 &pcfg_pull_none>; }; + /omit-if-no-ref/ cam_clk3_out: cam-clk3-out { rockchip,pins = From 61c9d9c4b89d2a94ba18e64795c76749dc31bc32 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Tue, 3 Jan 2023 16:49:39 +0800 Subject: [PATCH 137/258] arm64: dts: rockchip: add camera dtsi for rk3562 evb1 Add dts for gc8034 on rk3562 evb1 board. Signed-off-by: Zefa Chen Change-Id: I64f34f37522a861b96ed509f95415dc0372bac97 Signed-off-by: Xu Hongfei --- .../boot/dts/rockchip/rk3562-evb1-cam.dtsi | 213 ++++++++++++++++++ .../dts/rockchip/rk3562-evb1-lp4x-v10.dtsi | 1 + 2 files changed, 214 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-cam.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-cam.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb1-cam.dtsi new file mode 100644 index 000000000000..b66f45e15824 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-cam.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5695_out0>; + data-lanes = <1 2>; + }; + + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc_mipicsi0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&dw9714>; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc_mipicsi0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out0: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi index c910ed867442..bfd17a8d4af1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi @@ -9,6 +9,7 @@ #include "dt-bindings/usb/pd.h" #include "rk3562.dtsi" #include "rk3562-evb.dtsi" +#include "rk3562-evb1-cam.dtsi" #include #include #include From 53881cfb5fce9d3c5cc1592f6ef0dacdfb60d981 Mon Sep 17 00:00:00 2001 From: Jianlong Wang Date: Sat, 9 Jul 2022 14:33:54 +0800 Subject: [PATCH 138/258] arm64: configs: add rockchip_linux_docker.config enable kernel config for docker for rk356x: make ARCH=arm64 rockchip_linux_defconfig rockchip_linux_docker.config for rk3588: make ARCH=arm64 rockchip_linux_defconfig rk3588_linux.config rockchip_linux_docker.config Signed-off-by: Jianlong Wang Change-Id: Idf52c56a30d6918ea12fb985c14dacccfaeb2583 --- .../configs/rockchip_linux_docker.config | 244 ++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 arch/arm64/configs/rockchip_linux_docker.config diff --git a/arch/arm64/configs/rockchip_linux_docker.config b/arch/arm64/configs/rockchip_linux_docker.config new file mode 100644 index 000000000000..3d82af600d37 --- /dev/null +++ b/arch/arm64/configs/rockchip_linux_docker.config @@ -0,0 +1,244 @@ +CONFIG_BLK_CGROUP=y +CONFIG_BLK_DEV_DM=y +CONFIG_BPF_SYSCALL=y +CONFIG_BRIDGE=y +CONFIG_BTRFS_FS=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_XXHASH=y +CONFIG_DUMMY=y +CONFIG_HUGETLBFS=y +CONFIG_INET_ESP=y +CONFIG_IPVLAN=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_VS=y +CONFIG_MACVLAN=y +CONFIG_MEMCG=y +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_SCHED=y +CONFIG_NF_CONNTRACK=y +CONFIG_OVERLAY_FS=y +CONFIG_POSIX_MQUEUE=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_VETH=y +CONFIG_VLAN_8021Q=y +CONFIG_VXLAN=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +# CONFIG_BCM_SBA_RAID is not set +# CONFIG_BLK_CGROUP_IOCOST is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOPRIO is not set +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BPF_EVENTS=y +# CONFIG_BPF_PRELOAD is not set +# CONFIG_BPF_STREAM_PARSER is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_MRP is not set +CONFIG_BRIDGE_NETFILTER=y +# CONFIG_BRIDGE_NF_EBTABLES is not set +CONFIG_BRIDGE_VLAN_FILTERING=y +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_REF_VERIFY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_DM_BIO_PRISON=y +# CONFIG_DM_BOW is not set +CONFIG_DM_BUFIO=y +# CONFIG_DM_CACHE is not set +# CONFIG_DM_CLONE is not set +# CONFIG_DM_CRYPT is not set +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_EBS is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_INIT is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_MULTIPATH is not set +CONFIG_DM_PERSISTENT_DATA=y +# CONFIG_DM_RAID is not set +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_SWITCH is not set +CONFIG_DM_THIN_PROVISIONING=y +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_USER=y +# CONFIG_DM_VERITY is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ZERO is not set +CONFIG_DST_CACHE=y +CONFIG_HUGETLB_PAGE=y +# CONFIG_INET_ESPINTCP is not set +# CONFIG_INET_ESP_OFFLOAD is not set +CONFIG_IPVLAN_L3S=y +# CONFIG_IPVTAP is not set +CONFIG_IP_NF_NAT=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +# CONFIG_IP_VS_DEBUG is not set +# CONFIG_IP_VS_DH is not set +# CONFIG_IP_VS_FO is not set +# CONFIG_IP_VS_FTP is not set +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_LBLC is not set +# CONFIG_IP_VS_LBLCR is not set +# CONFIG_IP_VS_LC is not set +# CONFIG_IP_VS_MH is not set +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NFCT=y +# CONFIG_IP_VS_NQ is not set +# CONFIG_IP_VS_OVF is not set +# CONFIG_IP_VS_PROTO_AH is not set +# CONFIG_IP_VS_PROTO_ESP is not set +# CONFIG_IP_VS_PROTO_SCTP is not set +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=y +# CONFIG_IP_VS_SED is not set +# CONFIG_IP_VS_SH is not set +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +# CONFIG_IP_VS_WLC is not set +# CONFIG_IP_VS_WRR is not set +CONFIG_LLC=y +# CONFIG_MACVTAP is not set +CONFIG_MEMCG_KMEM=y +CONFIG_MEMCG_SWAP=y +CONFIG_MQ_IOSCHED_DEADLINE_CGROUP=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +# CONFIG_NETFILTER_XT_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +CONFIG_NETFILTER_XT_MATCH_IPVS=y +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +CONFIG_NETFILTER_XT_NAT=y +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_ACT is not set +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_BPF is not set +CONFIG_NET_CLS_CGROUP=y +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_EMATCH is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_DEFAULT is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_ETS is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_TEQL is not set +CONFIG_NET_UDP_TUNNEL=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_BRIDGE is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_LABELS is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_TFTP=y +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +# CONFIG_NF_CT_NETLINK is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_DEFRAG_IPV6=y +CONFIG_NF_NAT=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_TFTP=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_METACOPY is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +CONFIG_PAGE_COUNTER=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_RAID6_PQ=y +CONFIG_RAID6_PQ_BENCHMARK=y +# CONFIG_SLUB_MEMCG_SYSFS_ON is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_STP=y +CONFIG_TASKS_TRACE_RCU=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_XDP_SOCKETS is not set +CONFIG_XFRM_ESP=y +CONFIG_XOR_BLOCKS=y From e4d1514867ef75ed0a24a0948f81ba4803fceae9 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Fri, 10 Feb 2023 17:59:05 +0800 Subject: [PATCH 139/258] drm/rockchip: gem: fix for VVOP enabled but VOP and VOP2 not In some case we need to select the CONFIG_ROCKCHIP_VVOP but unselect the CONFIG_ROCKCHIP_VOP and CONFIG_ROCKCHIP_VOP2, this patch can fix it to not do vop iommu map/unmap. Change-Id: Ib48a11fd1dc6c0230701edb94c19c9f2a1a08a0a Signed-off-by: Jianqun Xu --- drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index 5e71093c9a2e..df985456b598 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -414,6 +414,11 @@ static void rockchip_gem_free_secure(struct rockchip_gem_object *rk_obj) rk_obj->base.size); } +static inline bool is_vop_enabled(void) +{ + return (IS_ENABLED(CONFIG_ROCKCHIP_VOP) || IS_ENABLED(CONFIG_ROCKCHIP_VOP2)); +} + static int rockchip_gem_alloc_buf(struct rockchip_gem_object *rk_obj, bool alloc_kmap) { @@ -422,7 +427,7 @@ static int rockchip_gem_alloc_buf(struct rockchip_gem_object *rk_obj, struct rockchip_drm_private *private = drm->dev_private; int ret = 0; - if (!private->domain) + if (!private->domain && is_vop_enabled()) rk_obj->flags |= ROCKCHIP_BO_CONTIG; if (rk_obj->flags & ROCKCHIP_BO_SECURE) { @@ -462,7 +467,7 @@ static int rockchip_gem_alloc_buf(struct rockchip_gem_object *rk_obj, ret = rockchip_gem_iommu_map(rk_obj); if (ret < 0) goto err_free; - } else { + } else if (is_vop_enabled()) { WARN_ON(!rk_obj->dma_handle); rk_obj->dma_addr = rk_obj->dma_handle; } From 24250deb774ccab3ce5fc78d1eaaf5ea2bdb3dbb Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Sun, 15 Jan 2023 12:16:36 +0000 Subject: [PATCH 140/258] arm64: dts: rockchip: rk3562-rk817-tablet: add camera configuration Change-Id: I57b5841eb91c2a6a7cd3650bf1a75695aa646a4c Signed-off-by: Jianwei Fan --- .../rockchip/rk3562-rk817-tablet-camera.dtsi | 307 ++++++++++++++++++ .../dts/rockchip/rk3562-rk817-tablet-v10.dts | 1 + 2 files changed, 308 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-camera.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-camera.dtsi new file mode 100644 index 000000000000..ac0586411d97 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-camera.dtsi @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ +/ { + vcc_mipipwr: vcc-mipipwr-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicam_pwr>; + regulator-name = "vcc_mipipwr"; + enable-active-high; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + + dw9763: dw9763@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13855: ov13855@36 { + status = "okay"; + compatible = "ovti,ov13855"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc_mipipwr>; + dvdd-supply = <&vcc1v2_dvp>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "KYT-10203-v1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763>; + + port { + ov13855_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc_mipipwr>; + dvdd-supply = <&vcc1v2_dvp>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "KYT-10203-v1"; + rockchip,camera-module-lens-name = "default"; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0_in0>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp_vir0_in1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + isp_vir0_in1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + cam { + mipicam_pwr: mipicam-pwr { + rockchip,pins = + /* camera power en */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts index 38c916ccb47a..22cc6295ae55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts @@ -14,6 +14,7 @@ #include "dt-bindings/usb/pd.h" #include "rk3562.dtsi" #include "rk3562-android.dtsi" +#include "rk3562-rk817-tablet-camera.dtsi" / { model = "Rockchip RK3562 RK817 TABLET LP4 Board"; From 3d2844c61ba1fc3e1a39f482955d8aba8008cfe8 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Sat, 11 Feb 2023 10:31:36 +0800 Subject: [PATCH 141/258] ARM: dts: rockchip: rk3036: add spdif-sound node Change-Id: I34672a839876afa1e54c70b151f90479bb8f8a19 Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3036.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 447218d5d74b..0c5d5090c4ab 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -408,6 +408,20 @@ status = "disabled"; }; + spdif_tx: spdif-tx@10204000 { + compatible = "rockchip,rk3066-spdif"; + reg = <0x10204000 0x1000>; + clocks = <&cru SCLK_SPDIF>, <&cru SCLK_SPDIF>; + clock-names = "mclk", "hclk"; + interrupts = ; + dmas = <&pdma 13>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_out>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sfc: sfc@10208000 { compatible = "rockchip,sfc"; reg = <0x10208000 0x200>; @@ -902,6 +916,12 @@ }; }; + spdif_tx { + spdif_out: spdif-out { + rockchip,pins = <0 RK_PD4 1 &pcfg_pull_default>; + }; + }; + emac { emac_xfer: emac-xfer { rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ From 5ee5151fed4fccc013809c721aad0d1186ca68ef Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Sat, 11 Feb 2023 10:34:06 +0800 Subject: [PATCH 142/258] ARM: dts: rockchip: rk3036: remove hdmi_sound node Change-Id: I3cb4010e255559c31eb0fe46c14b3f700b060d64 Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3036.dtsi | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 0c5d5090c4ab..da80ff303164 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -589,25 +589,6 @@ }; }; - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,hdmi"; - simple-audio-card,widgets = "Headphone", "Out Jack", - "Line", "In Jack"; - status = "disabled"; - - simple-audio-card,dai-link { - format = "i2s"; - mclk-fs = <256>; - cpu { - sound-dai = <&i2s>; - }; - codec { - sound-dai = <&hdmi>; - }; - }; - }; - timer: timer@20044000 { compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; From ec0ab209677f087feb04628c00bd4a8b659200ba Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Sat, 11 Feb 2023 10:36:39 +0800 Subject: [PATCH 143/258] ARM: dts: rockchip: rk3036: update acodec compatible to rockchip,rk3036-codec Change-Id: I094a62ccd06f4b62bb175cc7260117622628cd30 Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3036.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index da80ff303164..33092646c064 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -557,7 +557,7 @@ }; acodec: acodec-ana@20030000 { - compatible = "rk3036-codec"; + compatible = "rockchip,rk3036-codec"; reg = <0x20030000 0x4000>; rockchip,grf = <&grf>; clock-names = "acodec_pclk"; From b7b36e0653d03bc03efdf84010fdaf6625eadbc2 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Sat, 11 Feb 2023 10:39:49 +0800 Subject: [PATCH 144/258] ARM: dts: rockchip: rk3036-evb1: add support multi-sounds and spdif-sound Change-Id: Id0f7286003f08aeb0632a28cf1f08c1f2799010b Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts | 64 ++++++++++++++++++++-- 1 file changed, 59 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts index 9884deec143a..2936812493f5 100644 --- a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts +++ b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts @@ -22,12 +22,60 @@ reg = <0x60000000 0x20000000>; }; - multi_sound: multi-sound { + multi_sounds: multi-sounds { status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip,hdmi-codec"; - rockchip,cpu = <&i2s>; - rockchip,codec = <&acodec>, <&hdmi>; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,rk3036-sounds"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s>; + }; + codec { + sound-dai = <&acodec>; + }; + }; + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&i2s>; + }; + codec { + sound-dai = <&hdmi>; + }; + }; + simple-audio-card,dai-link@2 { + format = "i2s"; + cpu { + sound-dai = <&i2s>; + }; + codec { + sound-dai = <&es8311>; + }; + }; + }; + + spdiftx_codec: spdiftx-codec { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-sound"; + simple-audio-card,dai-link { + mclk-fs = <256>; + cpu { + sound-dai = <&spdif_tx>; + }; + codec { + sound-dai = <&spdiftx_codec>; + }; + }; }; vdd_arm: vdd-arm-regulator { @@ -118,6 +166,7 @@ }; &hdmi { + #sound-dai-cells = <0>; status = "okay"; }; @@ -437,6 +486,11 @@ status = "okay"; }; +&spdif_tx { + status = "okay"; + #sound-dai-cells = <0>; +}; + &pinctrl { usb { host_vbus_drv: host-vbus-drv { From 3ab683e330b580793747ec16aed096d8e8b08d6e Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Thu, 9 Feb 2023 10:18:32 +0800 Subject: [PATCH 145/258] ARM: dts: rockchip: rk3036-evb1: fix es8311 default aec mode For products with light performance like RK3036, the playback function may not be so important, and the stereo recording can be guaranteed first. Therefore, the default left channel is ADC input data. Change-Id: Iffc51986f58fd5946a35ea39d12104b2e1f2d39f Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts index 2936812493f5..756f94a12b38 100644 --- a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts +++ b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts @@ -205,7 +205,7 @@ adc-pga-gain = <8>; adc-volume = <0xdf>; dac-volume = <0xbf>; - aec-mode = "dac left, adc right"; + aec-mode = "adc left, adc right"; pinctrl-names = "default"; pinctrl-0 = <&i2s_mclk>; From 0ce21e247761c214c7d9c43e600a6fe78c0e9212 Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Tue, 7 Feb 2023 21:07:58 +0800 Subject: [PATCH 146/258] video: rockchip: mpp: fix jpege dma coherence issue for rkvenc2 Signed-off-by: Yandong Lin Change-Id: Ida23480b46ce37bcd40b1f7de7907e889b267fc4 --- drivers/video/rockchip/mpp/mpp_rkvenc2.c | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/video/rockchip/mpp/mpp_rkvenc2.c b/drivers/video/rockchip/mpp/mpp_rkvenc2.c index d68e1316c315..4d911088f215 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvenc2.c +++ b/drivers/video/rockchip/mpp/mpp_rkvenc2.c @@ -226,6 +226,10 @@ struct rkvenc_task { u32 slice_wr_cnt; u32 slice_rd_cnt; DECLARE_KFIFO(slice_info, union rkvenc2_slice_len_info, RKVENC_MAX_SLICE_FIFO_LEN); + + /* jpege bitstream */ + struct dma_buf *dmabuf_bs; + u32 offset_bs; }; #define RKVENC_MAX_RCB_NUM (4) @@ -921,6 +925,24 @@ static void *rkvenc_alloc_task(struct mpp_session *session, if (!reg) continue; + if (fmt == RKVENC_FMT_JPEGE && class == RKVENC_CLASS_PIC && + !task->dmabuf_bs) { + int bs_fd, bs_index; + struct dma_buf *dmabuf_bs; + + bs_index = mpp->var->trans_info[fmt].table[2]; + bs_fd = reg[bs_index]; + task->offset_bs = mpp_query_reg_offset_info(&task->off_inf, + bs_index + ss); + dmabuf_bs = dma_buf_get(bs_fd); + if (!IS_ERR(dmabuf_bs)) { + dma_buf_end_cpu_access_partial(dmabuf_bs, + DMA_TO_DEVICE, + 0, task->offset_bs); + task->dmabuf_bs = dmabuf_bs; + } + } + ret = mpp_translate_reg_address(session, mpp_task, fmt, reg, NULL); if (ret) goto fail; @@ -943,6 +965,11 @@ static void *rkvenc_alloc_task(struct mpp_session *session, return mpp_task; fail: + if (task->dmabuf_bs) { + dma_buf_put(task->dmabuf_bs); + task->dmabuf_bs = NULL; + task->offset_bs = 0; + } mpp_task_dump_mem_region(mpp, mpp_task); mpp_task_dump_reg(mpp, mpp_task); mpp_task_finalize(session, mpp_task); @@ -1381,6 +1408,13 @@ static int rkvenc_finish(struct mpp_dev *mpp, struct mpp_task *mpp_task) } + if (task->dmabuf_bs) { + u32 bs_size = mpp_read(mpp, 0x4064); + + dma_buf_begin_cpu_access_partial(task->dmabuf_bs, DMA_FROM_DEVICE, 0, + bs_size / 8 + task->offset_bs); + } + /* revert hack for irq status */ reg = rkvenc_get_class_reg(task, task->hw_info->int_sta_base); if (reg) @@ -1422,6 +1456,12 @@ static int rkvenc_free_task(struct mpp_session *session, { struct rkvenc_task *task = to_rkvenc_task(mpp_task); + if (task->dmabuf_bs) { + dma_buf_put(task->dmabuf_bs); + task->dmabuf_bs = NULL; + task->offset_bs = 0; + } + mpp_task_finalize(session, mpp_task); rkvenc_free_class_msg(task); kfree(task); From ddea4b4025d5b2eae83fb96f8ea8ca4baf9e2b6d Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 9 Feb 2023 13:03:32 +0800 Subject: [PATCH 147/258] clk: rockchip: rk3562: change pll to slow mode before power down Signed-off-by: Finley Xiao Change-Id: I7ee6d2478bc012bf70ca061738534ed57d1612f0 --- drivers/clk/rockchip/clk-pll.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index b076568cb377..15e41d50f107 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -647,17 +647,25 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, static int rockchip_rk3036_pll_enable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), pll->reg_base + RK3036_PLLCON(1)); rockchip_rk3036_pll_wait_lock(pll); + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + return 0; } static void rockchip_rk3036_pll_disable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, RK3036_PLLCON1_PWRDOWN, 0), From 813eabe45b0f10796abb0753ae69244ecf38c3c6 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 9 Feb 2023 14:25:39 +0800 Subject: [PATCH 148/258] clk: rockchip: rk3562: Make aclk pclk core CLK_IGNORE_UNUSED Don't add enable count to apll. Signed-off-by: Finley Xiao Change-Id: Id970ba227033599e894b3108af29bc6d2ae0cda5 --- drivers/clk/rockchip/clk-rk3562.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c index ae80763a6d84..68e0e241db06 100644 --- a/drivers/clk/rockchip/clk-rk3562.c +++ b/drivers/clk/rockchip/clk-rk3562.c @@ -466,10 +466,10 @@ static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = { RK3562_CLKGATE_CON(27), 2, GFLAGS), /* PD_CORE */ - COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IS_CRITICAL, + COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED, RK3562_CLKSEL_CON(11), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3562_CLKGATE_CON(4), 3, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IS_CRITICAL, + COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED, RK3562_CLKSEL_CON(12), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3562_CLKGATE_CON(4), 5, GFLAGS), COMPOSITE_NOMUX(HCLK_CORE, "hclk_core", "gpll", CLK_IS_CRITICAL, From deb2de164b73fd609532e7ae5a04b1fe7e3fbc32 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 9 Feb 2023 15:27:01 +0800 Subject: [PATCH 149/258] clk: rockchip: rk3562: Add ROCKCHIP_PLL_ALLOW_POWER_DOWN flag Signed-off-by: Finley Xiao Change-Id: I7047fee17bd26e6b23fb84b431010880ff577276 --- drivers/clk/rockchip/clk-pll.c | 7 +++++-- drivers/clk/rockchip/clk.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 15e41d50f107..91a067401967 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1685,8 +1685,11 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, init.name = pll_name; #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE - /* keep all plls untouched for now */ - init.flags = flags | CLK_IGNORE_UNUSED; + if (clk_pll_flags & ROCKCHIP_PLL_ALLOW_POWER_DOWN) + init.flags = flags; + else + /* keep all plls untouched for now */ + init.flags = flags | CLK_IGNORE_UNUSED; #else init.flags = flags; #endif diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 4ace4dfb0a3f..79852e59a0c7 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -578,6 +578,7 @@ struct rockchip_pll_clock { #define ROCKCHIP_PLL_SYNC_RATE BIT(0) /* normal mode only. now only for pll_rk3036, pll_rk3328 type */ #define ROCKCHIP_PLL_FIXED_MODE BIT(1) +#define ROCKCHIP_PLL_ALLOW_POWER_DOWN BIT(2) #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ _lshift, _pflags, _rtable) \ From 9fe7f3814761de221745826c3f2e3a7fda0f44ad Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 9 Feb 2023 15:29:08 +0800 Subject: [PATCH 150/258] clk: rockchip: rk3562: Add ROCKCHIP_PLL_ALLOW_POWER_DOWN for apll vpp and hpll Signed-off-by: Finley Xiao Change-Id: I95661f4f17245487169afd7f8a70f845f95ddb6d --- drivers/clk/rockchip/clk-rk3562.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c index 68e0e241db06..d88791d4d529 100644 --- a/drivers/clk/rockchip/clk-rk3562.c +++ b/drivers/clk/rockchip/clk-rk3562.c @@ -194,16 +194,19 @@ PNAME(clk_mipidsi_ref_p) = { "clk_mipidsiphy_xin24m", "clk_24m_sscsrc" }; static struct rockchip_pll_clock rk3562_pll_clks[] __initdata = { [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3562_PLL_CON(0), - RK3562_MODE_CON, 0, 0, 0, rk3562_pll_rates), + RK3562_MODE_CON, 0, 0, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, RK3562_PLL_CON(24), RK3562_MODE_CON, 2, 3, 0, rk3562_pll_rates), [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, 0, RK3562_PLL_CON(32), - RK3562_MODE_CON, 6, 4, 0, rk3562_pll_rates), + RK3562_MODE_CON, 6, 4, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, 0, RK3562_PLL_CON(40), - RK3562_MODE_CON, 8, 5, 0, rk3562_pll_rates), + RK3562_MODE_CON, 8, 5, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, RK3562_PMU1_PLL_CON(0), RK3562_PMU1_MODE_CON, 0, 2, 0, rk3562_pll_rates), From b38fc755a5e3b70805fd3be1157ec3d21f6951fb Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Thu, 1 Sep 2022 17:42:41 +0800 Subject: [PATCH 151/258] media: rockchip: isp: add isp32 lite Change-Id: I3cdd29809e629df7903605d07e2dd2da40bcef01 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/capture.c | 19 +- .../media/platform/rockchip/isp/capture_v32.c | 200 ++++-- drivers/media/platform/rockchip/isp/common.h | 1 + drivers/media/platform/rockchip/isp/csi.c | 7 +- drivers/media/platform/rockchip/isp/dev.c | 24 +- drivers/media/platform/rockchip/isp/dmarx.c | 22 +- drivers/media/platform/rockchip/isp/hw.c | 34 +- drivers/media/platform/rockchip/isp/hw.h | 1 + .../platform/rockchip/isp/isp_params_v32.c | 617 +++++++++++++++--- .../platform/rockchip/isp/isp_params_v32.h | 9 + .../platform/rockchip/isp/isp_stats_v32.c | 519 ++++++++++++--- .../platform/rockchip/isp/isp_stats_v32.h | 6 +- drivers/media/platform/rockchip/isp/procfs.c | 40 +- drivers/media/platform/rockchip/isp/regs.c | 60 ++ drivers/media/platform/rockchip/isp/regs.h | 3 +- .../media/platform/rockchip/isp/regs_v3x.h | 98 +++ drivers/media/platform/rockchip/isp/rkisp.c | 64 +- drivers/media/platform/rockchip/isp/rkisp.h | 6 +- include/uapi/linux/rkisp32-config.h | 119 ++++ 19 files changed, 1535 insertions(+), 314 deletions(-) diff --git a/drivers/media/platform/rockchip/isp/capture.c b/drivers/media/platform/rockchip/isp/capture.c index 19c1b0000412..a361021c3ef1 100644 --- a/drivers/media/platform/rockchip/isp/capture.c +++ b/drivers/media/platform/rockchip/isp/capture.c @@ -18,11 +18,11 @@ #define STREAM_MAX_SP_RSZ_OUTPUT_WIDTH 1920 #define STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT 1080 #define STREAM_MIN_RSZ_OUTPUT_WIDTH 32 -#define STREAM_MIN_RSZ_OUTPUT_HEIGHT 16 +#define STREAM_MIN_RSZ_OUTPUT_HEIGHT 32 #define STREAM_OUTPUT_STEP_WISE 8 -#define STREAM_MIN_MP_SP_INPUT_WIDTH 32 -#define STREAM_MIN_MP_SP_INPUT_HEIGHT 32 +#define STREAM_MIN_MP_SP_INPUT_WIDTH STREAM_MIN_RSZ_OUTPUT_WIDTH +#define STREAM_MIN_MP_SP_INPUT_HEIGHT STREAM_MIN_RSZ_OUTPUT_HEIGHT static int hdr_dma_frame(struct rkisp_device *dev) { @@ -739,7 +739,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, /* 128bit AXI, 16byte align for bytesperline */ if ((dev->isp_ver == ISP_V20 && stream->id == RKISP_STREAM_SP) || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + dev->isp_ver >= ISP_V30) plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline, 16); plane_fmt->sizeimage = plane_fmt->bytesperline * height; @@ -1685,6 +1685,13 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev) st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32; st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32; ret = rkisp_register_stream_v32(dev); + } else if (dev->isp_ver == ISP_V32_L) { + st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L; + st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32_L; + st_cfg = &rkisp_sp_stream_config; + st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L; + st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32_L; + ret = rkisp_register_stream_v32(dev); } INIT_WORK(&cap_dev->fast_work, rkisp_stream_fast); @@ -1701,7 +1708,7 @@ void rkisp_unregister_stream_vdevs(struct rkisp_device *dev) rkisp_unregister_stream_v21(dev); else if (dev->isp_ver == ISP_V30) rkisp_unregister_stream_v30(dev); - else if (dev->isp_ver == ISP_V32) + else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L) rkisp_unregister_stream_v32(dev); } @@ -1715,6 +1722,6 @@ void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev) rkisp_mi_v21_isr(mis_val, dev); else if (dev->isp_ver == ISP_V30) rkisp_mi_v30_isr(mis_val, dev); - else if (dev->isp_ver == ISP_V32) + else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L) rkisp_mi_v32_isr(mis_val, dev); } diff --git a/drivers/media/platform/rockchip/isp/capture_v32.c b/drivers/media/platform/rockchip/isp/capture_v32.c index 565d7e4e5f39..05f4fc1e5e2f 100644 --- a/drivers/media/platform/rockchip/isp/capture_v32.c +++ b/drivers/media/platform/rockchip/isp/capture_v32.c @@ -13,13 +13,16 @@ #include "dev.h" #include "regs.h" -/* +/* ISP32 * |--mainpath----[wrap]--------->enc(or ddr) * | |->mainpath_4x4sampling--->ddr *output->|->bypasspath----------------->ddr * | |->bypasspath_4x4sampling->ddr * |->selfpath------------------->ddr * |->lumapath------------------->ddr + * ISP32_LITE + *output->|--mainpath------------------->ddr + * |--selfpath------------------->ddr */ #define CIF_ISP_REQ_BUFS_MIN 0 @@ -184,7 +187,7 @@ static const struct capture_fmt sp_fmts[] = { .bpp = { 32 }, .mplanes = 1, .write_format = MI_CTRL_SP_WRITE_PLA, - .output_format = MI_CTRL_SP_OUTPUT_RGB888, + .output_format = MI_CTRL_SP_OUTPUT_ARGB888, }, { .fourcc = V4L2_PIX_FMT_RGB565, .fmt_type = FMT_RGB, @@ -195,6 +198,110 @@ static const struct capture_fmt sp_fmts[] = { }, }; +static const struct capture_fmt sp_fmts_lite[] = { + /* yuv422 */ + { + .fourcc = V4L2_PIX_FMT_UYVY, + .fmt_type = FMT_YUV, + .bpp = { 16 }, + .cplanes = 1, + .mplanes = 1, + .uv_swap = 0, + .write_format = MI_CTRL_SP_WRITE_INT, + .output_format = MI_CTRL_SP_OUTPUT_YUV422, + }, { + .fourcc = V4L2_PIX_FMT_NV16, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 1, + .uv_swap = 0, + .write_format = MI_CTRL_SP_WRITE_SPLA, + .output_format = MI_CTRL_SP_OUTPUT_YUV422, + }, { + .fourcc = V4L2_PIX_FMT_NV61, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 1, + .uv_swap = 1, + .write_format = MI_CTRL_SP_WRITE_SPLA, + .output_format = MI_CTRL_SP_OUTPUT_YUV422, + }, + /* yuv420 */ + { + .fourcc = V4L2_PIX_FMT_NV21, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 1, + .uv_swap = 1, + .write_format = MI_CTRL_SP_WRITE_SPLA, + .output_format = MI_CTRL_SP_OUTPUT_YUV420, + }, { + .fourcc = V4L2_PIX_FMT_NV12, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 1, + .uv_swap = 0, + .write_format = MI_CTRL_SP_WRITE_SPLA, + .output_format = MI_CTRL_SP_OUTPUT_YUV420, + }, { + .fourcc = V4L2_PIX_FMT_NV21M, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 2, + .uv_swap = 1, + .write_format = MI_CTRL_SP_WRITE_SPLA, + .output_format = MI_CTRL_SP_OUTPUT_YUV420, + }, { + .fourcc = V4L2_PIX_FMT_NV12M, + .fmt_type = FMT_YUV, + .bpp = { 8, 16 }, + .cplanes = 2, + .mplanes = 2, + .uv_swap = 0, + .write_format = MI_CTRL_SP_WRITE_SPLA, + .output_format = MI_CTRL_SP_OUTPUT_YUV420, + }, + /* yuv400 */ + { + .fourcc = V4L2_PIX_FMT_GREY, + .fmt_type = FMT_YUV, + .bpp = { 8 }, + .cplanes = 1, + .mplanes = 1, + .uv_swap = 0, + .write_format = MI_CTRL_SP_WRITE_PLA, + .output_format = MI_CTRL_SP_OUTPUT_YUV400, + }, + /* rgb */ + { + .fourcc = V4L2_PIX_FMT_XBGR32, + .fmt_type = FMT_RGB, + .bpp = { 32 }, + .mplanes = 1, + .write_format = MI_CTRL_SP_WRITE_PLA, + .output_format = MI_CTRL_SP_OUTPUT_ARGB888, + }, { + .fourcc = V4L2_PIX_FMT_RGB565, + .fmt_type = FMT_RGB, + .bpp = { 16 }, + .mplanes = 1, + .write_format = MI_CTRL_SP_WRITE_PLA, + .output_format = MI_CTRL_SP_OUTPUT_RGB565, + }, { + .fourcc = V4L2_PIX_FMT_RGB24, + .fmt_type = FMT_RGB, + .bpp = { 24 }, + .mplanes = 1, + .write_format = MI_CTRL_SP_WRITE_PLA, + .output_format = MI_CTRL_SP_OUTPUT_RGB888, + }, +}; + static const struct capture_fmt bp_fmts[] = { { .fourcc = V4L2_PIX_FMT_UYVY, @@ -596,8 +703,13 @@ static int mp_config_mi(struct rkisp_stream *stream) rkisp_clear_bits(dev, 0x1814, BIT(0), false); } val = out_fmt->plane_fmt[0].bytesperline; - rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); + /* in bytes for isp32 */ + if (dev->isp_ver == ISP_V32) + rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); val /= DIV_ROUND_UP(fmt->bpp[0], 8); + /* in pixels for isp32 lite */ + if (dev->isp_ver == ISP_V32_L) + rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false); val *= height; rkisp_write(dev, stream->config->mi.y_pic_size, val, false); val = out_fmt->plane_fmt[0].bytesperline * height; @@ -909,6 +1021,8 @@ static void update_mi(struct rkisp_stream *stream) u32 val, reg; bool is_cr_cfg = false; + if (dev->isp_ver == ISP_V32_L) + dummy_buf = &dev->hw_dev->dummy_buf; if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP) is_cr_cfg = true; @@ -960,11 +1074,14 @@ static void update_mi(struct rkisp_stream *stream) stream->next_buf = NULL; } } else if (dummy_buf->mem_priv) { - /* wrap buf ENC */ val = dummy_buf->dma_addr; reg = stream->config->mi.y_base_ad_init; rkisp_write(dev, reg, val, false); - val += stream->out_fmt.plane_fmt[0].bytesperline * dev->cap_dev.wrap_line; + /* wrap buf ENC */ + if (dev->isp_ver == ISP_V32) + val += stream->out_fmt.plane_fmt[0].bytesperline * dev->cap_dev.wrap_line; + else + stream->dbg.frameloss++; reg = stream->config->mi.cb_base_ad_init; rkisp_write(dev, reg, val, false); if (is_cr_cfg) { @@ -1209,9 +1326,10 @@ static struct streams_ops rkisp_luma_streams_ops = { static int mi_frame_start(struct rkisp_stream *stream, u32 mis) { + struct rkisp_device *dev = stream->ispdev; unsigned long lock_flags = 0; - if (stream->streaming) { + if (stream->streaming && dev->isp_ver == ISP_V32) { rkisp_rockit_buf_done(stream, ROCKIT_DVBM_START); rkisp_rockit_ctrl_fps(stream); } @@ -1371,7 +1489,7 @@ static int rkisp_start(struct rkisp_stream *stream) } if (dev->hw_dev->is_single) stream_self_update(stream); - if (stream->ops->enable_mi) + if (stream->ops->enable_mi && !stream->is_pause) stream->ops->enable_mi(stream); if (is_update) @@ -1699,7 +1817,8 @@ rkisp_start_streaming(struct vb2_queue *queue, unsigned int count) if (ret < 0) goto buffer_done; - if (count == 0 && !stream->dummy_buf.mem_priv && + if (dev->isp_ver == ISP_V32 && + count == 0 && !stream->dummy_buf.mem_priv && list_empty(&stream->buf_queue)) { v4l2_err(v4l2_dev, "no buf for %s\n", node->vdev.name); ret = -EINVAL; @@ -1805,8 +1924,13 @@ static int rkisp_stream_init(struct rkisp_device *dev, u32 id) strscpy(vdev->name, SP_VDEV_NAME, sizeof(vdev->name)); stream->ops = &rkisp_sp_streams_ops; stream->config = &rkisp_sp_stream_config; - stream->config->fmts = sp_fmts; - stream->config->fmt_size = ARRAY_SIZE(sp_fmts); + if (dev->isp_ver == ISP_V32) { + stream->config->fmts = sp_fmts; + stream->config->fmt_size = ARRAY_SIZE(sp_fmts); + } else { + stream->config->fmts = sp_fmts_lite; + stream->config->fmt_size = ARRAY_SIZE(sp_fmts_lite); + } break; case RKISP_STREAM_BP: strscpy(vdev->name, BP_VDEV_NAME, sizeof(vdev->name)); @@ -1869,28 +1993,29 @@ int rkisp_register_stream_v32(struct rkisp_device *dev) struct rkisp_capture_device *cap_dev = &dev->cap_dev; int ret; - rkisp_dvbm_get(dev); - - rkisp_rockit_dev_init(dev); - ret = rkisp_stream_init(dev, RKISP_STREAM_MP); if (ret < 0) goto err; ret = rkisp_stream_init(dev, RKISP_STREAM_SP); if (ret < 0) goto err_free_mp; - ret = rkisp_stream_init(dev, RKISP_STREAM_BP); - if (ret < 0) - goto err_free_sp; - ret = rkisp_stream_init(dev, RKISP_STREAM_MPDS); - if (ret < 0) - goto err_free_bp; - ret = rkisp_stream_init(dev, RKISP_STREAM_BPDS); - if (ret < 0) - goto err_free_mpds; - ret = rkisp_stream_init(dev, RKISP_STREAM_LUMA); - if (ret < 0) - goto err_free_bpds; + + if (dev->isp_ver == ISP_V32) { + ret = rkisp_stream_init(dev, RKISP_STREAM_BP); + if (ret < 0) + goto err_free_sp; + ret = rkisp_stream_init(dev, RKISP_STREAM_MPDS); + if (ret < 0) + goto err_free_bp; + ret = rkisp_stream_init(dev, RKISP_STREAM_BPDS); + if (ret < 0) + goto err_free_mpds; + ret = rkisp_stream_init(dev, RKISP_STREAM_LUMA); + if (ret < 0) + goto err_free_bpds; + rkisp_dvbm_get(dev); + rkisp_rockit_dev_init(dev); + } return 0; err_free_bpds: rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_BPDS]); @@ -1911,20 +2036,21 @@ void rkisp_unregister_stream_v32(struct rkisp_device *dev) struct rkisp_capture_device *cap_dev = &dev->cap_dev; struct rkisp_stream *stream; - rkisp_rockit_dev_deinit(); - stream = &cap_dev->stream[RKISP_STREAM_MP]; rkisp_unregister_stream_vdev(stream); stream = &cap_dev->stream[RKISP_STREAM_SP]; - rkisp_unregister_stream_vdev(stream); - stream = &cap_dev->stream[RKISP_STREAM_BP]; - rkisp_unregister_stream_vdev(stream); - stream = &cap_dev->stream[RKISP_STREAM_MPDS]; - rkisp_unregister_stream_vdev(stream); - stream = &cap_dev->stream[RKISP_STREAM_BPDS]; - rkisp_unregister_stream_vdev(stream); - stream = &cap_dev->stream[RKISP_STREAM_LUMA]; - rkisp_unregister_stream_vdev(stream); + if (dev->isp_ver == ISP_V32) { + rkisp_unregister_stream_vdev(stream); + stream = &cap_dev->stream[RKISP_STREAM_BP]; + rkisp_unregister_stream_vdev(stream); + stream = &cap_dev->stream[RKISP_STREAM_MPDS]; + rkisp_unregister_stream_vdev(stream); + stream = &cap_dev->stream[RKISP_STREAM_BPDS]; + rkisp_unregister_stream_vdev(stream); + stream = &cap_dev->stream[RKISP_STREAM_LUMA]; + rkisp_unregister_stream_vdev(stream); + rkisp_rockit_dev_deinit(); + } } /**************** Interrupter Handler ****************/ diff --git a/drivers/media/platform/rockchip/isp/common.h b/drivers/media/platform/rockchip/isp/common.h index aa50cb36420f..609d95074c04 100644 --- a/drivers/media/platform/rockchip/isp/common.h +++ b/drivers/media/platform/rockchip/isp/common.h @@ -74,6 +74,7 @@ enum rkisp_isp_ver { ISP_V21 = 0x50, ISP_V30 = 0x60, ISP_V32 = 0x70, + ISP_V32_L = 0x80, }; enum rkisp_sd_type { diff --git a/drivers/media/platform/rockchip/isp/csi.c b/drivers/media/platform/rockchip/isp/csi.c index 12ec032fd2c3..4e7d28f3fe67 100644 --- a/drivers/media/platform/rockchip/isp/csi.c +++ b/drivers/media/platform/rockchip/isp/csi.c @@ -599,8 +599,7 @@ int rkisp_csi_config_patch(struct rkisp_device *dev) v4l2_subdev_call(mipi_sensor, core, ioctl, RKISP_VICAP_CMD_MODE, &mode); dev->vicap_in = mode.input; /* vicap direct to isp */ - if ((dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) && - !mode.rdbk_mode) { + if (dev->isp_ver >= ISP_V30 && !mode.rdbk_mode) { switch (dev->hdr.op_mode) { case HDR_RDBK_FRAME3: dev->hdr.op_mode = HDR_LINEX3_DDR; @@ -664,7 +663,7 @@ int rkisp_csi_config_patch(struct rkisp_device *dev) rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true, dev->hw_dev->is_unite); - if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + if (dev->isp_ver >= ISP_V30) rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, true, dev->hw_dev->is_unite); @@ -733,7 +732,7 @@ int rkisp_register_csi_subdev(struct rkisp_device *dev, csi_dev->pads[CSI_SRC_CH2].flags = MEDIA_PAD_FL_SOURCE; csi_dev->pads[CSI_SRC_CH3].flags = MEDIA_PAD_FL_SOURCE; csi_dev->pads[CSI_SRC_CH4].flags = MEDIA_PAD_FL_SOURCE; - } else if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { + } else if (dev->isp_ver >= ISP_V30) { return 0; } diff --git a/drivers/media/platform/rockchip/isp/dev.c b/drivers/media/platform/rockchip/isp/dev.c index 8333ba9aef56..51efdfd457d2 100644 --- a/drivers/media/platform/rockchip/isp/dev.c +++ b/drivers/media/platform/rockchip/isp/dev.c @@ -286,8 +286,7 @@ static int rkisp_pipeline_close(struct rkisp_pipeline *p) atomic_dec(&p->power_cnt); - if (!atomic_read(&p->power_cnt) && - (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)) + if (!atomic_read(&p->power_cnt) && dev->isp_ver >= ISP_V30) rkisp_rx_buf_pool_free(dev); return 0; @@ -508,7 +507,7 @@ static int _set_pipeline_default_fmt(struct rkisp_device *dev, bool is_init) #endif } - if (dev->isp_ver == ISP_V32) { + if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L) { struct v4l2_pix_format_mplane pixm = { .width = width, .height = height, @@ -517,12 +516,14 @@ static int _set_pipeline_default_fmt(struct rkisp_device *dev, bool is_init) rkisp_dmarx_set_fmt(&dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0], pixm); rkisp_dmarx_set_fmt(&dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2], pixm); - rkisp_set_stream_def_fmt(dev, RKISP_STREAM_BP, - width, height, V4L2_PIX_FMT_NV12); - rkisp_set_stream_def_fmt(dev, RKISP_STREAM_MPDS, - width / 4, height / 4, V4L2_PIX_FMT_NV12); - rkisp_set_stream_def_fmt(dev, RKISP_STREAM_BPDS, - width / 4, height / 4, V4L2_PIX_FMT_NV12); + if (dev->isp_ver == ISP_V32) { + rkisp_set_stream_def_fmt(dev, RKISP_STREAM_BP, + width, height, V4L2_PIX_FMT_NV12); + rkisp_set_stream_def_fmt(dev, RKISP_STREAM_MPDS, + width / 4, height / 4, V4L2_PIX_FMT_NV12); + rkisp_set_stream_def_fmt(dev, RKISP_STREAM_BPDS, + width / 4, height / 4, V4L2_PIX_FMT_NV12); + } } return 0; } @@ -891,9 +892,10 @@ static int rkisp_plat_probe(struct platform_device *pdev) pm_runtime_enable(dev); /* create & register platefom subdev (from of_node) */ ret = rkisp_register_platform_subdevs(isp_dev); - if (ret < 0) + if (ret < 0) { + v4l2_err(v4l2_dev, "Failed to register platform subdevs:%d\n", ret); goto err_unreg_media_dev; - + } rkisp_wait_line = 0; of_property_read_u32(dev->of_node, "wait-line", &rkisp_wait_line); diff --git a/drivers/media/platform/rockchip/isp/dmarx.c b/drivers/media/platform/rockchip/isp/dmarx.c index ef8a788de1cf..e190fef6386a 100644 --- a/drivers/media/platform/rockchip/isp/dmarx.c +++ b/drivers/media/platform/rockchip/isp/dmarx.c @@ -507,7 +507,7 @@ static void dmarx_stop(struct rkisp_stream *stream) !dev->hw_dev->is_shutdown) { ret = wait_event_timeout(stream->done, !stream->streaming, - msecs_to_jiffies(100)); + msecs_to_jiffies(300)); if (!ret) v4l2_warn(v4l2_dev, "dmarx:%d waiting on event return error %d\n", @@ -677,10 +677,7 @@ static void dmarx_stop_streaming(struct vb2_queue *queue) destroy_buf_queue(stream, VB2_BUF_STATE_ERROR); if (stream->id == RKISP_STREAM_RAWRD2 && - (stream->ispdev->isp_ver == ISP_V20 || - stream->ispdev->isp_ver == ISP_V21 || - stream->ispdev->isp_ver == ISP_V30 || - stream->ispdev->isp_ver == ISP_V32)) + stream->ispdev->isp_ver >= ISP_V20) kfifo_reset(&stream->ispdev->rdbk_kfifo); } @@ -793,10 +790,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, fmt->fmt_type == FMT_BAYER) height += RKMODULE_EXTEND_LINE; - if ((stream->ispdev->isp_ver == ISP_V20 || - stream->ispdev->isp_ver == ISP_V21 || - stream->ispdev->isp_ver == ISP_V30 || - stream->ispdev->isp_ver == ISP_V32) && + if (stream->ispdev->isp_ver >= ISP_V20 && fmt->fmt_type == FMT_BAYER && !stream->memory && stream->id != RKISP_STREAM_DMARX) @@ -1200,10 +1194,7 @@ int rkisp_register_dmarx_vdev(struct rkisp_device *dev) if (ret < 0) goto err; #endif - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || - dev->isp_ver == ISP_V32) { + if (dev->isp_ver >= ISP_V20) { ret = dmarx_init(dev, RKISP_STREAM_RAWRD0); if (ret < 0) goto err_free_dmarx; @@ -1240,10 +1231,7 @@ void rkisp_unregister_dmarx_vdev(struct rkisp_device *dev) rkisp_unregister_dmarx_video(stream); #endif - if (dev->isp_ver == ISP_V20 || - dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || - dev->isp_ver == ISP_V32) { + if (dev->isp_ver >= ISP_V20) { stream = &dmarx_dev->stream[RKISP_STREAM_RAWRD0]; rkisp_unregister_dmarx_video(stream); diff --git a/drivers/media/platform/rockchip/isp/hw.c b/drivers/media/platform/rockchip/isp/hw.c index 98ebb9d8f8dc..a11f3d1dff5a 100644 --- a/drivers/media/platform/rockchip/isp/hw.c +++ b/drivers/media/platform/rockchip/isp/hw.c @@ -121,6 +121,7 @@ static void default_sw_reg_flag(struct rkisp_device *dev) size = ARRAY_SIZE(v30_reg); break; case ISP_V32: + case ISP_V32_L: reg = v32_reg; size = ARRAY_SIZE(v32_reg); break; @@ -163,10 +164,7 @@ static irqreturn_t mipi_irq_hdl(int irq, void *ctx) if (err1 || err2 || err3) rkisp_mipi_v13_isr(err1, err2, err3, isp); - } else if (hw_dev->isp_ver == ISP_V20 || - hw_dev->isp_ver == ISP_V21 || - hw_dev->isp_ver == ISP_V30 || - hw_dev->isp_ver == ISP_V32) { + } else if (hw_dev->isp_ver >= ISP_V20) { u32 phy, packet, overflow, state; state = readl(base + CSI2RX_ERR_STAT); @@ -252,10 +250,7 @@ static irqreturn_t isp_irq_hdl(int irq, void *ctx) t = ktime_get(); mis_val = readl(base + CIF_ISP_MIS); - if (hw_dev->isp_ver == ISP_V20 || - hw_dev->isp_ver == ISP_V21 || - hw_dev->isp_ver == ISP_V30 || - hw_dev->isp_ver == ISP_V32) + if (hw_dev->isp_ver >= ISP_V20) mis_3a = readl(base + ISP_ISP3A_MIS); if (mis_val || mis_3a) rkisp_isp_isr(mis_val, mis_3a, isp); @@ -276,10 +271,7 @@ static irqreturn_t irq_handler(int irq, void *ctx) unsigned int mis_val, mis_3a = 0; mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS); - if (hw_dev->isp_ver == ISP_V20 || - hw_dev->isp_ver == ISP_V21 || - hw_dev->isp_ver == ISP_V30 || - hw_dev->isp_ver == ISP_V32) + if (hw_dev->isp_ver >= ISP_V20) mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS); if (mis_val || mis_3a) rkisp_isp_isr(mis_val, mis_3a, isp); @@ -663,6 +655,8 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure) writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN); writel(0x37, dev->base_addr + ISP32_MI_WR_WRAP_CTRL); + } else if (dev->isp_ver == ISP_V32_L) { + writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN); } } @@ -673,11 +667,12 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on) CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK | CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK; - if ((dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) && on) + if ((dev->isp_ver == ISP_V20 || dev->isp_ver >= ISP_V30) && on) val |= ICCL_MPFBC_CLK; - if (dev->isp_ver == ISP_V32) { + if (dev->isp_ver >= ISP_V32) { val |= ISP32_BRSZ_CLK_ENABLE | BIT(0) | BIT(16); - rv1106_sdmmc_get_lock(); + if (dev->isp_ver == ISP_V32) + rv1106_sdmmc_get_lock(); } writel(val, dev->base_addr + CIF_ICCL); if (dev->isp_ver == ISP_V32) @@ -693,8 +688,7 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on) CIF_CLK_CTRL_CP | CIF_CLK_CTRL_IE; writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12); - } else if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { + } else if (dev->isp_ver >= ISP_V20) { val = !on ? 0 : CLK_CTRL_MI_LDC | CLK_CTRL_MI_MP | CLK_CTRL_MI_JPEG | CLK_CTRL_MI_DP | @@ -703,7 +697,7 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on) CLK_CTRL_MI_READ | CLK_CTRL_MI_RAWRD | CLK_CTRL_ISP_RAW; - if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + if (dev->isp_ver >= ISP_V30) val = 0; if ((dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) && on) @@ -986,6 +980,7 @@ static int __maybe_unused rkisp_runtime_suspend(struct device *dev) hw_dev->dev_link_num = 0; hw_dev->is_single = true; hw_dev->is_multi_overflow = false; + hw_dev->is_frm_buf = false; disable_sys_clk(hw_dev); return pinctrl_pm_select_sleep_state(dev); } @@ -1001,6 +996,9 @@ void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev) hw_dev->max_in.h = 0; } hw_dev->dev_link_num = 0; + hw_dev->is_single = true; + hw_dev->is_multi_overflow = false; + hw_dev->is_frm_buf = false; for (i = 0; i < hw_dev->dev_num; i++) { isp = hw_dev->isp[i]; if (!isp || (isp && !isp->is_hw_link)) diff --git a/drivers/media/platform/rockchip/isp/hw.h b/drivers/media/platform/rockchip/isp/hw.h index 478d8b37542d..cd689701e005 100644 --- a/drivers/media/platform/rockchip/isp/hw.h +++ b/drivers/media/platform/rockchip/isp/hw.h @@ -100,6 +100,7 @@ struct rkisp_hw_dev { bool is_unite; bool is_multi_overflow; bool is_runing; + bool is_frm_buf; }; int rkisp_register_irq(struct rkisp_hw_dev *dev); diff --git a/drivers/media/platform/rockchip/isp/isp_params_v32.c b/drivers/media/platform/rockchip/isp/isp_params_v32.c index bd136d73a3cb..783a2c319297 100644 --- a/drivers/media/platform/rockchip/isp/isp_params_v32.c +++ b/drivers/media/platform/rockchip/isp/isp_params_v32.c @@ -9,21 +9,34 @@ #include "regs.h" #include "isp_params_v32.h" -#define ISP32_MODULE_EN BIT(0) -#define ISP32_SELF_FORCE_UPD BIT(31) -#define ISP32_REG_WR_MASK BIT(31) //disable write protect +#define ISP32_MODULE_EN BIT(0) +#define ISP32_SELF_FORCE_UPD BIT(31) +#define ISP32_REG_WR_MASK BIT(31) //disable write protect -#define ISP32_NOBIG_OVERFLOW_SIZE (1536 * 896) -#define ISP32_AUTO_BIGMODE_WIDTH 1536 -#define ISP32_VIR2_NOBIG_OVERFLOW_SIZE (960 * 540) -#define ISP32_VIR2_AUTO_BIGMODE_WIDTH 960 -#define ISP32_VIR4_NOBIG_OVERFLOW_SIZE (640 * 400) -#define ISP32_VIR4_AUTO_BIGMODE_WIDTH 640 +#define ISP32_NOBIG_OVERFLOW_SIZE (1536 * 896) +#define ISP32_AUTO_BIGMODE_WIDTH 1536 +#define ISP32_VIR2_NOBIG_OVERFLOW_SIZE (960 * 540) +#define ISP32_VIR2_AUTO_BIGMODE_WIDTH 960 +#define ISP32_VIR4_NOBIG_OVERFLOW_SIZE (640 * 400) +#define ISP32_VIR4_AUTO_BIGMODE_WIDTH 640 -#define ISP32_VIR2_MAX_WIDTH 1920 -#define ISP32_VIR2_MAX_SIZE (1920 * 1080) -#define ISP32_VIR4_MAX_WIDTH 1280 -#define ISP32_VIR4_MAX_SIZE (1280 * 800) +#define ISP32_VIR2_MAX_WIDTH 1920 +#define ISP32_VIR2_MAX_SIZE (1920 * 1080) +#define ISP32_VIR4_MAX_WIDTH 1280 +#define ISP32_VIR4_MAX_SIZE (1280 * 800) + +#define ISP32_LITE_NOBIG_OVERFLOW_SIZE (2688 * 1536) +#define ISP32_LITE_AUTO_BIGMODE_WIDTH 2688 +#define ISP32_LITE_VIR2_NOBIG_OVERFLOW_SIZE (1920 * 1080) +#define ISP32_LITE_VIR2_AUTO_BIGMODE_WIDTH 1920 +#define ISP32_LITE_VIR4_NOBIG_OVERFLOW_SIZE (1280 * 800) +#define ISP32_LITE_VIR4_AUTO_BIGMODE_WIDTH 1280 +#define ISP32_LITE_VIR2_MAX_WIDTH 3840 +#define ISP32_LITE_VIR2_MAX_SIZE (3840 * 2160) +#define ISP32_LITE_VIR4_MAX_WIDTH 2688 +#define ISP32_LITE_VIR4_MAX_SIZE (2688 * 1536) + +#define ISP32_LITE_FRM_BUF_SIZE 0x1d000 static inline void isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev, @@ -453,6 +466,68 @@ isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) ISP3X_ISP_CTRL0); } +static void __maybe_unused +isp_lsc_matrix_cfg_ddr(struct rkisp_isp_params_vdev *params_vdev, + const struct isp3x_lsc_cfg *pconfig) +{ + struct rkisp_isp_params_val_v32 *priv_val; + u32 data, buf_idx, *vaddr[4], index[4]; + void *buf_vaddr; + int i, j; + + memset(&index[0], 0, sizeof(index)); + priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + buf_idx = (priv_val->buf_lsclut_idx++) % ISP32_LSC_LUT_BUF_NUM; + buf_vaddr = priv_val->buf_lsclut[buf_idx].vaddr; + + vaddr[0] = buf_vaddr; + vaddr[1] = buf_vaddr + ISP32_LSC_LUT_TBL_SIZE; + vaddr[2] = buf_vaddr + ISP32_LSC_LUT_TBL_SIZE * 2; + vaddr[3] = buf_vaddr + ISP32_LSC_LUT_TBL_SIZE * 3; + + /* program data tables (table size is 9 * 17 = 153) */ + for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX; + i += CIF_ISP_LSC_SECTORS_MAX) { + /* + * 17 sectors with 2 values in one DWORD = 9 + * DWORDs (2nd value of last DWORD unused) + */ + for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) { + data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], + pconfig->r_data_tbl[i + j + 1]); + vaddr[0][index[0]++] = data; + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], + pconfig->gr_data_tbl[i + j + 1]); + vaddr[1][index[1]++] = data; + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], + pconfig->b_data_tbl[i + j + 1]); + vaddr[2][index[2]++] = data; + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], + pconfig->gb_data_tbl[i + j + 1]); + vaddr[3][index[3]++] = data; + } + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], 0); + vaddr[0][index[0]++] = data; + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], 0); + vaddr[1][index[1]++] = data; + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], 0); + vaddr[2][index[2]++] = data; + + data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], 0); + vaddr[3][index[3]++] = data; + } + rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_lsclut[buf_idx]); + data = priv_val->buf_lsclut[buf_idx].dma_addr; + isp3_param_write(params_vdev, data, ISP3X_MI_LUT_LSC_RD_BASE); + isp3_param_write(params_vdev, ISP32_LSC_LUT_TBL_SIZE, ISP3X_MI_LUT_LSC_RD_WSIZE); +} + static void isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, const struct isp3x_lsc_cfg *pconfig, @@ -469,7 +544,7 @@ isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, table = isp3_param_read_direct(params_vdev, ISP3X_LSC_STATUS); table &= ISP3X_LSC_ACTIVE_TABLE; /* default table 0 for multi device */ - if (!dev->hw_dev->is_single) + if (!dev->hw_dev->is_single || dev->isp_ver == ISP_V32_L) table = ISP3X_LSC_ACTIVE_TABLE; /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */ @@ -541,10 +616,24 @@ isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev, int i; lsc_ctrl = isp3_param_read(params_vdev, ISP3X_LSC_CTRL); - params_rec->others.lsc_cfg = *arg; - if (dev->hw_dev->is_single && (lsc_ctrl & ISP_LSC_EN)) - tasklet_schedule(&priv_val->lsc_tasklet); - + if (dev->isp_ver == ISP_V32_L) { + /* one lsc sram table + * online mode lsc lut load from ddr quick for some sensor VB short + * readback mode lsc lut AHB config to sram, once for single device, + * need record to switch for multi-device. + */ + if (!IS_HDR_RDBK(dev->rd_mode)) + isp_lsc_matrix_cfg_ddr(params_vdev, arg); + else if (dev->hw_dev->is_single) + isp_lsc_matrix_cfg_sram(params_vdev, arg, false); + else + params_rec->others.lsc_cfg = *arg; + } else { + /* two lsc sram table */ + params_rec->others.lsc_cfg = *arg; + if (dev->hw_dev->is_single && (lsc_ctrl & ISP_LSC_EN)) + tasklet_schedule(&priv_val->lsc_tasklet); + } for (i = 0; i < ISP32_LSC_SIZE_TBL_SIZE / 4; i++) { /* program x size tables */ data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2], arg->x_size_tbl[i * 2 + 1]); @@ -575,12 +664,15 @@ isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev, lsc_ctrl |= ISP3X_LSC_SECTOR_16X16; else lsc_ctrl &= ~ISP3X_LSC_SECTOR_16X16; + if (dev->isp_ver == ISP_V32_L && !IS_HDR_RDBK(dev->rd_mode)) + lsc_ctrl |= ISP3X_LSC_LUT_EN; isp3_param_write(params_vdev, lsc_ctrl, ISP3X_LSC_CTRL); } static void isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) { + struct rkisp_device *dev = params_vdev->dev; struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; u32 val = isp3_param_read(params_vdev, ISP3X_LSC_CTRL); @@ -589,8 +681,10 @@ isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) if (en) { val = ISP_LSC_EN | ISP32_SELF_FORCE_UPD; + if (dev->isp_ver == ISP_V32_L && !IS_HDR_RDBK(dev->rd_mode)) + val |= ISP3X_LSC_LUT_EN; isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, val); - if (params_vdev->dev->hw_dev->is_single) + if (dev->isp_ver == ISP_V32 && params_vdev->dev->hw_dev->is_single) isp_lsc_matrix_cfg_sram(params_vdev, ¶ms_rec->others.lsc_cfg, false); } else { @@ -608,8 +702,9 @@ isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev, value = isp3_param_read(params_vdev, ISP3X_DEBAYER_CONTROL); value &= ISP_DEBAYER_EN; - value |= !!arg->filter_c_en << 8 | - !!arg->filter_g_en << 4; + value |= !!arg->filter_g_en << 4; + if (params_vdev->dev->isp_ver == ISP_V32) + value |= !!arg->filter_c_en << 8; isp3_param_write(params_vdev, value, ISP3X_DEBAYER_CONTROL); value = (arg->max_ratio & 0x3F) << 24 | arg->select_thed << 16 | @@ -631,6 +726,9 @@ isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev, value = (arg->offset & 0x7FF); isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_FILTER_OFFSET); + if (params_vdev->dev->isp_ver != ISP_V32) + return; + value = arg->guid_gaus_coe2 << 16 | arg->guid_gaus_coe1 << 8 | arg->guid_gaus_coe0; isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_GUIDE_GAUS); @@ -938,8 +1036,8 @@ isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) } static void -isp_rawaebig_config_foraf(struct rkisp_isp_params_vdev *params_vdev, - const struct isp32_rawaf_meas_cfg *arg) +isp_rawae_config_foraf(struct rkisp_isp_params_vdev *params_vdev, + const struct isp32_rawaf_meas_cfg *arg) { u32 block_hsize, block_vsize; u32 addr, value; @@ -948,7 +1046,12 @@ isp_rawaebig_config_foraf(struct rkisp_isp_params_vdev *params_vdev, 1, 5, 15, 15 }; - addr = ISP3X_RAWAE_BIG1_BASE; + if (params_vdev->dev->isp_ver == ISP_V32_L && !!arg->ae_sel) { + wnd_num_idx = 1; + addr = ISP3X_RAWAE_LITE_BASE; + } else { + addr = ISP3X_RAWAE_BIG1_BASE; + } value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); value &= ISP3X_RAWAE_BIG_EN; @@ -1013,6 +1116,12 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, } isp3_param_write(params_vdev, var, ISP3X_RAWAF_INT_LINE); + if (params_vdev->dev->isp_ver == ISP_V32_L) { + var = (arg->hldg_dilate_num & 0x7) << 16 | + !!arg->bls_en << 12 | (arg->bls_offset & 0x1FF); + isp3_param_write(params_vdev, var, ISP32L_RAWAF_CTRL1); + } + var = isp3_param_read(params_vdev, ISP3X_RAWAF_THRES); var &= ~0xFFFF; var |= arg->afm_thres; @@ -1020,6 +1129,8 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, var = (arg->lum_var_shift[1] & 0x7) << 20 | (arg->lum_var_shift[0] & 0x7) << 16 | (arg->afm_var_shift[1] & 0x7) << 4 | (arg->afm_var_shift[0] & 0x7); + if (params_vdev->dev->isp_ver == ISP_V32_L) + var |= (arg->tnrin_shift & 0xf) << 8; isp3_param_write(params_vdev, var, ISP3X_RAWAF_VAR_SHIFT); for (i = 0; i < ISP32_RAWAF_GAMMA_NUM / 2; i++) { @@ -1029,8 +1140,9 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, var = ISP_PACK_2SHORT(arg->gamma_y[16], 0); isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y8); - var = (arg->v2iir_var_shift & 0x7) << 12 | (arg->v1iir_var_shift & 0x7) << 8 | - (arg->h2iir_var_shift & 0x7) << 4 | (arg->h1iir_var_shift & 0x7); + var = (arg->v1iir_var_shift & 0x7) << 8 | (arg->h1iir_var_shift & 0x7); + if (params_vdev->dev->isp_ver == ISP_V32) + var |= (arg->v2iir_var_shift & 0x7) << 12 | (arg->h2iir_var_shift & 0x7) << 4; isp3_param_write(params_vdev, var, ISP3X_RAWAF_HVIIR_VAR_SHIFT); var = ISP_PACK_2SHORT(arg->h_fv_thresh, arg->v_fv_thresh); @@ -1051,6 +1163,13 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, isp3_param_write(params_vdev, arg->highlit_thresh, ISP3X_RAWAF_HIGHLIT_THRESH); + if (params_vdev->dev->isp_ver == ISP_V32_L) { + var = ISP_PACK_2SHORT(arg->h_fv_limit, arg->h_fv_slope); + isp3_param_write(params_vdev, var, ISP32L_RAWAF_CORING_H); + var = ISP_PACK_2SHORT(arg->v_fv_limit, arg->v_fv_slope); + isp3_param_write(params_vdev, var, ISP32L_RAWAF_CORING_V); + } + viir_en = arg->viir_en; gaus_en = arg->gaus_en; v1_fir_sel = arg->v1_fir_sel; @@ -1066,6 +1185,10 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR1_COE01 + i * 4); var = ISP_PACK_2SHORT(arg->h1iir2_coe[i * 2], arg->h1iir2_coe[i * 2 + 1]); isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR2_COE01 + i * 4); + + if (params_vdev->dev->isp_ver == ISP_V32_L) + continue; + var = ISP_PACK_2SHORT(arg->h2iir1_coe[i * 2], arg->h2iir1_coe[i * 2 + 1]); isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR1_COE01 + i * 4); var = ISP_PACK_2SHORT(arg->h2iir2_coe[i * 2], arg->h2iir2_coe[i * 2 + 1]); @@ -1075,7 +1198,10 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, if (viir_en) { ctrl |= ISP3X_RAWAF_VIIR_EN; for (i = 0; i < ISP32_RAWAF_VIIR_COE_NUM; i++) { - var = ISP_PACK_2SHORT(arg->v1iir_coe[i], arg->v2iir_coe[i]); + if (params_vdev->dev->isp_ver == ISP_V32) + var = ISP_PACK_2SHORT(arg->v1iir_coe[i], arg->v2iir_coe[i]); + else + var = ISP_PACK_2SHORT(arg->v1iir_coe[i], 0); isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4); } } @@ -1099,30 +1225,52 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->from_awb << 18 | (arg->v_dnscl_mode & 0x3) << 16 | !!arg->sobel_sel << 15 | !!arg->vldg_sel << 14 | !!arg->y_mode << 13 | !!arg->ae_mode << 12 | - !!arg->v2_fv_mode << 11 | !!arg->v1_fv_mode << 10 | - !!arg->h2_fv_mode << 9 | !!arg->h1_fv_mode << 8 | + !!arg->v1_fv_mode << 10 | !!arg->h1_fv_mode << 8 | !!arg->accu_8bit_mode << 6 | !!v1_fir_sel << 3 | !!gaus_en << 2 | !!arg->gamma_en << 1; + if (params_vdev->dev->isp_ver == ISP_V32) + ctrl |= !!arg->v2_fv_mode << 11 | !!arg->h2_fv_mode << 9; + else + ctrl |= !!arg->hiir_left_border_mode << 21 | + !!arg->avg_ds_en << 22 | + !!arg->avg_ds_mode << 23 | + !!arg->h1_acc_mode << 24 | + !!arg->h2_acc_mode << 25 | + !!arg->v1_acc_mode << 26 | + !!arg->v2_acc_mode << 27 | + !!arg->ae_sel << 29; isp3_param_write(params_vdev, ctrl, ISP3X_RAWAF_CTRL); ctrl = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH); - if ((ctrl & ISP3X_RAWAF_SEL(3)) != ISP3X_RAWAF_SEL(arg->rawaf_sel)) { + if (((ctrl & ISP3X_RAWAF_SEL(3)) != ISP3X_RAWAF_SEL(arg->rawaf_sel)) || + (((!!(ctrl & ISP32L_BNR2AF_SEL)) != arg->bnr2af_sel) && + (params_vdev->dev->isp_ver == ISP_V32_L))) { + ctrl &= ~(ISP3X_RAWAF_SEL(3)); ctrl |= ISP3X_RAWAF_SEL(arg->rawaf_sel); + if (params_vdev->dev->isp_ver == ISP_V32_L) { + if (arg->bnr2af_sel) + ctrl |= ISP32L_BNR2AF_SEL; + else + ctrl &= ~ISP32L_BNR2AF_SEL; + } isp3_param_write(params_vdev, ctrl, ISP3X_VI_ISP_PATH); } params_vdev->afaemode_en = arg->ae_mode; if (params_vdev->afaemode_en) - isp_rawaebig_config_foraf(params_vdev, arg); + isp_rawae_config_foraf(params_vdev, arg); } static void -isp_rawaebig_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en) +isp_rawae_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en) { u32 exp_ctrl; u32 addr = ISP3X_RAWAE_BIG1_BASE; + if (params_vdev->dev->isp_ver == ISP_V32_L) + addr = ISP3X_RAWAE_LITE_BASE; + exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL); exp_ctrl &= ~ISP32_REG_WR_MASK; if (en) @@ -1146,7 +1294,7 @@ isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) isp3_param_write(params_vdev, afm_ctrl, ISP3X_RAWAF_CTRL); if (params_vdev->afaemode_en) { - isp_rawaebig_enable_foraf(params_vdev, en); + isp_rawae_enable_foraf(params_vdev, en); if (!en) params_vdev->afaemode_en = false; } @@ -1252,13 +1400,14 @@ isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev, if (arg->subwin_en[0]) value |= ISP3X_RAWAE_BIG_WND1_EN; - if (arg->subwin_en[1]) - value |= ISP3X_RAWAE_BIG_WND2_EN; - if (arg->subwin_en[2]) - value |= ISP3X_RAWAE_BIG_WND3_EN; - if (arg->subwin_en[3]) - value |= ISP3X_RAWAE_BIG_WND4_EN; - + if (params_vdev->dev->isp_ver == ISP_V32) { + if (arg->subwin_en[1]) + value |= ISP3X_RAWAE_BIG_WND2_EN; + if (arg->subwin_en[2]) + value |= ISP3X_RAWAE_BIG_WND3_EN; + if (arg->subwin_en[3]) + value |= ISP3X_RAWAE_BIG_WND4_EN; + } isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL); isp3_param_write(params_vdev, @@ -1384,7 +1533,7 @@ isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev *params_vdev, { u32 i, val = ISP32_MODULE_EN; - if (is_check && + if (params_vdev->dev->isp_ver == ISP_V32 && is_check && !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL) & val)) return; @@ -1406,7 +1555,7 @@ isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev, struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params; struct isp32_rawawb_meas_cfg *arg_rec = ¶ms_rec->meas.rawawb; const struct isp2x_bls_fixed_val *pval = &arg->bls2_val; - u32 value, val, mask; + u32 value, val, mask, i; value = isp3_param_read(params_vdev, ISP3X_BLS_CTRL); value &= ~ISP32_BLS_BLS2_EN; @@ -1448,6 +1597,8 @@ isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->blk_measure_xytype << 2 | !!arg->blk_measure_mode << 1 | !!arg->blk_measure_enable; + if (params_vdev->dev->isp_ver == ISP_V32_L) + value |= !!arg->ds16x8_mode_en << 7; isp3_param_write(params_vdev, value, ISP3X_RAWAWB_BLK_CTRL); isp3_param_write(params_vdev, @@ -2043,11 +2194,17 @@ isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev, arg->exc_wp_region6_weight, 0), ISP32_RAWAWB_EXC_WP_WEIGHT4_6); - if (params_vdev->dev->hw_dev->is_single) - isp_rawawb_cfg_sram(params_vdev, arg, false); - else - memcpy(arg_rec->wp_blk_wei_w, arg->wp_blk_wei_w, - ISP32_RAWAWB_WEIGHT_NUM); + if (params_vdev->dev->isp_ver == ISP_V32) { + if (params_vdev->dev->hw_dev->is_single) + isp_rawawb_cfg_sram(params_vdev, arg, false); + else + memcpy(arg_rec->wp_blk_wei_w, arg->wp_blk_wei_w, + ISP32_RAWAWB_WEIGHT_NUM); + } else { + for (i = 0; i < ISP32L_RAWAWB_WEIGHT_NUM; i++) + isp3_param_write(params_vdev, arg->win_weight[i], + ISP32L_RAWAWB_WIN_WEIGHT_0 + i * 4); + } /* avoid to override the old enable value */ value = isp3_param_read_cache(params_vdev, ISP3X_RAWAWB_CTRL); @@ -2112,9 +2269,10 @@ isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev, hist_ctrl &= ISP3X_RAWHIST_EN; hist_ctrl = hist_ctrl | ISP3X_RAWHIST_MODE(arg->mode) | - ISP3X_RAWHIST_DATASEL(arg->data_sel) | - ISP3X_RAWHIST_WATERLINE(arg->waterline) | ISP3X_RAWHIST_STEPSIZE(arg->stepsize); + if (params_vdev->dev->isp_ver == ISP_V32) + hist_ctrl |= ISP3X_RAWHIST_DATASEL(arg->data_sel) | + ISP3X_RAWHIST_WATERLINE(arg->waterline); isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL); isp3_param_write(params_vdev, @@ -2242,10 +2400,11 @@ isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev, hist_ctrl &= ISP3X_RAWHIST_EN; hist_ctrl = hist_ctrl | ISP3X_RAWHIST_MODE(arg->mode) | - ISP3X_RAWHIST_DATASEL(arg->data_sel) | - ISP3X_RAWHIST_WATERLINE(arg->waterline) | ISP3X_RAWHIST_WND_NUM(arg->wnd_num) | ISP3X_RAWHIST_STEPSIZE(arg->stepsize); + if (params_vdev->dev->isp_ver == ISP_V32) + hist_ctrl |= ISP3X_RAWHIST_DATASEL(arg->data_sel) | + ISP3X_RAWHIST_WATERLINE(arg->waterline); isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL); isp3_param_write(params_vdev, @@ -2465,7 +2624,10 @@ isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev, value = ISP_PACK_2SHORT(arg->scale_y[2 * i], 0); isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i); - value = ISP_PACK_2SHORT(arg->min_ogain, arg->iir_weight); + if (params_vdev->dev->isp_ver == ISP_V32) + value = ISP_PACK_2SHORT(arg->min_ogain, arg->iir_weight); + else + value = ISP_PACK_2SHORT(arg->min_ogain, 0); isp3_param_write(params_vdev, value, ISP3X_DRC_IIRWG_GAIN); value = arg->gas_t & 0x1fff; @@ -2875,6 +3037,8 @@ isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev, isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL3); value = ISP_PACK_2SHORT(arg->lbf_weight_thres, arg->frame_full_size); + if (params_vdev->dev->isp_ver == ISP_V32_L) + value |= (arg->frame_add4line & 0xf) << 12; isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL4); value = (arg->low_gauss1_coeff2 & 0xFFFF) << 16 | @@ -3059,8 +3223,12 @@ isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev, value |= !!arg->bypass << 1 | !!arg->center_mode << 2 | !!arg->exgain_bypass << 3 | - !!arg->radius_ds_mode << 4 | - !!arg->noiseclip_mode << 5; + !!arg->radius_ds_mode << 4; + if (params_vdev->dev->isp_ver == ISP_V32) + value |= !!arg->noiseclip_mode << 5; + else + value |= !!arg->clip_hf_mode << 6 | + !!arg->add_mode << 7; isp3_param_write(params_vdev, value, ISP3X_SHARP_EN); value = ISP_PACK_4BYTE(arg->pbf_ratio, arg->gaus_ratio, @@ -3154,9 +3322,35 @@ isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev, value = ISP_PACK_4BYTE(arg->strength[i * 4], arg->strength[i * 4 + 1], 0, 0); isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4); - value = (arg->noise_strength & 0x3fff) << 16 | (arg->enhance_bit & 0xf) << 12 | - (arg->noise_sigma & 0x3ff); - isp3_param_write(params_vdev, value, ISP32_SHARP_TEXTURE); + if (params_vdev->dev->isp_ver == ISP_V32) { + value = (arg->noise_strength & 0x3fff) << 16 | (arg->enhance_bit & 0xf) << 12 | + (arg->noise_sigma & 0x3ff); + isp3_param_write(params_vdev, value, ISP32_SHARP_TEXTURE); + } else { + value = (arg->ehf_th[2] & 0x3FF) << 20 | + (arg->ehf_th[1] & 0x3FF) << 10 | + (arg->ehf_th[0] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_0); + value = (arg->ehf_th[5] & 0x3FF) << 20 | + (arg->ehf_th[4] & 0x3FF) << 10 | + (arg->ehf_th[3] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_1); + value = (arg->ehf_th[7] & 0x3FF) << 10 | + (arg->ehf_th[6] & 0x3FF); + isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_2); + + value = (arg->clip_neg[2] & 0x3FF) << 20 | + (arg->clip_neg[1] & 0x3FF) << 10 | + (arg->clip_neg[0] & 0x3FF); + isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_0); + value = (arg->clip_neg[5] & 0x3FF) << 20 | + (arg->clip_neg[4] & 0x3FF) << 10 | + (arg->clip_neg[3] & 0x3FF); + isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_1); + value = (arg->clip_neg[7] & 0x3FF) << 10 | + (arg->clip_neg[6] & 0x3FF); + isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_2); + } } static void @@ -3266,13 +3460,14 @@ isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev, !!arg->logaus3_bypass_en << 10 | !!arg->logaus5_bypass_en << 9 | !!arg->lomed_bypass_en << 8 | - !!arg->hichnsplit_en << 7 | !!arg->hiabs_possel << 6 | !!arg->higaus_bypass_en << 5 | - !!arg->himed_bypass_en << 4 | //!!arg->lobypass_en << 3 | !!arg->hibypass_en << 2 | !!arg->bypass_en << 1; + if (params_vdev->dev->isp_ver == ISP_V32) + value |= !!arg->hichnsplit_en << 7 | + !!arg->himed_bypass_en << 4; if (!(value & ISP32_MODULE_EN)) { value &= ~ISP32_BAY3D_BWSAVING(1); if (arg->bwsaving_en) @@ -3286,17 +3481,21 @@ isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev, isp3_param_write(params_vdev, value, ISP3X_BAY3D_CTRL); value = !!arg->wgtmix_opt_en << 12 | - !!arg->higaus5x5_en << 11 | - (arg->higaus3_mode & 0x3) << 9 | !!arg->curds_high_en << 8 | !!arg->iirwr_rnd_en << 7 | - !!arg->pksig_ind_sel << 6 | - !!arg->hisig_ind_sel << 5 | !!arg->lo4x4_en << 4 | !!arg->lo4x8_en << 3 | !!arg->bwopt_gain_dis << 2 | - !!arg->hichncor_en << 1 | !!arg->hiwgt_opt_en; + if (params_vdev->dev->isp_ver == ISP_V32) + value |= !!arg->higaus5x5_en << 11 | + (arg->higaus3_mode & 0x3) << 9 | + !!arg->pksig_ind_sel << 6 | + !!arg->hisig_ind_sel << 5 | + !!arg->hichncor_en << 1; + else + value |= !!arg->wgtmm_sel_en << 14 | + !!arg->wgtmm_opt_en << 13; if (priv_val->is_lo8x8) value &= ~(BIT(3) | BIT(4)); else if (!(value & (BIT(3) | BIT(4)))) @@ -3335,6 +3534,11 @@ isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev, isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG2_Y0 + 4 * i); } + if (params_vdev->dev->isp_ver == ISP_V32_L) { + value = ISP_PACK_2SHORT(0, arg->wgtmin); + isp3_param_write(params_vdev, value, ISP3X_BAY3D_LODIF_STAT1); + } + value = ISP_PACK_2SHORT(arg->hisigrat0, arg->hisigrat1); isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGRAT); @@ -3347,8 +3551,9 @@ isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev, value = ISP_PACK_2SHORT(arg->rgain_off, arg->bgain_off); isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGPK); - value = ISP_PACK_4BYTE(arg->siggaus0, arg->siggaus1, - arg->siggaus2, arg->siggaus3); + value = ISP_PACK_4BYTE(arg->siggaus0, arg->siggaus1, arg->siggaus2, 0); + if (params_vdev->dev->isp_ver == ISP_V32) + value |= (arg->siggaus3 << 24); isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGGAUS); } @@ -3393,12 +3598,15 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) value = priv_val->bay3d_cur_wsize; isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_LENGTH); isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_LENGTH); - value = priv_val->bay3d_cur_wrap_line << 16 | 28; + value = priv_val->bay3d_cur_wrap_line << 16 | + (ispdev->isp_ver == ISP_V32 ? 28 : 20); isp3_param_write(params_vdev, value, ISP3X_BAY3D_MI_ST); /* mibuf_size for fifo_cur_full, set to max: (3072 - 2) / 2, 2 align */ - value = 0x5fe << 16; - isp3_param_set_bits(params_vdev, ISP3X_BAY3D_IN_IRQ_LINECNT, value); + if (ispdev->isp_ver == ISP_V32) { + value = 0x5fe << 16; + isp3_param_set_bits(params_vdev, ISP3X_BAY3D_IN_IRQ_LINECNT, value); + } value = isp3_param_read_cache(params_vdev, ISP32_BAY3D_CTRL1); if (priv_val->is_lo8x8) { @@ -3448,15 +3656,19 @@ isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en) val = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL); if (en) { - val |= priv_val->lut3d_en << 20 | - priv_val->dhaz_en << 16 | - priv_val->drc_en << 12 | - priv_val->lsc_en << 8 | - priv_val->bay3d_en << 4; - if (isp3_param_read(params_vdev, ISP3X_HDRMGE_CTRL) & BIT(0)) - val |= BIT(1); - if (val) + if (params_vdev->dev->isp_ver == ISP_V32) { + val |= priv_val->lut3d_en << 20 | + priv_val->dhaz_en << 16 | + priv_val->drc_en << 12 | + priv_val->lsc_en << 8 | + priv_val->bay3d_en << 4; + if (isp3_param_read(params_vdev, ISP3X_HDRMGE_CTRL) & BIT(0)) + val |= BIT(1); + if (val) + val |= ISP32_MODULE_EN; + } else { val |= ISP32_MODULE_EN; + } } isp3_param_write(params_vdev, val, ISP3X_GAIN_CTRL); } @@ -3740,6 +3952,10 @@ void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev, (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops; u64 module_cfg_update = new_params->module_cfg_update; + if (params_vdev->dev->isp_ver == ISP_V32_L) + module_cfg_update &= ~(ISP32_MODULE_GIC | ISP32_MODULE_BAYNR | + ISP32_MODULE_VSM | ISP32_MODULE_CAC); + if (type == RKISP_PARAMS_SHD) { if ((module_cfg_update & ISP32_MODULE_HDRMGE)) ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type); @@ -3846,6 +4062,10 @@ void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev, u64 module_ens = new_params->module_ens; u32 gain_ctrl, cnr_ctrl, val; + if (params_vdev->dev->isp_ver == ISP_V32_L) + module_en_update &= ~(ISP32_MODULE_GIC | ISP32_MODULE_BAYNR | + ISP32_MODULE_VSM | ISP32_MODULE_CAC); + if (type == RKISP_PARAMS_SHD) return; @@ -3962,6 +4182,10 @@ void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, u64 module_cfg_update = new_params->module_cfg_update; params_vdev->cur_frame_id = new_params->frame_id; + if (params_vdev->dev->isp_ver == ISP_V32_L) + module_cfg_update &= ~(ISP32_MODULE_RAWAE1 | ISP32_MODULE_RAWAE2 | + ISP32_MODULE_RAWHIST1 | ISP32_MODULE_RAWHIST2); + if (type == RKISP_PARAMS_SHD) return; @@ -3972,7 +4196,8 @@ void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, if ((module_cfg_update & ISP32_MODULE_RAWAF)) ops->rawaf_config(params_vdev, &new_params->meas.rawaf); - if ((module_cfg_update & ISP32_MODULE_RAWAE0)) + if ((module_cfg_update & ISP32_MODULE_RAWAE0) && + !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32_L)) ops->rawae0_config(params_vdev, &new_params->meas.rawae0); if ((module_cfg_update & ISP32_MODULE_RAWAE1)) @@ -3981,7 +4206,8 @@ void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev, if ((module_cfg_update & ISP32_MODULE_RAWAE2)) ops->rawae2_config(params_vdev, &new_params->meas.rawae2); - if ((module_cfg_update & ISP32_MODULE_RAWAE3) && !params_vdev->afaemode_en) + if ((module_cfg_update & ISP32_MODULE_RAWAE3) && + !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32)) ops->rawae3_config(params_vdev, &new_params->meas.rawae3); if ((module_cfg_update & ISP32_MODULE_RAWHIST0)) @@ -4012,6 +4238,9 @@ void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev, u64 module_en_update = new_params->module_en_update; u64 module_ens = new_params->module_ens; + if (params_vdev->dev->isp_ver == ISP_V32_L) + module_en_update &= ~(ISP32_MODULE_RAWAE1 | ISP32_MODULE_RAWAE2 | + ISP32_MODULE_RAWHIST1 | ISP32_MODULE_RAWHIST2); if (type == RKISP_PARAMS_SHD) return; @@ -4022,7 +4251,8 @@ void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev, if (module_en_update & ISP32_MODULE_RAWAF) ops->rawaf_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAF)); - if (module_en_update & ISP32_MODULE_RAWAE0) + if ((module_en_update & ISP32_MODULE_RAWAE0) && + !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32_L)) ops->rawae0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE0)); if (module_en_update & ISP32_MODULE_RAWAE1) @@ -4031,7 +4261,8 @@ void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev, if (module_en_update & ISP32_MODULE_RAWAE2) ops->rawae2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE2)); - if ((module_en_update & ISP32_MODULE_RAWAE3) && !params_vdev->afaemode_en) + if ((module_en_update & ISP32_MODULE_RAWAE3) && + !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32)) ops->rawae3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE3)); if (module_en_update & ISP32_MODULE_RAWHIST0) @@ -4167,7 +4398,10 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, } } - wrap_line = priv_val->is_lo8x8 ? 76 : 36; + if (dev->isp_ver == ISP_V32) + wrap_line = priv_val->is_lo8x8 ? 76 : 36; + else + wrap_line = priv_val->is_lo8x8 ? 64 : 32; wsize = is_bwopt_dis ? w : w * 2; if (is_bwsaving) wsize = wsize * 3 / 4; @@ -4202,7 +4436,38 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev, priv_val->bay3d_cur_wsize = wsize; priv_val->bay3d_cur_wrap_line = wrap_line; } + + if (dev->isp_ver == ISP_V32_L) { + if (dev->hw_dev->is_frm_buf && !priv_val->buf_frm.mem_priv) { + priv_val->buf_frm.size = ISP32_LITE_FRM_BUF_SIZE; + ret = rkisp_alloc_buffer(dev, &priv_val->buf_frm); + if (ret) { + dev_err(dev->dev, "alloc frm buf fail:%d\n", ret); + goto free_3dnr; + } + } + + priv_val->buf_lsclut_idx = 0; + for (i = 0; i < ISP32_LSC_LUT_BUF_NUM; i++) { + priv_val->buf_lsclut[i].is_need_vaddr = true; + priv_val->buf_lsclut[i].size = ISP32_LSC_LUT_BUF_SIZE; + ret = rkisp_alloc_buffer(dev, &priv_val->buf_lsclut[i]); + if (ret) { + dev_err(dev->dev, "alloc lsc buf fail:%d\n", ret); + goto err_lsc; + } + } + } return 0; +err_lsc: + if (priv_val->buf_frm.mem_priv) + rkisp_free_buffer(dev, &priv_val->buf_frm); + for (i -= 1; i >= 0; i--) + rkisp_free_buffer(dev, &priv_val->buf_lsclut[i]); +free_3dnr: + rkisp_free_buffer(dev, &priv_val->buf_3dnr_cur); + rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir); + rkisp_free_buffer(dev, &priv_val->buf_3dnr_ds); err_3dnr: i = ISP32_3DLUT_BUF_NUM; err_3dlut: @@ -4211,6 +4476,177 @@ err_3dlut: return ret; } +static bool +rkisp_params_check_bigmode_v32_lite(struct rkisp_isp_params_vdev *params_vdev) +{ + struct rkisp_device *ispdev = params_vdev->dev; + struct device *dev = params_vdev->dev->dev; + struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev; + struct v4l2_rect *crop = ¶ms_vdev->dev->isp_sdev.in_crop; + u32 width = hw->max_in.w, height = hw->max_in.h, size = width * height; + u32 bigmode_max_w, bigmode_max_size; + int k = 0, idx1[DEV_MAX] = { 0 }; + int n = 0, idx2[DEV_MAX] = { 0 }; + int i = 0, j = 0; + bool is_bigmode = false; + +using_frm_buf: + if (hw->is_frm_buf) { + ispdev->multi_index = 0; + ispdev->multi_mode = 0; + bigmode_max_w = ISP32_LITE_AUTO_BIGMODE_WIDTH; + bigmode_max_size = ISP32_LITE_NOBIG_OVERFLOW_SIZE; + dev_info(dev, "virtual isp%d %dx%d using frm buf\n", + ispdev->dev_id, crop->width, crop->height); + goto end; + } + + switch (hw->dev_link_num) { + case 4: + bigmode_max_w = ISP32_LITE_VIR4_AUTO_BIGMODE_WIDTH; + bigmode_max_size = ISP32_LITE_VIR4_NOBIG_OVERFLOW_SIZE; + ispdev->multi_index = ispdev->dev_id; + ispdev->multi_mode = 2; + /* internal buf of hw divided to four parts + * bigmode nobigmode + * _________ max width:2688 max width:1280 + * |_sensor0_| max size:2688*1536 max size:1280*800 + * |_sensor1_| max size:2688*1536 max size:1280*800 + * |_sensor2_| max size:2688*1536 max size:1280*800 + * |_sensor3_| max size:2688*1536 max size:1280*800 + */ + for (i = 0; i < hw->dev_num; i++) { + if (hw->isp_size[i].w <= ISP32_LITE_VIR4_MAX_WIDTH && + hw->isp_size[i].size <= ISP32_LITE_VIR4_MAX_SIZE) + continue; + hw->is_frm_buf = true; + goto using_frm_buf; + } + break; + case 3: + bigmode_max_w = ISP32_LITE_VIR4_AUTO_BIGMODE_WIDTH; + bigmode_max_size = ISP32_LITE_VIR4_NOBIG_OVERFLOW_SIZE; + ispdev->multi_index = ispdev->dev_id; + ispdev->multi_mode = 2; + /* case0: bigmode nobigmode + * _________ max width:2688 max width:1280 + * |_sensor0_| max size:2688*1536 max size:1280*800 + * |_sensor1_| max size:2688*1536 max size:1280*800 + * |_sensor2_| max size:2688*1536 max size:1280*800 + * |_________| + * + * case1: bigmode special reg cfg + * _________ max width:3840 + * | sensor0 | max size:3840*2160 mode=0 index=0 + * |_________| + * |_sensor1_| max size:2688*1536 mode=2 index=2 + * |_sensor2_| max size:2688*1536 mode=2 index=3 + * max width:2688 + */ + for (i = 0; i < hw->dev_num; i++) { + if (!hw->isp_size[i].size) { + if (i < hw->dev_link_num) + idx2[n++] = i; + continue; + } + if (hw->isp_size[i].w <= ISP32_LITE_VIR4_MAX_WIDTH && + hw->isp_size[i].size <= ISP32_LITE_VIR4_MAX_SIZE) + continue; + idx1[k++] = i; + } + if (k) { + is_bigmode = true; + if (k != 1 || + (hw->isp_size[idx1[0]].size > ISP32_LITE_VIR2_MAX_SIZE)) { + hw->is_frm_buf = true; + goto using_frm_buf; + } else { + if (idx1[0] == ispdev->dev_id) { + ispdev->multi_mode = 0; + ispdev->multi_index = 0; + } else { + ispdev->multi_mode = 2; + if (ispdev->multi_index == 0 || + ispdev->multi_index == 1) + ispdev->multi_index = 3; + } + } + } else if (ispdev->multi_index >= hw->dev_link_num) { + ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num]; + } + break; + case 2: + bigmode_max_w = ISP32_LITE_VIR2_AUTO_BIGMODE_WIDTH; + bigmode_max_size = ISP32_LITE_VIR2_NOBIG_OVERFLOW_SIZE; + ispdev->multi_index = ispdev->dev_id; + ispdev->multi_mode = 1; + /* case0: bigmode nobigmode + * _________ max width:3840 max width:1920 + * | sensor0 | max size:3840*2160 max size:1920*1080 + * |_________| + * | sensor1 | max size:3840*2160 max size:1920*1080 + * |_________| + * + * case1: bigmode special reg cfg + * _________ max width:4224 + * | sensor0 | max size: mode=0 index=0 + * | | 3840*2160+2688*1536 + * |_________| + * |_sensor1_| max size:2688*1536 mode=2 index=3 + * max width:2688 + */ + for (i = 0; i < hw->dev_num; i++) { + if (!hw->isp_size[i].size) { + if (i < hw->dev_link_num) + idx2[n++] = i; + continue; + } + if (hw->isp_size[i].w <= ISP32_LITE_VIR2_MAX_WIDTH && + hw->isp_size[i].size <= ISP32_LITE_VIR2_MAX_SIZE) { + if (hw->isp_size[i].w > ISP32_LITE_VIR4_MAX_WIDTH || + hw->isp_size[i].size > ISP32_LITE_VIR4_MAX_SIZE) + j++; + continue; + } + idx1[k++] = i; + } + if (k) { + is_bigmode = true; + if (k == 2 || j || + hw->isp_size[idx1[k - 1]].size > (ISP32_LITE_VIR4_MAX_SIZE + ISP32_LITE_VIR2_MAX_SIZE)) { + hw->is_frm_buf = true; + goto using_frm_buf; + } else { + if (idx1[0] == ispdev->dev_id) { + ispdev->multi_mode = 0; + ispdev->multi_index = 0; + } else { + ispdev->multi_mode = 2; + ispdev->multi_index = 3; + } + } + } else if (ispdev->multi_index >= hw->dev_link_num) { + ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num]; + } + break; + default: + bigmode_max_w = ISP32_LITE_AUTO_BIGMODE_WIDTH; + bigmode_max_size = ISP32_LITE_NOBIG_OVERFLOW_SIZE; + ispdev->multi_mode = 0; + ispdev->multi_index = 0; + width = crop->width; + height = crop->height; + size = width * height; + break; + } + +end: + if (!is_bigmode && + (width > bigmode_max_w || size > bigmode_max_size)) + is_bigmode = true; + return ispdev->is_bigmode = is_bigmode; +} + static bool rkisp_params_check_bigmode_v32(struct rkisp_isp_params_vdev *params_vdev) { @@ -4225,6 +4661,9 @@ rkisp_params_check_bigmode_v32(struct rkisp_isp_params_vdev *params_vdev) int i = 0, j = 0; bool is_bigmode = false; + if (ispdev->isp_ver == ISP_V32_L) + return rkisp_params_check_bigmode_v32_lite(params_vdev); + multi_overflow: if (hw->is_multi_overflow) { ispdev->multi_index = 0; @@ -4395,7 +4834,7 @@ rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev) struct rkisp_isp_params_val_v32 *priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; - dev->is_bigmode = rkisp_params_check_bigmode_v32(params_vdev); + rkisp_params_check_bigmode_v32(params_vdev); spin_lock(¶ms_vdev->config_lock); /* override the default things */ if (!params_vdev->isp32_params->module_cfg_update && @@ -4423,6 +4862,11 @@ rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev) priv_val->last_hdrdrc = priv_val->cur_hdrdrc; spin_unlock(¶ms_vdev->config_lock); + if (dev->hw_dev->is_frm_buf && priv_val->buf_frm.mem_priv) { + isp3_param_write(params_vdev, priv_val->buf_frm.size, ISP32L_FRM_BUF_WR_SIZE); + isp3_param_write(params_vdev, priv_val->buf_frm.dma_addr, ISP32L_FRM_BUF_WR_BASE); + isp3_param_write(params_vdev, priv_val->buf_frm.dma_addr, ISP32L_FRM_BUF_RD_BASE); + } if (dev->hw_dev->is_single && (dev->isp_state & ISP_START)) rkisp_set_bits(dev, ISP3X_ISP_CTRL0, 0, CIF_ISP_CTRL_ISP_CFG_UPD, true); } @@ -4606,6 +5050,10 @@ rkisp_params_info2ddr_cfg_v32(struct rkisp_isp_params_vdev *params_vdev, void *a u32 reg, ctrl, mask, size, val, wsize = 0, vsize = 0; int i, ret; + if (dev->isp_ver == ISP_V32_L && cfg->owner == RKISP_INFO2DRR_OWNER_GAIN) { + dev_err(dev->dev, "%s no support gain for lite\n", __func__); + return -EINVAL; + } priv_val = params_vdev->priv_val; if (cfg->buf_cnt > RKISP_INFO2DDR_BUF_MAX) @@ -4719,9 +5167,12 @@ rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev *params_vdev) int i; priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val; + rkisp_free_buffer(ispdev, &priv_val->buf_frm); rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir); rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur); rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds); + for (i = 0; i < ISP32_LSC_LUT_BUF_NUM; i++) + rkisp_free_buffer(ispdev, &priv_val->buf_lsclut[i]); for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[i]); for (i = 0; i < RKISP_STATS_DDR_BUF_NUM; i++) diff --git a/drivers/media/platform/rockchip/isp/isp_params_v32.h b/drivers/media/platform/rockchip/isp/isp_params_v32.h index 540bb6b212f9..30c2e06a3ca8 100644 --- a/drivers/media/platform/rockchip/isp/isp_params_v32.h +++ b/drivers/media/platform/rockchip/isp/isp_params_v32.h @@ -12,6 +12,10 @@ #define ISP32_3DLUT_BUF_NUM 2 #define ISP32_3DLUT_BUF_SIZE (9 * 9 * 9 * 4) +#define ISP32_LSC_LUT_BUF_NUM 2 +#define ISP32_LSC_LUT_TBL_SIZE (9 * 17 * 4) +#define ISP32_LSC_LUT_BUF_SIZE (ISP32_LSC_LUT_TBL_SIZE * 4) + #define ISP32_RAWHISTBIG_ROW_NUM 15 #define ISP32_RAWHISTBIG_COLUMN_NUM 15 #define ISP32_RAWHISTBIG_WEIGHT_REG_SIZE \ @@ -174,6 +178,9 @@ struct rkisp_isp_params_val_v32 { struct rkisp_dummy_buffer buf_3dlut[ISP32_3DLUT_BUF_NUM]; u32 buf_3dlut_idx; + struct rkisp_dummy_buffer buf_lsclut[ISP32_LSC_LUT_BUF_NUM]; + u32 buf_lsclut_idx; + struct rkisp_dummy_buffer buf_ldch[ISP3X_MESH_BUF_NUM]; u32 buf_ldch_idx; @@ -192,6 +199,8 @@ struct rkisp_isp_params_val_v32 { struct rkisp_dummy_buffer buf_3dnr_cur; struct rkisp_dummy_buffer buf_3dnr_ds; + struct rkisp_dummy_buffer buf_frm; + struct isp32_hdrmge_cfg last_hdrmge; struct isp32_drc_cfg last_hdrdrc; struct isp32_hdrmge_cfg cur_hdrmge; diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v32.c b/drivers/media/platform/rockchip/isp/isp_stats_v32.c index fb6a9bb0c723..b7206238faac 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats_v32.c +++ b/drivers/media/platform/rockchip/isp/isp_stats_v32.c @@ -57,10 +57,10 @@ rkisp_stats_get_vsm_stats(struct rkisp_isp_stats_vdev *stats_vdev, } static int -rkisp_stats_get_bls_stats(struct rkisp_isp_stats_vdev *stats_vdev, - struct rkisp32_isp_stat_buffer *pbuf) +rkisp_stats_get_bls_stats(struct rkisp_isp_stats_vdev *stats_vdev, void *pbuf) { - struct ispsd_in_fmt in_fmt = stats_vdev->dev->isp_sdev.in_fmt; + struct rkisp_device *dev = stats_vdev->dev; + struct ispsd_in_fmt in_fmt = dev->isp_sdev.in_fmt; enum rkisp_fmt_raw_pat_type raw_type = in_fmt.bayer_pat; struct isp2x_bls_stat *bls; u32 value; @@ -68,10 +68,19 @@ rkisp_stats_get_bls_stats(struct rkisp_isp_stats_vdev *stats_vdev, if (!pbuf) return 0; - bls = &pbuf->params.bls; value = isp3_stats_read(stats_vdev, ISP3X_BLS_CTRL); if (value & (ISP_BLS_ENA | ISP_BLS_MODE_MEASURED)) { - pbuf->meas_type |= ISP32_STAT_BLS; + if (dev->isp_ver == ISP_V32) { + struct rkisp32_isp_stat_buffer *p = pbuf; + + bls = &p->params.bls; + p->meas_type |= ISP32_STAT_BLS; + } else { + struct rkisp32_lite_stat_buffer *p = pbuf; + + bls = &p->params.bls; + p->meas_type |= ISP32_STAT_BLS; + } switch (raw_type) { case RAW_BGGR: @@ -106,19 +115,28 @@ rkisp_stats_get_bls_stats(struct rkisp_isp_stats_vdev *stats_vdev, } static int -rkisp_stats_get_dhaz_stats(struct rkisp_isp_stats_vdev *stats_vdev, - struct rkisp32_isp_stat_buffer *pbuf) +rkisp_stats_get_dhaz_stats(struct rkisp_isp_stats_vdev *stats_vdev, void *pbuf) { + struct rkisp_device *dev = stats_vdev->dev; struct isp3x_dhaz_stat *dhaz; u32 value, i; if (!pbuf) return 0; - dhaz = &pbuf->params.dhaz; value = isp3_stats_read(stats_vdev, ISP3X_DHAZ_CTRL); if (value & ISP_DHAZ_ENMUX) { - pbuf->meas_type |= ISP32_STAT_DHAZ; + if (dev->isp_ver == ISP_V32) { + struct rkisp32_isp_stat_buffer *p = pbuf; + + dhaz = &p->params.dhaz; + p->meas_type |= ISP32_STAT_DHAZ; + } else { + struct rkisp32_lite_stat_buffer *p = pbuf; + + dhaz = &p->params.dhaz; + p->meas_type |= ISP32_STAT_DHAZ; + } value = isp3_stats_read(stats_vdev, ISP3X_DHAZ_SUMH_RD); dhaz->dhaz_pic_sumh = value; @@ -437,72 +455,83 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev) } static void -rkisp_stats_info2ddr(struct rkisp_isp_stats_vdev *stats_vdev, - struct rkisp32_isp_stat_buffer *pbuf) +rkisp_stats_info2ddr(struct rkisp_isp_stats_vdev *stats_vdev, void *pbuf) { struct rkisp_device *dev = stats_vdev->dev; struct rkisp_isp_params_val_v32 *priv_val; + struct rkisp_dummy_buffer *buf; + int idx, buf_fd = -1; + u32 reg = 0, ctrl; priv_val = (struct rkisp_isp_params_val_v32 *)dev->params_vdev.priv_val; - if (priv_val->buf_info_owner && pbuf) { - int idx = priv_val->buf_info_idx; - struct rkisp_dummy_buffer *buf; - u32 reg = 0, ctrl; - - if (priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_GAIN) { - reg = ISP3X_GAIN_CTRL; - ctrl = ISP3X_GAIN_2DDR_EN; - } else { - reg = ISP3X_RAWAWB_CTRL; - ctrl = ISP32_RAWAWB_2DDR_PATH_EN; - } - if (idx >= 0) { - buf = &priv_val->buf_info[idx]; - rkisp_finish_buffer(dev, buf); - if (*(u32 *)buf->vaddr != RKISP_INFO2DDR_BUF_INIT && - (reg != ISP3X_RAWAWB_CTRL || - !(rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR))) { - pbuf->params.info2ddr.buf_fd = buf->dma_fd; - pbuf->params.info2ddr.owner = priv_val->buf_info_owner; - pbuf->meas_type |= ISP32_STAT_INFO2DDR; - } else if (reg == ISP3X_RAWAWB_CTRL && - rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR) { - v4l2_warn(&dev->v4l2_dev, - "rawawb2ddr path error idx:%d\n", idx); - } - - if (pbuf->params.info2ddr.buf_fd == -1) - return; - } - /* get next unused buf to hw */ - for (idx = 0; idx < priv_val->buf_info_cnt; idx++) { - buf = &priv_val->buf_info[idx]; - if (*(u32 *)buf->vaddr == RKISP_INFO2DDR_BUF_INIT) - break; - } - - if (idx == priv_val->buf_info_cnt) { - rkisp_clear_bits(dev, reg, ctrl, false); - priv_val->buf_info_idx = -1; - } else { - buf = &priv_val->buf_info[idx]; - rkisp_write(dev, ISP3X_MI_GAIN_WR_BASE, buf->dma_addr, false); - if (dev->hw_dev->is_single) - rkisp_write(dev, ISP3X_MI_WR_CTRL2, ISP3X_GAINSELF_UPD, true); - if (priv_val->buf_info_idx < 0) - rkisp_set_bits(dev, reg, 0, ctrl, false); - priv_val->buf_info_idx = idx; - } - } else if (priv_val->buf_info_idx >= 0) { + if (!priv_val->buf_info_owner && priv_val->buf_info_idx >= 0) { priv_val->buf_info_idx = -1; rkisp_clear_bits(dev, ISP3X_GAIN_CTRL, ISP3X_GAIN_2DDR_EN, false); rkisp_clear_bits(dev, ISP3X_RAWAWB_CTRL, ISP32_RAWAWB_2DDR_PATH_EN, false); + return; + } + + if (priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_GAIN) { + reg = ISP3X_GAIN_CTRL; + ctrl = ISP3X_GAIN_2DDR_EN; + } else { + reg = ISP3X_RAWAWB_CTRL; + ctrl = ISP32_RAWAWB_2DDR_PATH_EN; + } + + idx = priv_val->buf_info_idx; + if (idx >= 0) { + buf = &priv_val->buf_info[idx]; + rkisp_finish_buffer(dev, buf); + if (*(u32 *)buf->vaddr != RKISP_INFO2DDR_BUF_INIT && pbuf && + (reg != ISP3X_RAWAWB_CTRL || + !(rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR))) { + if (dev->isp_ver == ISP_V32) { + struct rkisp32_isp_stat_buffer *p = pbuf; + + p->params.info2ddr.buf_fd = buf->dma_fd; + p->params.info2ddr.owner = priv_val->buf_info_owner; + p->meas_type |= ISP32_STAT_INFO2DDR; + } else { + struct rkisp32_lite_stat_buffer *p = pbuf; + + p->params.info2ddr.buf_fd = buf->dma_fd; + p->params.info2ddr.owner = priv_val->buf_info_owner; + p->meas_type |= ISP32_STAT_INFO2DDR; + } + buf_fd = buf->dma_fd; + } else if (reg == ISP3X_RAWAWB_CTRL && + rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR) { + v4l2_warn(&dev->v4l2_dev, "rawawb2ddr path error idx:%d\n", idx); + } + + if (buf_fd == -1) + return; + } + /* get next unused buf to hw */ + for (idx = 0; idx < priv_val->buf_info_cnt; idx++) { + buf = &priv_val->buf_info[idx]; + if (*(u32 *)buf->vaddr == RKISP_INFO2DDR_BUF_INIT) + break; + } + + if (idx == priv_val->buf_info_cnt) { + rkisp_clear_bits(dev, reg, ctrl, false); + priv_val->buf_info_idx = -1; + } else { + buf = &priv_val->buf_info[idx]; + rkisp_write(dev, ISP3X_MI_GAIN_WR_BASE, buf->dma_addr, false); + if (dev->hw_dev->is_single) + rkisp_write(dev, ISP3X_MI_WR_CTRL2, ISP3X_GAINSELF_UPD, true); + if (priv_val->buf_info_idx < 0) + rkisp_set_bits(dev, reg, 0, ctrl, false); + priv_val->buf_info_idx = idx; } } static void -rkisp_stats_send_meas_v32(struct rkisp_isp_stats_vdev *stats_vdev, - struct rkisp_isp_readout_work *meas_work) +rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp_isp_readout_work *meas_work) { unsigned int cur_frame_id = -1; struct rkisp_buffer *cur_buf = stats_vdev->cur_buf; @@ -537,18 +566,6 @@ rkisp_stats_send_meas_v32(struct rkisp_isp_stats_vdev *stats_vdev, cur_buf = NULL; } - if (meas_work->isp_ris & ISP3X_AFM_SUM_OF) - v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, - "ISP3X_AFM_SUM_OF\n"); - - if (meas_work->isp_ris & ISP3X_AFM_LUM_OF) - v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, - "ISP3X_AFM_LUM_OF\n"); - - if (meas_work->isp3a_ris & ISP3X_3A_RAWAF_SUM) - v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, - "ISP3X_3A_RAWAF_SUM\n"); - if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB) ret |= ops->get_rawawb_meas(stats_vdev, cur_stat_buf); @@ -624,6 +641,341 @@ rkisp_stats_send_meas_v32(struct rkisp_isp_stats_vdev *stats_vdev, } } +static int +rkisp_stats_get_rawawb_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_lite_stat_buffer *pbuf) +{ + struct isp32_lite_rawawb_meas_stat *awb; + u32 i, val, ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_CTRL); + + if (!(ctrl & ISP32_3A_MEAS_DONE)) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, ctrl:0x%x\n", __func__, ctrl); + return -ENODATA; + } + + if (!pbuf) + goto out; + awb = &pbuf->params.rawawb; + for (i = 0; i < ISP32_RAWAWB_SUM_NUM; i++) { + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_SUM_RGAIN_NOR_0 + 0x30 * i); + awb->sum[i].rgain_nor = val; + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_SUM_BGAIN_NOR_0 + 0x30 * i); + awb->sum[i].bgain_nor = val; + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_WP_NUM_NOR_0 + 0x30 * i); + awb->sum[i].wp_num_nor = val; + + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_SUM_RGAIN_BIG_0 + 0x30 * i); + awb->sum[i].rgain_big = val; + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_SUM_BGAIN_BIG_0 + 0x30 * i); + awb->sum[i].bgain_big = val; + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_WP_NUM_BIG_0 + 0x30 * i); + awb->sum[i].wp_num_big = val; + + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_WPNUM2_0 + 4 * i); + awb->sum[i].wp_num2 = val; + } + + for (i = 0; i < ISP32_RAWAWB_EXCL_STAT_NUM; i++) { + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_SUM_R_EXC0 + 0x10 * i); + awb->sum_exc[i].rgain_exc = val; + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_SUM_B_EXC0 + 0x10 * i); + awb->sum_exc[i].bgain_exc = val; + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_WP_NM_EXC0 + 0x10 * i); + awb->sum_exc[i].wp_num_exc = val; + } + + for (i = 0; i < ISP32_RAWAWB_HSTBIN_NUM / 2; i++) { + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_Y_HIST01 + 4 * i); + awb->yhist_bin[2 * i] = val & 0xffff; + awb->yhist_bin[2 * i + 1] = (val >> 16) & 0xffff; + } + + /* RAMDATA R/G/B/WP */ + for (i = 0; i < ISP32L_RAWAWB_RAMDATA_RGB_NUM; i++) { + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_RAM_DATA_BASE); + awb->ramdata_r[i] = val & 0x1fffff; + awb->ramdata_g[i] = (val >> 21) & 0x7ff; + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_RAM_DATA_BASE); + awb->ramdata_g[i] |= ((val & 0x3ff) << 11); + awb->ramdata_b[i] = (val >> 10) & 0x1fffff; + } + for (i = 0; i < ISP32L_RAWAWB_RAMDATA_WP_NUM; i++) { + val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_RAM_DATA_BASE); + awb->ramdata_wpnum0[i] = val & 0x3fff; + awb->ramdata_wpnum1[i] = (val >> 16) & 0x3fff; + } + + pbuf->meas_type |= ISP32_STAT_RAWAWB; +out: + isp3_module_done(stats_vdev, ISP3X_RAWAWB_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawaf_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_lite_stat_buffer *pbuf) +{ + struct isp32_lite_rawaf_stat *af; + u32 i, val, ctrl; + + ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAF_CTRL); + if (!(ctrl & ISP32_3A_MEAS_DONE)) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, ctrl:0x%x\n", __func__, ctrl); + return -ENODATA; + } + + if (!pbuf || stats_vdev->af_meas_done_next) + goto out; + + af = &pbuf->params.rawaf; + af->afm_sum_b = isp3_stats_read(stats_vdev, ISP3X_RAWAF_SUM_B); + af->afm_lum_b = isp3_stats_read(stats_vdev, ISP3X_RAWAF_LUM_B); + af->int_state = isp3_stats_read(stats_vdev, ISP3X_RAWAF_INT_STATE); + af->highlit_cnt_winb = isp3_stats_read(stats_vdev, ISP3X_RAWAF_HIGHLIT_CNT_WINB); + /* hiir: first 25 word, viir: remaining 25 word */ + for (i = 0; i < ISP32L_RAWAF_WND_DATA; i++) { + val = isp3_stats_read(stats_vdev, ISP3X_RAWAF_RAM_DATA); + af->ramdata.hiir_wnd_data[i] = val; + } + for (i = 0; i < ISP32L_RAWAF_WND_DATA; i++) { + val = isp3_stats_read(stats_vdev, ISP3X_RAWAF_RAM_DATA); + af->ramdata.viir_wnd_data[i] = val; + } + + pbuf->meas_type |= ISP32_STAT_RAWAF; +out: + /* af should not clean mease done during isp working for af_ae_mode */ + stats_vdev->af_meas_done_next = false; + if ((ctrl & ISP3X_RAWAF_AE_MODE) && + (isp3_stats_read(stats_vdev, ISP3X_DPCC0_BASE) & ISP3X_DPCC_WORKING)) + stats_vdev->af_meas_done_next = true; + else + isp3_module_done(stats_vdev, ISP3X_RAWAF_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawae3_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_lite_stat_buffer *pbuf) +{ + struct isp32_lite_rawaebig_stat *ae = NULL; + u32 i, val, addr, ctrl, base = RAWAE_BIG1_BASE; + + ctrl = isp3_stats_read(stats_vdev, base + ISP3X_RAWAE_BIG_CTRL); + if (!(ctrl & ISP32_3A_MEAS_DONE)) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, addr:0x%x ctrl:0x%x\n", + __func__, base, ctrl); + return -ENODATA; + } + + if (!pbuf || stats_vdev->ae_meas_done_next) + goto out; + + ae = &pbuf->params.rawae3; + addr = base + ISP3X_RAWAE_BIG_WND1_SUMR; + ae->sumr = isp3_stats_read(stats_vdev, addr); + addr = base + ISP3X_RAWAE_BIG_WND1_SUMG; + ae->sumg = isp3_stats_read(stats_vdev, addr); + addr = base + ISP3X_RAWAE_BIG_WND1_SUMB; + ae->sumb = isp3_stats_read(stats_vdev, addr); + + addr = base + ISP3X_RAWAE_BIG_RO_MEAN_BASE_ADDR; + for (i = 0; i < ISP32_RAWAEBIG_MEAN_NUM; i++) { + val = isp3_stats_read(stats_vdev, addr); + ae->data[i].channelg_xy = val & 0xfff; + ae->data[i].channelb_xy = (val >> 12) & 0x3ff; + ae->data[i].channelr_xy = (val >> 22) & 0x3ff; + } + + pbuf->meas_type |= ISP32_STAT_RAWAE3; +out: + /* ae should not clean mease done during isp working for af_ae_mode */ + if (stats_vdev->af_meas_done_next) { + stats_vdev->ae_meas_done_next = true; + } else { + isp3_module_done(stats_vdev, base + ISP3X_RAWAE_BIG_CTRL, ctrl); + stats_vdev->ae_meas_done_next = false; + } + return 0; +} + +static int +rkisp_stats_get_rawhst3_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_lite_stat_buffer *pbuf) +{ + struct isp2x_rawhistbig_stat *hst; + u32 i, ctrl, addr, base = ISP3X_RAWHIST_BIG1_BASE; + + ctrl = isp3_stats_read(stats_vdev, base + ISP3X_RAWHIST_BIG_CTRL); + if (!(ctrl & ISP32_3A_MEAS_DONE)) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, addr:0x%x ctrl:0x%x\n", + __func__, base, ctrl); + return -ENODATA; + } + + if (!pbuf) + goto out; + hst = &pbuf->params.rawhist3; + addr = base + ISP3X_RAWHIST_BIG_RO_BASE_BIN; + for (i = 0; i < ISP3X_HIST_BIN_N_MAX; i++) + hst->hist_bin[i] = isp3_stats_read(stats_vdev, addr); + + pbuf->meas_type |= ISP32_STAT_RAWHST3; +out: + isp3_module_done(stats_vdev, base + ISP3X_RAWHIST_BIG_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawaelite_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_lite_stat_buffer *pbuf) +{ + struct isp2x_rawaelite_stat *ae; + u32 i, val, ctrl; + + ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWAE_LITE_CTRL); + if ((ctrl & ISP32_3A_MEAS_DONE) == 0) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, ctrl:0x%x\n", __func__, ctrl); + return -ENODATA; + } + + if (!pbuf) + goto out; + ae = &pbuf->params.rawae0; + for (i = 0; i < ISP32_RAWAELITE_MEAN_NUM; i++) { + val = isp3_stats_read(stats_vdev, ISP3X_RAWAE_LITE_RO_MEAN + 4 * i); + ae->data[i].channelg_xy = val & 0xfff; + ae->data[i].channelb_xy = (val >> 12) & 0x3ff; + ae->data[i].channelr_xy = (val >> 22) & 0x3ff; + } + + pbuf->meas_type |= ISP32_STAT_RAWAE0; +out: + isp3_module_done(stats_vdev, ISP3X_RAWAE_LITE_CTRL, ctrl); + return 0; +} + +static int +rkisp_stats_get_rawhstlite_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp32_lite_stat_buffer *pbuf) +{ + struct isp32_lite_rawhistlite_stat *hst; + u32 i, ctrl; + + ctrl = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_LITE_CTRL); + if ((ctrl & ISP32_3A_MEAS_DONE) == 0) { + v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev, + "%s fail, ctrl:0x%x\n", __func__, ctrl); + return -ENODATA; + } + + if (!pbuf) + goto out; + hst = &pbuf->params.rawhist0; + for (i = 0; i < ISP32L_HIST_LITE_BIN_N_MAX; i++) + hst->hist_bin[i] = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_LITE_RO_BASE_BIN); + + pbuf->meas_type |= ISP32_STAT_RAWHST0; +out: + isp3_module_done(stats_vdev, ISP3X_RAWHIST_LITE_CTRL, ctrl); + return 0; +} + +static void +rkisp_stats_send_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp_isp_readout_work *meas_work) +{ + struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev; + unsigned int cur_frame_id = meas_work->frame_id; + struct rkisp_buffer *cur_buf = NULL; + struct rkisp32_lite_stat_buffer *cur_stat_buf = NULL; + u32 size = sizeof(struct rkisp32_lite_stat_buffer); + int ret = 0; + + spin_lock(&stats_vdev->rd_lock); + if (!list_empty(&stats_vdev->stat)) { + cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue); + list_del(&cur_buf->queue); + } + spin_unlock(&stats_vdev->rd_lock); + + if (cur_buf) { + cur_stat_buf = (struct rkisp32_lite_stat_buffer *)(cur_buf->vaddr[0]); + cur_stat_buf->frame_id = cur_frame_id; + cur_stat_buf->params_id = params_vdev->cur_frame_id; + cur_stat_buf->params.info2ddr.buf_fd = -1; + cur_stat_buf->params.info2ddr.owner = 0; + } + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB) + ret |= rkisp_stats_get_rawawb_meas_lite(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAF || + stats_vdev->af_meas_done_next) + ret |= rkisp_stats_get_rawaf_meas_lite(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG || + stats_vdev->ae_meas_done_next) + ret |= rkisp_stats_get_rawae3_meas_lite(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG) + ret |= rkisp_stats_get_rawhst3_meas_lite(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0) + ret |= rkisp_stats_get_rawaelite_meas_lite(stats_vdev, cur_stat_buf); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0) + ret |= rkisp_stats_get_rawhstlite_meas_lite(stats_vdev, cur_stat_buf); + + if (meas_work->isp_ris & ISP3X_FRAME) { + ret |= rkisp_stats_get_bls_stats(stats_vdev, cur_stat_buf); + ret |= rkisp_stats_get_dhaz_stats(stats_vdev, cur_stat_buf); + } + + if (cur_buf) { + if (ret || !cur_stat_buf->meas_type) { + unsigned long flags; + + spin_lock_irqsave(&stats_vdev->rd_lock, flags); + list_add_tail(&cur_buf->queue, &stats_vdev->stat); + spin_unlock_irqrestore(&stats_vdev->rd_lock, flags); + } else { + rkisp_stats_info2ddr(stats_vdev, cur_stat_buf); + vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size); + cur_buf->vb.sequence = cur_frame_id; + cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp; + vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + } + } +} + +static void +rkisp_stats_send_meas_v32(struct rkisp_isp_stats_vdev *stats_vdev, + struct rkisp_isp_readout_work *meas_work) +{ + if (meas_work->isp_ris & ISP3X_AFM_SUM_OF) + v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, + "ISP3X_AFM_SUM_OF\n"); + + if (meas_work->isp_ris & ISP3X_AFM_LUM_OF) + v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, + "ISP3X_AFM_LUM_OF\n"); + + if (meas_work->isp3a_ris & ISP3X_3A_RAWAF_SUM) + v4l2_warn(stats_vdev->vnode.vdev.v4l2_dev, + "ISP3X_3A_RAWAF_SUM\n"); + + if (stats_vdev->dev->isp_ver == ISP_V32) + rkisp_stats_send_meas(stats_vdev, meas_work); + else + rkisp_stats_send_meas_lite(stats_vdev, meas_work); +} + static void rkisp_stats_isr_v32(struct rkisp_isp_stats_vdev *stats_vdev, u32 isp_ris, u32 isp3a_ris) @@ -728,14 +1080,21 @@ void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) { + u32 size; + stats_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_STAT_3A; - stats_vdev->vdev_fmt.fmt.meta.buffersize = - sizeof(struct rkisp32_isp_stat_buffer); - + if (stats_vdev->dev->isp_ver == ISP_V32) { + stats_vdev->priv_ops = &stats_ddr_ops_v32; + stats_vdev->rd_stats_from_ddr = true; + size = sizeof(struct rkisp32_isp_stat_buffer); + } else { + stats_vdev->priv_ops = NULL; + stats_vdev->rd_stats_from_ddr = false; + size = sizeof(struct rkisp32_lite_stat_buffer); + } + stats_vdev->vdev_fmt.fmt.meta.buffersize = size; stats_vdev->ops = &rkisp_isp_stats_ops_tbl; - stats_vdev->priv_ops = &stats_ddr_ops_v32; - stats_vdev->rd_stats_from_ddr = true; } void rkisp_uninit_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) diff --git a/drivers/media/platform/rockchip/isp/isp_stats_v32.h b/drivers/media/platform/rockchip/isp/isp_stats_v32.h index e5331c338eff..58d6eb5a2556 100644 --- a/drivers/media/platform/rockchip/isp/isp_stats_v32.h +++ b/drivers/media/platform/rockchip/isp/isp_stats_v32.h @@ -33,10 +33,8 @@ struct rkisp_stats_ops_v32 { struct rkisp32_isp_stat_buffer *pbuf); int (*get_rawhst3_meas)(struct rkisp_isp_stats_vdev *stats_vdev, struct rkisp32_isp_stat_buffer *pbuf); - int (*get_bls_stats)(struct rkisp_isp_stats_vdev *stats_vdev, - struct rkisp32_isp_stat_buffer *pbuf); - int (*get_dhaz_stats)(struct rkisp_isp_stats_vdev *stats_vdev, - struct rkisp32_isp_stat_buffer *pbuf); + int (*get_bls_stats)(struct rkisp_isp_stats_vdev *stats_vdev, void *pbuf); + int (*get_dhaz_stats)(struct rkisp_isp_stats_vdev *stats_vdev, void *pbuf); int (*get_vsm_stats)(struct rkisp_isp_stats_vdev *stats_vdev, struct rkisp32_isp_stat_buffer *pbuf); }; diff --git a/drivers/media/platform/rockchip/isp/procfs.c b/drivers/media/platform/rockchip/isp/procfs.c index ea02ffdee49d..6a8e9b2906d7 100644 --- a/drivers/media/platform/rockchip/isp/procfs.c +++ b/drivers/media/platform/rockchip/isp/procfs.c @@ -684,15 +684,26 @@ static void isp32_show(struct rkisp_device *dev, struct seq_file *p) priv = (struct rkisp_isp_params_val_v32 *)dev->params_vdev.priv_val; - seq_printf(p, "%-10s %s warp:%d\n", "ISP2ENC", - dev->cap_dev.wrap_line ? "online" : "offline", - dev->cap_dev.wrap_line); - tmp = rkisp_read(dev, ISP32_MI_WR_VFLIP_CTRL, false); + if (dev->isp_ver == ISP_V32) { + seq_printf(p, "%-10s %s warp:%d\n", "ISP2ENC", + dev->cap_dev.wrap_line ? "online" : "offline", + dev->cap_dev.wrap_line); + tmp = rkisp_read(dev, ISP32_MI_WR_VFLIP_CTRL, false); + val = rkisp_read(dev, ISP3X_ISP_CTRL0, false); + seq_printf(p, "%-10s mirror:%d flip(mp:%d sp:%d bp:%d mpds:%d bpds:%d)\n", + "MIR_FLIP", !!(val & BIT(5)), + !!(tmp & BIT(0)), !!(tmp & BIT(1)), !!(tmp & BIT(2)), + !!(tmp & BIT(4)), !!(tmp & BIT(5))); + val = rkisp_read(dev, ISP3X_BAYNR_CTRL, false); + seq_printf(p, "%-10s %s(0x%x)\n", "BAYNR", (val & 1) ? "ON" : "OFF", val); + val = rkisp_read(dev, ISP3X_GIC_CONTROL, false); + seq_printf(p, "%-10s %s(0x%x)\n", "GIC", (val & 1) ? "ON" : "OFF", val); + val = rkisp_read(dev, ISP3X_CAC_CTRL, false); + seq_printf(p, "%-10s %s(0x%x)\n", "CAC", (val & 1) ? "ON" : "OFF", val); + val = rkisp_read(dev, ISP32_VSM_MODE, false); + seq_printf(p, "%-10s %s(0x%x)\n", "VSM", (val & 1) ? "ON" : "OFF", val); + } val = rkisp_read(dev, ISP3X_ISP_CTRL0, false); - seq_printf(p, "%-10s mirror:%d flip(mp:%d sp:%d bp:%d mpds:%d bpds:%d)\n", - "MIR_FLIP", !!(val & BIT(5)), - !!(tmp & BIT(0)), !!(tmp & BIT(1)), !!(tmp & BIT(2)), - !!(tmp & BIT(4)), !!(tmp & BIT(5))); seq_printf(p, "%-10s %s(0x%x)\n", "SDG", (val & BIT(6)) ? "ON" : "OFF", val); seq_printf(p, "%-10s %s(0x%x) (gain0:0x%08x 0x%08x gain1:0x%x 0x%x)\n", "AWBGAIN", (val & BIT(7)) ? "ON" : "OFF", val, @@ -700,8 +711,6 @@ static void isp32_show(struct rkisp_device *dev, struct seq_file *p) rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_RB, false), rkisp_read(dev, ISP32_ISP_AWB1_GAIN_G, false), rkisp_read(dev, ISP32_ISP_AWB1_GAIN_RB, false)); - val = rkisp_read(dev, ISP32_VSM_MODE, false); - seq_printf(p, "%-10s %s(0x%x)\n", "VSM", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_CMSK_CTRL0, false); seq_printf(p, "%-10s %s(0x%x)\n", "CMSK", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_DPCC0_MODE, false); @@ -727,12 +736,10 @@ static void isp32_show(struct rkisp_device *dev, struct seq_file *p) seq_printf(p, "%-10s %s(0x%x)\n", "HDRDRC", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_HDRMGE_CTRL, false); seq_printf(p, "%-10s %s(0x%x)\n", "HDRMGE", (val & 1) ? "ON" : "OFF", val); - val = rkisp_read(dev, ISP3X_BAYNR_CTRL, false); - seq_printf(p, "%-10s %s(0x%x)\n", "BAYNR", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_BAY3D_CTRL, false); tmp = rkisp_read(dev, ISP32_BAY3D_CTRL1, false); - seq_printf(p, "%-10s %s(0x%x 0x%x) bwsaving:%d mode:(%s %s)\n", "BAY3D", - (val & 1) ? "ON" : "OFF", val, tmp, !!(val & BIT(13)), + seq_printf(p, "%-10s %s(0x%x 0x%x) bypass:%d bwsaving:%d mode:(%s %s)\n", "BAY3D", + (val & 1) ? "ON" : "OFF", val, tmp, !!(val & BIT(1)), !!(val & BIT(13)), (tmp & BIT(4)) ? "lo4x4" : ((tmp & BIT(3)) ? "lo4x8" : "lo8x8"), priv->is_sram ? "sram" : "ddr"); val = rkisp_read(dev, ISP3X_YNR_GLOBAL_CTRL, false); @@ -741,8 +748,6 @@ static void isp32_show(struct rkisp_device *dev, struct seq_file *p) seq_printf(p, "%-10s %s(0x%x)\n", "CNR", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_SHARP_EN, false); seq_printf(p, "%-10s %s(0x%x)\n", "SHARP", (val & 1) ? "ON" : "OFF", val); - val = rkisp_read(dev, ISP3X_GIC_CONTROL, false); - seq_printf(p, "%-10s %s(0x%x)\n", "GIC", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_DHAZ_CTRL, false); seq_printf(p, "%-10s %s(0x%x)\n", "DHAZ", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_3DLUT_CTRL, false); @@ -765,8 +770,6 @@ static void isp32_show(struct rkisp_device *dev, struct seq_file *p) rkisp_read(dev, ISP3X_ISP_CC_COEFF_6, false), rkisp_read(dev, ISP3X_ISP_CC_COEFF_7, false), rkisp_read(dev, ISP3X_ISP_CC_COEFF_8, false)); - val = rkisp_read(dev, ISP3X_CAC_CTRL, false); - seq_printf(p, "%-10s %s(0x%x)\n", "CAC", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_GAIN_CTRL, false); seq_printf(p, "%-10s %s(0x%x)\n", "GAIN", (val & 1) ? "ON" : "OFF", val); val = rkisp_read(dev, ISP3X_RAWAF_CTRL, false); @@ -937,6 +940,7 @@ static int isp_show(struct seq_file *p, void *v) } break; case ISP_V32: + case ISP_V32_L: if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32)) isp32_show(dev, p); break; diff --git a/drivers/media/platform/rockchip/isp/regs.c b/drivers/media/platform/rockchip/isp/regs.c index eef92d66eee3..a808d34f6d65 100644 --- a/drivers/media/platform/rockchip/isp/regs.c +++ b/drivers/media/platform/rockchip/isp/regs.c @@ -303,6 +303,59 @@ static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y, rkisp_write(dev, rsz_ctrl_addr, rsz_ctrl, false); } +static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y, + struct v4l2_rect *in_c, struct v4l2_rect *out_y, + struct v4l2_rect *out_c, bool async) +{ + struct rkisp_device *dev = stream->ispdev; + u32 rsz_ctrl = 0, val, hy, hc; + bool is_avg = false; + + rkisp_write(dev, ISP32_SELF_SCALE_HY_OFFS, 0, true); + rkisp_write(dev, ISP32_SELF_SCALE_HC_OFFS, 0, true); + rkisp_write(dev, ISP32_SELF_SCALE_PHASE_HY, 0, true); + rkisp_write(dev, ISP32_SELF_SCALE_PHASE_HC, 0, true); + rkisp_write(dev, ISP32_SELF_SCALE_PHASE_VY, 0, true); + rkisp_write(dev, ISP32_SELF_SCALE_PHASE_VC, 0, true); + + val = in_y->width | in_y->height << 16; + rkisp_write(dev, ISP32_SELF_SCALE_SRC_SIZE, val, false); + val = out_y->width | out_y->height << 16; + rkisp_write(dev, ISP32_SELF_SCALE_DST_SIZE, val, false); + + if (in_y->width != out_y->width) { + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE | CIF_RSZ_CTRL_SCALE_HC_ENABLE; + if (is_avg) { + hy = ((out_y->width - 1) * ISP32_SCALE_AVE_FACTOR) / (in_y->width - 1) + 1; + hc = ((out_c->width - 1) * ISP32_SCALE_AVE_FACTOR) / (in_c->width - 1) + 1; + rsz_ctrl |= ISP32_SCALE_AVG_H_EN; + } else { + hy = ((in_y->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->width - 1); + hc = ((in_c->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_c->width - 1); + } + rkisp_write(dev, ISP32_SELF_SCALE_HY_FAC, hy, false); + rkisp_write(dev, ISP32_SELF_SCALE_HC_FAC, hc, false); + } + + if (in_y->height != out_y->height) { + rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE | CIF_RSZ_CTRL_SCALE_VC_ENABLE; + if (is_avg) { + val = ((out_y->height - 1) * ISP32_SCALE_AVE_FACTOR) / (in_y->height - 1) + 1; + rsz_ctrl |= ISP32_SCALE_AVG_V_EN; + } else { + val = ((in_y->height - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->height - 1); + } + rkisp_write(dev, ISP32_SELF_SCALE_VY_FAC, val, false); + rkisp_write(dev, ISP32_SELF_SCALE_VC_FAC, val, false); + } + + rkisp_write(dev, ISP32_SELF_SCALE_CTRL, rsz_ctrl, false); + val = ISP32_SCALE_FORCE_UPD; + if (async && dev->hw_dev->is_single) + val = ISP32_SCALE_GEN_UPD; + rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, val, true); +} + void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y, struct v4l2_rect *in_c, struct v4l2_rect *out_y, struct v4l2_rect *out_c, bool async) @@ -311,6 +364,11 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y, int i = 0; bool is_unite = dev->hw_dev->is_unite; + if (dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP) { + set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async); + return; + } + /* No phase offset */ rkisp_write(dev, stream->config->rsz.phase_hy, 0, true); rkisp_write(dev, stream->config->rsz.phase_hc, 0, true); @@ -333,5 +391,7 @@ void rkisp_disable_rsz(struct rkisp_stream *stream, bool async) bool is_unite = stream->ispdev->hw_dev->is_unite; rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false, is_unite); + if (stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP) + return; update_rsz_shadow(stream, async); } diff --git a/drivers/media/platform/rockchip/isp/regs.h b/drivers/media/platform/rockchip/isp/regs.h index c902dc0044e5..b24eba03f57c 100644 --- a/drivers/media/platform/rockchip/isp/regs.h +++ b/drivers/media/platform/rockchip/isp/regs.h @@ -182,7 +182,8 @@ #define MI_CTRL_SP_OUTPUT_YUV444 (3 << 28) #define MI_CTRL_SP_OUTPUT_RGB565 (4 << 28) #define MI_CTRL_SP_OUTPUT_RGB666 (5 << 28) -#define MI_CTRL_SP_OUTPUT_RGB888 (6 << 28) +#define MI_CTRL_SP_OUTPUT_ARGB888 (6 << 28) +#define MI_CTRL_SP_OUTPUT_RGB888 (7 << 28) #define MI_CTRL_MP_FMT_MASK GENMASK(23, 22) #define MI_CTRL_SP_FMT_MASK GENMASK(30, 24) diff --git a/drivers/media/platform/rockchip/isp/regs_v3x.h b/drivers/media/platform/rockchip/isp/regs_v3x.h index df6c1ee55e3e..60ab10e66291 100644 --- a/drivers/media/platform/rockchip/isp/regs_v3x.h +++ b/drivers/media/platform/rockchip/isp/regs_v3x.h @@ -377,6 +377,45 @@ #define ISP3X_SELF_RESIZE_HC_OFFS_MI_SHD (ISP3X_SELF_RESIZE_BASE + 0x00074) #define ISP3X_SELF_RESIZE_IN_CROP_OFFSET (ISP3X_SELF_RESIZE_BASE + 0x00078) +#define ISP32_SELF_SCALE_BASE 0x00001000 +#define ISP32_SELF_SCALE_CTRL (ISP32_SELF_SCALE_BASE + 0x0000) +#define ISP32_SELF_SCALE_UPDATE (ISP32_SELF_SCALE_BASE + 0x0004) +#define ISP32_SELF_SCALE_SRC_SIZE (ISP32_SELF_SCALE_BASE + 0x0008) +#define ISP32_SELF_SCALE_DST_SIZE (ISP32_SELF_SCALE_BASE + 0x000c) +#define ISP32_SELF_SCALE_HY_FAC (ISP32_SELF_SCALE_BASE + 0x0010) +#define ISP32_SELF_SCALE_HC_FAC (ISP32_SELF_SCALE_BASE + 0x0014) +#define ISP32_SELF_SCALE_VY_FAC (ISP32_SELF_SCALE_BASE + 0x0018) +#define ISP32_SELF_SCALE_VC_FAC (ISP32_SELF_SCALE_BASE + 0x001c) +#define ISP32_SELF_SCALE_HY_OFFS (ISP32_SELF_SCALE_BASE + 0x0020) +#define ISP32_SELF_SCALE_HC_OFFS (ISP32_SELF_SCALE_BASE + 0x0024) +#define ISP32_SELF_SCALE_PHASE_HY (ISP32_SELF_SCALE_BASE + 0x0030) +#define ISP32_SELF_SCALE_PHASE_HC (ISP32_SELF_SCALE_BASE + 0x0034) +#define ISP32_SELF_SCALE_PHASE_VY (ISP32_SELF_SCALE_BASE + 0x0038) +#define ISP32_SELF_SCALE_PHASE_VC (ISP32_SELF_SCALE_BASE + 0x003c) +#define ISP32_SELF_SCALE_HY_SIZE (ISP32_SELF_SCALE_BASE + 0x0040) +#define ISP32_SELF_SCALE_HC_SIZE (ISP32_SELF_SCALE_BASE + 0x0044) +#define ISP32_SELF_SCALE_HY_OFFS_MI (ISP32_SELF_SCALE_BASE + 0x0048) +#define ISP32_SELF_SCALE_HC_OFFS_MI (ISP32_SELF_SCALE_BASE + 0x004c) +#define ISP32_SELF_SCALE_IN_CROP_OFFSET (ISP32_SELF_SCALE_BASE + 0x0050) +#define ISP32_SELF_SCALE_CTRL_SHD (ISP32_SELF_SCALE_BASE + 0x0080) +#define ISP32_SELF_SCALE_SRC_SIZE_SHD (ISP32_SELF_SCALE_BASE + 0x0088) +#define ISP32_SELF_SCALE_DST_SIZE_SHD (ISP32_SELF_SCALE_BASE + 0x008c) +#define ISP32_SELF_SCALE_HY_FAC_SHD (ISP32_SELF_SCALE_BASE + 0x0090) +#define ISP32_SELF_SCALE_HC_FAC_SHD (ISP32_SELF_SCALE_BASE + 0x0094) +#define ISP32_SELF_SCALE_VY_FAC_SHD (ISP32_SELF_SCALE_BASE + 0x0098) +#define ISP32_SELF_SCALE_VC_FAC_SHD (ISP32_SELF_SCALE_BASE + 0x009c) +#define ISP32_SELF_SCALE_HY_OFFS_SHD (ISP32_SELF_SCALE_BASE + 0x00a0) +#define ISP32_SELF_SCALE_HC_OFFS_SHD (ISP32_SELF_SCALE_BASE + 0x00a4) +#define ISP32_SELF_SCALE_PHASE_HY_SHD (ISP32_SELF_SCALE_BASE + 0x00b0) +#define ISP32_SELF_SCALE_PHASE_HC_SHD (ISP32_SELF_SCALE_BASE + 0x00b4) +#define ISP32_SELF_SCALE_PHASE_VY_SHD (ISP32_SELF_SCALE_BASE + 0x00b8) +#define ISP32_SELF_SCALE_PHASE_VC_SHD (ISP32_SELF_SCALE_BASE + 0x00bc) +#define ISP32_SELF_SCALE_HY_SIZE_SHD (ISP32_SELF_SCALE_BASE + 0x00c0) +#define ISP32_SELF_SCALE_HC_SIZE_SHD (ISP32_SELF_SCALE_BASE + 0x00c4) +#define ISP32_SELF_SCALE_HY_OFFS_MI_SHD (ISP32_SELF_SCALE_BASE + 0x00c8) +#define ISP32_SELF_SCALE_HC_OFFS_MI_SHD (ISP32_SELF_SCALE_BASE + 0x00cc) +#define ISP32_SELF_SCALE_IN_CROP_OFFSET_SHD (ISP32_SELF_SCALE_BASE + 0x00d0) + #define ISP3X_MI_BASE 0x00001400 #define ISP3X_MI_WR_CTRL (ISP3X_MI_BASE + 0x00000) #define ISP3X_MI_WR_INIT (ISP3X_MI_BASE + 0x00004) @@ -586,6 +625,23 @@ #define ISP3X_MI_BAY3D_DS_RD_BASE (ISP3X_MI_BASE + 0x005F0) #define ISP3X_MI_BAY3D_DS_RD_LENGTH (ISP3X_MI_BASE + 0x005F4) #define ISP3X_MI_BAY3D_DS_RD_BASE_SHD (ISP3X_MI_BASE + 0x005F8) +#define ISP32L_IRLDCH_RD_BASE (ISP3X_MI_BASE + 0x00600) +#define ISP32L_IRLDCH_RD_LENGTH (ISP3X_MI_BASE + 0x00604) +#define ISP32L_IRLDCH_RD_H_WSIZE (ISP3X_MI_BASE + 0x00608) +#define ISP32L_IRLDCH_RD_V_SIZE (ISP3X_MI_BASE + 0x0060C) +#define ISP32L_IRLDCV_RD_BASE (ISP3X_MI_BASE + 0x00610) +#define ISP32L_IRLDCV_RD_LENGTH (ISP3X_MI_BASE + 0x00614) +#define ISP32L_IRLDCV_RD_H_WSIZE (ISP3X_MI_BASE + 0x00618) +#define ISP32L_IRLDCV_RD_V_SIZE (ISP3X_MI_BASE + 0x0061C) +#define ISP32L_IRLDCH_RD_BASE_SHD (ISP3X_MI_BASE + 0x00620) +#define ISP32L_IRLDCV_RD_BASE_SHD (ISP3X_MI_BASE + 0x00624) +#define ISP32L_AXI_CONF_RD_CTRL (ISP3X_MI_BASE + 0x00640) +#define ISP32L_AXI_CONF_RD_BASE (ISP3X_MI_BASE + 0x00644) +#define ISP32L_AXI_CONF_RD_H_WSIZE (ISP3X_MI_BASE + 0x00648) +#define ISP32L_AXI_CONF_RD_V_SIZE (ISP3X_MI_BASE + 0x0064C) +#define ISP32L_FRM_BUF_WR_BASE (ISP3X_MI_BASE + 0x00650) +#define ISP32L_FRM_BUF_WR_SIZE (ISP3X_MI_BASE + 0x00654) +#define ISP32L_FRM_BUF_RD_BASE (ISP3X_MI_BASE + 0x00658) #define ISP3X_MPFBC_BASE 0x000018C0 #define ISP3X_MPFBC_CTRL (ISP3X_MPFBC_BASE + 0x00000) @@ -851,6 +907,9 @@ #define ISP32_SHARP_GAIN_DIS_STRENGTH4 (ISP3X_SHARP_BASE + 0x00084) #define ISP32_SHARP_GAIN_DIS_STRENGTH5 (ISP3X_SHARP_BASE + 0x00088) #define ISP32_SHARP_TEXTURE (ISP3X_SHARP_BASE + 0x0008c) +#define ISP32L_SHARP_CLIP_NEG_0 (ISP3X_SHARP_BASE + 0x00090) +#define ISP32L_SHARP_CLIP_NEG_1 (ISP3X_SHARP_BASE + 0x00094) +#define ISP32L_SHARP_CLIP_NEG_2 (ISP3X_SHARP_BASE + 0x00098) #define ISP3X_BAY3D_BASE 0x00002C00 #define ISP3X_BAY3D_CTRL (ISP3X_BAY3D_BASE + 0x00000) @@ -1385,6 +1444,8 @@ #define ISP32_DHAZ_ENH_LUMA3 (ISP3X_DHAZ_BASE + 0x0019c) #define ISP32_DHAZ_ENH_LUMA4 (ISP3X_DHAZ_BASE + 0x001a0) #define ISP32_DHAZ_ENH_LUMA5 (ISP3X_DHAZ_BASE + 0x001a4) +#define ISP32L_DHAZ_STAB_FRAME (ISP3X_DHAZ_BASE + 0x001f8) +#define ISP32L_DHAZ_PRE_FRAME (ISP3X_DHAZ_BASE + 0x001fc) #define ISP3X_3DLUT_BASE 0x00003E00 #define ISP3X_3DLUT_CTRL (ISP3X_3DLUT_BASE + 0x00000) @@ -1470,6 +1531,7 @@ #define ISP3X_RAWAF_OFFSET_WINB (ISP3X_RAWAF_BASE + 0x0000c) #define ISP3X_RAWAF_SIZE_WINB (ISP3X_RAWAF_BASE + 0x00010) #define ISP3X_RAWAF_INT_LINE (ISP3X_RAWAF_BASE + 0x00014) +#define ISP32L_RAWAF_CTRL1 (ISP3X_RAWAF_BASE + 0x00018) #define ISP3X_RAWAF_THRES (ISP3X_RAWAF_BASE + 0x0001c) #define ISP3X_RAWAF_VAR_SHIFT (ISP3X_RAWAF_BASE + 0x00020) #define ISP3X_RAWAF_HVIIR_VAR_SHIFT (ISP3X_RAWAF_BASE + 0x00024) @@ -1523,6 +1585,8 @@ #define ISP3X_RAWAF_HIGHLIT_THRESH (ISP3X_RAWAF_BASE + 0x000D0) #define ISP3X_RAWAF_HIGHLIT_CNT_WINB (ISP3X_RAWAF_BASE + 0x000D8) #define ISP3X_RAWAF_RAM_DATA (ISP3X_RAWAF_BASE + 0x000E0) +#define ISP32L_RAWAF_CORING_H (ISP3X_RAWAF_BASE + 0x000AC) +#define ISP32L_RAWAF_CORING_V (ISP3X_RAWAF_BASE + 0x000BC) #define ISP3X_RAWAWB_BASE 0x00005000 #define ISP3X_RAWAWB_CTRL (ISP3X_RAWAWB_BASE + 0x0000) @@ -1786,6 +1850,11 @@ #define ISP3X_RAWAWB_WRAM_CTRL (ISP3X_RAWAWB_BASE + 0x0654) #define ISP3X_RAWAWB_WRAM_DATA_BASE (ISP3X_RAWAWB_BASE + 0x0660) #define ISP3X_RAWAWB_RAM_DATA_BASE (ISP3X_RAWAWB_BASE + 0x0700) +#define ISP32L_RAWAWB_WIN_WEIGHT_0 (ISP3X_RAWAWB_BASE + 0x0660) +#define ISP32L_RAWAWB_WIN_WEIGHT_1 (ISP3X_RAWAWB_BASE + 0x0664) +#define ISP32L_RAWAWB_WIN_WEIGHT_2 (ISP3X_RAWAWB_BASE + 0x0668) +#define ISP32L_RAWAWB_WIN_WEIGHT_3 (ISP3X_RAWAWB_BASE + 0x066c) +#define ISP32L_RAWAWB_WIN_WEIGHT_4 (ISP3X_RAWAWB_BASE + 0x0670) /* VI_ISP_PATH */ #define ISP3X_RAWAE3_SEL(x) (((x) & 3) << 16) @@ -1795,6 +1864,7 @@ #define ISP3X_LSC_CFG_SEL(x) (((x) & 3) << 24) #define ISP32_BNR2AWB_SEL BIT(26) #define ISP32_DRC2AWB_SEL BIT(27) +#define ISP32L_BNR2AF_SEL BIT(28) /* VI_ICCL */ #define ISP32_BRSZ_CLK_ENABLE BIT(13) @@ -1840,6 +1910,9 @@ #define ISP3X_SENSOR_INDEX(x) (((x) & 3) << 28) #define ISP3X_ACQ_H_OFFS(x) ((x) & 0x7fff) +#define ISP32L_SENSOR_MODE(x) (((x) & 7) << 20) +#define ISP32L_SENSOR_FORCE_INDEX(x) (((x) & 0xf) << 24) + /* isp interrupt */ #define ISP3X_OFF BIT(0) #define ISP3X_FRAME BIT(1) @@ -1906,6 +1979,15 @@ #define ISP3X_SCL_CLIP_EN BIT(11) #define ISP3X_SCL_IN_CLIP_EN BIT(12) +#define ISP32_SCALE_AVG_H_EN BIT(8) +#define ISP32_SCALE_AVG_V_EN BIT(9) + +#define ISP32_SCALE_FORCE_UPD BIT(4) +#define ISP32_SCALE_GEN_UPD BIT(5) + +#define ISP32_SCALE_BIL_FACTOR BIT(12) +#define ISP32_SCALE_AVE_FACTOR BIT(16) + /* mi interrupt */ #define ISP3X_MI_MP_FRAME BIT(0) #define ISP3X_MI_SP_FRAME BIT(1) @@ -2057,6 +2139,21 @@ #define ISP3X_MPFBC_FORCE_UPD BIT(31) #define ISP3X_MPFBC_EN_SHD BIT(31) +/* AXI_CONFIG_RD_CTRL */ +#define ISP32L_AXI_CONF_RD_ST BIT(0) +#define ISP32L_AXI_CONF_RD_ST_MODE BIT(1) +#define ISP32L_AXI_CONF_RD_CLEAR BIT(4) +#define ISP32L_AXI_CONF_RD_DIS BIT(7) +#define ISP32L_WR_FRM_BUF_EN BIT(8) +#define ISP32L_RD_FRM_BUF_EN BIT(9) +#define ISP32L_WR_FRM_BUF_EN_SHD BIT(10) +#define ISP32L_RD_FRM_BUF_EN_SHD BIT(11) +#define ISP32L_FRM_BUF_FORCE_UPD BIT(16) +#define ISP32L_WR_FRM_BUF_ERROR BIT(28) +#define ISP32L_FRM_BUF_RW_CONFLICT BIT(29) +#define ISP32L_AXI_CONF_FAIL BIT(30) +#define ISP32L_AXI_CONF_RD_DONE BIT(31) + /* CSI2RX */ /* DEBAYER */ @@ -2138,6 +2235,7 @@ #define ISP3X_LSC_TABLE_ADDRESS_0 0 #define ISP3X_LSC_TABLE_ADDRESS_153 153 +#define ISP3X_LSC_LUT_EN BIT(1) #define ISP3X_LSC_SECTOR_16X16 BIT(2) #define ISP3X_LSC_PRE_RD_ST_MODE BIT(4) diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c index 824dcae774f3..ed63881799c5 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.c +++ b/drivers/media/platform/rockchip/isp/rkisp.c @@ -225,6 +225,10 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev, max_w = CIF_ISP_INPUT_W_MAX_V32; max_h = CIF_ISP_INPUT_H_MAX_V32; break; + case ISP_V32_L: + max_w = CIF_ISP_INPUT_W_MAX_V32_L; + max_h = CIF_ISP_INPUT_H_MAX_V32_L; + break; default: max_w = CIF_ISP_INPUT_W_MAX; max_h = CIF_ISP_INPUT_H_MAX; @@ -634,17 +638,19 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo val = rkisp_read(dev, MI_WR_CTRL2, false); rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true); rkisp_write(dev, MI_WR_INIT, ISP21_SP_FORCE_UPD | ISP21_MP_FORCE_UPD, true); - } else if (dev->isp_ver == ISP_V30) { + } else { + if (dev->isp_ver == ISP_V32_L) + rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true); rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite); - } else if (dev->isp_ver == ISP_V32) { - writel(CIF_MI_INIT_SOFT_UPD, hw->base_addr + ISP3X_MI_WR_INIT); } /* sensor mode & index */ - if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30 || - dev->isp_ver == ISP_V32) { + if (dev->isp_ver >= ISP_V21) { val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS); - val |= ISP21_SENSOR_MODE(dev->multi_mode) | - ISP21_SENSOR_INDEX(dev->multi_index); + val |= ISP21_SENSOR_INDEX(dev->multi_index); + if (dev->isp_ver == ISP_V32_L) + val |= ISP32L_SENSOR_MODE(dev->multi_mode); + else + val |= ISP21_SENSOR_MODE(dev->multi_mode); writel(val, hw->base_addr + ISP_ACQ_H_OFFS); if (hw->is_unite) writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS); @@ -671,9 +677,7 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo dev->irq_ends_mask |= ISP_FRAME_BP; } - if (dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || - dev->isp_ver == ISP_V32) + if (dev->isp_ver > ISP_V20) dma2frm = 0; if (dma2frm > 2) dma2frm = 2; @@ -992,7 +996,8 @@ static void rkisp_config_ism(struct rkisp_device *dev) bool is_unite = dev->hw_dev->is_unite; /* isp2.0 no ism */ - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21) + if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || + dev->isp_ver == ISP_V32_L) return; if (is_unite) @@ -1565,8 +1570,7 @@ static int rkisp_config_isp(struct rkisp_device *dev) if (in_fmt->mbus_code == MEDIA_BUS_FMT_Y8_1X8 || in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 || in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) { - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + if (dev->isp_ver >= ISP_V20) rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, 0, false, is_unite); else @@ -1574,8 +1578,7 @@ static int rkisp_config_isp(struct rkisp_device *dev) CIF_ISP_DEMOSAIC_BYPASS | CIF_ISP_DEMOSAIC_TH(0xc), false); } else { - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + if (dev->isp_ver >= ISP_V20) rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, SW_DEBAYER_EN | SW_DEBAYER_FILTER_G_EN | @@ -1672,8 +1675,7 @@ static int rkisp_config_isp(struct rkisp_device *dev) /* interrupt mask */ irq_mask |= CIF_ISP_FRAME | CIF_ISP_V_START | CIF_ISP_PIC_SIZE_ERROR; - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + if (dev->isp_ver >= ISP_V20) irq_mask |= ISP2X_LSC_LUT_ERR; if (dev->is_pre_on) irq_mask |= CIF_ISP_FRAME_IN; @@ -1953,8 +1955,7 @@ static int rkisp_isp_stop(struct rkisp_device *dev) readl(base + CIF_ISP_CSI0_ERR1); readl(base + CIF_ISP_CSI0_ERR2); readl(base + CIF_ISP_CSI0_ERR3); - } else if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { + } else if (dev->isp_ver >= ISP_V20) { writel(0, base + CSI2RX_MASK_PHY); writel(0, base + CSI2RX_MASK_PACKET); writel(0, base + CSI2RX_MASK_OVERFLOW); @@ -1971,8 +1972,7 @@ static int rkisp_isp_stop(struct rkisp_device *dev) writel(0, base + CIF_ISP_IMSC); writel(~0, base + CIF_ISP_ICR); - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { + if (dev->isp_ver >= ISP_V20) { writel(0, base + ISP_ISP3A_IMSC); writel(~0, base + ISP_ISP3A_ICR); } @@ -1988,8 +1988,7 @@ static int rkisp_isp_stop(struct rkisp_device *dev) udelay(20); } /* stop lsc to avoid lsclut error */ - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + if (dev->isp_ver >= ISP_V20) writel(0, base + ISP_LSC_CTRL); /* stop ISP */ val = readl(base + CIF_ISP_CTRL); @@ -2028,8 +2027,7 @@ static int rkisp_isp_stop(struct rkisp_device *dev) writel(0, base + CIF_ISP_CSI0_MASK1); writel(0, base + CIF_ISP_CSI0_MASK2); writel(0, base + CIF_ISP_CSI0_MASK3); - } else if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { + } else if (dev->isp_ver >= ISP_V20) { writel(0, base + CSI2RX_CSI2_RESETN); if (hw->is_unite) rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true); @@ -2044,8 +2042,7 @@ end: dev->sw_rd_cnt = 0; rkisp_set_state(&dev->isp_state, ISP_STOP); - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + if (dev->isp_ver >= ISP_V20) kfifo_reset(&dev->rdbk_kfifo); if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) memset(&dev->cmsk_cfg, 0, sizeof(dev->cmsk_cfg)); @@ -2587,6 +2584,10 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd, max_w = CIF_ISP_INPUT_W_MAX_V32; max_h = CIF_ISP_INPUT_H_MAX_V32; break; + case ISP_V32_L: + max_w = CIF_ISP_INPUT_W_MAX_V32_L; + max_h = CIF_ISP_INPUT_H_MAX_V32_L; + break; default: max_w = CIF_ISP_INPUT_W_MAX; max_h = CIF_ISP_INPUT_H_MAX; @@ -2677,16 +2678,14 @@ static int rkisp_isp_sd_set_selection(struct v4l2_subdev *sd, if (sel->pad == RKISP_ISP_PAD_SINK) { isp_sd->in_crop = *crop; /* don't have out crop */ - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) { + if (dev->isp_ver >= ISP_V20) { isp_sd->out_crop = *crop; isp_sd->out_crop.left = 0; isp_sd->out_crop.top = 0; dev->br_dev.crop = isp_sd->out_crop; } } else { - if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 || - dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32) + if (dev->isp_ver >= ISP_V20) *crop = isp_sd->out_crop; isp_sd->out_crop = *crop; } @@ -3046,8 +3045,7 @@ static int rkisp_isp_sd_s_power(struct v4l2_subdev *sd, int on) "%s on:%d\n", __func__, on); if (on) { - if (isp_dev->isp_ver == ISP_V20 || isp_dev->isp_ver == ISP_V21 || - isp_dev->isp_ver == ISP_V30 || isp_dev->isp_ver == ISP_V32) + if (isp_dev->isp_ver >= ISP_V20) kfifo_reset(&isp_dev->rdbk_kfifo); ret = pm_runtime_get_sync(isp_dev->dev); } else { diff --git a/drivers/media/platform/rockchip/isp/rkisp.h b/drivers/media/platform/rockchip/isp/rkisp.h index a4e5b84e58a1..0522163e7f4a 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.h +++ b/drivers/media/platform/rockchip/isp/rkisp.h @@ -57,8 +57,10 @@ #define CIF_ISP_INPUT_H_MAX_V30_UNITE 6144 #define CIF_ISP_INPUT_W_MAX_V32 3072 #define CIF_ISP_INPUT_H_MAX_V32 1728 -#define CIF_ISP_INPUT_W_MIN 208 -#define CIF_ISP_INPUT_H_MIN 128 +#define CIF_ISP_INPUT_W_MAX_V32_L 4224 +#define CIF_ISP_INPUT_H_MAX_V32_L 3136 +#define CIF_ISP_INPUT_W_MIN 272 +#define CIF_ISP_INPUT_H_MIN 256 #define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX #define CIF_ISP_OUTPUT_H_MAX CIF_ISP_INPUT_H_MAX #define CIF_ISP_OUTPUT_W_MIN CIF_ISP_INPUT_W_MIN diff --git a/include/uapi/linux/rkisp32-config.h b/include/uapi/linux/rkisp32-config.h index a967b3aad751..a49f481579a0 100644 --- a/include/uapi/linux/rkisp32-config.h +++ b/include/uapi/linux/rkisp32-config.h @@ -87,6 +87,9 @@ #define ISP32_RAWAWB_WEIGHT_NUM ISP3X_RAWAWB_WEIGHT_NUM #define ISP32_RAWAWB_SUM_NUM 4 #define ISP32_RAWAWB_RAMDATA_NUM ISP3X_RAWAWB_RAMDATA_NUM +#define ISP32L_RAWAWB_WEIGHT_NUM 5 +#define ISP32L_RAWAWB_RAMDATA_RGB_NUM 25 +#define ISP32L_RAWAWB_RAMDATA_WP_NUM 13 #define ISP32_RAWAEBIG_SUBWIN_NUM ISP3X_RAWAEBIG_SUBWIN_NUM #define ISP32_RAWAEBIG_MEAN_NUM ISP3X_RAWAEBIG_MEAN_NUM @@ -95,6 +98,7 @@ #define ISP32_RAWHISTBIG_SUBWIN_NUM ISP3X_RAWHISTBIG_SUBWIN_NUM #define ISP32_RAWHISTLITE_SUBWIN_NUM ISP3X_RAWHISTLITE_SUBWIN_NUM #define ISP32_HIST_BIN_N_MAX ISP3X_HIST_BIN_N_MAX +#define ISP32L_HIST_LITE_BIN_N_MAX 64 #define ISP32_RAWAF_CURVE_NUM ISP3X_RAWAF_CURVE_NUM #define ISP32_RAWAF_HIIR_COE_NUM ISP3X_RAWAF_HIIR_COE_NUM @@ -105,6 +109,7 @@ #define ISP32_RAWAF_SUMDATA_NUM ISP3X_RAWAF_SUMDATA_NUM #define ISP32_RAWAF_VIIR_COE_NUM 3 #define ISP32_RAWAF_GAUS_COE_NUM 9 +#define ISP32L_RAWAF_WND_DATA 25 #define ISP32_DPCC_PDAF_POINT_NUM ISP3X_DPCC_PDAF_POINT_NUM @@ -380,6 +385,11 @@ struct isp32_bay3d_cfg { u8 higaus3_mode; u8 higaus5x5_en; u8 wgtmix_opt_en; + + /* for isp32_lite */ + u8 wgtmm_opt_en; + u8 wgtmm_sel_en; + /* BAY3D_SIGGAUS */ u8 siggaus0; u8 siggaus1; @@ -398,6 +408,10 @@ struct isp32_bay3d_cfg { u16 sig1_y[ISP32_BAY3D_XY_NUM]; u16 sig2_x[ISP32_BAY3D_XY_NUM]; u16 sig2_y[ISP32_BAY3D_XY_NUM]; + + /* LODIF_STAT1 for isp32_lite */ + u16 wgtmin; + /* BAY3D_HISIGRAT */ u16 hisigrat0; u16 hisigrat1; @@ -432,6 +446,9 @@ struct isp32_ynr_cfg { /* YNR_NLM_COE */ u8 nlm_coe[ISP32_YNR_NLM_COE_NUM]; + /* LOWNR_CTRL4 for isp32_lite */ + u8 frame_add4line; + u16 global_gain; /* YNR_RNR_MAX_R */ @@ -539,6 +556,11 @@ struct isp32_sharp_cfg { u8 exgain_bypass; u8 radius_ds_mode; u8 noiseclip_mode; + + /* for isp32_lite */ + u8 clip_hf_mode; + u8 add_mode; + /* SHARP_RATIO */ u8 sharp_ratio; u8 bf_ratio; @@ -582,6 +604,11 @@ struct isp32_sharp_cfg { /* SHARP_TEXTURE */ u16 noise_sigma; u16 noise_strength; + + /* EHF_TH for isp32_lite */ + u16 ehf_th[ISP32_SHARP_Y_NUM]; + /* CLIP_NEG for isp32_lite */ + u16 clip_neg[ISP32_SHARP_Y_NUM]; } __attribute__ ((packed)); struct isp32_dhaz_cfg { @@ -861,6 +888,10 @@ struct isp32_rawawb_meas_cfg { u8 blk_measure_xytype; u8 blk_rtdw_measure_en; u8 blk_measure_illu_idx; + + /* for isp32_lite */ + u8 ds16x8_mode_en; + u8 blk_with_luma_wei_en; u16 in_overexposure_threshold; /* RAWAWB_LIMIT_RG_MAX*/ @@ -1138,12 +1169,17 @@ struct isp32_rawawb_meas_cfg { u32 islope23_3; u32 islope30_3; + /* WIN_WEIGHT for isp32_lite */ + u32 win_weight[ISP32L_RAWAWB_WEIGHT_NUM]; struct isp2x_bls_fixed_val bls2_val; } __attribute__ ((packed)); struct isp32_rawaf_meas_cfg { u8 rawaf_sel; u8 num_afm_win; + /* for isp32_lite */ + u8 bnr2af_sel; + /* CTRL */ u8 gamma_en; u8 gaus_en; @@ -1164,6 +1200,23 @@ struct isp32_rawaf_meas_cfg { u8 from_awb; u8 from_ynr; u8 ae_config_use; + /* for isp32_lite */ + u8 ae_sel; + + /* for isp32_lite */ + u8 hiir_left_border_mode; + u8 avg_ds_en; + u8 avg_ds_mode; + u8 h1_acc_mode; + u8 h2_acc_mode; + u8 v1_acc_mode; + u8 v2_acc_mode; + + /* CTRL1 for isp32_lite */ + s16 bls_offset; + u8 bls_en; + u8 hldg_dilate_num; + /* WINA_B */ struct isp2x_window win[ISP32_RAWAF_WIN_NUM]; /* INT_LINE */ @@ -1174,6 +1227,9 @@ struct isp32_rawaf_meas_cfg { /* VAR_SHIFT */ u8 afm_var_shift[ISP32_RAWAF_WIN_NUM]; u8 lum_var_shift[ISP32_RAWAF_WIN_NUM]; + /* for isp32_lite */ + u8 tnrin_shift; + /* HVIIR_VAR_SHIFT */ u8 h1iir_var_shift; u8 h2iir_var_shift; @@ -1198,6 +1254,13 @@ struct isp32_rawaf_meas_cfg { s16 v1fir_coe[ISP32_RAWAF_VFIR_COE_NUM]; s16 v2fir_coe[ISP32_RAWAF_VFIR_COE_NUM]; u16 highlit_thresh; + + /* CORING_H for isp32_lite */ + u16 h_fv_limit; + u16 h_fv_slope; + /* CORING_V for isp32_lite */ + u16 v_fv_limit; + u16 v_fv_slope; } __attribute__ ((packed)); struct isp32_cac_cfg { @@ -1405,4 +1468,60 @@ struct rkisp32_thunderboot_resmem_head { struct rkisp_thunderboot_resmem_head head; struct isp32_isp_params_cfg cfg; }; + +/****************isp32 lite********************/ + +struct isp32_lite_rawaebig_stat { + u32 sumr; + u32 sumg; + u32 sumb; + struct isp2x_rawae_meas_data data[ISP32_RAWAEBIG_MEAN_NUM]; +} __attribute__ ((packed)); + +struct isp32_lite_rawawb_meas_stat { + u32 ramdata_r[ISP32L_RAWAWB_RAMDATA_RGB_NUM]; + u32 ramdata_g[ISP32L_RAWAWB_RAMDATA_RGB_NUM]; + u32 ramdata_b[ISP32L_RAWAWB_RAMDATA_RGB_NUM]; + u32 ramdata_wpnum0[ISP32L_RAWAWB_RAMDATA_WP_NUM]; + u32 ramdata_wpnum1[ISP32L_RAWAWB_RAMDATA_WP_NUM]; + struct isp32_rawawb_sum sum[ISP32_RAWAWB_SUM_NUM]; + u16 yhist_bin[ISP32_RAWAWB_HSTBIN_NUM]; + struct isp32_rawawb_sum_exc sum_exc[ISP32_RAWAWB_EXCL_STAT_NUM]; +} __attribute__ ((packed)); + +struct isp32_lite_rawaf_ramdata { + u32 hiir_wnd_data[ISP32L_RAWAF_WND_DATA]; + u32 viir_wnd_data[ISP32L_RAWAF_WND_DATA]; +} __attribute__ ((packed)); + +struct isp32_lite_rawaf_stat { + struct isp32_lite_rawaf_ramdata ramdata; + u32 int_state; + u32 afm_sum_b; + u32 afm_lum_b; + u32 highlit_cnt_winb; +} __attribute__ ((packed)); + +struct isp32_lite_rawhistlite_stat { + u32 hist_bin[ISP32L_HIST_LITE_BIN_N_MAX]; +} __attribute__ ((packed)); + +struct isp32_lite_stat { + struct isp2x_bls_stat bls; + struct isp3x_dhaz_stat dhaz; + struct isp32_info2ddr_stat info2ddr; + struct isp2x_rawaelite_stat rawae0; + struct isp32_lite_rawaebig_stat rawae3; + struct isp32_lite_rawhistlite_stat rawhist0; + struct isp2x_rawhistbig_stat rawhist3; + struct isp32_lite_rawaf_stat rawaf; + struct isp32_lite_rawawb_meas_stat rawawb; +} __attribute__ ((packed)); + +struct rkisp32_lite_stat_buffer { + struct isp32_lite_stat params; + u32 meas_type; + u32 frame_id; + u32 params_id; +} __attribute__ ((packed)); #endif /* _UAPI_RKISP32_CONFIG_H */ From dcd2ac21b14113de24e0ab7865e7f7c6477f4050 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Fri, 14 Oct 2022 14:14:59 +0800 Subject: [PATCH 152/258] media: rockchip: isp: add rk3562 config Change-Id: I52cbcc819036b9b594a1fac0a24e8447c8ea536c Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/Kconfig | 4 +- drivers/media/platform/rockchip/isp/hw.c | 45 +++++++++++++++++++++ 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rockchip/isp/Kconfig b/drivers/media/platform/rockchip/isp/Kconfig index a6225de3f0a8..ea033da13f89 100644 --- a/drivers/media/platform/rockchip/isp/Kconfig +++ b/drivers/media/platform/rockchip/isp/Kconfig @@ -30,8 +30,8 @@ config VIDEO_ROCKCHIP_ISP_VERSION_V30 default y if CPU_RK3588 config VIDEO_ROCKCHIP_ISP_VERSION_V32 - bool "isp32 for rv1106" - default y if CPU_RV1106 + bool "isp32 for rv1106 rk3562" + default y if CPU_RV1106 || CPU_RK3562 config VIDEO_ROCKCHIP_THUNDER_BOOT_ISP bool "Rockchip Image Signal Processing Thunderboot helper" diff --git a/drivers/media/platform/rockchip/isp/hw.c b/drivers/media/platform/rockchip/isp/hw.c index a11f3d1dff5a..6013f3a6da50 100644 --- a/drivers/media/platform/rockchip/isp/hw.c +++ b/drivers/media/platform/rockchip/isp/hw.c @@ -348,6 +348,12 @@ int rkisp_register_irq(struct rkisp_hw_dev *hw_dev) return 0; } +static const char * const rk3562_isp_clks[] = { + "clk_isp_core", + "aclk_isp", + "hclk_isp", +}; + static const char * const rk3568_isp_clks[] = { "clk_isp", "aclk_isp", @@ -388,6 +394,22 @@ static const char * const rv1126_isp_clks[] = { "hclk_isp", }; +static const struct isp_clk_info rk3562_isp_clk_rate[] = { + { + .clk_rate = 300, + .refer_data = 1920, //width + }, { + .clk_rate = 400, + .refer_data = 2688, + }, { + .clk_rate = 500, + .refer_data = 3072, + }, { + .clk_rate = 600, + .refer_data = 3840, + } +}; + static const struct isp_clk_info rk3568_isp_clk_rate[] = { { .clk_rate = 300, @@ -455,6 +477,12 @@ static const struct isp_clk_info rv1126_isp_clk_rate[] = { } }; +static struct isp_irqs_data rk3562_isp_irqs[] = { + {"isp_irq", isp_irq_hdl}, + {"mi_irq", mi_irq_hdl}, + {"mipi_irq", mipi_irq_hdl} +}; + static struct isp_irqs_data rk3568_isp_irqs[] = { {"isp_irq", isp_irq_hdl}, {"mi_irq", mi_irq_hdl}, @@ -501,6 +529,17 @@ static const struct isp_match_data rv1126_isp_match_data = { .unite = false, }; +static const struct isp_match_data rk3562_isp_match_data = { + .clks = rk3562_isp_clks, + .num_clks = ARRAY_SIZE(rk3562_isp_clks), + .isp_ver = ISP_V32_L, + .clk_rate_tbl = rk3562_isp_clk_rate, + .num_clk_rate_tbl = ARRAY_SIZE(rk3562_isp_clk_rate), + .irqs = rk3562_isp_irqs, + .num_irqs = ARRAY_SIZE(rk3562_isp_irqs), + .unite = false, +}; + static const struct isp_match_data rk3568_isp_match_data = { .clks = rk3568_isp_clks, .num_clks = ARRAY_SIZE(rk3568_isp_clks), @@ -535,6 +574,12 @@ static const struct isp_match_data rk3588_isp_unite_match_data = { }; static const struct of_device_id rkisp_hw_of_match[] = { +#ifdef CONFIG_CPU_RK3562 + { + .compatible = "rockchip,rk3562-rkisp", + .data = &rk3562_isp_match_data, + }, +#endif #ifdef CONFIG_CPU_RK3568 { .compatible = "rockchip,rk3568-rkisp", From e83e121d6f3902fcda8190a8f6c25c30734ee432 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Fri, 3 Feb 2023 14:19:43 +0800 Subject: [PATCH 153/258] media: rockchip: isp: add iqtool video for isp32 lite Change-Id: If5d31fc2b75e9aa0980044c47a8e429cc7e2a1b5 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/capture.c | 52 +++++- drivers/media/platform/rockchip/isp/capture.h | 2 +- .../media/platform/rockchip/isp/capture_v30.c | 2 + .../media/platform/rockchip/isp/capture_v32.c | 171 ++++++++++++++++-- include/uapi/linux/rkisp2-config.h | 4 + 5 files changed, 205 insertions(+), 26 deletions(-) diff --git a/drivers/media/platform/rockchip/isp/capture.c b/drivers/media/platform/rockchip/isp/capture.c index a361021c3ef1..6a049548d0bb 100644 --- a/drivers/media/platform/rockchip/isp/capture.c +++ b/drivers/media/platform/rockchip/isp/capture.c @@ -676,18 +676,24 @@ static int rkisp_set_fmt(struct rkisp_stream *stream, pixm->height = max_rsz.height; } } else if (stream->id == RKISP_STREAM_VIR) { - for (i = RKISP_STREAM_MP; i < RKISP_STREAM_VIR; i++) { - struct rkisp_stream *t = &dev->cap_dev.stream[i]; + struct rkisp_stream *t; - if (t->out_isp_fmt.fmt_type != FMT_YUV || !t->streaming) - continue; - if (t->out_fmt.plane_fmt[0].sizeimage > imagsize) { - imagsize = t->out_fmt.plane_fmt[0].sizeimage; - *pixm = t->out_fmt; - stream->conn_id = t->id; + if (stream->conn_id != -1) { + t = &dev->cap_dev.stream[stream->conn_id]; + *pixm = t->out_fmt; + } else { + for (i = RKISP_STREAM_MP; i < RKISP_STREAM_VIR; i++) { + t = &dev->cap_dev.stream[i]; + if (t->out_isp_fmt.fmt_type != FMT_YUV || !t->streaming) + continue; + if (t->out_fmt.plane_fmt[0].sizeimage > imagsize) { + imagsize = t->out_fmt.plane_fmt[0].sizeimage; + *pixm = t->out_fmt; + stream->conn_id = t->id; + } } } - if (!imagsize) { + if (stream->conn_id == -1) { v4l2_err(&dev->v4l2_dev, "no output stream for iqtool\n"); return -EINVAL; } @@ -1052,10 +1058,11 @@ static int rkisp_get_stream_info(struct rkisp_stream *stream, u32 id = 0; rkisp_dmarx_get_frame(stream->ispdev, &id, NULL, NULL, true); - info->cur_frame_id = id; + info->cur_frame_id = stream->dbg.id; info->input_frame_loss = dev->isp_sdev.dbg.frameloss; info->output_frame_loss = stream->dbg.frameloss; info->stream_on = stream->streaming; + info->stream_id = stream->id; return 0; } @@ -1167,6 +1174,28 @@ int rkisp_free_tb_stream_buf(struct rkisp_stream *stream) return sd->ops->core->ioctl(sd, RKISP_CMD_FREE_SHARED_BUF, NULL); } +static int rkisp_set_iqtool_connect_id(struct rkisp_stream *stream, int stream_id) +{ + struct rkisp_device *dev = stream->ispdev; + + if (stream->id != RKISP_STREAM_VIR) { + v4l2_err(&dev->v4l2_dev, "only support for iqtool video\n"); + goto err; + } + + if (stream_id != RKISP_STREAM_MP && + stream_id != RKISP_STREAM_SP && + stream_id != RKISP_STREAM_BP) { + v4l2_err(&dev->v4l2_dev, "invalid connect stream id\n"); + goto err; + } + + stream->conn_id = stream_id; + return 0; +err: + return -EINVAL; +} + static long rkisp_ioctl_default(struct file *file, void *fh, bool valid_prio, unsigned int cmd, void *arg) { @@ -1237,6 +1266,9 @@ static long rkisp_ioctl_default(struct file *file, void *fh, case RKISP_CMD_FREE_TB_STREAM_BUF: ret = rkisp_free_tb_stream_buf(stream); break; + case RKISP_CMD_SET_IQTOOL_CONN_ID: + ret = rkisp_set_iqtool_connect_id(stream, *(int *)arg); + break; default: ret = -EINVAL; } diff --git a/drivers/media/platform/rockchip/isp/capture.h b/drivers/media/platform/rockchip/isp/capture.h index 7f7408e363ec..04e90d628311 100644 --- a/drivers/media/platform/rockchip/isp/capture.h +++ b/drivers/media/platform/rockchip/isp/capture.h @@ -285,7 +285,7 @@ struct rkisp_stream { unsigned int burst; atomic_t sequence; struct frame_debug_info dbg; - u8 conn_id; + int conn_id; u32 memory; union { struct rkisp_stream_sp sp; diff --git a/drivers/media/platform/rockchip/isp/capture_v30.c b/drivers/media/platform/rockchip/isp/capture_v30.c index 8e51d4d9b228..80e38646cdcb 100644 --- a/drivers/media/platform/rockchip/isp/capture_v30.c +++ b/drivers/media/platform/rockchip/isp/capture_v30.c @@ -1248,6 +1248,7 @@ static void rkisp_stop_streaming(struct vb2_queue *queue) if (!completion_done(&dev->cap_dev.vir_cpy.cmpl)) complete(&dev->cap_dev.vir_cpy.cmpl); + stream->conn_id = -1; goto end; } @@ -1572,6 +1573,7 @@ static int rkisp_stream_init(struct rkisp_device *dev, u32 id) strscpy(vdev->name, VIR_VDEV_NAME, sizeof(vdev->name)); stream->ops = NULL; stream->config = &rkisp_mp_stream_config; + stream->conn_id = -1; break; default: strscpy(vdev->name, MP_VDEV_NAME, sizeof(vdev->name)); diff --git a/drivers/media/platform/rockchip/isp/capture_v32.c b/drivers/media/platform/rockchip/isp/capture_v32.c index 05f4fc1e5e2f..347ef4c1bb9a 100644 --- a/drivers/media/platform/rockchip/isp/capture_v32.c +++ b/drivers/media/platform/rockchip/isp/capture_v32.c @@ -1080,8 +1080,6 @@ static void update_mi(struct rkisp_stream *stream) /* wrap buf ENC */ if (dev->isp_ver == ISP_V32) val += stream->out_fmt.plane_fmt[0].bytesperline * dev->cap_dev.wrap_line; - else - stream->dbg.frameloss++; reg = stream->config->mi.cb_base_ad_init; rkisp_write(dev, reg, val, false); if (is_cr_cfg) { @@ -1373,10 +1371,14 @@ static int mi_frame_end(struct rkisp_stream *stream) unsigned long lock_flags = 0; u32 i; + if (stream->id == RKISP_STREAM_VIR) + return 0; + set_mirror_flip(stream); if (stream->curr_buf) { struct vb2_buffer *vb2_buf = &stream->curr_buf->vb.vb2_buf; + struct rkisp_stream *vir = &dev->cap_dev.stream[RKISP_STREAM_VIR]; if (dev->skip_frame) { spin_lock_irqsave(&stream->vbq_lock, lock_flags); @@ -1391,10 +1393,20 @@ static int mi_frame_end(struct rkisp_stream *stream) vb2_set_plane_payload(vb2_buf, i, payload_size); } - if (vb2_buf->memory) - rkisp_stream_buf_done(stream, stream->curr_buf); - else + if (vb2_buf->memory) { + if (vir->streaming && vir->conn_id == stream->id) { + spin_lock_irqsave(&vir->vbq_lock, lock_flags); + list_add_tail(&stream->curr_buf->queue, + &dev->cap_dev.vir_cpy.queue); + spin_unlock_irqrestore(&vir->vbq_lock, lock_flags); + if (!completion_done(&dev->cap_dev.vir_cpy.cmpl)) + complete(&dev->cap_dev.vir_cpy.cmpl); + } else { + rkisp_stream_buf_done(stream, stream->curr_buf); + } + } else { rkisp_rockit_buf_done(stream, ROCKIT_DVBM_END); + } } next: spin_lock_irqsave(&stream->vbq_lock, lock_flags); @@ -1590,7 +1602,7 @@ static void rkisp_buf_queue(struct vb2_buffer *vb) spin_lock_irqsave(&stream->vbq_lock, lock_flags); /* single sensor with pingpong buf, update next if need */ - if (stream->ispdev->hw_dev->is_single && + if (dev->hw_dev->is_single && stream->id != RKISP_STREAM_VIR && stream->id != RKISP_STREAM_LUMA && stream->streaming && !stream->next_buf) { @@ -1680,7 +1692,7 @@ static void rkisp_stop_streaming(struct vb2_queue *queue) if (!stream->streaming) goto end; - if (stream->id == RKISP_STREAM_LUMA) { + if (stream->id == RKISP_STREAM_LUMA || stream->id == RKISP_STREAM_VIR) { stream->stopping = true; if (!dev->hw_dev->is_shutdown) wait_event_timeout(stream->done, @@ -1689,7 +1701,12 @@ static void rkisp_stop_streaming(struct vb2_queue *queue) stream->streaming = false; stream->stopping = false; destroy_buf_queue(stream, VB2_BUF_STATE_ERROR); - tasklet_disable(&dev->cap_dev.rd_tasklet); + if (stream->id == RKISP_STREAM_LUMA) { + tasklet_disable(&dev->cap_dev.rd_tasklet); + } else if (!completion_done(&dev->cap_dev.vir_cpy.cmpl)) { + complete(&dev->cap_dev.vir_cpy.cmpl); + stream->conn_id = -1; + } goto end; } @@ -1721,6 +1738,97 @@ end: } } +static void vir_cpy_image(struct work_struct *work) +{ + struct rkisp_vir_cpy *cpy = + container_of(work, struct rkisp_vir_cpy, work); + struct rkisp_stream *vir = cpy->stream; + struct rkisp_buffer *src_buf = NULL; + unsigned long lock_flags = 0; + u32 i; + + v4l2_dbg(1, rkisp_debug, &vir->ispdev->v4l2_dev, + "%s enter\n", __func__); + + vir->streaming = true; + spin_lock_irqsave(&vir->vbq_lock, lock_flags); + if (!list_empty(&cpy->queue)) { + src_buf = list_first_entry(&cpy->queue, + struct rkisp_buffer, queue); + list_del(&src_buf->queue); + } + spin_unlock_irqrestore(&vir->vbq_lock, lock_flags); + + while (src_buf || vir->streaming) { + if (vir->stopping || !vir->streaming) + goto end; + + if (!src_buf) + wait_for_completion(&cpy->cmpl); + + vir->frame_end = false; + spin_lock_irqsave(&vir->vbq_lock, lock_flags); + + if (!src_buf && !list_empty(&cpy->queue)) { + src_buf = list_first_entry(&cpy->queue, + struct rkisp_buffer, queue); + list_del(&src_buf->queue); + } + + if (src_buf && !vir->curr_buf && !list_empty(&vir->buf_queue)) { + vir->curr_buf = list_first_entry(&vir->buf_queue, + struct rkisp_buffer, queue); + list_del(&vir->curr_buf->queue); + } + spin_unlock_irqrestore(&vir->vbq_lock, lock_flags); + + if (!vir->curr_buf || !src_buf) + goto end; + + for (i = 0; i < vir->out_isp_fmt.mplanes; i++) { + u32 payload_size = vir->out_fmt.plane_fmt[i].sizeimage; + void *src = vb2_plane_vaddr(&src_buf->vb.vb2_buf, i); + void *dst = vb2_plane_vaddr(&vir->curr_buf->vb.vb2_buf, i); + + if (!src || !dst) + break; + vb2_set_plane_payload(&vir->curr_buf->vb.vb2_buf, i, payload_size); + memcpy(dst, src, payload_size); + } + + vir->curr_buf->vb.sequence = src_buf->vb.sequence; + vir->curr_buf->vb.vb2_buf.timestamp = src_buf->vb.vb2_buf.timestamp; + vb2_buffer_done(&vir->curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + vir->curr_buf = NULL; +end: + if (src_buf) + vb2_buffer_done(&src_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + src_buf = NULL; + spin_lock_irqsave(&vir->vbq_lock, lock_flags); + + if (!list_empty(&cpy->queue)) { + src_buf = list_first_entry(&cpy->queue, + struct rkisp_buffer, queue); + list_del(&src_buf->queue); + } else if (vir->stopping) { + vir->streaming = false; + } + + spin_unlock_irqrestore(&vir->vbq_lock, lock_flags); + } + + vir->frame_end = true; + + if (vir->stopping) { + vir->stopping = false; + vir->streaming = false; + wake_up(&vir->done); + } + + v4l2_dbg(1, rkisp_debug, &vir->ispdev->v4l2_dev, + "%s exit\n", __func__); +} + static int rkisp_stream_start(struct rkisp_stream *stream) { struct rkisp_device *dev = stream->ispdev; @@ -1779,6 +1887,25 @@ rkisp_start_streaming(struct vb2_queue *queue, unsigned int count) return -EBUSY; } + if (stream->id == RKISP_STREAM_VIR) { + struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id]; + + if (t->streaming) { + INIT_WORK(&dev->cap_dev.vir_cpy.work, vir_cpy_image); + init_completion(&dev->cap_dev.vir_cpy.cmpl); + INIT_LIST_HEAD(&dev->cap_dev.vir_cpy.queue); + dev->cap_dev.vir_cpy.stream = stream; + schedule_work(&dev->cap_dev.vir_cpy.work); + ret = 0; + } else { + v4l2_err(&dev->v4l2_dev, "no stream enable for iqtool\n"); + destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED); + ret = -EINVAL; + } + mutex_unlock(&dev->hw_dev->dev_lock); + return ret; + } + memset(&stream->dbg, 0, sizeof(stream->dbg)); if (stream->id == RKISP_STREAM_LUMA) { @@ -1960,6 +2087,12 @@ static int rkisp_stream_init(struct rkisp_device *dev, u32 id) (unsigned long)stream); tasklet_disable(&cap_dev->rd_tasklet); break; + case RKISP_STREAM_VIR: + strscpy(vdev->name, VIR_VDEV_NAME, sizeof(vdev->name)); + stream->ops = NULL; + stream->config = &rkisp_mp_stream_config; + stream->conn_id = -1; + break; default: strscpy(vdev->name, MP_VDEV_NAME, sizeof(vdev->name)); stream->ops = &rkisp_mp_streams_ops; @@ -2015,6 +2148,10 @@ int rkisp_register_stream_v32(struct rkisp_device *dev) goto err_free_bpds; rkisp_dvbm_get(dev); rkisp_rockit_dev_init(dev); + } else { + ret = rkisp_stream_init(dev, RKISP_STREAM_VIR); + if (ret < 0) + goto err_free_sp; } return 0; err_free_bpds: @@ -2050,6 +2187,9 @@ void rkisp_unregister_stream_v32(struct rkisp_device *dev) stream = &cap_dev->stream[RKISP_STREAM_LUMA]; rkisp_unregister_stream_vdev(stream); rkisp_rockit_dev_deinit(); + } else { + stream = &cap_dev->stream[RKISP_STREAM_VIR]; + rkisp_unregister_stream_vdev(stream); } } @@ -2067,7 +2207,8 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) for (i = 0; i < RKISP_MAX_STREAM; ++i) { stream = &dev->cap_dev.stream[i]; - if (!(mis_val & CIF_MI_FRAME(stream))) + if (!(mis_val & CIF_MI_FRAME(stream)) || + stream->id == RKISP_STREAM_VIR) continue; mi_frame_end_int_clear(stream); @@ -2081,13 +2222,13 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) if (stream->curr_buf) { stream->curr_buf->vb.sequence = seq; stream->curr_buf->vb.vb2_buf.timestamp = ns; - } - ns = ktime_get_ns(); - stream->dbg.interval = ns - stream->dbg.timestamp; - stream->dbg.delay = ns - dev->isp_sdev.frm_timestamp; - stream->dbg.timestamp = ns; - stream->dbg.id = seq; + ns = ktime_get_ns(); + stream->dbg.interval = ns - stream->dbg.timestamp; + stream->dbg.delay = ns - dev->isp_sdev.frm_timestamp; + stream->dbg.timestamp = ns; + stream->dbg.id = seq; + } if (stream->is_tb_s_info) { struct rkisp_tb_stream_info *tb_info = &dev->tb_stream_info; u32 idx; diff --git a/include/uapi/linux/rkisp2-config.h b/include/uapi/linux/rkisp2-config.h index 667aad1f4d1a..cb0078ccccf1 100644 --- a/include/uapi/linux/rkisp2-config.h +++ b/include/uapi/linux/rkisp2-config.h @@ -96,6 +96,9 @@ #define RKISP_CMD_FREE_TB_STREAM_BUF \ _IO('V', BASE_VIDIOC_PRIVATE + 112) + +#define RKISP_CMD_SET_IQTOOL_CONN_ID \ + _IOW('V', BASE_VIDIOC_PRIVATE + 113, int) /*************************************************************/ #define ISP2X_ID_DPCC (0) @@ -375,6 +378,7 @@ struct rkisp_stream_info { unsigned int input_frame_loss; unsigned int output_frame_loss; unsigned char stream_on; + unsigned char stream_id; } __attribute__ ((packed)); /* struct rkisp_mirror_flip From 982a6aceb151259fc05b6a183deced96019100b5 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Tue, 10 May 2022 17:21:36 +0800 Subject: [PATCH 154/258] arm64: dts: rockchip: rk3399-evb-ind: add dp alt mode node Add dp alt mode node to support tcpm Signed-off-by: Zhang Yubing Change-Id: I8130045074c9bc8c8b8223f44ebe5341db20b97d --- .../boot/dts/rockchip/rk3399-evb-ind.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi index cd2b6f1ef664..78c2d2f87e5d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi @@ -874,6 +874,19 @@ source-pdos = ; + displayport = <&cdn_dp>; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; @@ -884,6 +897,12 @@ remote-endpoint = <&tcphy0_orientation_switch>; }; }; + port@1 { + reg = <1>; + dp_mode_sw: endpoint { + remote-endpoint = <&tcphy_dp_altmode_switch>; + }; + }; }; }; }; @@ -1209,6 +1228,7 @@ &tcphy0 { status = "okay"; + svid = <0xff01>; orientation-switch; port { #address-cells = <1>; @@ -1217,6 +1237,10 @@ reg = <0>; remote-endpoint = <&usbc0_orien_sw>; }; + tcphy_dp_altmode_switch: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_mode_sw>; + }; }; }; From 00d76e6608fc6f352bf38980f46240a761916eda Mon Sep 17 00:00:00 2001 From: Hu Kejun Date: Tue, 14 Feb 2023 10:59:19 +0800 Subject: [PATCH 155/258] media: i2c: dw9714: fix i2c error in resume function Signed-off-by: Hu Kejun Change-Id: Ieb2b4f0c7a3bdef20392b746c7330fb6a0a72df1 --- drivers/media/i2c/dw9714.c | 345 ++++++++++++++++++++++++------------- 1 file changed, 222 insertions(+), 123 deletions(-) diff --git a/drivers/media/i2c/dw9714.c b/drivers/media/i2c/dw9714.c index df0d80a56e9d..685234a5b50a 100644 --- a/drivers/media/i2c/dw9714.c +++ b/drivers/media/i2c/dw9714.c @@ -15,6 +15,7 @@ #include #include #include +#include #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x0) #define DW9714_NAME "dw9714" @@ -95,6 +96,9 @@ struct dw9714_device { struct rk_cam_vcm_cfg vcm_cfg; struct gpio_desc *xsd_gpio; + struct regulator *supply; + struct i2c_client *client; + bool power_on; }; struct TimeTabel_s { @@ -631,8 +635,98 @@ static const struct v4l2_ctrl_ops dw9714_vcm_ctrl_ops = { .s_ctrl = dw9714_set_ctrl, }; +static int dw9714_init(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct dw9714_device *dw9714_dev = sd_to_dw9714_vcm(sd); + unsigned char data = 0x0; + int ret = 0; + + if (dw9714_dev->adcanced_mode) { + // need to wait 1ms after poweron + usleep_range(1000, 1200); + // Advanced Mode + ret = dw9714_write_msg(client, 0xED, 0xAB); + if (ret) + goto err; + // Power down + ret = dw9714_write_msg(client, DW9714_ADVMODE_CONTROL, 0x01); + if (ret) + goto err; + // active + ret = dw9714_write_msg(client, DW9714_ADVMODE_CONTROL, 0x00); + if (ret) + goto err; + // delay 1ms + usleep_range(1000, 1200); + // SAC mode & nrc_time & nrc_infl + data = DW9714_ADVMODE_RING_EN << 7 | + (dw9714_dev->nrc_infl & 0x3) << 5 | + (dw9714_dev->nrc_time & 0x1) << 4 | + (dw9714_dev->sac_mode & 0xF); + ret = dw9714_write_msg(client, DW9714_ADVMODE_SAC_CFG, data); + if (ret) + goto err; + // Set Tvib (PRESC[1:0] ) + ret = dw9714_write_msg(client, DW9714_ADVMODE_PRESC, dw9714_dev->sac_prescl); + if (ret) + goto err; + // Set Tvib (SACT[6:0] ) + ret = dw9714_write_msg(client, DW9714_ADVMODE_SAC_TIME, dw9714_dev->sac_time); + if (ret) + goto err; + // nrc preset + ret = dw9714_write_msg(client, DW9714_ADVMODE_PRESET, dw9714_dev->nrc_preset); + if (ret) + goto err; + // nrc en & nrc mode + data = (dw9714_dev->nrc_en & 0x1) << 1 | + (dw9714_dev->nrc_mode & 0x1); + ret = dw9714_write_msg(client, DW9714_ADVMODE_NRC, data); + if (ret) + goto err; + } else { + // need to wait 12ms after poweron + usleep_range(12000, 12500); + + ret = dw9714_write_msg(client, 0xEC, 0xA3); + if (ret) + goto err; + + data = (dw9714_dev->mclk & 0x3) | 0x04 | + ((dw9714_dev->dlc_enable << 0x3) & 0x08); + ret = dw9714_write_msg(client, 0xA1, data); + if (ret) + goto err; + + data = (dw9714_dev->t_src << 0x3) & 0xf8; + ret = dw9714_write_msg(client, 0xF2, data); + if (ret) + goto err; + + ret = dw9714_write_msg(client, 0xDC, 0x51); + if (ret) + goto err; + + /* set normal mode */ + ret = dw9714_write_msg(client, 0xDF, 0x5B); + if (ret != 0) + dev_err(&client->dev, + "%s: failed with error %d\n", __func__, ret); + } + + return 0; +err: + dev_err(&client->dev, "failed with error %d\n", ret); + return -1; +} + static int dw9714_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { + struct dw9714_device *dev_vcm = sd_to_dw9714_vcm(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int move_time; + int dac = 0; int rval; rval = pm_runtime_get_sync(sd->dev); @@ -641,11 +735,50 @@ static int dw9714_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) return rval; } + dw9714_init(client); + + dev_dbg(&client->dev, "%s: current_lens_pos %d, current_related_pos %d\n", + __func__, dev_vcm->current_lens_pos, dev_vcm->current_related_pos); + move_time = 1000 * dw9714_move_time(dev_vcm, DW9714_GRADUAL_MOVELENS_STEPS); + while (dac <= dev_vcm->current_lens_pos) { + dw9714_set_dac(dev_vcm, dac); + usleep_range(move_time, move_time + 1000); + dac += DW9714_GRADUAL_MOVELENS_STEPS; + if (dac >= dev_vcm->current_lens_pos) + break; + } + + if (dac > dev_vcm->current_lens_pos) { + dac = dev_vcm->current_lens_pos; + dw9714_set_dac(dev_vcm, dac); + } + return 0; } static int dw9714_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { + struct dw9714_device *dev_vcm = sd_to_dw9714_vcm(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int dac = dev_vcm->current_lens_pos; + unsigned int move_time; + + dev_dbg(&client->dev, "%s: current_lens_pos %d, current_related_pos %d\n", + __func__, dev_vcm->current_lens_pos, dev_vcm->current_related_pos); + move_time = 1000 * dw9714_move_time(dev_vcm, DW9714_GRADUAL_MOVELENS_STEPS); + while (dac >= 0) { + dw9714_set_dac(dev_vcm, dac); + usleep_range(move_time, move_time + 1000); + dac -= DW9714_GRADUAL_MOVELENS_STEPS; + if (dac <= 0) + break; + } + + if (dac < 0) { + dac = 0; + dw9714_set_dac(dev_vcm, dac); + } + pm_runtime_put(sd->dev); return 0; @@ -899,6 +1032,76 @@ static inline int remove_sysfs_interfaces(struct device *dev) } #endif +static int dw9714_set_power(struct dw9714_device *dw9714, bool on) +{ + struct i2c_client *client = dw9714->client; + int ret = 0; + + dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on); + + if (dw9714->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = regulator_enable(dw9714->supply); + if (ret < 0) { + dev_err(&client->dev, "Failed to enable regulator\n"); + goto unlock_and_return; + } + dw9714->power_on = true; + } else { + ret = regulator_disable(dw9714->supply); + if (ret < 0) { + dev_err(&client->dev, "Failed to disable regulator\n"); + goto unlock_and_return; + } + dw9714->power_on = false; + } + +unlock_and_return: + return ret; +} + +static int dw9714_check_i2c(struct dw9714_device *dw9714, + struct i2c_client *client) +{ + struct device *dev = &client->dev; + int ret; + + if (dw9714->adcanced_mode) { + // need to wait 1ms after poweron + usleep_range(1000, 1200); + // Advanced Mode + ret = dw9714_write_msg(client, 0xED, 0xAB); + } else { + // need to wait 12ms after poweron + usleep_range(12000, 12500); + ret = dw9714_write_msg(client, 0xEC, 0xA3); + } + if (!ret) + dev_info(dev, "check dw9714 connection OK!\n"); + else + dev_info(dev, "dw9714 not connect!\n"); + + return ret; +} + +static int dw9714_configure_regulator(struct dw9714_device *dw9714) +{ + struct i2c_client *client = dw9714->client; + int ret = 0; + + dw9714->supply = devm_regulator_get(&client->dev, "avdd"); + if (IS_ERR(dw9714->supply)) { + ret = PTR_ERR(dw9714->supply); + if (ret != -EPROBE_DEFER) + dev_err(&client->dev, "could not get regulator avdd\n"); + return ret; + } + dw9714->power_on = false; + return ret; +} + static int dw9714_parse_dt_property(struct i2c_client *client, struct dw9714_device *dev_vcm) { @@ -1051,6 +1254,13 @@ static int dw9714_parse_dt_property(struct i2c_client *client, return -EINVAL; } + dev_vcm->client = client; + ret = dw9714_configure_regulator(dev_vcm); + if (ret) { + dev_err(&client->dev, "Failed to get power regulator!\n"); + return ret; + } + dev_dbg(&client->dev, "current: %d, %d, %d, dlc_en: %d, t_src: %d, mclk: %d", dev_vcm->max_current, dev_vcm->start_current, @@ -1104,6 +1314,14 @@ static int dw9714_probe(struct i2c_client *client, if (ret < 0) goto err_cleanup; + ret = dw9714_set_power(dw9714_dev, true); + if (ret) + goto err_cleanup; + + ret = dw9714_check_i2c(dw9714_dev, client); + if (ret) + goto err_power_off; + sd = &dw9714_dev->sd; sd->entity.function = MEDIA_ENT_F_LENS; @@ -1135,6 +1353,8 @@ static int dw9714_probe(struct i2c_client *client, return 0; +err_power_off: + dw9714_set_power(dw9714_dev, false); err_cleanup: dw9714_subdev_cleanup(dw9714_dev); dev_err(&client->dev, "Probe failed: %d\n", ret); @@ -1153,115 +1373,13 @@ static int dw9714_remove(struct i2c_client *client) return 0; } -static int dw9714_init(struct i2c_client *client) -{ - struct v4l2_subdev *sd = i2c_get_clientdata(client); - struct dw9714_device *dw9714_dev = sd_to_dw9714_vcm(sd); - unsigned char data = 0x0; - int ret = 0; - - if (dw9714_dev->adcanced_mode) { - // need to wait 1ms after poweron - usleep_range(1000, 1200); - // Advanced Mode - ret = dw9714_write_msg(client, 0xED, 0xAB); - if (ret) - goto err; - // Power down - ret = dw9714_write_msg(client, DW9714_ADVMODE_CONTROL, 0x01); - if (ret) - goto err; - // active - ret = dw9714_write_msg(client, DW9714_ADVMODE_CONTROL, 0x00); - if (ret) - goto err; - // delay 1ms - usleep_range(1000, 1200); - // SAC mode & nrc_time & nrc_infl - data = DW9714_ADVMODE_RING_EN << 7 | - (dw9714_dev->nrc_infl & 0x3) << 5 | - (dw9714_dev->nrc_time & 0x1) << 4 | - (dw9714_dev->sac_mode & 0xF); - ret = dw9714_write_msg(client, DW9714_ADVMODE_SAC_CFG, data); - if (ret) - goto err; - // Set Tvib (PRESC[1:0] ) - ret = dw9714_write_msg(client, DW9714_ADVMODE_PRESC, dw9714_dev->sac_prescl); - if (ret) - goto err; - // Set Tvib (SACT[6:0] ) - ret = dw9714_write_msg(client, DW9714_ADVMODE_SAC_TIME, dw9714_dev->sac_time); - if (ret) - goto err; - // nrc preset - ret = dw9714_write_msg(client, DW9714_ADVMODE_PRESET, dw9714_dev->nrc_preset); - if (ret) - goto err; - // nrc en & nrc mode - data = (dw9714_dev->nrc_en & 0x1) << 1 | - (dw9714_dev->nrc_mode & 0x1); - ret = dw9714_write_msg(client, DW9714_ADVMODE_NRC, data); - if (ret) - goto err; - } else { - // need to wait 12ms after poweron - usleep_range(12000, 12500); - - ret = dw9714_write_msg(client, 0xEC, 0xA3); - if (ret) - goto err; - - data = (dw9714_dev->mclk & 0x3) | 0x04 | - ((dw9714_dev->dlc_enable << 0x3) & 0x08); - ret = dw9714_write_msg(client, 0xA1, data); - if (ret) - goto err; - - data = (dw9714_dev->t_src << 0x3) & 0xf8; - ret = dw9714_write_msg(client, 0xF2, data); - if (ret) - goto err; - - ret = dw9714_write_msg(client, 0xDC, 0x51); - if (ret) - goto err; - - /* set normal mode */ - ret = dw9714_write_msg(client, 0xDF, 0x5B); - if (ret != 0) - dev_err(&client->dev, - "%s: failed with error %d\n", __func__, ret); - } - - return 0; -err: - dev_err(&client->dev, "failed with error %d\n", ret); - return -1; -} - static int __maybe_unused dw9714_vcm_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); struct dw9714_device *dev_vcm = sd_to_dw9714_vcm(sd); - int dac = dev_vcm->current_lens_pos; - unsigned int move_time; - dev_dbg(&client->dev, "%s: current_lens_pos %d, current_related_pos %d\n", - __func__, dev_vcm->current_lens_pos, dev_vcm->current_related_pos); - move_time = 1000 * dw9714_move_time(dev_vcm, DW9714_GRADUAL_MOVELENS_STEPS); - while (dac >= 0) { - dw9714_set_dac(dev_vcm, dac); - usleep_range(move_time, move_time + 1000); - dac -= DW9714_GRADUAL_MOVELENS_STEPS; - if (dac <= 0) - break; - } - - if (dac < 0) { - dac = 0; - dw9714_set_dac(dev_vcm, dac); - } + dw9714_set_power(dev_vcm, false); return 0; } @@ -1270,27 +1388,8 @@ static int __maybe_unused dw9714_vcm_resume(struct device *dev) struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *sd = i2c_get_clientdata(client); struct dw9714_device *dev_vcm = sd_to_dw9714_vcm(sd); - unsigned int move_time; - int dac = 0; - - dw9714_init(client); - - dev_dbg(&client->dev, "%s: current_lens_pos %d, current_related_pos %d\n", - __func__, dev_vcm->current_lens_pos, dev_vcm->current_related_pos); - move_time = 1000 * dw9714_move_time(dev_vcm, DW9714_GRADUAL_MOVELENS_STEPS); - while (dac <= dev_vcm->current_lens_pos) { - dw9714_set_dac(dev_vcm, dac); - usleep_range(move_time, move_time + 1000); - dac += DW9714_GRADUAL_MOVELENS_STEPS; - if (dac >= dev_vcm->current_lens_pos) - break; - } - - if (dac > dev_vcm->current_lens_pos) { - dac = dev_vcm->current_lens_pos; - dw9714_set_dac(dev_vcm, dac); - } + dw9714_set_power(dev_vcm, true); return 0; } From 5156642dd94c1d9e77f625fa97e2605b6b9bf5cf Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 14 Feb 2023 11:12:05 +0800 Subject: [PATCH 156/258] arm64: dts: rockchip: rk3562-evb: add rgb->panel display board RGB panel FX070-DHM11BOE-A supports RGB666 and RGB888 mode. Signed-off-by: Damon Ding Change-Id: Ice4688d7f9ff66094836baf474e09ed8edba747a --- arch/arm64/boot/dts/rockchip/Makefile | 1 + ...562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts | 131 ++++++++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 42ea1ce9871d..a1c5a04a8507 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux-amp.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-mcu-k350c4516t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb2lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts new file mode 100644 index 000000000000..c52b35ce02a8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + + +/ { + model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB VOP3 RGB24BIT DISPLAY Ext Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A", "rockchip,rk3562"; + + panel: panel { + compatible = "simple-panel"; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + reset-value = <0>; + reset-delay-ms = <10>; + status = "okay"; + + display-timings { + native-mode = <&fx070_dhm11boe_timing>; + + fx070_dhm11boe_timing: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <140>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <20>; + hsync-len = <20>; + vsync-len = <2>; //value range <2~22> + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; +}; + +&backlight { + pwms = <&pwm9 0 25000 0>; + status = "okay"; +}; + +&csi2_dphy0 { + status = "disabled"; +}; + +&dsi { + status = "disabled"; +}; + +/* + * The pins of gmac0/pcie2x1/pdm_codec and rgb are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&pcie2x1 { + status = "disabled"; +}; + +&pdm_codec { + status = "disabled"; +}; + +&pwm9 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + pinctrl-0 = <&rgb666_pins>; + + ports { + port@1 { + reg = <1>; + + rgb_out_panel: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&rgb_in_vp1 { + status = "disabled"; +}; + +&route_rgb { + status = "okay"; + connect = <&vp0_out_rgb>; +}; + +/* + * The pins of sai0/vcc_mipicsi0 and rgb are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&vcc_mipicsi0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; From 8b2a7f91459ef6d6ed4974c0d19a0f5173193807 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Tue, 10 May 2022 17:09:14 +0800 Subject: [PATCH 157/258] phy: rockchip-typec: add support to tcpm framework add support to tcpm framework and remove extcon. Change-Id: I6ea7aa21b65a50eca2d85f8959d8d317184204e2 Signed-off-by: Zhang Yubing --- drivers/phy/rockchip/phy-rockchip-typec.c | 194 +++++++++++++--------- 1 file changed, 120 insertions(+), 74 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 4d1604de9db7..9ae89e34864f 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include @@ -411,10 +412,16 @@ struct phy_config { int pe; }; +enum { + TYPEC_PHY_USB, + TYPEC_PHY_DP, + TYPEC_PHY_MAX, +}; + struct rockchip_typec_phy { struct device *dev; void __iomem *base; - struct extcon_dev *extcon; + struct typec_mux *mux; struct typec_switch *sw; struct regmap *grf_regs; struct clk *clk_core; @@ -422,12 +429,14 @@ struct rockchip_typec_phy { struct reset_control *uphy_rst; struct reset_control *pipe_rst; struct reset_control *tcphy_rst; + struct phy *phys[TYPEC_PHY_MAX]; const struct rockchip_usb3phy_port_cfg *port_cfgs; /* mutex to protect access to individual PHYs */ struct mutex lock; bool flip; u8 mode; + u8 new_mode; struct phy_config config[3][4]; }; @@ -1335,50 +1344,7 @@ static void tcphy_phy_deinit(struct rockchip_typec_phy *tcphy) static int tcphy_get_mode(struct rockchip_typec_phy *tcphy) { - struct extcon_dev *edev = tcphy->extcon; - union extcon_property_value property; - unsigned int id; - bool ufp, dp; - u8 mode; - int ret; - - if (!edev) - return MODE_DFP_USB; - - ufp = extcon_get_state(edev, EXTCON_USB); - dp = extcon_get_state(edev, EXTCON_DISP_DP); - - mode = MODE_DFP_USB; - id = EXTCON_USB_HOST; - - if (ufp) { - mode = MODE_UFP_USB; - id = EXTCON_USB; - } else if (dp) { - mode = MODE_DFP_DP; - id = EXTCON_DISP_DP; - - ret = extcon_get_property(edev, id, EXTCON_PROP_USB_SS, - &property); - if (ret) { - dev_err(tcphy->dev, "get superspeed property failed\n"); - return ret; - } - - if (property.intval) - mode |= MODE_DFP_USB; - } - - ret = extcon_get_property(edev, id, EXTCON_PROP_USB_TYPEC_POLARITY, - &property); - if (ret) { - dev_err(tcphy->dev, "get polarity property failed\n"); - return ret; - } - - tcphy->flip = property.intval ? 1 : 0; - - return mode; + return tcphy->new_mode; } static int tcphy_orien_sw_set(struct typec_switch *sw, @@ -1388,10 +1354,13 @@ static int tcphy_orien_sw_set(struct typec_switch *sw, mutex_lock(&tcphy->lock); - if (orien == TYPEC_ORIENTATION_NONE) + if (orien == TYPEC_ORIENTATION_NONE) { + tcphy->new_mode = MODE_DISCONNECT; goto unlock_ret; + } tcphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false; + tcphy->new_mode = MODE_DFP_USB; unlock_ret: mutex_unlock(&tcphy->lock); @@ -1615,6 +1584,68 @@ static const struct phy_ops rockchip_dp_phy_ops = { .owner = THIS_MODULE, }; +static int tcphy_typec_mux_set(struct typec_mux *mux, struct typec_mux_state *state) +{ + struct rockchip_typec_phy *tcphy = typec_mux_get_drvdata(mux); + struct typec_displayport_data *data; + int hpd = 0; + + mutex_lock(&tcphy->lock); + + switch (state->mode) { + case TYPEC_STATE_SAFE: + fallthrough; + case TYPEC_STATE_USB: + tcphy->new_mode = MODE_DFP_USB; + phy_set_bus_width(tcphy->phys[TYPEC_PHY_DP], 0); + break; + case TYPEC_DP_STATE_C: + case TYPEC_DP_STATE_E: + tcphy->new_mode = MODE_DFP_DP; + data = state->data; + hpd = !!(data->status & DP_STATUS_HPD_STATE); + phy_set_bus_width(tcphy->phys[TYPEC_PHY_DP], hpd ? 4 : 0); + break; + case TYPEC_DP_STATE_D: + tcphy->new_mode = MODE_DFP_DP | MODE_DFP_USB; + data = state->data; + hpd = !!(data->status & DP_STATUS_HPD_STATE); + phy_set_bus_width(tcphy->phys[TYPEC_PHY_DP], hpd ? 2 : 0); + break; + default: + break; + } + + mutex_unlock(&tcphy->lock); + + return 0; +} + +static int tcphy_setup_typec_mux(struct rockchip_typec_phy *tcphy) +{ + struct typec_mux_desc mux_desc = {}; + + mux_desc.drvdata = tcphy; + mux_desc.fwnode = dev_fwnode(tcphy->dev); + mux_desc.set = tcphy_typec_mux_set; + + tcphy->mux = typec_mux_register(tcphy->dev, &mux_desc); + if (IS_ERR(tcphy->mux)) { + dev_err(tcphy->dev, "Error register typec mux: %ld\n", + PTR_ERR(tcphy->mux)); + return PTR_ERR(tcphy->mux); + } + + return 0; +} + +static void tcphy_typec_mux_unregister(void *data) +{ + struct rockchip_typec_phy *tcphy = data; + + typec_mux_unregister(tcphy->mux); +} + static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy, struct device *dev) { @@ -1740,24 +1771,24 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev) typec_phy_pre_init(tcphy); - tcphy->extcon = extcon_get_edev_by_phandle(dev, 0); - if (IS_ERR(tcphy->extcon)) { - if (PTR_ERR(tcphy->extcon) == -ENODEV) { - tcphy->extcon = NULL; - if (device_property_present(dev, "orientation-switch")) { - ret = tcphy_setup_orien_switch(tcphy); - if (ret) - return ret; - ret = devm_add_action_or_reset(dev, udphy_orien_switch_unregister, - tcphy); - if (ret) - return ret; - } - } else { - if (PTR_ERR(tcphy->extcon) != -EPROBE_DEFER) - dev_err(dev, "Invalid or missing extcon\n"); - return PTR_ERR(tcphy->extcon); - } + if (device_property_present(dev, "orientation-switch")) { + ret = tcphy_setup_orien_switch(tcphy); + if (ret) + return ret; + ret = devm_add_action_or_reset(dev, udphy_orien_switch_unregister, + tcphy); + if (ret) + return ret; + } + + if (device_property_present(dev, "svid")) { + ret = tcphy_setup_typec_mux(tcphy); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, tcphy_typec_mux_unregister, tcphy); + if (ret) + return ret; } pm_runtime_enable(dev); @@ -1765,20 +1796,31 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(np, child_np) { struct phy *phy; - if (of_node_name_eq(child_np, "dp-port")) + if (!of_node_cmp(child_np->name, "dp-port")) { phy = devm_phy_create(dev, child_np, &rockchip_dp_phy_ops); - else if (of_node_name_eq(child_np, "usb3-port")) + if (IS_ERR(phy)) { + dev_err(dev, "failed to create phy: %s\n", + child_np->name); + of_node_put(child_np); + ret = PTR_ERR(phy); + goto error; + } + tcphy->phys[TYPEC_PHY_DP] = phy; + } else if (!of_node_cmp(child_np->name, "usb3-port")) { phy = devm_phy_create(dev, child_np, &rockchip_usb3_phy_ops); - else + if (IS_ERR(phy)) { + dev_err(dev, "failed to create phy: %s\n", + child_np->name); + of_node_put(child_np); + ret = PTR_ERR(phy); + goto error; + } + tcphy->phys[TYPEC_PHY_USB] = phy; + } else { continue; - if (IS_ERR(phy)) { - dev_err(dev, "failed to create phy: %pOFn\n", - child_np); - pm_runtime_disable(dev); - return PTR_ERR(phy); } phy_set_drvdata(phy, tcphy); @@ -1787,11 +1829,15 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (IS_ERR(phy_provider)) { dev_err(dev, "Failed to register phy provider\n"); - pm_runtime_disable(dev); - return PTR_ERR(phy_provider); + ret = PTR_ERR(phy_provider); + goto error; } return 0; + +error: + pm_runtime_disable(dev); + return ret; } static int rockchip_typec_phy_remove(struct platform_device *pdev) From b942725058dfb165a766f1a0e19c67cf32b2aea1 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 14 Feb 2023 11:27:38 +0800 Subject: [PATCH 158/258] arm64: dts: rockchip: rk3562-evb: fix mcu display board naming errors Fix board model and compatible and remove bl-gpios in mcu_panel node. Signed-off-by: Damon Ding Change-Id: I80b696e4df0cd409023b9656c5a13ba850d15340 --- .../dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts index 93c225312cdb..2d9763c48ca4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts @@ -10,8 +10,8 @@ #include "rk3562-rk817.dtsi" / { - model = "Rockchip RK3562 EVB2 DDR4 V10 Board + RK EVB MCU PANLE DISPLAY Ext Board"; - compatible = "rockchip,rk3562-evb2-ddr4-v10-mcu-k350c4516t", "rockchip,rk3562"; + model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB MCU PANLE DISPLAY Ext Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10-mcu-k350c4516t", "rockchip,rk3562"; }; &backlight { @@ -58,7 +58,6 @@ */ bus-format = ; backlight = <&backlight>; - bl-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; enable-delay-ms = <20>; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; From 002ff3ed953f20ac2e638bb476a020cbc3bf405c Mon Sep 17 00:00:00 2001 From: Wangqiang Guo Date: Mon, 30 Jan 2023 11:23:03 +0000 Subject: [PATCH 159/258] arm64: dts: rockchip: rk3562-evb2: add camera dtsi. Add dts for gc8034 on rk3562 evb2 board. Change-Id: I3d190106b40b21f27f9c9f474a882238bcf0cb87 Signed-off-by: Wangqiang Guo Signed-off-by: Jianwei Fan --- .../boot/dts/rockchip/rk3562-evb2-cam.dtsi | 325 ++++++++++++++++++ .../dts/rockchip/rk3562-evb2-ddr4-v10.dts | 1 + 2 files changed, 326 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-cam.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-cam.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-cam.dtsi new file mode 100644 index 000000000000..3b254024ff11 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-cam.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out1>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + // dvdd-supply = <&vcc_mipicsi0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&dw9714>; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + dw9714_1: dw9714_1@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + }; + + gc8034_1: gc8034_1@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + // dvdd-supply = <&vcc_mipicsi1>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&dw9714_1>; + port { + gc8034_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + isp_vir1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera1 power en */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts index 8d26ce9c67c6..2288139495b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts @@ -7,3 +7,4 @@ #include "rk3562-evb2-ddr4-v10.dtsi" #include "rk3562-android.dtsi" #include "rk3562-rk809.dtsi" +#include "rk3562-evb2-cam.dtsi" From a2e98940eee76535d4a0dc585013e06fb151ffc5 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Mon, 13 Feb 2023 16:33:31 +0800 Subject: [PATCH 160/258] Revert "drm/rockchip: gem: add dmabuf sync partial to dma_buf_ops" This reverts commit 64097b127c6c4853026fd839036e613097bccb6f. Change-Id: I18917edcda996538b09da55d999dcb76544fdafb Signed-off-by: Jianqun Xu --- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 22 ------ drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 75 --------------------- drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 9 --- 3 files changed, 106 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 92967fd48363..212191aa8cd2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -1666,26 +1666,6 @@ static int rockchip_drm_gem_dmabuf_end_cpu_access(struct dma_buf *dma_buf, return rockchip_gem_prime_end_cpu_access(obj, dir); } -static int rockchip_drm_gem_begin_cpu_access_partial( - struct dma_buf *dma_buf, - enum dma_data_direction dir, - unsigned int offset, unsigned int len) -{ - struct drm_gem_object *obj = dma_buf->priv; - - return rockchip_gem_prime_begin_cpu_access_partial(obj, dir, offset, len); -} - -static int rockchip_drm_gem_end_cpu_access_partial( - struct dma_buf *dma_buf, - enum dma_data_direction dir, - unsigned int offset, unsigned int len) -{ - struct drm_gem_object *obj = dma_buf->priv; - - return rockchip_gem_prime_end_cpu_access_partial(obj, dir, offset, len); -} - static const struct dma_buf_ops rockchip_drm_gem_prime_dmabuf_ops = { .cache_sgt_mapping = true, .attach = drm_gem_map_attach, @@ -1699,8 +1679,6 @@ static const struct dma_buf_ops rockchip_drm_gem_prime_dmabuf_ops = { .get_uuid = drm_gem_dmabuf_get_uuid, .begin_cpu_access = rockchip_drm_gem_dmabuf_begin_cpu_access, .end_cpu_access = rockchip_drm_gem_dmabuf_end_cpu_access, - .begin_cpu_access_partial = rockchip_drm_gem_begin_cpu_access_partial, - .end_cpu_access_partial = rockchip_drm_gem_end_cpu_access_partial, }; static struct drm_gem_object *rockchip_drm_gem_prime_import_dev(struct drm_device *dev, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index df985456b598..48893f5cff42 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -992,78 +992,3 @@ int rockchip_gem_prime_end_cpu_access(struct drm_gem_object *obj, rk_obj->sgt->nents, dir); return 0; } - -static int rockchip_gem_prime_sgl_sync_range(struct device *dev, - struct scatterlist *sgl, unsigned int nents, - unsigned int offset, unsigned int length, - enum dma_data_direction dir, bool for_cpu) -{ - int i; - struct scatterlist *sg; - unsigned int len = 0; - dma_addr_t sg_dma_addr; - - for_each_sg(sgl, sg, nents, i) { - unsigned int sg_offset, sg_left, size = 0; - - len += sg->length; - if (len <= offset) - continue; - - sg_dma_addr = sg_phys(sg); - sg_left = len - offset; - sg_offset = sg->length - sg_left; - - size = (length < sg_left) ? length : sg_left; - if (for_cpu) - dma_sync_single_range_for_cpu(dev, sg_dma_addr, - sg_offset, size, dir); - else - dma_sync_single_range_for_device(dev, sg_dma_addr, - sg_offset, size, dir); - - offset += size; - length -= size; - - if (length == 0) - break; - } - - return 0; -} - -int rockchip_gem_prime_begin_cpu_access_partial(struct drm_gem_object *obj, - enum dma_data_direction dir, - unsigned int offset, - unsigned int len) -{ - struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj); - struct drm_device *drm = obj->dev; - - if (!rk_obj->sgt) - return 0; - - rockchip_gem_prime_sgl_sync_range(drm->dev, rk_obj->sgt->sgl, - rk_obj->sgt->nents, - offset, len, dir, true); - - return 0; -} - -int rockchip_gem_prime_end_cpu_access_partial(struct drm_gem_object *obj, - enum dma_data_direction dir, - unsigned int offset, - unsigned int len) -{ - struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj); - struct drm_device *drm = obj->dev; - - if (!rk_obj->sgt) - return 0; - - rockchip_gem_prime_sgl_sync_range(drm->dev, rk_obj->sgt->sgl, - rk_obj->sgt->nents, - offset, len, dir, false); - - return 0; -} diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h index 6a1d8e55b35a..34bcb76b20e3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h @@ -81,14 +81,5 @@ int rockchip_gem_prime_begin_cpu_access(struct drm_gem_object *obj, int rockchip_gem_prime_end_cpu_access(struct drm_gem_object *obj, enum dma_data_direction dir); -int rockchip_gem_prime_begin_cpu_access_partial(struct drm_gem_object *obj, - enum dma_data_direction dir, - unsigned int offset, - unsigned int len); - -int rockchip_gem_prime_end_cpu_access_partial(struct drm_gem_object *obj, - enum dma_data_direction dir, - unsigned int offset, - unsigned int len); void rockchip_gem_get_ddr_info(void); #endif /* _ROCKCHIP_DRM_GEM_H */ From ce99bb8b5b5d6c0df50595ca9db1897f9447fa4c Mon Sep 17 00:00:00 2001 From: Wang Panzhenzhuan Date: Tue, 2 Aug 2022 06:52:02 +0000 Subject: [PATCH 161/258] arm64: dts: rockchip: rk3568-evb1: add dual camera add dtsi & dts for gc2093+gc2053 dual camera module Signed-off-by: Wang Panzhenzhuan Change-Id: I4e0111db8ade20ead54188a2eed5b91dff350cb4 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rk3568-evb1-ddr4-v10-dual-camera.dts | 9 + .../dts/rockchip/rk3568-evb1-dual-camera.dtsi | 247 ++++++++++++++++++ 3 files changed, 257 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-dual-camera.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-evb1-dual-camera.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index a1c5a04a8507..26cf69d030fd 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -112,6 +112,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-camera.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-spi-nor.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-dual-camera.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-dual-camera.dts new file mode 100644 index 000000000000..c4106a353e49 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-dual-camera.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" +#include "rk3568-evb1-dual-camera.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-dual-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb1-dual-camera.dtsi new file mode 100644 index 000000000000..334651d67576 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-dual-camera.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dphy_hw { + status = "okay"; +}; + +/* + * csi2_dphy1 & csi2_dphy2 used for split mode, + * csi2_dphy0 used for full mode, + * full mode and split mode are mutually exclusive + */ +&csi2_dphy0 { + status = "disabled"; + /delete-node/ ports; +}; + +&csi2_dphy1 { + status = "okay"; + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_gc2093_rgb: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc2093_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_gc2053_ir: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2053_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp_in1>; + }; + }; + }; +}; + +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy1_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + /delete-node/ gc8034@37; + /delete-node/ os04a10@36; + /delete-node/ ov5695@36; + + gc2053: gc2053@37 { + status = "okay"; + compatible = "galaxycore,gc2053"; + reg = <0x37>; + clocks = <&pmucru CLK_WIFI>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&refclk_pins>; + reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "DW-RV2093-V1.0"; + rockchip,camera-module-lens-name = "JZ-7070AS-A3"; + port { + gc2053_out: endpoint { + remote-endpoint = <&mipi_in_gc2053_ir>; + data-lanes = <1 2>; + }; + }; + }; + + gc2093: gc2093@7e { + status = "okay"; + compatible = "galaxycore,gc2093"; + reg = <0x7e>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "DW-RV2093-V1.0"; + rockchip,camera-module-lens-name = "JZ-7070AS-A1"; + port { + gc2093_out: endpoint { + remote-endpoint = <&mipi_in_gc2093_rgb>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_in2>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + + +&rkisp { + status = "okay"; + max-input = <3840 2160 30>; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + /* gc2053-ir->dphy2->isp_vir0 */ + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy2_out>; + }; + }; +}; + +&rkisp_vir1 { + status = "okay"; + /* gc2093-rgb->dphy1->csi2->vicap */ + /* vicap sditf->isp_vir1 */ + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_in2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; From 3080b1c4e8b996f06e99268767533573743a0048 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Wed, 15 Feb 2023 09:39:24 +0800 Subject: [PATCH 162/258] Revert "media: rockchip: isp: extend pixel to 32 for isp30 unite mode" This reverts commit b3260da5e915c88874a2efc7460c2166efdd5fe9. Signed-off-by: Cai YiWei Change-Id: I3c322a0d187fcfcf38daac2dbd0f4ada6fd89fe4 --- include/uapi/linux/rk-camera-module.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/rk-camera-module.h b/include/uapi/linux/rk-camera-module.h index 008b2355efe7..489f50b7947c 100644 --- a/include/uapi/linux/rk-camera-module.h +++ b/include/uapi/linux/rk-camera-module.h @@ -13,7 +13,7 @@ #define RKMODULE_API_VERSION KERNEL_VERSION(0, 1, 0x2) /* using for rk3588 dual isp unite */ -#define RKMOUDLE_UNITE_EXTEND_PIXEL 32 +#define RKMOUDLE_UNITE_EXTEND_PIXEL 128 /* using for rv1109 and rv1126 */ #define RKMODULE_EXTEND_LINE 24 From c544fe878d28105bcd952def1d056850d6a83d2e Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 15 Feb 2023 14:35:41 +0800 Subject: [PATCH 163/258] PCI: rockchip: dw: Fix warning in initial progress 1.missing unwind goto 2.Value stored to 'ret' is never read Fixes: fa919e9611b4 ("pcie: rockchip: dw: Support dmatest") Change-Id: I20ae68b97a6512cbb340668b1ffb7811dc6ef674 Signed-off-by: Jon Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 25a33e8252b4..696ce42b70a6 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -1319,8 +1319,8 @@ static int rk_pcie_phy_init(struct rk_pcie *rk_pcie) } if (rk_pcie->bifurcation) - ret = phy_set_mode_ext(rk_pcie->phy, rk_pcie->phy_mode, - PHY_MODE_PCIE_BIFURCATION); + phy_set_mode_ext(rk_pcie->phy, rk_pcie->phy_mode, + PHY_MODE_PCIE_BIFURCATION); ret = phy_init(rk_pcie->phy); if (ret < 0) { @@ -2111,7 +2111,7 @@ retry_regulator: ret = rk_pcie_init_dma_trx(rk_pcie); if (ret) { dev_err(dev, "failed to add dma extension\n"); - return ret; + goto remove_irq_domain; } if (rk_pcie->dma_obj) { From 97811627ff0b4de80909a82cab562e16cbaf9d74 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Wed, 15 Feb 2023 11:31:04 +0800 Subject: [PATCH 164/258] phy: rockchip-samsung-hdptx-hdmi: Reduce ROPLL loop bandwidth 24M clock noise is carried into the PHY ROPLL loop filter. Due to the low noise frequency, it can pass through the low-pass loop filter of ROPLL, resulting in hdmi flash. Reduce ROPLL loop bandwidth can solve this problem. Signed-off-by: Algea Cao Change-Id: Ibea774bc26ea8c2b06cf79c84b6cd6456df66ea5 --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c index aeb6bcf02102..c5095ff4f077 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c @@ -1269,9 +1269,9 @@ static int hdptx_ropll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsigned lon hdptx_write(hdptx, CMN_REG0043, 0x00); hdptx_write(hdptx, CMN_REG0044, 0x46); hdptx_write(hdptx, CMN_REG0045, 0x24); - hdptx_write(hdptx, CMN_REG0046, 0xff); + hdptx_write(hdptx, CMN_REG0046, 0xdd); hdptx_write(hdptx, CMN_REG0047, 0x00); - hdptx_write(hdptx, CMN_REG0048, 0x44); + hdptx_write(hdptx, CMN_REG0048, 0x11); hdptx_write(hdptx, CMN_REG0049, 0xfa); hdptx_write(hdptx, CMN_REG004A, 0x08); hdptx_write(hdptx, CMN_REG004B, 0x00); From c52799a13ca26138a96b36196daa94f75b68824e Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 15 Feb 2023 09:10:46 +0800 Subject: [PATCH 165/258] clk: rockchip: pvtm: Fix rockchip_clock_pvtm_get_value() timeout Signed-off-by: Tao Huang Change-Id: I04e02ab210c682eca7c78e3f9229498c41568adf --- drivers/clk/rockchip/clk-pvtm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-pvtm.c b/drivers/clk/rockchip/clk-pvtm.c index ad02b6a571d8..c748589dd922 100644 --- a/drivers/clk/rockchip/clk-pvtm.c +++ b/drivers/clk/rockchip/clk-pvtm.c @@ -106,11 +106,12 @@ static u32 rockchip_clock_pvtm_get_value(struct rockchip_clock_pvtm *pvtm, rockchip_clock_pvtm_delay(time_us); check_cnt = 100; - while (check_cnt--) { + while (check_cnt) { regmap_read(pvtm->grf, info->sta, &sta); if (sta & 0x1) break; udelay(4); + check_cnt--; } if (check_cnt) { From 28c7e478176292e2c18b9a0f5ff6cf1658084174 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Wed, 15 Feb 2023 14:52:50 +0800 Subject: [PATCH 166/258] phy: rockchip: inno-hdmi: Fix 'warn: missing unwind goto' Signed-off-by: Algea Cao Change-Id: I7044cc4e7268c9899f43eb927f29084e2e2f34b2 --- drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c index 451f088ed620..37c002ba2d6a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c @@ -1541,13 +1541,15 @@ static int inno_hdmi_phy_probe(struct platform_device *pdev) if (of_get_property(np, "rockchip,phy-table", &val)) { if (val % PHY_TAB_LEN || !val) { dev_err(dev, "Invalid phy cfg table format!\n"); - return -EINVAL; + ret = -EINVAL; + goto err_regsmap; } phy_config = kmalloc(val, GFP_KERNEL); if (!phy_config) { dev_err(dev, "kmalloc phy table failed\n"); - return -ENOMEM; + ret = -ENOMEM; + goto err_regsmap; } phy_table_size = val / PHY_TAB_LEN; @@ -1556,7 +1558,8 @@ static int inno_hdmi_phy_probe(struct platform_device *pdev) GFP_KERNEL); if (!inno->phy_cfg) { kfree(phy_config); - return -ENOMEM; + ret = -ENOMEM; + goto err_regsmap; } of_property_read_u32_array(np, "rockchip,phy-table", phy_config, val / sizeof(u32)); @@ -1565,7 +1568,7 @@ static int inno_hdmi_phy_probe(struct platform_device *pdev) phy_table_size); if (ret) { kfree(phy_config); - return ret; + goto err_regsmap; } kfree(phy_config); } else { From 5f8124c0aecbf967ba3c9730963426b63cca7da6 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Wed, 15 Feb 2023 15:12:41 +0800 Subject: [PATCH 167/258] media: rockchip: isp: fix build warn Change-Id: I1bf4a66df7f39275a3b670a2ff6dd457f69e6634 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/capture_v32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/rockchip/isp/capture_v32.c b/drivers/media/platform/rockchip/isp/capture_v32.c index 347ef4c1bb9a..c43f50973838 100644 --- a/drivers/media/platform/rockchip/isp/capture_v32.c +++ b/drivers/media/platform/rockchip/isp/capture_v32.c @@ -1193,7 +1193,7 @@ static void luma_frame_readout(unsigned long arg) if (val & ISP32_YNR_LUMA_RDBK_RDY) break; } - if (!timeout) { + if (timeout < 0) { v4l2_err(&dev->v4l2_dev, "%s no ready\n", __func__); return; } From 8cb1b2ad5069119df238f8d17a77b3bb3b4e47db Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 15 Feb 2023 16:30:35 +0800 Subject: [PATCH 168/258] rk: scripts: update mkbootimg/unpack_bootimg AOSP f85a2fd5640d ("Revert "unpack_bootimg: Export 'vendor_ramdisk' for vendor_boot v4"") Revert 7261bb083a97 ("Check DTB image size for boot image header version 2 and above") which failed to repack image without dtb. Include gki.generate_gki_certificate. Signed-off-by: Tao Huang Change-Id: Ibf9543fd4a10547f9d956b6ffc09834389fbb20f --- scripts/mkbootimg | 639 ++++++++++++++++++++++++++++++++--------- scripts/unpack_bootimg | 577 ++++++++++++++++++++++++++++--------- 2 files changed, 954 insertions(+), 262 deletions(-) diff --git a/scripts/mkbootimg b/scripts/mkbootimg index 0c6093e19416..610548fd6b58 100755 --- a/scripts/mkbootimg +++ b/scripts/mkbootimg @@ -1,4 +1,5 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 +# # Copyright 2015, The Android Open Source Project # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -13,16 +14,81 @@ # See the License for the specific language governing permissions and # limitations under the License. -from __future__ import print_function +"""Creates the boot image.""" -from argparse import ArgumentParser, FileType, Action +from argparse import (ArgumentParser, ArgumentTypeError, + FileType, RawDescriptionHelpFormatter) from hashlib import sha1 from os import fstat -import re from struct import pack +import array +import collections +import os +import re +import tempfile +# from gki.generate_gki_certificate import generate_gki_certificate +def generate_gki_certificate(image, avbtool, name, algorithm, key, salt, + additional_avb_args, output): + """Shell out to avbtool to generate a GKI certificate.""" + + # Need to specify a value of --partition_size for avbtool to work. + # We use 64 MB below, but avbtool will not resize the boot image to + # this size because --do_not_append_vbmeta_image is also specified. + avbtool_cmd = [ + avbtool, 'add_hash_footer', + '--partition_name', name, + '--partition_size', str(64 * 1024 * 1024), + '--image', image, + '--algorithm', algorithm, + '--key', key, + '--do_not_append_vbmeta_image', + '--output_vbmeta_image', output, + ] + + if salt is not None: + avbtool_cmd += ['--salt', salt] + + avbtool_cmd += additional_avb_args + + subprocess.check_call(avbtool_cmd) + + +# Constant and structure definition is in +# system/tools/mkbootimg/include/bootimg/bootimg.h +BOOT_MAGIC = 'ANDROID!' +BOOT_MAGIC_SIZE = 8 +BOOT_NAME_SIZE = 16 +BOOT_ARGS_SIZE = 512 +BOOT_EXTRA_ARGS_SIZE = 1024 +BOOT_IMAGE_HEADER_V1_SIZE = 1648 +BOOT_IMAGE_HEADER_V2_SIZE = 1660 +BOOT_IMAGE_HEADER_V3_SIZE = 1580 BOOT_IMAGE_HEADER_V3_PAGESIZE = 4096 +BOOT_IMAGE_HEADER_V4_SIZE = 1584 +BOOT_IMAGE_V4_SIGNATURE_SIZE = 4096 + +VENDOR_BOOT_MAGIC = 'VNDRBOOT' +VENDOR_BOOT_MAGIC_SIZE = 8 +VENDOR_BOOT_NAME_SIZE = BOOT_NAME_SIZE +VENDOR_BOOT_ARGS_SIZE = 2048 +VENDOR_BOOT_IMAGE_HEADER_V3_SIZE = 2112 +VENDOR_BOOT_IMAGE_HEADER_V4_SIZE = 2128 + +VENDOR_RAMDISK_TYPE_NONE = 0 +VENDOR_RAMDISK_TYPE_PLATFORM = 1 +VENDOR_RAMDISK_TYPE_RECOVERY = 2 +VENDOR_RAMDISK_TYPE_DLKM = 3 +VENDOR_RAMDISK_NAME_SIZE = 32 +VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE = 16 +VENDOR_RAMDISK_TABLE_ENTRY_V4_SIZE = 108 + +# Names with special meaning, mustn't be specified in --ramdisk_name. +VENDOR_RAMDISK_NAME_BLOCKLIST = {b'default'} + +PARSER_ARGUMENT_VENDOR_RAMDISK_FRAGMENT = '--vendor_ramdisk_fragment' + def filesize(f): if f is None: @@ -49,87 +115,141 @@ def pad_file(f, padding): def get_number_of_pages(image_size, page_size): """calculates the number of pages required for the image""" - return (image_size + page_size - 1) / page_size + return (image_size + page_size - 1) // page_size def get_recovery_dtbo_offset(args): """calculates the offset of recovery_dtbo image in the boot image""" num_header_pages = 1 # header occupies a page num_kernel_pages = get_number_of_pages(filesize(args.kernel), args.pagesize) - num_ramdisk_pages = get_number_of_pages(filesize(args.ramdisk), args.pagesize) + num_ramdisk_pages = get_number_of_pages(filesize(args.ramdisk), + args.pagesize) num_second_pages = get_number_of_pages(filesize(args.second), args.pagesize) dtbo_offset = args.pagesize * (num_header_pages + num_kernel_pages + num_ramdisk_pages + num_second_pages) return dtbo_offset -def write_header_v3(args): - BOOT_IMAGE_HEADER_V3_SIZE = 1580 - BOOT_MAGIC = 'ANDROID!'.encode() +def should_add_legacy_gki_boot_signature(args): + if args.gki_signing_key and args.gki_signing_algorithm: + return True + return False - args.output.write(pack('8s', BOOT_MAGIC)) - args.output.write(pack( - '4I', - filesize(args.kernel), # kernel size in bytes - filesize(args.ramdisk), # ramdisk size in bytes - (args.os_version << 11) | args.os_patch_level, # os version and patch level - BOOT_IMAGE_HEADER_V3_SIZE)) - args.output.write(pack('4I', 0, 0, 0, 0)) # reserved +def write_header_v3_and_above(args): + if args.header_version > 3: + boot_header_size = BOOT_IMAGE_HEADER_V4_SIZE + else: + boot_header_size = BOOT_IMAGE_HEADER_V3_SIZE - args.output.write(pack('I', args.header_version)) # version of bootimage header - args.output.write(pack('1536s', args.cmdline.encode())) + args.output.write(pack(f'{BOOT_MAGIC_SIZE}s', BOOT_MAGIC.encode())) + # kernel size in bytes + args.output.write(pack('I', filesize(args.kernel))) + # ramdisk size in bytes + args.output.write(pack('I', filesize(args.ramdisk))) + # os version and patch level + args.output.write(pack('I', (args.os_version << 11) | args.os_patch_level)) + args.output.write(pack('I', boot_header_size)) + # reserved + args.output.write(pack('4I', 0, 0, 0, 0)) + # version of boot image header + args.output.write(pack('I', args.header_version)) + args.output.write(pack(f'{BOOT_ARGS_SIZE + BOOT_EXTRA_ARGS_SIZE}s', + args.cmdline)) + if args.header_version >= 4: + # The signature used to verify boot image v4. + boot_signature_size = 0 + if should_add_legacy_gki_boot_signature(args): + boot_signature_size = BOOT_IMAGE_V4_SIGNATURE_SIZE + args.output.write(pack('I', boot_signature_size)) pad_file(args.output, BOOT_IMAGE_HEADER_V3_PAGESIZE) + def write_vendor_boot_header(args): - VENDOR_BOOT_IMAGE_HEADER_V3_SIZE = 2112 - BOOT_MAGIC = 'VNDRBOOT'.encode() + if args.header_version > 3: + vendor_ramdisk_size = args.vendor_ramdisk_total_size + vendor_boot_header_size = VENDOR_BOOT_IMAGE_HEADER_V4_SIZE + else: + vendor_ramdisk_size = filesize(args.vendor_ramdisk) + vendor_boot_header_size = VENDOR_BOOT_IMAGE_HEADER_V3_SIZE - args.vendor_boot.write(pack('8s', BOOT_MAGIC)) - args.vendor_boot.write(pack( - '5I', - args.header_version, # version of header - args.pagesize, # flash page size we assume - args.base + args.kernel_offset, # kernel physical load addr - args.base + args.ramdisk_offset, # ramdisk physical load addr - filesize(args.vendor_ramdisk))) # vendor ramdisk size in bytes - args.vendor_boot.write(pack('2048s', args.vendor_cmdline.encode())) - args.vendor_boot.write(pack('I', args.base + args.tags_offset)) # physical addr for kernel tags - args.vendor_boot.write(pack('16s', args.board.encode())) # asciiz product name - args.vendor_boot.write(pack('I', VENDOR_BOOT_IMAGE_HEADER_V3_SIZE)) # header size in bytes - if filesize(args.dtb) == 0: - raise ValueError("DTB image must not be empty.") - args.vendor_boot.write(pack('I', filesize(args.dtb))) # size in bytes - args.vendor_boot.write(pack('Q', args.base + args.dtb_offset)) # dtb physical load address - pad_file(args.vendor_boot, args.pagesize) + args.vendor_boot.write(pack(f'{VENDOR_BOOT_MAGIC_SIZE}s', + VENDOR_BOOT_MAGIC.encode())) + # version of boot image header + args.vendor_boot.write(pack('I', args.header_version)) + # flash page size + args.vendor_boot.write(pack('I', args.pagesize)) + # kernel physical load address + args.vendor_boot.write(pack('I', args.base + args.kernel_offset)) + # ramdisk physical load address + args.vendor_boot.write(pack('I', args.base + args.ramdisk_offset)) + # ramdisk size in bytes + args.vendor_boot.write(pack('I', vendor_ramdisk_size)) + args.vendor_boot.write(pack(f'{VENDOR_BOOT_ARGS_SIZE}s', + args.vendor_cmdline)) + # kernel tags physical load address + args.vendor_boot.write(pack('I', args.base + args.tags_offset)) + # asciiz product name + args.vendor_boot.write(pack(f'{VENDOR_BOOT_NAME_SIZE}s', args.board)) -def write_header(args): - BOOT_IMAGE_HEADER_V1_SIZE = 1648 - BOOT_IMAGE_HEADER_V2_SIZE = 1660 - BOOT_MAGIC = 'ANDROID!'.encode() + # header size in bytes + args.vendor_boot.write(pack('I', vendor_boot_header_size)) + + # dtb size in bytes + args.vendor_boot.write(pack('I', filesize(args.dtb))) + # dtb physical load address + args.vendor_boot.write(pack('Q', args.base + args.dtb_offset)) if args.header_version > 3: - raise ValueError('Boot header version %d not supported' % args.header_version) - elif args.header_version == 3: - return write_header_v3(args) + vendor_ramdisk_table_size = (args.vendor_ramdisk_table_entry_num * + VENDOR_RAMDISK_TABLE_ENTRY_V4_SIZE) + # vendor ramdisk table size in bytes + args.vendor_boot.write(pack('I', vendor_ramdisk_table_size)) + # number of vendor ramdisk table entries + args.vendor_boot.write(pack('I', args.vendor_ramdisk_table_entry_num)) + # vendor ramdisk table entry size in bytes + args.vendor_boot.write(pack('I', VENDOR_RAMDISK_TABLE_ENTRY_V4_SIZE)) + # bootconfig section size in bytes + args.vendor_boot.write(pack('I', filesize(args.vendor_bootconfig))) + pad_file(args.vendor_boot, args.pagesize) - args.output.write(pack('8s', BOOT_MAGIC)) - final_ramdisk_offset = (args.base + args.ramdisk_offset) if filesize(args.ramdisk) > 0 else 0 - final_second_offset = (args.base + args.second_offset) if filesize(args.second) > 0 else 0 - args.output.write(pack( - '10I', - filesize(args.kernel), # size in bytes - args.base + args.kernel_offset, # physical load addr - filesize(args.ramdisk), # size in bytes - final_ramdisk_offset, # physical load addr - filesize(args.second), # size in bytes - final_second_offset, # physical load addr - args.base + args.tags_offset, # physical addr for kernel tags - args.pagesize, # flash page size we assume - args.header_version, # version of bootimage header - (args.os_version << 11) | args.os_patch_level)) # os version and patch level - args.output.write(pack('16s', args.board.encode())) # asciiz product name - args.output.write(pack('512s', args.cmdline[:512].encode())) + +def write_header(args): + if args.header_version > 4: + raise ValueError( + f'Boot header version {args.header_version} not supported') + if args.header_version in {3, 4}: + return write_header_v3_and_above(args) + + ramdisk_load_address = ((args.base + args.ramdisk_offset) + if filesize(args.ramdisk) > 0 else 0) + second_load_address = ((args.base + args.second_offset) + if filesize(args.second) > 0 else 0) + + args.output.write(pack(f'{BOOT_MAGIC_SIZE}s', BOOT_MAGIC.encode())) + # kernel size in bytes + args.output.write(pack('I', filesize(args.kernel))) + # kernel physical load address + args.output.write(pack('I', args.base + args.kernel_offset)) + # ramdisk size in bytes + args.output.write(pack('I', filesize(args.ramdisk))) + # ramdisk physical load address + args.output.write(pack('I', ramdisk_load_address)) + # second bootloader size in bytes + args.output.write(pack('I', filesize(args.second))) + # second bootloader physical load address + args.output.write(pack('I', second_load_address)) + # kernel tags physical load address + args.output.write(pack('I', args.base + args.tags_offset)) + # flash page size + args.output.write(pack('I', args.pagesize)) + # version of boot image header + args.output.write(pack('I', args.header_version)) + # os version and patch level + args.output.write(pack('I', (args.os_version << 11) | args.os_patch_level)) + # asciiz product name + args.output.write(pack(f'{BOOT_NAME_SIZE}s', args.board)) + args.output.write(pack(f'{BOOT_ARGS_SIZE}s', args.cmdline)) sha = sha1() update_sha(sha, args.kernel) @@ -144,14 +264,18 @@ def write_header(args): img_id = pack('32s', sha.digest()) args.output.write(img_id) - args.output.write(pack('1024s', args.cmdline[512:].encode())) + args.output.write(pack(f'{BOOT_EXTRA_ARGS_SIZE}s', args.extra_cmdline)) if args.header_version > 0: - args.output.write(pack('I', filesize(args.recovery_dtbo))) # size in bytes if args.recovery_dtbo: - args.output.write(pack('Q', get_recovery_dtbo_offset(args))) # recovery dtbo offset + # recovery dtbo size in bytes + args.output.write(pack('I', filesize(args.recovery_dtbo))) + # recovert dtbo offset in the boot image + args.output.write(pack('Q', get_recovery_dtbo_offset(args))) else: - args.output.write(pack('Q', 0)) # Will be set to 0 for devices without a recovery dtbo + # Set to zero if no recovery dtbo + args.output.write(pack('I', 0)) + args.output.write(pack('Q', 0)) # Populate boot image header size for header versions 1 and 2. if args.header_version == 1: @@ -160,29 +284,101 @@ def write_header(args): args.output.write(pack('I', BOOT_IMAGE_HEADER_V2_SIZE)) if args.header_version > 1: - # if filesize(args.dtb) == 0: - # raise ValueError("DTB image must not be empty.") + # raise ValueError('DTB image must not be empty.') + + # dtb size in bytes + args.output.write(pack('I', filesize(args.dtb))) + # dtb physical load address + args.output.write(pack('Q', args.base + args.dtb_offset)) - args.output.write(pack('I', filesize(args.dtb))) # size in bytes - args.output.write(pack('Q', args.base + args.dtb_offset)) # dtb physical load address pad_file(args.output, args.pagesize) return img_id -class ValidateStrLenAction(Action): - def __init__(self, option_strings, dest, nargs=None, **kwargs): - if 'maxlen' not in kwargs: - raise ValueError('maxlen must be set') - self.maxlen = int(kwargs['maxlen']) - del kwargs['maxlen'] - super(ValidateStrLenAction, self).__init__(option_strings, dest, **kwargs) +class AsciizBytes: + """Parses a string and encodes it as an asciiz bytes object. - def __call__(self, parser, namespace, values, option_string=None): - if len(values) > self.maxlen: + >>> AsciizBytes(bufsize=4)('foo') + b'foo\\x00' + >>> AsciizBytes(bufsize=4)('foob') + Traceback (most recent call last): + ... + argparse.ArgumentTypeError: Encoded asciiz length exceeded: max 4, got 5 + """ + + def __init__(self, bufsize): + self.bufsize = bufsize + + def __call__(self, arg): + arg_bytes = arg.encode() + b'\x00' + if len(arg_bytes) > self.bufsize: + raise ArgumentTypeError( + 'Encoded asciiz length exceeded: ' + f'max {self.bufsize}, got {len(arg_bytes)}') + return arg_bytes + + +class VendorRamdiskTableBuilder: + """Vendor ramdisk table builder. + + Attributes: + entries: A list of VendorRamdiskTableEntry namedtuple. + ramdisk_total_size: Total size in bytes of all ramdisks in the table. + """ + + VendorRamdiskTableEntry = collections.namedtuple( # pylint: disable=invalid-name + 'VendorRamdiskTableEntry', + ['ramdisk_path', 'ramdisk_size', 'ramdisk_offset', 'ramdisk_type', + 'ramdisk_name', 'board_id']) + + def __init__(self): + self.entries = [] + self.ramdisk_total_size = 0 + self.ramdisk_names = set() + + def add_entry(self, ramdisk_path, ramdisk_type, ramdisk_name, board_id): + # Strip any trailing null for simple comparison. + stripped_ramdisk_name = ramdisk_name.rstrip(b'\x00') + if stripped_ramdisk_name in VENDOR_RAMDISK_NAME_BLOCKLIST: raise ValueError( - 'String argument too long: max {0:d}, got {1:d}'.format(self.maxlen, len(values))) - setattr(namespace, self.dest, values) + f'Banned vendor ramdisk name: {stripped_ramdisk_name}') + if stripped_ramdisk_name in self.ramdisk_names: + raise ValueError( + f'Duplicated vendor ramdisk name: {stripped_ramdisk_name}') + self.ramdisk_names.add(stripped_ramdisk_name) + + if board_id is None: + board_id = array.array( + 'I', [0] * VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE) + else: + board_id = array.array('I', board_id) + if len(board_id) != VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE: + raise ValueError('board_id size must be ' + f'{VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE}') + + with open(ramdisk_path, 'rb') as f: + ramdisk_size = filesize(f) + self.entries.append(self.VendorRamdiskTableEntry( + ramdisk_path, ramdisk_size, self.ramdisk_total_size, ramdisk_type, + ramdisk_name, board_id)) + self.ramdisk_total_size += ramdisk_size + + def write_ramdisks_padded(self, fout, alignment): + for entry in self.entries: + with open(entry.ramdisk_path, 'rb') as f: + fout.write(f.read()) + pad_file(fout, alignment) + + def write_entries_padded(self, fout, alignment): + for entry in self.entries: + fout.write(pack('I', entry.ramdisk_size)) + fout.write(pack('I', entry.ramdisk_offset)) + fout.write(pack('I', entry.ramdisk_type)) + fout.write(pack(f'{VENDOR_RAMDISK_NAME_SIZE}s', + entry.ramdisk_name)) + fout.write(entry.board_id) + pad_file(fout, alignment) def write_padded_file(f_out, f_in, padding): @@ -225,49 +421,221 @@ def parse_os_patch_level(x): return 0 +def parse_vendor_ramdisk_type(x): + type_dict = { + 'none': VENDOR_RAMDISK_TYPE_NONE, + 'platform': VENDOR_RAMDISK_TYPE_PLATFORM, + 'recovery': VENDOR_RAMDISK_TYPE_RECOVERY, + 'dlkm': VENDOR_RAMDISK_TYPE_DLKM, + } + if x.lower() in type_dict: + return type_dict[x.lower()] + return parse_int(x) + + +def get_vendor_boot_v4_usage(): + return """vendor boot version 4 arguments: + --ramdisk_type {none,platform,recovery,dlkm} + specify the type of the ramdisk + --ramdisk_name NAME + specify the name of the ramdisk + --board_id{0..15} NUMBER + specify the value of the board_id vector, defaults to 0 + --vendor_ramdisk_fragment VENDOR_RAMDISK_FILE + path to the vendor ramdisk file + + These options can be specified multiple times, where each vendor ramdisk + option group ends with a --vendor_ramdisk_fragment option. + Each option group appends an additional ramdisk to the vendor boot image. +""" + + +def parse_vendor_ramdisk_args(args, args_list): + """Parses vendor ramdisk specific arguments. + + Args: + args: An argparse.Namespace object. Parsed results are stored into this + object. + args_list: A list of argument strings to be parsed. + + Returns: + A list argument strings that are not parsed by this method. + """ + parser = ArgumentParser(add_help=False) + parser.add_argument('--ramdisk_type', type=parse_vendor_ramdisk_type, + default=VENDOR_RAMDISK_TYPE_NONE) + parser.add_argument('--ramdisk_name', + type=AsciizBytes(bufsize=VENDOR_RAMDISK_NAME_SIZE), + required=True) + for i in range(VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE): + parser.add_argument(f'--board_id{i}', type=parse_int, default=0) + parser.add_argument(PARSER_ARGUMENT_VENDOR_RAMDISK_FRAGMENT, required=True) + + unknown_args = [] + + vendor_ramdisk_table_builder = VendorRamdiskTableBuilder() + if args.vendor_ramdisk is not None: + vendor_ramdisk_table_builder.add_entry( + args.vendor_ramdisk.name, VENDOR_RAMDISK_TYPE_PLATFORM, b'', None) + + while PARSER_ARGUMENT_VENDOR_RAMDISK_FRAGMENT in args_list: + idx = args_list.index(PARSER_ARGUMENT_VENDOR_RAMDISK_FRAGMENT) + 2 + vendor_ramdisk_args = args_list[:idx] + args_list = args_list[idx:] + + ramdisk_args, extra_args = parser.parse_known_args(vendor_ramdisk_args) + ramdisk_args_dict = vars(ramdisk_args) + unknown_args.extend(extra_args) + + ramdisk_path = ramdisk_args.vendor_ramdisk_fragment + ramdisk_type = ramdisk_args.ramdisk_type + ramdisk_name = ramdisk_args.ramdisk_name + board_id = [ramdisk_args_dict[f'board_id{i}'] + for i in range(VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE)] + vendor_ramdisk_table_builder.add_entry(ramdisk_path, ramdisk_type, + ramdisk_name, board_id) + + if len(args_list) > 0: + unknown_args.extend(args_list) + + args.vendor_ramdisk_total_size = (vendor_ramdisk_table_builder + .ramdisk_total_size) + args.vendor_ramdisk_table_entry_num = len(vendor_ramdisk_table_builder + .entries) + args.vendor_ramdisk_table_builder = vendor_ramdisk_table_builder + return unknown_args + + def parse_cmdline(): - parser = ArgumentParser() - parser.add_argument('--kernel', help='path to the kernel', type=FileType('rb')) - parser.add_argument('--ramdisk', help='path to the ramdisk', type=FileType('rb')) - parser.add_argument('--second', help='path to the 2nd bootloader', type=FileType('rb')) - parser.add_argument('--dtb', help='path to dtb', type=FileType('rb')) - recovery_dtbo_group = parser.add_mutually_exclusive_group() - recovery_dtbo_group.add_argument('--recovery_dtbo', help='path to the recovery DTBO', - type=FileType('rb')) - recovery_dtbo_group.add_argument('--recovery_acpio', help='path to the recovery ACPIO', - type=FileType('rb'), metavar='RECOVERY_ACPIO', - dest='recovery_dtbo') - parser.add_argument('--cmdline', help='extra arguments to be passed on the ' - 'kernel command line', default='', action=ValidateStrLenAction, maxlen=1536) + version_parser = ArgumentParser(add_help=False) + version_parser.add_argument('--header_version', type=parse_int, default=0) + if version_parser.parse_known_args()[0].header_version < 3: + # For boot header v0 to v2, the kernel commandline field is split into + # two fields, cmdline and extra_cmdline. Both fields are asciiz strings, + # so we minus one here to ensure the encoded string plus the + # null-terminator can fit in the buffer size. + cmdline_size = BOOT_ARGS_SIZE + BOOT_EXTRA_ARGS_SIZE - 1 + else: + cmdline_size = BOOT_ARGS_SIZE + BOOT_EXTRA_ARGS_SIZE + + parser = ArgumentParser(formatter_class=RawDescriptionHelpFormatter, + epilog=get_vendor_boot_v4_usage()) + parser.add_argument('--kernel', type=FileType('rb'), + help='path to the kernel') + parser.add_argument('--ramdisk', type=FileType('rb'), + help='path to the ramdisk') + parser.add_argument('--second', type=FileType('rb'), + help='path to the second bootloader') + parser.add_argument('--dtb', type=FileType('rb'), help='path to the dtb') + dtbo_group = parser.add_mutually_exclusive_group() + dtbo_group.add_argument('--recovery_dtbo', type=FileType('rb'), + help='path to the recovery DTBO') + dtbo_group.add_argument('--recovery_acpio', type=FileType('rb'), + metavar='RECOVERY_ACPIO', dest='recovery_dtbo', + help='path to the recovery ACPIO') + parser.add_argument('--cmdline', type=AsciizBytes(bufsize=cmdline_size), + default='', help='kernel command line arguments') parser.add_argument('--vendor_cmdline', - help='kernel command line arguments contained in vendor boot', - default='', action=ValidateStrLenAction, maxlen=2048) - parser.add_argument('--base', help='base address', type=parse_int, default=0x10000000) - parser.add_argument('--kernel_offset', help='kernel offset', type=parse_int, default=0x00008000) - parser.add_argument('--ramdisk_offset', help='ramdisk offset', type=parse_int, - default=0x01000000) - parser.add_argument('--second_offset', help='2nd bootloader offset', type=parse_int, - default=0x00f00000) - parser.add_argument('--dtb_offset', help='dtb offset', type=parse_int, default=0x01f00000) + type=AsciizBytes(bufsize=VENDOR_BOOT_ARGS_SIZE), + default='', + help='vendor boot kernel command line arguments') + parser.add_argument('--base', type=parse_int, default=0x10000000, + help='base address') + parser.add_argument('--kernel_offset', type=parse_int, default=0x00008000, + help='kernel offset') + parser.add_argument('--ramdisk_offset', type=parse_int, default=0x01000000, + help='ramdisk offset') + parser.add_argument('--second_offset', type=parse_int, default=0x00f00000, + help='second bootloader offset') + parser.add_argument('--dtb_offset', type=parse_int, default=0x01f00000, + help='dtb offset') - parser.add_argument('--os_version', help='operating system version', type=parse_os_version, - default=0) - parser.add_argument('--os_patch_level', help='operating system patch level', - type=parse_os_patch_level, default=0) - parser.add_argument('--tags_offset', help='tags offset', type=parse_int, default=0x00000100) - parser.add_argument('--board', help='board name', default='', action=ValidateStrLenAction, - maxlen=16) - parser.add_argument('--pagesize', help='page size', type=parse_int, - choices=[2**i for i in range(11, 15)], default=2048) - parser.add_argument('--id', help='print the image ID on standard output', - action='store_true') - parser.add_argument('--header_version', help='boot image header version', type=parse_int, - default=0) - parser.add_argument('-o', '--output', help='output file name', type=FileType('wb')) - parser.add_argument('--vendor_boot', help='vendor boot output file name', type=FileType('wb')) - parser.add_argument('--vendor_ramdisk', help='path to the vendor ramdisk', type=FileType('rb')) + parser.add_argument('--os_version', type=parse_os_version, default=0, + help='operating system version') + parser.add_argument('--os_patch_level', type=parse_os_patch_level, + default=0, help='operating system patch level') + parser.add_argument('--tags_offset', type=parse_int, default=0x00000100, + help='tags offset') + parser.add_argument('--board', type=AsciizBytes(bufsize=BOOT_NAME_SIZE), + default='', help='board name') + parser.add_argument('--pagesize', type=parse_int, + choices=[2**i for i in range(11, 15)], default=2048, + help='page size') + parser.add_argument('--id', action='store_true', + help='print the image ID on standard output') + parser.add_argument('--header_version', type=parse_int, default=0, + help='boot image header version') + parser.add_argument('-o', '--output', type=FileType('wb'), + help='output file name') + parser.add_argument('--vendor_boot', type=FileType('wb'), + help='vendor boot output file name') + parser.add_argument('--vendor_ramdisk', type=FileType('rb'), + help='path to the vendor ramdisk') + parser.add_argument('--vendor_bootconfig', type=FileType('rb'), + help='path to the vendor bootconfig file') - return parser.parse_args() + gki_2_0_signing_args = parser.add_argument_group( + '[DEPRECATED] GKI 2.0 signing arguments') + gki_2_0_signing_args.add_argument( + '--gki_signing_algorithm', help='GKI signing algorithm to use') + gki_2_0_signing_args.add_argument( + '--gki_signing_key', help='path to RSA private key file') + gki_2_0_signing_args.add_argument( + '--gki_signing_signature_args', default='', + help='other hash arguments passed to avbtool') + gki_2_0_signing_args.add_argument( + '--gki_signing_avbtool_path', default='avbtool', + help='path to avbtool for boot signature generation') + + args, extra_args = parser.parse_known_args() + if args.vendor_boot is not None and args.header_version > 3: + extra_args = parse_vendor_ramdisk_args(args, extra_args) + if len(extra_args) > 0: + raise ValueError(f'Unrecognized arguments: {extra_args}') + + if args.header_version < 3: + args.extra_cmdline = args.cmdline[BOOT_ARGS_SIZE-1:] + args.cmdline = args.cmdline[:BOOT_ARGS_SIZE-1] + b'\x00' + assert len(args.cmdline) <= BOOT_ARGS_SIZE + assert len(args.extra_cmdline) <= BOOT_EXTRA_ARGS_SIZE + + return args + + +def add_boot_image_signature(args, pagesize): + """Adds the boot image signature. + + Note that the signature will only be verified in VTS to ensure a + generic boot.img is used. It will not be used by the device + bootloader at boot time. The bootloader should only verify + the boot vbmeta at the end of the boot partition (or in the top-level + vbmeta partition) via the Android Verified Boot process, when the + device boots. + """ + # Flush the buffer for signature calculation. + args.output.flush() + + # Outputs the signed vbmeta to a separate file, then append to boot.img + # as the boot signature. + with tempfile.TemporaryDirectory() as temp_out_dir: + boot_signature_output = os.path.join(temp_out_dir, 'boot_signature') + generate_gki_certificate( + image=args.output.name, avbtool=args.gki_signing_avbtool_path, + name='boot', algorithm=args.gki_signing_algorithm, + key=args.gki_signing_key, salt='d00df00d', + additional_avb_args=args.gki_signing_signature_args.split(), + output=boot_signature_output, + ) + with open(boot_signature_output, 'rb') as boot_signature: + boot_signature_bytes = boot_signature.read() + if len(boot_signature_bytes) > BOOT_IMAGE_V4_SIGNATURE_SIZE: + raise ValueError( + f'boot sigature size is > {BOOT_IMAGE_V4_SIGNATURE_SIZE}') + boot_signature_bytes += b'\x00' * ( + BOOT_IMAGE_V4_SIGNATURE_SIZE - len(boot_signature_bytes)) + assert len(boot_signature_bytes) == BOOT_IMAGE_V4_SIGNATURE_SIZE + args.output.write(boot_signature_bytes) + pad_file(args.output, pagesize) def write_data(args, pagesize): @@ -279,37 +647,44 @@ def write_data(args, pagesize): write_padded_file(args.output, args.recovery_dtbo, pagesize) if args.header_version == 2: write_padded_file(args.output, args.dtb, pagesize) + if args.header_version >= 4 and should_add_legacy_gki_boot_signature(args): + add_boot_image_signature(args, pagesize) def write_vendor_boot_data(args): - write_padded_file(args.vendor_boot, args.vendor_ramdisk, args.pagesize) - write_padded_file(args.vendor_boot, args.dtb, args.pagesize) + if args.header_version > 3: + builder = args.vendor_ramdisk_table_builder + builder.write_ramdisks_padded(args.vendor_boot, args.pagesize) + write_padded_file(args.vendor_boot, args.dtb, args.pagesize) + builder.write_entries_padded(args.vendor_boot, args.pagesize) + write_padded_file(args.vendor_boot, args.vendor_bootconfig, + args.pagesize) + else: + write_padded_file(args.vendor_boot, args.vendor_ramdisk, args.pagesize) + write_padded_file(args.vendor_boot, args.dtb, args.pagesize) def main(): args = parse_cmdline() if args.vendor_boot is not None: - if args.header_version < 3: - raise ValueError('--vendor_boot not compatible with given header version') - if args.vendor_ramdisk is None: + if args.header_version not in {3, 4}: + raise ValueError( + '--vendor_boot not compatible with given header version') + if args.header_version == 3 and args.vendor_ramdisk is None: raise ValueError('--vendor_ramdisk missing or invalid') write_vendor_boot_header(args) write_vendor_boot_data(args) if args.output is not None: - if args.kernel is None: - raise ValueError('kernel must be supplied when creating a boot image') if args.second is not None and args.header_version > 2: - raise ValueError('--second not compatible with given header version') + raise ValueError( + '--second not compatible with given header version') img_id = write_header(args) if args.header_version > 2: write_data(args, BOOT_IMAGE_HEADER_V3_PAGESIZE) else: write_data(args, args.pagesize) if args.id and img_id is not None: - # Python 2's struct.pack returns a string, but py3 returns bytes. - if isinstance(img_id, str): - img_id = [ord(x) for x in img_id] - print('0x' + ''.join('{:02x}'.format(c) for c in img_id)) + print('0x' + ''.join(f'{octet:02x}' for octet in img_id)) if __name__ == '__main__': diff --git a/scripts/unpack_bootimg b/scripts/unpack_bootimg index 83c2bbe33d7d..a3f1a508796b 100755 --- a/scripts/unpack_bootimg +++ b/scripts/unpack_bootimg @@ -1,4 +1,5 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 +# # Copyright 2018, The Android Open Source Project # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -13,18 +14,20 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""unpacks the bootimage. +"""Unpacks the boot image. Extracts the kernel, ramdisk, second bootloader, dtb and recovery dtbo images. """ -from __future__ import print_function -from argparse import ArgumentParser, FileType +from argparse import ArgumentParser, RawDescriptionHelpFormatter from struct import unpack import os +import shlex BOOT_IMAGE_HEADER_V3_PAGESIZE = 4096 -VENDOR_BOOT_IMAGE_HEADER_V3_SIZE = 2112 +VENDOR_RAMDISK_NAME_SIZE = 32 +VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE = 16 + def create_out_dir(dir_path): """creates a directory 'dir_path' if it does not exist""" @@ -50,196 +53,510 @@ def cstr(s): def format_os_version(os_version): + if os_version == 0: + return None a = os_version >> 14 b = os_version >> 7 & ((1<<7) - 1) c = os_version & ((1<<7) - 1) - return '{}.{}.{}'.format(a, b, c) + return f'{a}.{b}.{c}' def format_os_patch_level(os_patch_level): + if os_patch_level == 0: + return None y = os_patch_level >> 4 y += 2000 m = os_patch_level & ((1<<4) - 1) - return '{:04d}-{:02d}'.format(y, m) + return f'{y:04d}-{m:02d}' -def print_os_version_patch_level(value): - os_version = value >> 11 - os_patch_level = value & ((1<<11) - 1) - print('os version: %s' % format_os_version(os_version)) - print('os patch level: %s' % format_os_patch_level(os_patch_level)) +def decode_os_version_patch_level(os_version_patch_level): + """Returns a tuple of (os_version, os_patch_level).""" + os_version = os_version_patch_level >> 11 + os_patch_level = os_version_patch_level & ((1<<11) - 1) + return (format_os_version(os_version), + format_os_patch_level(os_patch_level)) -def unpack_bootimage(args): +class BootImageInfoFormatter: + """Formats the boot image info.""" + + def format_pretty_text(self): + lines = [] + lines.append(f'boot magic: {self.boot_magic}') + + if self.header_version < 3: + lines.append(f'kernel_size: {self.kernel_size}') + lines.append( + f'kernel load address: {self.kernel_load_address:#010x}') + lines.append(f'ramdisk size: {self.ramdisk_size}') + lines.append( + f'ramdisk load address: {self.ramdisk_load_address:#010x}') + lines.append(f'second bootloader size: {self.second_size}') + lines.append( + f'second bootloader load address: ' + f'{self.second_load_address:#010x}') + lines.append( + f'kernel tags load address: {self.tags_load_address:#010x}') + lines.append(f'page size: {self.page_size}') + else: + lines.append(f'kernel_size: {self.kernel_size}') + lines.append(f'ramdisk size: {self.ramdisk_size}') + + lines.append(f'os version: {self.os_version}') + lines.append(f'os patch level: {self.os_patch_level}') + lines.append(f'boot image header version: {self.header_version}') + + if self.header_version < 3: + lines.append(f'product name: {self.product_name}') + + lines.append(f'command line args: {self.cmdline}') + + if self.header_version < 3: + lines.append(f'additional command line args: {self.extra_cmdline}') + + if self.header_version in {1, 2}: + lines.append(f'recovery dtbo size: {self.recovery_dtbo_size}') + lines.append( + f'recovery dtbo offset: {self.recovery_dtbo_offset:#018x}') + lines.append(f'boot header size: {self.boot_header_size}') + + if self.header_version == 2: + lines.append(f'dtb size: {self.dtb_size}') + lines.append(f'dtb address: {self.dtb_load_address:#018x}') + + if self.header_version >= 4: + lines.append( + f'boot.img signature size: {self.boot_signature_size}') + + return '\n'.join(lines) + + def format_mkbootimg_argument(self): + args = [] + args.extend(['--header_version', str(self.header_version)]) + if self.os_version: + args.extend(['--os_version', self.os_version]) + if self.os_patch_level: + args.extend(['--os_patch_level', self.os_patch_level]) + + args.extend(['--kernel', os.path.join(self.image_dir, 'kernel')]) + args.extend(['--ramdisk', os.path.join(self.image_dir, 'ramdisk')]) + + if self.header_version <= 2: + if self.second_size > 0: + args.extend(['--second', + os.path.join(self.image_dir, 'second')]) + if self.recovery_dtbo_size > 0: + args.extend(['--recovery_dtbo', + os.path.join(self.image_dir, 'recovery_dtbo')]) + if self.dtb_size > 0: + args.extend(['--dtb', os.path.join(self.image_dir, 'dtb')]) + + args.extend(['--pagesize', f'{self.page_size:#010x}']) + + # Kernel load address is base + kernel_offset in mkbootimg.py. + # However we don't know the value of 'base' when unpacking a boot + # image in this script, so we set 'base' to zero and 'kernel_offset' + # to the kernel load address, 'ramdisk_offset' to the ramdisk load + # address, ... etc. + args.extend(['--base', f'{0:#010x}']) + args.extend(['--kernel_offset', + f'{self.kernel_load_address:#010x}']) + args.extend(['--ramdisk_offset', + f'{self.ramdisk_load_address:#010x}']) + args.extend(['--second_offset', + f'{self.second_load_address:#010x}']) + args.extend(['--tags_offset', f'{self.tags_load_address:#010x}']) + + # dtb is added in boot image v2, and is absent in v1 or v0. + if self.header_version == 2: + # dtb_offset is uint64_t. + args.extend(['--dtb_offset', f'{self.dtb_load_address:#018x}']) + + args.extend(['--board', self.product_name]) + args.extend(['--cmdline', self.cmdline + self.extra_cmdline]) + else: + args.extend(['--cmdline', self.cmdline]) + + return args + + +def unpack_boot_image(boot_img, output_dir): """extracts kernel, ramdisk, second bootloader and recovery dtbo""" - kernel_ramdisk_second_info = unpack('9I', args.boot_img.read(9 * 4)) - version = kernel_ramdisk_second_info[8] - if version < 3: - print('kernel_size: %s' % kernel_ramdisk_second_info[0]) - print('kernel load address: %#x' % kernel_ramdisk_second_info[1]) - print('ramdisk size: %s' % kernel_ramdisk_second_info[2]) - print('ramdisk load address: %#x' % kernel_ramdisk_second_info[3]) - print('second bootloader size: %s' % kernel_ramdisk_second_info[4]) - print('second bootloader load address: %#x' % kernel_ramdisk_second_info[5]) - print('kernel tags load address: %#x' % kernel_ramdisk_second_info[6]) - print('page size: %s' % kernel_ramdisk_second_info[7]) - print_os_version_patch_level(unpack('I', args.boot_img.read(1 * 4))[0]) + info = BootImageInfoFormatter() + info.boot_magic = unpack('8s', boot_img.read(8))[0].decode() + + kernel_ramdisk_second_info = unpack('9I', boot_img.read(9 * 4)) + # header_version is always at [8] regardless of the value of header_version. + info.header_version = kernel_ramdisk_second_info[8] + + if info.header_version < 3: + info.kernel_size = kernel_ramdisk_second_info[0] + info.kernel_load_address = kernel_ramdisk_second_info[1] + info.ramdisk_size = kernel_ramdisk_second_info[2] + info.ramdisk_load_address = kernel_ramdisk_second_info[3] + info.second_size = kernel_ramdisk_second_info[4] + info.second_load_address = kernel_ramdisk_second_info[5] + info.tags_load_address = kernel_ramdisk_second_info[6] + info.page_size = kernel_ramdisk_second_info[7] + os_version_patch_level = unpack('I', boot_img.read(1 * 4))[0] else: - print('kernel_size: %s' % kernel_ramdisk_second_info[0]) - print('ramdisk size: %s' % kernel_ramdisk_second_info[1]) - print_os_version_patch_level(kernel_ramdisk_second_info[2]) + info.kernel_size = kernel_ramdisk_second_info[0] + info.ramdisk_size = kernel_ramdisk_second_info[1] + os_version_patch_level = kernel_ramdisk_second_info[2] + info.second_size = 0 + info.page_size = BOOT_IMAGE_HEADER_V3_PAGESIZE - print('boot image header version: %s' % version) + info.os_version, info.os_patch_level = decode_os_version_patch_level( + os_version_patch_level) - if version < 3: - product_name = cstr(unpack('16s', args.boot_img.read(16))[0].decode()) - print('product name: %s' % product_name) - cmdline = cstr(unpack('512s', args.boot_img.read(512))[0].decode()) - print('command line args: %s' % cmdline) + if info.header_version < 3: + info.product_name = cstr(unpack('16s', + boot_img.read(16))[0].decode()) + info.cmdline = cstr(unpack('512s', boot_img.read(512))[0].decode()) + boot_img.read(32) # ignore SHA + info.extra_cmdline = cstr(unpack('1024s', + boot_img.read(1024))[0].decode()) else: - cmdline = cstr(unpack('1536s', args.boot_img.read(1536))[0].decode()) - print('command line args: %s' % cmdline) + info.cmdline = cstr(unpack('1536s', + boot_img.read(1536))[0].decode()) - if version < 3: - args.boot_img.read(32) # ignore SHA - - if version < 3: - extra_cmdline = cstr(unpack('1024s', - args.boot_img.read(1024))[0].decode()) - print('additional command line args: %s' % extra_cmdline) - - if version < 3: - kernel_size = kernel_ramdisk_second_info[0] - ramdisk_size = kernel_ramdisk_second_info[2] - second_size = kernel_ramdisk_second_info[4] - page_size = kernel_ramdisk_second_info[7] + if info.header_version in {1, 2}: + info.recovery_dtbo_size = unpack('I', boot_img.read(1 * 4))[0] + info.recovery_dtbo_offset = unpack('Q', boot_img.read(8))[0] + info.boot_header_size = unpack('I', boot_img.read(4))[0] else: - kernel_size = kernel_ramdisk_second_info[0] - ramdisk_size = kernel_ramdisk_second_info[1] - second_size = 0 - page_size = BOOT_IMAGE_HEADER_V3_PAGESIZE + info.recovery_dtbo_size = 0 - if 0 < version < 3: - recovery_dtbo_size = unpack('I', args.boot_img.read(1 * 4))[0] - print('recovery dtbo size: %s' % recovery_dtbo_size) - recovery_dtbo_offset = unpack('Q', args.boot_img.read(8))[0] - print('recovery dtbo offset: %#x' % recovery_dtbo_offset) - boot_header_size = unpack('I', args.boot_img.read(4))[0] - print('boot header size: %s' % boot_header_size) + if info.header_version == 2: + info.dtb_size = unpack('I', boot_img.read(4))[0] + info.dtb_load_address = unpack('Q', boot_img.read(8))[0] else: - recovery_dtbo_size = 0 - if 1 < version < 3: - dtb_size = unpack('I', args.boot_img.read(4))[0] - print('dtb size: %s' % dtb_size) - dtb_load_address = unpack('Q', args.boot_img.read(8))[0] - print('dtb address: %#x' % dtb_load_address) - else: - dtb_size = 0 + info.dtb_size = 0 + info.dtb_load_address = 0 + if info.header_version >= 4: + info.boot_signature_size = unpack('I', boot_img.read(4))[0] + else: + info.boot_signature_size = 0 # The first page contains the boot header num_header_pages = 1 - num_kernel_pages = get_number_of_pages(kernel_size, page_size) - kernel_offset = page_size * num_header_pages # header occupies a page - image_info_list = [(kernel_offset, kernel_size, 'kernel')] + # Convenient shorthand. + page_size = info.page_size - num_ramdisk_pages = get_number_of_pages(ramdisk_size, page_size) + num_kernel_pages = get_number_of_pages(info.kernel_size, page_size) + kernel_offset = page_size * num_header_pages # header occupies a page + image_info_list = [(kernel_offset, info.kernel_size, 'kernel')] + + num_ramdisk_pages = get_number_of_pages(info.ramdisk_size, page_size) ramdisk_offset = page_size * (num_header_pages + num_kernel_pages ) # header + kernel - image_info_list.append((ramdisk_offset, ramdisk_size, 'ramdisk')) + image_info_list.append((ramdisk_offset, info.ramdisk_size, 'ramdisk')) - if second_size > 0: + if info.second_size > 0: second_offset = page_size * ( num_header_pages + num_kernel_pages + num_ramdisk_pages ) # header + kernel + ramdisk - image_info_list.append((second_offset, second_size, 'second')) + image_info_list.append((second_offset, info.second_size, 'second')) - if recovery_dtbo_size > 0: - image_info_list.append((recovery_dtbo_offset, recovery_dtbo_size, + if info.recovery_dtbo_size > 0: + image_info_list.append((info.recovery_dtbo_offset, + info.recovery_dtbo_size, 'recovery_dtbo')) - if dtb_size > 0: - num_second_pages = get_number_of_pages(second_size, page_size) - num_recovery_dtbo_pages = get_number_of_pages(recovery_dtbo_size, page_size) + if info.dtb_size > 0: + num_second_pages = get_number_of_pages(info.second_size, page_size) + num_recovery_dtbo_pages = get_number_of_pages( + info.recovery_dtbo_size, page_size) dtb_offset = page_size * ( - num_header_pages + num_kernel_pages + num_ramdisk_pages + num_second_pages + - num_recovery_dtbo_pages - ) + num_header_pages + num_kernel_pages + num_ramdisk_pages + + num_second_pages + num_recovery_dtbo_pages) - image_info_list.append((dtb_offset, dtb_size, 'dtb')) + image_info_list.append((dtb_offset, info.dtb_size, 'dtb')) - for image_info in image_info_list: - extract_image(image_info[0], image_info[1], args.boot_img, - os.path.join(args.out, image_info[2])) + if info.boot_signature_size > 0: + # boot signature only exists in boot.img version >= v4. + # There are only kernel and ramdisk pages before the signature. + boot_signature_offset = page_size * ( + num_header_pages + num_kernel_pages + num_ramdisk_pages) + + image_info_list.append((boot_signature_offset, info.boot_signature_size, + 'boot_signature')) + + create_out_dir(output_dir) + for offset, size, name in image_info_list: + extract_image(offset, size, boot_img, os.path.join(output_dir, name)) + info.image_dir = output_dir + + return info -def unpack_vendor_bootimage(args): - kernel_ramdisk_info = unpack('5I', args.boot_img.read(5 * 4)) - print('vendor boot image header version: %s' % kernel_ramdisk_info[0]) - print('kernel load address: %#x' % kernel_ramdisk_info[2]) - print('ramdisk load address: %#x' % kernel_ramdisk_info[3]) - print('vendor ramdisk size: %s' % kernel_ramdisk_info[4]) +class VendorBootImageInfoFormatter: + """Formats the vendor_boot image info.""" - cmdline = cstr(unpack('2048s', args.boot_img.read(2048))[0].decode()) - print('vendor command line args: %s' % cmdline) + def format_pretty_text(self): + lines = [] + lines.append(f'boot magic: {self.boot_magic}') + lines.append(f'vendor boot image header version: {self.header_version}') + lines.append(f'page size: {self.page_size:#010x}') + lines.append(f'kernel load address: {self.kernel_load_address:#010x}') + lines.append(f'ramdisk load address: {self.ramdisk_load_address:#010x}') + if self.header_version > 3: + lines.append( + f'vendor ramdisk total size: {self.vendor_ramdisk_size}') + else: + lines.append(f'vendor ramdisk size: {self.vendor_ramdisk_size}') + lines.append(f'vendor command line args: {self.cmdline}') + lines.append( + f'kernel tags load address: {self.tags_load_address:#010x}') + lines.append(f'product name: {self.product_name}') + lines.append(f'vendor boot image header size: {self.header_size}') + lines.append(f'dtb size: {self.dtb_size}') + lines.append(f'dtb address: {self.dtb_load_address:#018x}') + if self.header_version > 3: + lines.append( + f'vendor ramdisk table size: {self.vendor_ramdisk_table_size}') + lines.append('vendor ramdisk table: [') + indent = lambda level: ' ' * 4 * level + for entry in self.vendor_ramdisk_table: + (output_ramdisk_name, ramdisk_size, ramdisk_offset, + ramdisk_type, ramdisk_name, board_id) = entry + lines.append(indent(1) + f'{output_ramdisk_name}: ''{') + lines.append(indent(2) + f'size: {ramdisk_size}') + lines.append(indent(2) + f'offset: {ramdisk_offset}') + lines.append(indent(2) + f'type: {ramdisk_type:#x}') + lines.append(indent(2) + f'name: {ramdisk_name}') + lines.append(indent(2) + 'board_id: [') + stride = 4 + for row_idx in range(0, len(board_id), stride): + row = board_id[row_idx:row_idx + stride] + lines.append( + indent(3) + ' '.join(f'{e:#010x},' for e in row)) + lines.append(indent(2) + ']') + lines.append(indent(1) + '}') + lines.append(']') + lines.append( + f'vendor bootconfig size: {self.vendor_bootconfig_size}') - tags_load_address = unpack('I', args.boot_img.read(1 * 4))[0] - print('kernel tags load address: %#x' % tags_load_address) + return '\n'.join(lines) - product_name = cstr(unpack('16s', args.boot_img.read(16))[0].decode()) - print('product name: %s' % product_name) + def format_mkbootimg_argument(self): + args = [] + args.extend(['--header_version', str(self.header_version)]) + args.extend(['--pagesize', f'{self.page_size:#010x}']) + args.extend(['--base', f'{0:#010x}']) + args.extend(['--kernel_offset', f'{self.kernel_load_address:#010x}']) + args.extend(['--ramdisk_offset', f'{self.ramdisk_load_address:#010x}']) + args.extend(['--tags_offset', f'{self.tags_load_address:#010x}']) + args.extend(['--dtb_offset', f'{self.dtb_load_address:#018x}']) + args.extend(['--vendor_cmdline', self.cmdline]) + args.extend(['--board', self.product_name]) - dtb_size = unpack('2I', args.boot_img.read(2 * 4))[1] - print('dtb size: %s' % dtb_size) - dtb_load_address = unpack('Q', args.boot_img.read(8))[0] - print('dtb address: %#x' % dtb_load_address) + if self.dtb_size > 0: + args.extend(['--dtb', os.path.join(self.image_dir, 'dtb')]) - ramdisk_size = kernel_ramdisk_info[4] - page_size = kernel_ramdisk_info[1] + if self.header_version > 3: + args.extend(['--vendor_bootconfig', + os.path.join(self.image_dir, 'bootconfig')]) + for entry in self.vendor_ramdisk_table: + (output_ramdisk_name, _, _, ramdisk_type, + ramdisk_name, board_id) = entry + args.extend(['--ramdisk_type', str(ramdisk_type)]) + args.extend(['--ramdisk_name', ramdisk_name]) + for idx, e in enumerate(board_id): + if e: + args.extend([f'--board_id{idx}', f'{e:#010x}']) + vendor_ramdisk_path = os.path.join( + self.image_dir, output_ramdisk_name) + args.extend(['--vendor_ramdisk_fragment', vendor_ramdisk_path]) + else: + args.extend(['--vendor_ramdisk', + os.path.join(self.image_dir, 'vendor_ramdisk')]) + + return args + + +def unpack_vendor_boot_image(boot_img, output_dir): + info = VendorBootImageInfoFormatter() + info.boot_magic = unpack('8s', boot_img.read(8))[0].decode() + info.header_version = unpack('I', boot_img.read(4))[0] + info.page_size = unpack('I', boot_img.read(4))[0] + info.kernel_load_address = unpack('I', boot_img.read(4))[0] + info.ramdisk_load_address = unpack('I', boot_img.read(4))[0] + info.vendor_ramdisk_size = unpack('I', boot_img.read(4))[0] + info.cmdline = cstr(unpack('2048s', boot_img.read(2048))[0].decode()) + info.tags_load_address = unpack('I', boot_img.read(4))[0] + info.product_name = cstr(unpack('16s', boot_img.read(16))[0].decode()) + info.header_size = unpack('I', boot_img.read(4))[0] + info.dtb_size = unpack('I', boot_img.read(4))[0] + info.dtb_load_address = unpack('Q', boot_img.read(8))[0] + + # Convenient shorthand. + page_size = info.page_size # The first pages contain the boot header - num_boot_header_pages = get_number_of_pages(VENDOR_BOOT_IMAGE_HEADER_V3_SIZE, page_size) - num_boot_ramdisk_pages = get_number_of_pages(ramdisk_size, page_size) - ramdisk_offset = page_size * num_boot_header_pages - image_info_list = [(ramdisk_offset, ramdisk_size, 'vendor_ramdisk')] + num_boot_header_pages = get_number_of_pages(info.header_size, page_size) + num_boot_ramdisk_pages = get_number_of_pages( + info.vendor_ramdisk_size, page_size) + num_boot_dtb_pages = get_number_of_pages(info.dtb_size, page_size) + + ramdisk_offset_base = page_size * num_boot_header_pages + image_info_list = [] + + if info.header_version > 3: + info.vendor_ramdisk_table_size = unpack('I', boot_img.read(4))[0] + vendor_ramdisk_table_entry_num = unpack('I', boot_img.read(4))[0] + vendor_ramdisk_table_entry_size = unpack('I', boot_img.read(4))[0] + info.vendor_bootconfig_size = unpack('I', boot_img.read(4))[0] + num_vendor_ramdisk_table_pages = get_number_of_pages( + info.vendor_ramdisk_table_size, page_size) + vendor_ramdisk_table_offset = page_size * ( + num_boot_header_pages + num_boot_ramdisk_pages + num_boot_dtb_pages) + + vendor_ramdisk_table = [] + vendor_ramdisk_symlinks = [] + for idx in range(vendor_ramdisk_table_entry_num): + entry_offset = vendor_ramdisk_table_offset + ( + vendor_ramdisk_table_entry_size * idx) + boot_img.seek(entry_offset) + ramdisk_size = unpack('I', boot_img.read(4))[0] + ramdisk_offset = unpack('I', boot_img.read(4))[0] + ramdisk_type = unpack('I', boot_img.read(4))[0] + ramdisk_name = cstr(unpack( + f'{VENDOR_RAMDISK_NAME_SIZE}s', + boot_img.read(VENDOR_RAMDISK_NAME_SIZE))[0].decode()) + board_id = unpack( + f'{VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE}I', + boot_img.read( + 4 * VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE)) + output_ramdisk_name = f'vendor_ramdisk{idx:02}' + + image_info_list.append((ramdisk_offset_base + ramdisk_offset, + ramdisk_size, output_ramdisk_name)) + vendor_ramdisk_symlinks.append((output_ramdisk_name, ramdisk_name)) + vendor_ramdisk_table.append( + (output_ramdisk_name, ramdisk_size, ramdisk_offset, + ramdisk_type, ramdisk_name, board_id)) + + info.vendor_ramdisk_table = vendor_ramdisk_table + + bootconfig_offset = page_size * (num_boot_header_pages + + num_boot_ramdisk_pages + num_boot_dtb_pages + + num_vendor_ramdisk_table_pages) + image_info_list.append((bootconfig_offset, info.vendor_bootconfig_size, + 'bootconfig')) + else: + image_info_list.append( + (ramdisk_offset_base, info.vendor_ramdisk_size, 'vendor_ramdisk')) dtb_offset = page_size * (num_boot_header_pages + num_boot_ramdisk_pages ) # header + vendor_ramdisk - image_info_list.append((dtb_offset, dtb_size, 'dtb')) + if info.dtb_size > 0: + image_info_list.append((dtb_offset, info.dtb_size, 'dtb')) - for image_info in image_info_list: - extract_image(image_info[0], image_info[1], args.boot_img, - os.path.join(args.out, image_info[2])) + create_out_dir(output_dir) + for offset, size, name in image_info_list: + extract_image(offset, size, boot_img, os.path.join(output_dir, name)) + info.image_dir = output_dir + + if info.header_version > 3: + vendor_ramdisk_by_name_dir = os.path.join( + output_dir, 'vendor-ramdisk-by-name') + create_out_dir(vendor_ramdisk_by_name_dir) + for src, dst in vendor_ramdisk_symlinks: + src_pathname = os.path.join('..', src) + dst_pathname = os.path.join( + vendor_ramdisk_by_name_dir, f'ramdisk_{dst}') + if os.path.lexists(dst_pathname): + os.remove(dst_pathname) + os.symlink(src_pathname, dst_pathname) + + return info -def unpack_image(args): - boot_magic = unpack('8s', args.boot_img.read(8))[0].decode() - print('boot_magic: %s' % boot_magic) - if boot_magic == "ANDROID!": - unpack_bootimage(args) - elif boot_magic == "VNDRBOOT": - unpack_vendor_bootimage(args) +def unpack_bootimg(boot_img, output_dir): + """Unpacks the |boot_img| to |output_dir|, and returns the 'info' object.""" + with open(boot_img, 'rb') as image_file: + boot_magic = unpack('8s', image_file.read(8))[0].decode() + image_file.seek(0) + if boot_magic == 'ANDROID!': + info = unpack_boot_image(image_file, output_dir) + elif boot_magic == 'VNDRBOOT': + info = unpack_vendor_boot_image(image_file, output_dir) + else: + raise ValueError(f'Not an Android boot image, magic: {boot_magic}') + + return info + + +def print_bootimg_info(info, output_format, null_separator): + """Format and print boot image info.""" + if output_format == 'mkbootimg': + mkbootimg_args = info.format_mkbootimg_argument() + if null_separator: + print('\0'.join(mkbootimg_args) + '\0', end='') + else: + print(shlex.join(mkbootimg_args)) + else: + print(info.format_pretty_text()) + + +def get_unpack_usage(): + return """Output format: + + * info + + Pretty-printed info-rich text format suitable for human inspection. + + * mkbootimg + + Output shell-escaped (quoted) argument strings that can be used to + reconstruct the boot image. For example: + + $ unpack_bootimg --boot_img vendor_boot.img --out out --format=mkbootimg | + tee mkbootimg_args + $ sh -c "mkbootimg $(cat mkbootimg_args) --vendor_boot repacked.img" + + vendor_boot.img and repacked.img would be equivalent. + + If the -0 option is specified, output unescaped null-terminated argument + strings that are suitable to be parsed by a shell script (xargs -0 format): + + $ unpack_bootimg --boot_img vendor_boot.img --out out --format=mkbootimg \\ + -0 | tee mkbootimg_args + $ declare -a MKBOOTIMG_ARGS=() + $ while IFS= read -r -d '' ARG; do + MKBOOTIMG_ARGS+=("${ARG}") + done Date: Wed, 8 Feb 2023 16:28:49 +0800 Subject: [PATCH 169/258] drm/rockchip: vconn: add support for DRM_MODE_CONNECTOR_VIRTUAL Support for multiple virtual connectors. The dts maybe like: vconn { compatible = "rockchip,virtual-connector"; virtual-connector-count = <2>; /* * virtual0 connected by default * virtual1 disconnected */ virtual1-disconnected; status = "okay"; }; Signed-off-by: Damon Ding Change-Id: I0871031fdeb124c2b7a6d77f5bf1aa111c3e093e --- drivers/gpu/drm/rockchip/rockchip_drm_vconn.c | 52 ++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vconn.c b/drivers/gpu/drm/rockchip/rockchip_drm_vconn.c index b9f637ffa8d7..f0fab09d386b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vconn.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vconn.c @@ -24,6 +24,7 @@ struct vconn_device { int bus_format; int if_id; int vp_id_mask; + bool connected; }; struct rockchip_vconn { @@ -235,7 +236,7 @@ static const struct drm_display_mode edid_cea_modes_1[] = { .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, }; -int vconn_drm_add_modes_noedid(struct drm_connector *connector) +static int vconn_drm_add_modes_noedid(struct drm_connector *connector) { struct drm_device *dev = connector->dev; struct drm_display_mode *mode; @@ -307,6 +308,18 @@ static const struct drm_encoder_helper_funcs rockchip_virtual_encoder_helper_fun .mode_set = rockchip_virtual_encoder_mode_set, }; +static enum drm_connector_status +rockchip_virtual_connector_detect(struct drm_connector *connector, bool force) +{ + struct vconn_device *vconn_dev = to_vconn_device(connector); + + if (vconn_dev->output_type == DRM_MODE_CONNECTOR_VIRTUAL) + return vconn_dev->connected ? connector_status_connected : + connector_status_disconnected; + + return connector_status_connected; +} + static void rockchip_virtual_connector_destroy(struct drm_connector *connector) { drm_connector_unregister(connector); @@ -314,6 +327,7 @@ static void rockchip_virtual_connector_destroy(struct drm_connector *connector) } static const struct drm_connector_funcs rockchip_virtual_connector_funcs = { + .detect = rockchip_virtual_connector_detect, .fill_modes = drm_helper_probe_single_connector_modes, .destroy = rockchip_virtual_connector_destroy, .reset = drm_atomic_helper_connector_reset, @@ -401,6 +415,8 @@ static int rockchip_vconn_get_encoder_type(int conn_type) return DRM_MODE_ENCODER_DSI; else if (conn_type == DRM_MODE_CONNECTOR_DPI) return DRM_MODE_ENCODER_DPI; + else if (conn_type == DRM_MODE_CONNECTOR_VIRTUAL) + return DRM_MODE_ENCODER_VIRTUAL; else return DRM_MODE_ENCODER_TMDS; } @@ -433,6 +449,38 @@ static int rockchip_vconn_device_create(struct rockchip_vconn *vconn, return 0; } +static int rockchip_virtual_connectors_create(struct rockchip_vconn *vconn) +{ + struct device_node *np = vconn->dev->of_node; + struct vconn_device *vconn_dev; + char propname[64]; + u32 count; + int i; + int ret; + + ret = of_property_read_u32(np, "virtual-connector-count", &count); + if (ret) + return ret; + + for (i = 0; i < count; i++) { + vconn_dev = devm_kzalloc(vconn->dev, sizeof(*vconn_dev), GFP_KERNEL); + if (!vconn_dev) + return -ENOMEM; + snprintf(propname, sizeof(propname), "virtual%d-disconnected", i); + vconn_dev->connected = !of_property_read_bool(np, propname); + vconn_dev->vconn = vconn; + vconn_dev->encoder_type = DRM_MODE_ENCODER_VIRTUAL; + vconn_dev->output_type = DRM_MODE_CONNECTOR_VIRTUAL; + vconn_dev->output_mode = ROCKCHIP_OUT_MODE_AAAA; + vconn_dev->bus_format = MEDIA_BUS_FMT_FIXED; + vconn_dev->if_id = 0; + vconn_dev->vp_id_mask = 0; + list_add_tail(&vconn_dev->list, &vconn->list_head); + } + + return 0; +} + static int rockchip_virtual_connector_bind(struct device *dev, struct device *master, void *data) { struct platform_device *pdev = to_platform_device(dev); @@ -486,6 +534,8 @@ static int rockchip_virtual_connector_bind(struct device *dev, struct device *ma ROCKCHIP_OUT_MODE_P888, MEDIA_BUS_FMT_RGB888_1X24, VOP_OUTPUT_IF_RGB); + rockchip_virtual_connectors_create(vconn); + platform_set_drvdata(pdev, vconn); rockchip_virtual_connector_register(vconn); From 3ca63279a075804809f18d889100df1c3994696e Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Thu, 29 Dec 2022 07:29:31 +0000 Subject: [PATCH 170/258] clk: rockchip: rk3528: Remove crypto clock They are moved to scmi clock. Signed-off-by: Joseph Chen Change-Id: I093a0f964c525efdf3a78fe5070c1860edac5a3c --- drivers/clk/rockchip/clk-rk3528.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3528.c b/drivers/clk/rockchip/clk-rk3528.c index 5303df086f00..00c682639bff 100644 --- a/drivers/clk/rockchip/clk-rk3528.c +++ b/drivers/clk/rockchip/clk-rk3528.c @@ -420,8 +420,6 @@ static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL, RK3528_CLKGATE_CON(9), 1, GFLAGS), - GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus_m_root", 0, - RK3528_CLKGATE_CON(10), 11, GFLAGS), COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL, RK3528_CLKSEL_CON(43), 6, 2, MFLAGS, RK3528_CLKGATE_CON(8), 4, GFLAGS), @@ -446,9 +444,6 @@ static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_bus_root", 0, RK3528_CLKGATE_CON(10), 3, GFLAGS), - GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus_root", 0, - RK3528_CLKGATE_CON(10), 12, GFLAGS), - COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, RK3528_CLKSEL_CON(43), 10, 2, MFLAGS, RK3528_CLKGATE_CON(8), 6, GFLAGS), @@ -475,12 +470,6 @@ static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED, RK3528_CLKGATE_CON(11), 12, GFLAGS), - COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_24m_p, 0, - RK3528_CLKSEL_CON(44), 0, 2, MFLAGS, - RK3528_CLKGATE_CON(10), 10, GFLAGS), - COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_24m_p, 0, - RK3528_CLKSEL_CON(43), 14, 2, MFLAGS, - RK3528_CLKGATE_CON(10), 9, GFLAGS), COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0, RK3528_CLKSEL_CON(44), 6, 2, MFLAGS, RK3528_CLKGATE_CON(11), 5, GFLAGS), From b5f76296d3f0b839832dd59fcf18075cce612b5c Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 15 Feb 2023 07:50:19 +0000 Subject: [PATCH 171/258] clk: rockchip: rk3528: Remove trng clock It was moved to scmi clock. Signed-off-by: Joseph Chen Change-Id: I51d0c70cb408af0c8a82a16133b3706c9c425cde --- drivers/clk/rockchip/clk-rk3528.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3528.c b/drivers/clk/rockchip/clk-rk3528.c index 00c682639bff..58becedac436 100644 --- a/drivers/clk/rockchip/clk-rk3528.c +++ b/drivers/clk/rockchip/clk-rk3528.c @@ -441,8 +441,6 @@ static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, RK3528_CLKSEL_CON(43), 8, 2, MFLAGS, RK3528_CLKGATE_CON(8), 5, GFLAGS), - GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_bus_root", 0, - RK3528_CLKGATE_CON(10), 3, GFLAGS), COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, RK3528_CLKSEL_CON(43), 10, 2, MFLAGS, From e18f50d37121e784ba851d06326b1210f449eabc Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Fri, 25 Nov 2022 10:12:25 +0000 Subject: [PATCH 172/258] arm64: dts: rockchip: rk3528: crypto use scmi clock and dummy softrst Signed-off-by: Joseph Chen Change-Id: I3340c8a2acb2ee4913e42a558f321e62f63899a2 --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 6 +++--- include/dt-bindings/clock/rk3528-cru.h | 18 ++++++++++-------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index c87d80333f0f..3ced26047c08 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1979,10 +1979,10 @@ compatible = "rockchip,crypto-v4"; reg = <0x0 0xffc40000 0x0 0x2000>; interrupts = ; - clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, - <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; + clocks = <&scmi_clk SCMI_ACLK_CRYPTO>, <&scmi_clk SCMI_HCLK_CRYPTO>, + <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; clock-names = "aclk", "hclk", "sclk", "pka"; - assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; + assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; assigned-clock-rates = <300000000>, <300000000>; resets = <&cru SRST_RESETN_CORE_CRYPTO>; reset-names = "crypto-rst"; diff --git a/include/dt-bindings/clock/rk3528-cru.h b/include/dt-bindings/clock/rk3528-cru.h index 086b0aaf4145..361e25e0a009 100644 --- a/include/dt-bindings/clock/rk3528-cru.h +++ b/include/dt-bindings/clock/rk3528-cru.h @@ -119,10 +119,6 @@ #define TCLK_WDT_NS 115 #define HCLK_TRNG_NS 116 #define PCLK_UART0 117 -#define CLK_CORE_CRYPTO 119 -#define CLK_PKA_CRYPTO 120 -#define ACLK_CRYPTO 121 -#define HCLK_CRYPTO 122 #define PCLK_DMA2DDR 123 #define ACLK_DMA2DDR 124 #define PCLK_PWM0 126 @@ -365,9 +361,6 @@ #define PCLK_WDT_S 480 #define TCLK_WDT_S 481 #define HCLK_TRNG_S 482 -#define PCLK_KLAD 483 -#define HCLK_CRYPTO_S 484 -#define HCLK_KLAD 485 #define HCLK_BOOTROM 486 #define PCLK_DCF 487 #define ACLK_SYSMEM 488 @@ -458,6 +451,15 @@ #define SCMI_CLK_DDR 20 #define SCMI_CLK_CPU 21 #define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 // CRU_SOFTRST_CON03(Offset:0xA0C) #define SRST_NCOREPORESET0 0x00000030 @@ -470,6 +472,7 @@ #define SRST_NCORESET3 0x00000037 #define SRST_NL2RESET 0x00000038 #define SRST_ARESETN_M_CORE_BIU 0x00000039 +#define SRST_RESETN_CORE_CRYPTO 0x0000003A // CRU_SOFTRST_CON05(Offset:0xA14) #define SRST_PRESETN_DBG 0x0000005D @@ -513,7 +516,6 @@ #define SRST_HRESETN_TRNG_NS 0x000000A3 #define SRST_PRESETN_UART0 0x000000A7 #define SRST_SRESETN_UART0 0x000000A8 -#define SRST_RESETN_CORE_CRYPTO 0x000000A9 #define SRST_RESETN_PKA_CRYPTO 0x000000AA #define SRST_ARESETN_CRYPTO 0x000000AB #define SRST_HRESETN_CRYPTO 0x000000AC From 5e16d409fee6d8544b1f1a58cd096ddffd07275b Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Tue, 14 Feb 2023 17:13:26 +0800 Subject: [PATCH 173/258] arm64: dts: rockchip: rk3528: trng use scmi clk Change-Id: I7a8bb9e824e9e7732a8fc497a2c828980086bd65 Signed-off-by: Lin Jinhan --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 2 +- include/dt-bindings/clock/rk3528-cru.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 3ced26047c08..b947fe4f2cf4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1993,7 +1993,7 @@ compatible = "rockchip,rkrng"; reg = <0x0 0xffc50000 0x0 0x200>; interrupts = ; - clocks = <&cru HCLK_TRNG_NS>; + clocks = <&scmi_clk SCMI_HCLK_TRNG>; clock-names = "hclk_trng"; resets = <&cru SRST_HRESETN_TRNG_NS>; reset-names = "reset"; diff --git a/include/dt-bindings/clock/rk3528-cru.h b/include/dt-bindings/clock/rk3528-cru.h index 361e25e0a009..7cfbc8c8524e 100644 --- a/include/dt-bindings/clock/rk3528-cru.h +++ b/include/dt-bindings/clock/rk3528-cru.h @@ -460,6 +460,7 @@ #define SCMI_PKA_CRYPTO_S 29 #define SCMI_CORE_KLAD 30 #define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 // CRU_SOFTRST_CON03(Offset:0xA0C) #define SRST_NCOREPORESET0 0x00000030 From 64c43c16fba78443916e195f8a3e002554cc6cec Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 14 Feb 2023 15:22:03 +0800 Subject: [PATCH 174/258] dt-bindings: display: virtual-connector: add virtual devices support Signed-off-by: Damon Ding Change-Id: I409ab14126c42b61340aa806525a8c4d04d37a70 --- .../bindings/display/rockchip/rockchip,virtual-connector.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,virtual-connector.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip,virtual-connector.txt index 4035a73e6130..2a104cd6c5dc 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,virtual-connector.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,virtual-connector.txt @@ -8,6 +8,9 @@ patternProperties: "connector-enable": if this connector should be enabled "connector-vp-id": which video port this connector attached to. The connector here should be hdmi0/1, dp0/1, mipi0/1 + "virtual-connector-count": the number of virtual connector devices. + "virtualX-disconnected": Set specified virtual connector to disconnected. + The X here should be less than virtual-connector-count. Example: vconn { @@ -16,6 +19,8 @@ vconn { hdmi1-enable; hdmi0-vp-id = <0>; hdmi1-vp-id = <1>; + virtual-connector-count = <2>; + virtual1-disconnected; status = "okay"; }; From 5df3a678bf9901fdb1dcd4889ec4de844d505f4c Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Wed, 15 Feb 2023 17:42:48 +0800 Subject: [PATCH 175/258] vdieo: rockchip: mpp: fix av1d iommu compile warning drivers/video/rockchip/mpp/mpp_iommu_av1d.c:911 av1_iommu_probe() warn: missing unwind goto? Signed-off-by: Yandong Lin Change-Id: Ia3ae5df50fa9d5ca7df84547b9b31d3ecd229922 --- drivers/video/rockchip/mpp/mpp_iommu_av1d.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_iommu_av1d.c b/drivers/video/rockchip/mpp/mpp_iommu_av1d.c index 9d21cb7874b5..39ff16c21ee9 100644 --- a/drivers/video/rockchip/mpp/mpp_iommu_av1d.c +++ b/drivers/video/rockchip/mpp/mpp_iommu_av1d.c @@ -907,18 +907,22 @@ static int av1_iommu_probe(struct platform_device *pdev) for (i = 0; i < iommu->num_irq; i++) { int irq = platform_get_irq(pdev, i); - if (irq < 0) - return irq; + if (irq < 0) { + err = -ENODEV; + goto err_diable_runtime; + } err = devm_request_irq(iommu->dev, irq, av1_iommu_irq, IRQF_SHARED, dev_name(dev), iommu); - if (err) { - pm_runtime_disable(dev); - goto err_remove_sysfs; - } + if (err) + goto err_diable_runtime; + } return 0; +err_diable_runtime: + pm_runtime_disable(dev); + iommu_device_unregister(&iommu->iommu); err_remove_sysfs: iommu_device_sysfs_remove(&iommu->iommu); err_put_group: From 91c0d689ea8a4867239036cb3e58af231a922c95 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 30 Jan 2023 10:41:55 +0800 Subject: [PATCH 176/258] Revert "regulator: fan53555: support reboot" This reverts commit 7d0153aa70271e3d40603531fd4a9997e552d3e6. Signed-off-by: Elaine Zhang Change-Id: I384b97e360d3954ea3798a127692d76c41433110 --- drivers/regulator/fan53555.c | 38 ------------------------------------ 1 file changed, 38 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index c672754ce98e..10026eed3960 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -777,45 +777,8 @@ static int fan53555_regulator_probe(struct i2c_client *client, ret = fan53555_regulator_register(di, &config); if (ret < 0) dev_err(&client->dev, "Failed to register regulator!\n"); - return ret; -} -static void fan53555_regulator_shutdown(struct i2c_client *client) -{ - struct fan53555_device_info *di; - int ret; - - di = i2c_get_clientdata(client); - - dev_info(di->dev, "fan53555..... reset\n"); - - switch (di->vendor) { - case FAN53555_VENDOR_FAIRCHILD: - case FAN53555_VENDOR_RK: - case FAN53555_VENDOR_SILERGY: - ret = regmap_update_bits(di->regmap, di->slew_reg, - CTL_RESET, CTL_RESET); - break; - case FAN53555_VENDOR_TCS: - ret = regmap_update_bits(di->regmap, TCS452X_LIMCONF, - CTL_RESET, CTL_RESET); - /* - * the device can't return 'ack' during the reset, - * it will return -ENXIO, ignore this error. - */ - if (ret == -ENXIO) - ret = 0; - break; - default: - ret = -EINVAL; - break; - } - - if (ret < 0) - dev_err(di->dev, "reset: force fan53555_reset error! ret=%d\n", ret); - else - dev_info(di->dev, "reset: force fan53555_reset ok!\n"); } static const struct i2c_device_id fan53555_id[] = { @@ -845,7 +808,6 @@ static struct i2c_driver fan53555_regulator_driver = { .of_match_table = of_match_ptr(fan53555_dt_ids), }, .probe = fan53555_regulator_probe, - .shutdown = fan53555_regulator_shutdown, .id_table = fan53555_id, }; From 389d57ff4808f4002553a1d3c95866655d4069d8 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 30 Jan 2023 10:43:16 +0800 Subject: [PATCH 177/258] Revert "regulator: fan53555: add support for Rockchip RK860X regulators" This reverts commit dbeca9d00aceafaaa4a638d398cfadbec0a37a31. RK860X please use rk860x-regulator.c Signed-off-by: Elaine Zhang Change-Id: I5dfb8a363cb5ea14397b5c183d931928792025b6 --- drivers/regulator/fan53555.c | 106 +++-------------------------- include/linux/regulator/fan53555.h | 1 - 2 files changed, 9 insertions(+), 98 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index 10026eed3960..babc18213606 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -27,10 +27,6 @@ #define FAN53555_VSEL0 0x00 #define FAN53555_VSEL1 0x01 -#define RK860X_VSEL0 0x06 -#define RK860X_VSEL1 0x07 -#define RK860X_MAX_SET 0x08 - #define TCS452X_VSEL0 0x11 #define TCS452X_VSEL1 0x10 #define TCS452X_TIME 0x13 @@ -61,8 +57,6 @@ #define CTL_MODE_VSEL0_MODE BIT(0) #define CTL_MODE_VSEL1_MODE BIT(1) -#define RK_VSEL_NSEL_MASK 0xff - #define TCS_VSEL_NSEL_MASK 0x7f #define TCS_VSEL0_MODE (1 << 7) #define TCS_VSEL1_MODE (1 << 6) @@ -72,12 +66,10 @@ #define FAN53555_NVOLTAGES_64 64 /* Numbers of voltages */ #define FAN53555_NVOLTAGES_127 127 /* Numbers of voltages */ -#define FAN53555_NVOLTAGES_160 160 /* Numbers of voltages */ enum fan53555_vendor { FAN53526_VENDOR_FAIRCHILD = 0, FAN53555_VENDOR_FAIRCHILD, - FAN53555_VENDOR_RK, FAN53555_VENDOR_SILERGY, FAN53555_VENDOR_TCS, }; @@ -125,8 +117,6 @@ struct fan53555_device_info { /* Voltage setting register */ unsigned int vol_reg; unsigned int sleep_reg; - unsigned int en_reg; - unsigned int sleep_en_reg; unsigned int mode_reg; unsigned int vol_mask; unsigned int mode_mask; @@ -151,26 +141,6 @@ static unsigned int fan53555_map_mode(unsigned int mode) REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; } -static int fan53555_get_voltage(struct regulator_dev *rdev) -{ - struct fan53555_device_info *di = rdev_get_drvdata(rdev); - unsigned int val; - int ret; - - if (di->vendor == FAN53555_VENDOR_RK) { - ret = regmap_read(di->regmap, RK860X_MAX_SET, &val); - if (ret < 0) - return ret; - ret = regulator_get_voltage_sel_regmap(rdev); - if (ret > val) - return val; - } else { - ret = regulator_get_voltage_sel_regmap(rdev); - } - - return ret; -} - static int fan53555_set_suspend_voltage(struct regulator_dev *rdev, int uV) { struct fan53555_device_info *di = rdev_get_drvdata(rdev); @@ -196,7 +166,7 @@ static int fan53555_set_suspend_enable(struct regulator_dev *rdev) { struct fan53555_device_info *di = rdev_get_drvdata(rdev); - return regmap_update_bits(di->regmap, di->sleep_en_reg, + return regmap_update_bits(di->regmap, di->sleep_reg, VSEL_BUCK_EN, VSEL_BUCK_EN); } @@ -204,7 +174,7 @@ static int fan53555_set_suspend_disable(struct regulator_dev *rdev) { struct fan53555_device_info *di = rdev_get_drvdata(rdev); - return regmap_update_bits(di->regmap, di->sleep_en_reg, + return regmap_update_bits(di->regmap, di->sleep_reg, VSEL_BUCK_EN, 0); } @@ -217,7 +187,7 @@ static int fan53555_set_enable(struct regulator_dev *rdev) return 0; } - return regmap_update_bits(di->regmap, di->en_reg, + return regmap_update_bits(rdev->regmap, di->vol_reg, VSEL_BUCK_EN, VSEL_BUCK_EN); } @@ -230,7 +200,7 @@ static int fan53555_set_disable(struct regulator_dev *rdev) return 0; } - return regmap_update_bits(di->regmap, di->en_reg, + return regmap_update_bits(rdev->regmap, di->vol_reg, VSEL_BUCK_EN, 0); } @@ -247,7 +217,7 @@ static int fan53555_is_enabled(struct regulator_dev *rdev) return gpiod_get_raw_value(di->vsel_gpio); } - ret = regmap_read(di->regmap, di->en_reg, &val); + ret = regmap_read(rdev->regmap, di->vol_reg, &val); if (ret < 0) return ret; if (val & VSEL_BUCK_EN) @@ -316,7 +286,6 @@ static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) switch (di->vendor) { case FAN53555_VENDOR_FAIRCHILD: - case FAN53555_VENDOR_RK: case FAN53555_VENDOR_SILERGY: slew_rate_t = slew_rates; slew_rate_n = ARRAY_SIZE(slew_rates); @@ -347,7 +316,7 @@ static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) static const struct regulator_ops fan53555_regulator_ops = { .set_voltage_sel = regulator_set_voltage_sel_regmap, - .get_voltage_sel = fan53555_get_voltage, + .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_time_sel = regulator_set_voltage_time_sel, .map_voltage = regulator_map_voltage_linear, .list_voltage = regulator_list_voltage_linear, @@ -438,51 +407,6 @@ static int fan53555_voltages_setup_fairchild(struct fan53555_device_info *di) return 0; } -static int fan53555_voltages_setup_rk(struct fan53555_device_info *di, - struct fan53555_platform_data *pdata) -{ - int ret = 0, val; - - if (di->sleep_vsel_id) { - di->sleep_reg = RK860X_VSEL1; - di->vol_reg = RK860X_VSEL0; - di->mode_reg = FAN53555_VSEL0; - di->en_reg = FAN53555_VSEL0; - di->sleep_en_reg = FAN53555_VSEL1; - } else { - di->sleep_reg = RK860X_VSEL0; - di->vol_reg = RK860X_VSEL1; - di->mode_reg = FAN53555_VSEL1; - di->en_reg = FAN53555_VSEL1; - di->sleep_en_reg = FAN53555_VSEL0; - } - - di->mode_mask = VSEL_MODE; - di->vol_mask = RK_VSEL_NSEL_MASK; - di->slew_reg = FAN53555_CONTROL; - di->slew_mask = CTL_SLEW_MASK; - di->slew_shift = CTL_SLEW_SHIFT; - - /* Init voltage range and step */ - di->vsel_min = 500000; - di->vsel_step = 6250; - di->n_voltages = FAN53555_NVOLTAGES_160; - - if (pdata->limit_volt) { - if (pdata->limit_volt < di->vsel_min || - pdata->limit_volt > 1500000) - pdata->limit_volt = 1500000; - val = (pdata->limit_volt - di->vsel_min) / di->vsel_step; - ret = regmap_write(di->regmap, RK860X_MAX_SET, val); - if (ret < 0) { - dev_err(di->dev, "Failed to set limit voltage!\n"); - return ret; - } - } - - return 0; -} - static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) { /* Init voltage range and step */ @@ -532,9 +456,6 @@ static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) di->vsel_step = 6250; di->n_voltages = FAN53555_NVOLTAGES_127; - di->en_reg = di->vol_reg; - di->sleep_en_reg = di->sleep_reg; - return 0; } @@ -563,9 +484,6 @@ static int fan53555_device_setup(struct fan53555_device_info *di, return -EINVAL; } - di->en_reg = di->vol_reg; - di->sleep_en_reg = di->sleep_reg; - /* Setup voltage range */ switch (di->vendor) { case FAN53526_VENDOR_FAIRCHILD: @@ -584,9 +502,6 @@ static int fan53555_device_setup(struct fan53555_device_info *di, case FAN53555_VENDOR_FAIRCHILD: ret = fan53555_voltages_setup_fairchild(di); break; - case FAN53555_VENDOR_RK: - ret = fan53555_voltages_setup_rk(di, pdata); - break; case FAN53555_VENDOR_SILERGY: ret = fan53555_voltages_setup_silergy(di); break; @@ -611,7 +526,7 @@ static int fan53555_regulator_register(struct fan53555_device_info *di, rdesc->ops = &fan53555_regulator_ops; rdesc->type = REGULATOR_VOLTAGE; rdesc->n_voltages = di->n_voltages; - rdesc->enable_reg = di->en_reg; + rdesc->enable_reg = di->vol_reg; rdesc->enable_mask = VSEL_BUCK_EN; rdesc->min_uV = di->vsel_min; rdesc->uV_step = di->vsel_step; @@ -634,7 +549,7 @@ static struct fan53555_platform_data *fan53555_parse_dt(struct device *dev, const struct regulator_desc *desc) { struct fan53555_platform_data *pdata; - int ret, flag, limit_volt; + int ret, flag; u32 tmp; pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); @@ -644,9 +559,6 @@ static struct fan53555_platform_data *fan53555_parse_dt(struct device *dev, pdata->regulator = of_get_regulator_init_data(dev, np, desc); pdata->regulator->constraints.initial_state = PM_SUSPEND_MEM; - if (!(of_property_read_u32(np, "limit-microvolt", &limit_volt))) - pdata->limit_volt = limit_volt; - ret = of_property_read_u32(np, "fcs,suspend-voltage-selector", &tmp); if (!ret) @@ -676,7 +588,7 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { }, { .compatible = "fcs,fan53555", .data = (void *)FAN53555_VENDOR_FAIRCHILD - }, { + }, { .compatible = "silergy,syr827", .data = (void *)FAN53555_VENDOR_SILERGY, }, { diff --git a/include/linux/regulator/fan53555.h b/include/linux/regulator/fan53555.h index e8703b6fc13d..9270fd7bd8da 100644 --- a/include/linux/regulator/fan53555.h +++ b/include/linux/regulator/fan53555.h @@ -52,7 +52,6 @@ struct fan53555_platform_data { unsigned int slew_rate; /* Sleep VSEL ID */ unsigned int sleep_vsel_id; - int limit_volt; struct gpio_desc *vsel_gpio; }; From 1387f9a1c8e117cc950704296b08c7ce8ef53a8c Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 30 Jan 2023 10:53:08 +0800 Subject: [PATCH 178/258] Revert "regulator: fan53555: add TCS4525 DCDC support" This reverts commit 1ca735225ab43f53328b832aff7e57fe8a0df9f9. Signed-off-by: Elaine Zhang Change-Id: I220561a0e2876bb217309e14305e6e37e6ef51b2 --- drivers/regulator/fan53555.c | 172 ++++++++++------------------------- 1 file changed, 48 insertions(+), 124 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index babc18213606..059cf3330bfa 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -26,13 +26,6 @@ /* Voltage setting */ #define FAN53555_VSEL0 0x00 #define FAN53555_VSEL1 0x01 - -#define TCS452X_VSEL0 0x11 -#define TCS452X_VSEL1 0x10 -#define TCS452X_TIME 0x13 -#define TCS452X_COMMAND 0x14 -#define TCS452X_LIMCONF 0x16 - /* Control register */ #define FAN53555_CONTROL 0x02 /* IC Type */ @@ -45,7 +38,6 @@ /* VSEL bit definitions */ #define VSEL_BUCK_EN (1 << 7) #define VSEL_MODE (1 << 6) -#define VSEL_NSEL_MASK 0x3F /* Chip ID and Verison */ #define DIE_ID 0x0F /* ID1 */ #define DIE_REV 0x0F /* ID2 */ @@ -57,21 +49,13 @@ #define CTL_MODE_VSEL0_MODE BIT(0) #define CTL_MODE_VSEL1_MODE BIT(1) -#define TCS_VSEL_NSEL_MASK 0x7f -#define TCS_VSEL0_MODE (1 << 7) -#define TCS_VSEL1_MODE (1 << 6) - -#define TCS_SLEW_SHIFT 3 -#define TCS_SLEW_MASK (0x3 < 3) - -#define FAN53555_NVOLTAGES_64 64 /* Numbers of voltages */ -#define FAN53555_NVOLTAGES_127 127 /* Numbers of voltages */ +#define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ +#define FAN53526_NVOLTAGES 128 enum fan53555_vendor { FAN53526_VENDOR_FAIRCHILD = 0, FAN53555_VENDOR_FAIRCHILD, FAN53555_VENDOR_SILERGY, - FAN53555_VENDOR_TCS, }; enum { @@ -106,10 +90,8 @@ enum { struct fan53555_device_info { enum fan53555_vendor vendor; - struct regmap *regmap; struct device *dev; struct regulator_desc desc; - struct regulator_dev *rdev; struct regulator_init_data *regulator; /* IC Type and Rev */ int chip_id; @@ -117,18 +99,13 @@ struct fan53555_device_info { /* Voltage setting register */ unsigned int vol_reg; unsigned int sleep_reg; - unsigned int mode_reg; - unsigned int vol_mask; - unsigned int mode_mask; - unsigned int slew_reg; - unsigned int slew_mask; - unsigned int slew_shift; /* Voltage range and step(linear) */ unsigned int vsel_min; unsigned int vsel_step; - unsigned int n_voltages; - /* Voltage slew rate limiting */ - unsigned int slew_rate; + unsigned int vsel_count; + /* Mode */ + unsigned int mode_reg; + unsigned int mode_mask; /* Sleep voltage cache */ unsigned int sleep_vol_cache; struct gpio_desc *vsel_gpio; @@ -151,8 +128,8 @@ static int fan53555_set_suspend_voltage(struct regulator_dev *rdev, int uV) ret = regulator_map_voltage_linear(rdev, uV, uV); if (ret < 0) return ret; - ret = regmap_update_bits(di->regmap, di->sleep_reg, - di->vol_mask, ret); + ret = regmap_update_bits(rdev->regmap, di->sleep_reg, + di->desc.vsel_mask, ret); if (ret < 0) return ret; /* Cache the sleep voltage setting. @@ -166,7 +143,7 @@ static int fan53555_set_suspend_enable(struct regulator_dev *rdev) { struct fan53555_device_info *di = rdev_get_drvdata(rdev); - return regmap_update_bits(di->regmap, di->sleep_reg, + return regmap_update_bits(rdev->regmap, di->sleep_reg, VSEL_BUCK_EN, VSEL_BUCK_EN); } @@ -174,7 +151,7 @@ static int fan53555_set_suspend_disable(struct regulator_dev *rdev) { struct fan53555_device_info *di = rdev_get_drvdata(rdev); - return regmap_update_bits(di->regmap, di->sleep_reg, + return regmap_update_bits(rdev->regmap, di->sleep_reg, VSEL_BUCK_EN, 0); } @@ -232,11 +209,11 @@ static int fan53555_set_mode(struct regulator_dev *rdev, unsigned int mode) switch (mode) { case REGULATOR_MODE_FAST: - regmap_update_bits(di->regmap, di->mode_reg, + regmap_update_bits(rdev->regmap, di->mode_reg, di->mode_mask, di->mode_mask); break; case REGULATOR_MODE_NORMAL: - regmap_update_bits(di->regmap, di->mode_reg, di->mode_mask, 0); + regmap_update_bits(rdev->regmap, di->vol_reg, di->mode_mask, 0); break; default: return -EINVAL; @@ -250,7 +227,7 @@ static unsigned int fan53555_get_mode(struct regulator_dev *rdev) unsigned int val; int ret = 0; - ret = regmap_read(di->regmap, di->mode_reg, &val); + ret = regmap_read(rdev->regmap, di->mode_reg, &val); if (ret < 0) return ret; if (val & di->mode_mask) @@ -270,36 +247,13 @@ static const int slew_rates[] = { 500, }; -static const int tcs_slew_rates[] = { - 18700, - 9300, - 4600, - 2300, -}; - static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) { struct fan53555_device_info *di = rdev_get_drvdata(rdev); int regval = -1, i; - const int *slew_rate_t; - int slew_rate_n; - switch (di->vendor) { - case FAN53555_VENDOR_FAIRCHILD: - case FAN53555_VENDOR_SILERGY: - slew_rate_t = slew_rates; - slew_rate_n = ARRAY_SIZE(slew_rates); - break; - case FAN53555_VENDOR_TCS: - slew_rate_t = tcs_slew_rates; - slew_rate_n = ARRAY_SIZE(tcs_slew_rates); - break; - default: - return -EINVAL; - } - - for (i = 0; i < slew_rate_n; i++) { - if (ramp <= slew_rate_t[i]) + for (i = 0; i < ARRAY_SIZE(slew_rates); i++) { + if (ramp <= slew_rates[i]) regval = i; else break; @@ -310,8 +264,8 @@ static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) return -EINVAL; } - return regmap_update_bits(di->regmap, di->slew_reg, - di->slew_mask, regval << di->slew_shift); + return regmap_update_bits(rdev->regmap, FAN53555_CONTROL, + CTL_SLEW_MASK, regval << CTL_SLEW_SHIFT); } static const struct regulator_ops fan53555_regulator_ops = { @@ -354,7 +308,7 @@ static int fan53526_voltages_setup_fairchild(struct fan53555_device_info *di) return -EINVAL; } - di->n_voltages = FAN53555_NVOLTAGES_64; + di->vsel_count = FAN53526_NVOLTAGES; return 0; } @@ -396,13 +350,8 @@ static int fan53555_voltages_setup_fairchild(struct fan53555_device_info *di) "Chip ID %d not supported!\n", di->chip_id); return -EINVAL; } - di->vol_mask = VSEL_NSEL_MASK; - di->mode_reg = di->vol_reg; - di->mode_mask = VSEL_MODE; - di->slew_reg = FAN53555_CONTROL; - di->slew_mask = CTL_SLEW_MASK; - di->slew_shift = CTL_SLEW_SHIFT; - di->n_voltages = FAN53555_NVOLTAGES_64; + + di->vsel_count = FAN53555_NVOLTAGES; return 0; } @@ -421,40 +370,8 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) "Chip ID %d not supported!\n", di->chip_id); return -EINVAL; } - di->vol_mask = VSEL_NSEL_MASK; - di->mode_reg = di->vol_reg; - di->mode_mask = VSEL_MODE; - di->slew_reg = FAN53555_CONTROL; - di->slew_reg = FAN53555_CONTROL; - di->slew_mask = CTL_SLEW_MASK; - di->slew_shift = CTL_SLEW_SHIFT; - di->n_voltages = FAN53555_NVOLTAGES_64; - return 0; -} - -static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) -{ - if (di->sleep_vsel_id) { - di->sleep_reg = TCS452X_VSEL1; - di->vol_reg = TCS452X_VSEL0; - di->mode_mask = TCS_VSEL0_MODE; - } else { - di->sleep_reg = TCS452X_VSEL0; - di->vol_reg = TCS452X_VSEL1; - di->mode_mask = TCS_VSEL1_MODE; - } - - di->mode_reg = TCS452X_COMMAND; - di->vol_mask = TCS_VSEL_NSEL_MASK; - di->slew_reg = TCS452X_TIME; - di->slew_mask = TCS_SLEW_MASK; - di->slew_shift = TCS_SLEW_MASK; - - /* Init voltage range and step */ - di->vsel_min = 600000; - di->vsel_step = 6250; - di->n_voltages = FAN53555_NVOLTAGES_127; + di->vsel_count = FAN53555_NVOLTAGES; return 0; } @@ -484,7 +401,7 @@ static int fan53555_device_setup(struct fan53555_device_info *di, return -EINVAL; } - /* Setup voltage range */ + /* Setup mode control register */ switch (di->vendor) { case FAN53526_VENDOR_FAIRCHILD: di->mode_reg = FAN53555_CONTROL; @@ -497,6 +414,20 @@ static int fan53555_device_setup(struct fan53555_device_info *di, di->mode_mask = CTL_MODE_VSEL0_MODE; break; } + break; + case FAN53555_VENDOR_FAIRCHILD: + case FAN53555_VENDOR_SILERGY: + di->mode_reg = di->vol_reg; + di->mode_mask = VSEL_MODE; + break; + default: + dev_err(di->dev, "vendor %d not supported!\n", di->vendor); + return -EINVAL; + } + + /* Setup voltage range */ + switch (di->vendor) { + case FAN53526_VENDOR_FAIRCHILD: ret = fan53526_voltages_setup_fairchild(di); break; case FAN53555_VENDOR_FAIRCHILD: @@ -505,9 +436,6 @@ static int fan53555_device_setup(struct fan53555_device_info *di, case FAN53555_VENDOR_SILERGY: ret = fan53555_voltages_setup_silergy(di); break; - case FAN53555_VENDOR_TCS: - ret = fan53555_voltages_setup_tcs(di); - break; default: dev_err(di->dev, "vendor %d not supported!\n", di->vendor); return -EINVAL; @@ -520,23 +448,24 @@ static int fan53555_regulator_register(struct fan53555_device_info *di, struct regulator_config *config) { struct regulator_desc *rdesc = &di->desc; + struct regulator_dev *rdev; rdesc->name = "fan53555-reg"; rdesc->supply_name = "vin"; rdesc->ops = &fan53555_regulator_ops; rdesc->type = REGULATOR_VOLTAGE; - rdesc->n_voltages = di->n_voltages; + rdesc->n_voltages = di->vsel_count; rdesc->enable_reg = di->vol_reg; rdesc->enable_mask = VSEL_BUCK_EN; rdesc->min_uV = di->vsel_min; rdesc->uV_step = di->vsel_step; rdesc->vsel_reg = di->vol_reg; - rdesc->vsel_mask = di->vol_mask; + rdesc->vsel_mask = di->vsel_count - 1; rdesc->owner = THIS_MODULE; rdesc->enable_time = 400; - di->rdev = devm_regulator_register(di->dev, &di->desc, config); - return PTR_ERR_OR_ZERO(di->rdev); + rdev = devm_regulator_register(di->dev, &di->desc, config); + return PTR_ERR_OR_ZERO(rdev); } static const struct regmap_config fan53555_regmap_config = { @@ -594,9 +523,6 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { }, { .compatible = "silergy,syr828", .data = (void *)FAN53555_VENDOR_SILERGY, - }, { - .compatible = "tcs,tcs452x", /* tcs4525/4526 */ - .data = (void *)FAN53555_VENDOR_TCS }, { } }; @@ -609,6 +535,7 @@ static int fan53555_regulator_probe(struct i2c_client *client, struct fan53555_device_info *di; struct fan53555_platform_data *pdata; struct regulator_config config = { }; + struct regmap *regmap; unsigned int val; int ret; @@ -650,22 +577,22 @@ static int fan53555_regulator_probe(struct i2c_client *client, di->vendor = id->driver_data; } - di->regmap = devm_regmap_init_i2c(client, &fan53555_regmap_config); - if (IS_ERR(di->regmap)) { + regmap = devm_regmap_init_i2c(client, &fan53555_regmap_config); + if (IS_ERR(regmap)) { dev_err(&client->dev, "Failed to allocate regmap!\n"); - return PTR_ERR(di->regmap); + return PTR_ERR(regmap); } di->dev = &client->dev; i2c_set_clientdata(client, di); /* Get chip ID */ - ret = regmap_read(di->regmap, FAN53555_ID1, &val); + ret = regmap_read(regmap, FAN53555_ID1, &val); if (ret < 0) { dev_err(&client->dev, "Failed to get chip ID!\n"); return ret; } di->chip_id = val & DIE_ID; /* Get chip revision */ - ret = regmap_read(di->regmap, FAN53555_ID2, &val); + ret = regmap_read(regmap, FAN53555_ID2, &val); if (ret < 0) { dev_err(&client->dev, "Failed to get chip Rev!\n"); return ret; @@ -682,7 +609,7 @@ static int fan53555_regulator_probe(struct i2c_client *client, /* Register regulator */ config.dev = di->dev; config.init_data = di->regulator; - config.regmap = di->regmap; + config.regmap = regmap; config.driver_data = di; config.of_node = np; @@ -706,9 +633,6 @@ static const struct i2c_device_id fan53555_id[] = { }, { .name = "syr828", .driver_data = FAN53555_VENDOR_SILERGY - }, { - .name = "tcs452x", - .driver_data = FAN53555_VENDOR_TCS }, { }, }; From a7acf5eb230418741903e2cbd794563db154641c Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 9 Feb 2023 10:21:30 +0800 Subject: [PATCH 179/258] Revert "regulator: fan53555: fix up the dcdc is disabled when reboot" This reverts commit 14d85ea556dcbb553d8d6a7ca6e8a5552d983834. Signed-off-by: Elaine Zhang Change-Id: I5c65709aa3d94e00157b8d73cdba6fb8ba006463 --- drivers/regulator/fan53555.c | 79 ++---------------------------- include/linux/regulator/fan53555.h | 1 - 2 files changed, 4 insertions(+), 76 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index 059cf3330bfa..f36d1c5ebaab 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -20,8 +20,6 @@ #include #include #include -#include -#include /* Voltage setting */ #define FAN53555_VSEL0 0x00 @@ -108,8 +106,6 @@ struct fan53555_device_info { unsigned int mode_mask; /* Sleep voltage cache */ unsigned int sleep_vol_cache; - struct gpio_desc *vsel_gpio; - unsigned int sleep_vsel_id; }; static unsigned int fan53555_map_mode(unsigned int mode) @@ -155,54 +151,6 @@ static int fan53555_set_suspend_disable(struct regulator_dev *rdev) VSEL_BUCK_EN, 0); } -static int fan53555_set_enable(struct regulator_dev *rdev) -{ - struct fan53555_device_info *di = rdev_get_drvdata(rdev); - - if (di->vsel_gpio) { - gpiod_set_raw_value(di->vsel_gpio, !di->sleep_vsel_id); - return 0; - } - - return regmap_update_bits(rdev->regmap, di->vol_reg, - VSEL_BUCK_EN, VSEL_BUCK_EN); -} - -static int fan53555_set_disable(struct regulator_dev *rdev) -{ - struct fan53555_device_info *di = rdev_get_drvdata(rdev); - - if (di->vsel_gpio) { - gpiod_set_raw_value(di->vsel_gpio, di->sleep_vsel_id); - return 0; - } - - return regmap_update_bits(rdev->regmap, di->vol_reg, - VSEL_BUCK_EN, 0); -} - -static int fan53555_is_enabled(struct regulator_dev *rdev) -{ - struct fan53555_device_info *di = rdev_get_drvdata(rdev); - unsigned int val; - int ret = 0; - - if (di->vsel_gpio) { - if (di->sleep_vsel_id) - return !gpiod_get_raw_value(di->vsel_gpio); - else - return gpiod_get_raw_value(di->vsel_gpio); - } - - ret = regmap_read(rdev->regmap, di->vol_reg, &val); - if (ret < 0) - return ret; - if (val & VSEL_BUCK_EN) - return 1; - else - return 0; -} - static int fan53555_set_mode(struct regulator_dev *rdev, unsigned int mode) { struct fan53555_device_info *di = rdev_get_drvdata(rdev); @@ -275,9 +223,9 @@ static const struct regulator_ops fan53555_regulator_ops = { .map_voltage = regulator_map_voltage_linear, .list_voltage = regulator_list_voltage_linear, .set_suspend_voltage = fan53555_set_suspend_voltage, - .enable = fan53555_set_enable, - .disable = fan53555_set_disable, - .is_enabled = fan53555_is_enabled, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, .set_mode = fan53555_set_mode, .get_mode = fan53555_get_mode, .set_ramp_delay = fan53555_set_ramp, @@ -462,7 +410,6 @@ static int fan53555_regulator_register(struct fan53555_device_info *di, rdesc->vsel_reg = di->vol_reg; rdesc->vsel_mask = di->vsel_count - 1; rdesc->owner = THIS_MODULE; - rdesc->enable_time = 400; rdev = devm_regulator_register(di->dev, &di->desc, config); return PTR_ERR_OR_ZERO(rdev); @@ -478,7 +425,7 @@ static struct fan53555_platform_data *fan53555_parse_dt(struct device *dev, const struct regulator_desc *desc) { struct fan53555_platform_data *pdata; - int ret, flag; + int ret; u32 tmp; pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); @@ -486,27 +433,12 @@ static struct fan53555_platform_data *fan53555_parse_dt(struct device *dev, return NULL; pdata->regulator = of_get_regulator_init_data(dev, np, desc); - pdata->regulator->constraints.initial_state = PM_SUSPEND_MEM; ret = of_property_read_u32(np, "fcs,suspend-voltage-selector", &tmp); if (!ret) pdata->sleep_vsel_id = tmp; - if (pdata->sleep_vsel_id) - flag = GPIOD_OUT_LOW; - else - flag = GPIOD_OUT_HIGH; - - pdata->vsel_gpio = - devm_gpiod_get_index_optional(dev, "vsel", 0, - flag); - if (IS_ERR(pdata->vsel_gpio)) { - ret = PTR_ERR(pdata->vsel_gpio); - dev_err(dev, "failed to get vesl gpio (%d)\n", ret); - pdata->vsel_gpio = NULL; - } - return pdata; } @@ -555,9 +487,6 @@ static int fan53555_regulator_probe(struct i2c_client *client, return -ENODEV; } - di->vsel_gpio = pdata->vsel_gpio; - di->sleep_vsel_id = pdata->sleep_vsel_id; - di->regulator = pdata->regulator; if (client->dev.of_node) { di->vendor = diff --git a/include/linux/regulator/fan53555.h b/include/linux/regulator/fan53555.h index 9270fd7bd8da..ce8df21863f0 100644 --- a/include/linux/regulator/fan53555.h +++ b/include/linux/regulator/fan53555.h @@ -52,7 +52,6 @@ struct fan53555_platform_data { unsigned int slew_rate; /* Sleep VSEL ID */ unsigned int sleep_vsel_id; - struct gpio_desc *vsel_gpio; }; #endif /* __FAN53555_H__ */ From 9b5ca694baa72af5926a22a57ff6c6fefeac9152 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 21 Apr 2021 18:03:38 -0300 Subject: [PATCH 180/258] UPSTREAM: regulator: fan53555: Add TCS4525 DCDC support TCS4525 main features: - 2.7V to 5.5V Input Voltage Range; - 3MHz Constant Switching Frequency; - 5A Available Load Current; - Programmable Output Voltage: 0.6V to 1.4V in 6.25mV Steps; - PFM/PWM Operation for Optimum Increased Efficiency; Signed-off-by: Joseph Chen [Ezequiel: Forward port] Signed-off-by: Ezequiel Garcia Link: https://lore.kernel.org/r/20210421210338.43819-3-ezequiel@collabora.com Signed-off-by: Mark Brown (cherry picked from commit 914df8faa7d6fdff7afa1fbde888a2bed8d72fa7) Signed-off-by: Elaine Zhang Change-Id: I8297b212781059721b37bce1bf15bb1c5804fdd6 --- drivers/regulator/fan53555.c | 136 +++++++++++++++++++++++++++++++---- 1 file changed, 122 insertions(+), 14 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index f36d1c5ebaab..a8630b02a45d 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -24,6 +24,12 @@ /* Voltage setting */ #define FAN53555_VSEL0 0x00 #define FAN53555_VSEL1 0x01 + +#define TCS4525_VSEL0 0x11 +#define TCS4525_VSEL1 0x10 +#define TCS4525_TIME 0x13 +#define TCS4525_COMMAND 0x14 + /* Control register */ #define FAN53555_CONTROL 0x02 /* IC Type */ @@ -49,11 +55,20 @@ #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ #define FAN53526_NVOLTAGES 128 +#define TCS4525_NVOLTAGES 127 /* Numbers of voltages */ + +#define TCS_VSEL_NSEL_MASK 0x7f +#define TCS_VSEL0_MODE (1 << 7) +#define TCS_VSEL1_MODE (1 << 6) + +#define TCS_SLEW_SHIFT 3 +#define TCS_SLEW_MASK (0x3 < 3) enum fan53555_vendor { FAN53526_VENDOR_FAIRCHILD = 0, FAN53555_VENDOR_FAIRCHILD, FAN53555_VENDOR_SILERGY, + FAN53555_VENDOR_TCS, }; enum { @@ -106,6 +121,11 @@ struct fan53555_device_info { unsigned int mode_mask; /* Sleep voltage cache */ unsigned int sleep_vol_cache; + /* Slew rate */ + unsigned int slew_reg; + unsigned int slew_mask; + unsigned int slew_shift; + unsigned int slew_rate; }; static unsigned int fan53555_map_mode(unsigned int mode) @@ -195,13 +215,37 @@ static const int slew_rates[] = { 500, }; +static const int tcs_slew_rates[] = { + 18700, + 9300, + 4600, + 2300, +}; + static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) { struct fan53555_device_info *di = rdev_get_drvdata(rdev); int regval = -1, i; + const int *slew_rate_t; + int slew_rate_n; - for (i = 0; i < ARRAY_SIZE(slew_rates); i++) { - if (ramp <= slew_rates[i]) + switch (di->vendor) { + case FAN53526_VENDOR_FAIRCHILD: + case FAN53555_VENDOR_FAIRCHILD: + case FAN53555_VENDOR_SILERGY: + slew_rate_t = slew_rates; + slew_rate_n = ARRAY_SIZE(slew_rates); + break; + case FAN53555_VENDOR_TCS: + slew_rate_t = tcs_slew_rates; + slew_rate_n = ARRAY_SIZE(tcs_slew_rates); + break; + default: + return -EINVAL; + } + + for (i = 0; i < slew_rate_n; i++) { + if (ramp <= slew_rate_t[i]) regval = i; else break; @@ -212,8 +256,8 @@ static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) return -EINVAL; } - return regmap_update_bits(rdev->regmap, FAN53555_CONTROL, - CTL_SLEW_MASK, regval << CTL_SLEW_SHIFT); + return regmap_update_bits(rdev->regmap, di->slew_reg, + di->slew_mask, regval << di->slew_shift); } static const struct regulator_ops fan53555_regulator_ops = { @@ -298,7 +342,9 @@ static int fan53555_voltages_setup_fairchild(struct fan53555_device_info *di) "Chip ID %d not supported!\n", di->chip_id); return -EINVAL; } - + di->slew_reg = FAN53555_CONTROL; + di->slew_mask = CTL_SLEW_MASK; + di->slew_shift = CTL_SLEW_SHIFT; di->vsel_count = FAN53555_NVOLTAGES; return 0; @@ -318,12 +364,29 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) "Chip ID %d not supported!\n", di->chip_id); return -EINVAL; } - + di->slew_reg = FAN53555_CONTROL; + di->slew_reg = FAN53555_CONTROL; + di->slew_mask = CTL_SLEW_MASK; + di->slew_shift = CTL_SLEW_SHIFT; di->vsel_count = FAN53555_NVOLTAGES; return 0; } +static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) +{ + di->slew_reg = TCS4525_TIME; + di->slew_mask = TCS_SLEW_MASK; + di->slew_shift = TCS_SLEW_MASK; + + /* Init voltage range and step */ + di->vsel_min = 600000; + di->vsel_step = 6250; + di->vsel_count = TCS4525_NVOLTAGES; + + return 0; +} + /* For 00,01,03,05 options: * VOUT = 0.60V + NSELx * 10mV, from 0.60 to 1.23V. * For 04 option: @@ -335,17 +398,41 @@ static int fan53555_device_setup(struct fan53555_device_info *di, int ret = 0; /* Setup voltage control register */ - switch (pdata->sleep_vsel_id) { - case FAN53555_VSEL_ID_0: - di->sleep_reg = FAN53555_VSEL0; - di->vol_reg = FAN53555_VSEL1; + switch (di->vendor) { + case FAN53526_VENDOR_FAIRCHILD: + case FAN53555_VENDOR_FAIRCHILD: + case FAN53555_VENDOR_SILERGY: + switch (pdata->sleep_vsel_id) { + case FAN53555_VSEL_ID_0: + di->sleep_reg = FAN53555_VSEL0; + di->vol_reg = FAN53555_VSEL1; + break; + case FAN53555_VSEL_ID_1: + di->sleep_reg = FAN53555_VSEL1; + di->vol_reg = FAN53555_VSEL0; + break; + default: + dev_err(di->dev, "Invalid VSEL ID!\n"); + return -EINVAL; + } break; - case FAN53555_VSEL_ID_1: - di->sleep_reg = FAN53555_VSEL1; - di->vol_reg = FAN53555_VSEL0; + case FAN53555_VENDOR_TCS: + switch (pdata->sleep_vsel_id) { + case FAN53555_VSEL_ID_0: + di->sleep_reg = TCS4525_VSEL0; + di->vol_reg = TCS4525_VSEL1; + break; + case FAN53555_VSEL_ID_1: + di->sleep_reg = TCS4525_VSEL1; + di->vol_reg = TCS4525_VSEL0; + break; + default: + dev_err(di->dev, "Invalid VSEL ID!\n"); + return -EINVAL; + } break; default: - dev_err(di->dev, "Invalid VSEL ID!\n"); + dev_err(di->dev, "vendor %d not supported!\n", di->vendor); return -EINVAL; } @@ -368,6 +455,18 @@ static int fan53555_device_setup(struct fan53555_device_info *di, di->mode_reg = di->vol_reg; di->mode_mask = VSEL_MODE; break; + case FAN53555_VENDOR_TCS: + di->mode_reg = TCS4525_COMMAND; + + switch (pdata->sleep_vsel_id) { + case FAN53555_VSEL_ID_0: + di->mode_mask = TCS_VSEL1_MODE; + break; + case FAN53555_VSEL_ID_1: + di->mode_mask = TCS_VSEL0_MODE; + break; + } + break; default: dev_err(di->dev, "vendor %d not supported!\n", di->vendor); return -EINVAL; @@ -384,6 +483,9 @@ static int fan53555_device_setup(struct fan53555_device_info *di, case FAN53555_VENDOR_SILERGY: ret = fan53555_voltages_setup_silergy(di); break; + case FAN53555_VENDOR_TCS: + ret = fan53555_voltages_setup_tcs(di); + break; default: dev_err(di->dev, "vendor %d not supported!\n", di->vendor); return -EINVAL; @@ -455,6 +557,9 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { }, { .compatible = "silergy,syr828", .data = (void *)FAN53555_VENDOR_SILERGY, + }, { + .compatible = "tcs,tcs4525", + .data = (void *)FAN53555_VENDOR_TCS }, { } }; @@ -562,6 +667,9 @@ static const struct i2c_device_id fan53555_id[] = { }, { .name = "syr828", .driver_data = FAN53555_VENDOR_SILERGY + }, { + .name = "tcs4525", + .driver_data = FAN53555_VENDOR_TCS }, { }, }; From b895b708f798b2aecc30d561cd7429358995f0cb Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Tue, 11 May 2021 17:13:33 -0400 Subject: [PATCH 181/258] UPSTREAM: regulator: fan53555: fix TCS4525 voltage calulation The TCS4525 has 128 voltage steps. With the calculation set to 127 the most significant bit is disregarded which leads to a miscalculation of the voltage by about 200mv. Fix the calculation to end deadlock on the rk3566-quartz64 which uses this as the cpu regulator. Fixes: 914df8faa7d6 ("regulator: fan53555: Add TCS4525 DCDC support") Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20210511211335.2935163-2-pgwipeout@gmail.com Signed-off-by: Mark Brown (cherry picked from commit d4db69eba290732357f03ba0a14350b81f778290) Signed-off-by: Elaine Zhang Change-Id: I26e61bbded2df512cbca0989e7df1217b677ca1b --- drivers/regulator/fan53555.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index a8630b02a45d..8d7b916f5d76 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -55,7 +55,6 @@ #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ #define FAN53526_NVOLTAGES 128 -#define TCS4525_NVOLTAGES 127 /* Numbers of voltages */ #define TCS_VSEL_NSEL_MASK 0x7f #define TCS_VSEL0_MODE (1 << 7) @@ -382,7 +381,7 @@ static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) /* Init voltage range and step */ di->vsel_min = 600000; di->vsel_step = 6250; - di->vsel_count = TCS4525_NVOLTAGES; + di->vsel_count = FAN53526_NVOLTAGES; return 0; } From 73b5c3105e6b7990b438aa8dac544967baf18760 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Tue, 11 May 2021 17:13:34 -0400 Subject: [PATCH 182/258] UPSTREAM: regulator: fan53555: only bind tcs4525 to correct chip id The tcs4525 regulator has a chip id of <12>. Only allow the driver to bind to the correct chip id for safety, in accordance with the other supported devices. Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20210511211335.2935163-3-pgwipeout@gmail.com Signed-off-by: Mark Brown (cherry picked from commit f9028dcdf589f4ab528372088623aa4e8d324df2) Signed-off-by: Elaine Zhang Change-Id: I68b8935e9e9d76620c54d132e7cb6921d817582e --- drivers/regulator/fan53555.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index 8d7b916f5d76..3b4af30eb941 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -89,6 +89,10 @@ enum { FAN53555_CHIP_ID_08 = 8, }; +enum { + TCS4525_CHIP_ID_12 = 12, +}; + /* IC mask revision */ enum { FAN53555_CHIP_REV_00 = 0x3, @@ -374,14 +378,21 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) { - di->slew_reg = TCS4525_TIME; - di->slew_mask = TCS_SLEW_MASK; - di->slew_shift = TCS_SLEW_MASK; + switch (di->chip_id) { + case TCS4525_CHIP_ID_12: + di->slew_reg = TCS4525_TIME; + di->slew_mask = TCS_SLEW_MASK; + di->slew_shift = TCS_SLEW_MASK; - /* Init voltage range and step */ - di->vsel_min = 600000; - di->vsel_step = 6250; - di->vsel_count = FAN53526_NVOLTAGES; + /* Init voltage range and step */ + di->vsel_min = 600000; + di->vsel_step = 6250; + di->vsel_count = FAN53526_NVOLTAGES; + break; + default: + dev_err(di->dev, "Chip ID %d not supported!\n", di->chip_id); + return -EINVAL; + } return 0; } From c998ab0bed08674cd8489e0019f0732a15d9f447 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Tue, 11 May 2021 17:13:35 -0400 Subject: [PATCH 183/258] UPSTREAM: regulator: fan53555: fix tcs4525 function names The tcs4525 is based off the fan53526. Rename the tcs4525 functions to align with this. Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20210511211335.2935163-4-pgwipeout@gmail.com Signed-off-by: Mark Brown (cherry picked from commit b3cc8ec04f50d9c860534fe4e3617a8d10ed9ea9) Signed-off-by: Elaine Zhang Change-Id: I553a8f6b28386d78edb9db36f72c0f4b93bc2b76 --- drivers/regulator/fan53555.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index 3b4af30eb941..cb55549687cb 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -67,7 +67,7 @@ enum fan53555_vendor { FAN53526_VENDOR_FAIRCHILD = 0, FAN53555_VENDOR_FAIRCHILD, FAN53555_VENDOR_SILERGY, - FAN53555_VENDOR_TCS, + FAN53526_VENDOR_TCS, }; enum { @@ -239,7 +239,7 @@ static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) slew_rate_t = slew_rates; slew_rate_n = ARRAY_SIZE(slew_rates); break; - case FAN53555_VENDOR_TCS: + case FAN53526_VENDOR_TCS: slew_rate_t = tcs_slew_rates; slew_rate_n = ARRAY_SIZE(tcs_slew_rates); break; @@ -376,7 +376,7 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) return 0; } -static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) +static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) { switch (di->chip_id) { case TCS4525_CHIP_ID_12: @@ -426,7 +426,7 @@ static int fan53555_device_setup(struct fan53555_device_info *di, return -EINVAL; } break; - case FAN53555_VENDOR_TCS: + case FAN53526_VENDOR_TCS: switch (pdata->sleep_vsel_id) { case FAN53555_VSEL_ID_0: di->sleep_reg = TCS4525_VSEL0; @@ -465,7 +465,7 @@ static int fan53555_device_setup(struct fan53555_device_info *di, di->mode_reg = di->vol_reg; di->mode_mask = VSEL_MODE; break; - case FAN53555_VENDOR_TCS: + case FAN53526_VENDOR_TCS: di->mode_reg = TCS4525_COMMAND; switch (pdata->sleep_vsel_id) { @@ -493,8 +493,8 @@ static int fan53555_device_setup(struct fan53555_device_info *di, case FAN53555_VENDOR_SILERGY: ret = fan53555_voltages_setup_silergy(di); break; - case FAN53555_VENDOR_TCS: - ret = fan53555_voltages_setup_tcs(di); + case FAN53526_VENDOR_TCS: + ret = fan53526_voltages_setup_tcs(di); break; default: dev_err(di->dev, "vendor %d not supported!\n", di->vendor); @@ -569,7 +569,7 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { .data = (void *)FAN53555_VENDOR_SILERGY, }, { .compatible = "tcs,tcs4525", - .data = (void *)FAN53555_VENDOR_TCS + .data = (void *)FAN53526_VENDOR_TCS }, { } }; @@ -679,7 +679,7 @@ static const struct i2c_device_id fan53555_id[] = { .driver_data = FAN53555_VENDOR_SILERGY }, { .name = "tcs4525", - .driver_data = FAN53555_VENDOR_TCS + .driver_data = FAN53526_VENDOR_TCS }, { }, }; From 92d2f71eee9cbcd5c1b0a18ed1036be0b7c9d42a Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Mon, 17 May 2021 09:03:17 +0800 Subject: [PATCH 184/258] UPSTREAM: regulator: fan53555: Fix slew_shift setting for tcs4525 Fix trivial copy-paste mistake. Signed-off-by: Axel Lin Link: https://lore.kernel.org/r/20210517010318.1027949-1-axel.lin@ingics.com Signed-off-by: Mark Brown (cherry picked from commit a7f003147b785d9780ceeac13a8e344927a3b9ea) Signed-off-by: Elaine Zhang Change-Id: I380536fe8ced404f045745301b538806d7b1f50d --- drivers/regulator/fan53555.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index cb55549687cb..3089e1743bce 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -382,7 +382,7 @@ static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) case TCS4525_CHIP_ID_12: di->slew_reg = TCS4525_TIME; di->slew_mask = TCS_SLEW_MASK; - di->slew_shift = TCS_SLEW_MASK; + di->slew_shift = TCS_SLEW_SHIFT; /* Init voltage range and step */ di->vsel_min = 600000; From 046932a8e0fe87b14d84e0289a015475f31eec6c Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Mon, 17 May 2021 09:03:18 +0800 Subject: [PATCH 185/258] UPSTREAM: regulator: fan53555: Cleanup unused define and redundant assignment TCS_VSEL_NSEL_MASK is not used so remove it. Also remove redundant assignment for di->slew_reg. Signed-off-by: Axel Lin Link: https://lore.kernel.org/r/20210517010318.1027949-2-axel.lin@ingics.com Signed-off-by: Mark Brown (cherry picked from commit 79c7e1447c1c998e2571191e3cad12f9285ee22e) Signed-off-by: Elaine Zhang Change-Id: I9e2d2ec3113e8706053c49f2fe42e14e89d22eaa --- drivers/regulator/fan53555.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index 3089e1743bce..8e43778ccc48 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -56,7 +56,6 @@ #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ #define FAN53526_NVOLTAGES 128 -#define TCS_VSEL_NSEL_MASK 0x7f #define TCS_VSEL0_MODE (1 << 7) #define TCS_VSEL1_MODE (1 << 6) @@ -368,7 +367,6 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) return -EINVAL; } di->slew_reg = FAN53555_CONTROL; - di->slew_reg = FAN53555_CONTROL; di->slew_mask = CTL_SLEW_MASK; di->slew_shift = CTL_SLEW_SHIFT; di->vsel_count = FAN53555_NVOLTAGES; From a0ccf3aabc44891acffd46a681cfb19d74f9333a Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Tue, 25 May 2021 20:40:16 +0800 Subject: [PATCH 186/258] UPSTREAM: regulator: fan53555: Fix missing slew_reg/mask/shift settings for FAN53526 The di->slew_reg/di->slew_mask/di->slew_shift was not set in current code, fix it. Fixes: f2a9eb975ab2 ("regulator: fan53555: Add support for FAN53526") Signed-off-by: Axel Lin Link: https://lore.kernel.org/r/20210525124017.2550029-1-axel.lin@ingics.com Signed-off-by: Mark Brown (cherry picked from commit 30b38b805b36c03db3703ef62397111c783b5f3b) Signed-off-by: Elaine Zhang Change-Id: I45888035e0c7591d986803737f983185dee31964 --- drivers/regulator/fan53555.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index 8e43778ccc48..30fc79325b23 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -302,6 +302,9 @@ static int fan53526_voltages_setup_fairchild(struct fan53555_device_info *di) return -EINVAL; } + di->slew_reg = FAN53555_CONTROL; + di->slew_mask = CTL_SLEW_MASK; + di->slew_shift = CTL_SLEW_SHIFT; di->vsel_count = FAN53526_NVOLTAGES; return 0; From c1700419cdaa959e3a1c985a13caae7898f263b6 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Wed, 2 Jun 2021 11:29:47 +0000 Subject: [PATCH 187/258] UPSTREAM: regulator: fan53555: add tcs4526 For rk3399pro boards the tcs4526 regulator supports the vdd_gpu regulator. The tcs4526 regulator has a chip id of <0>. Add the compatibile tcs,tcs4526 without this patch, the dmesg output is: fan53555-regulator 0-0010: Chip ID 0 not supported! fan53555-regulator 0-0010: Failed to setup device! fan53555-regulator: probe of 0-0010 failed with error -22 with this patch, the dmesg output is: vdd_gpu: supplied by vcc5v0_sys The regulators are described as: - Dedicated power management IC TCS4525 - Lithium battery protection chip TCS4526 This has been tested with a Radxa Rock Pi N10. Signed-off-by: Rudi Heitbaum Link: https://lore.kernel.org/r/20210602112943.GA119@5f9be87369f8 Signed-off-by: Mark Brown (cherry picked from commit 5eee5eced95f1b35c8567688ed52932b7e58deee) Signed-off-by: Elaine Zhang Change-Id: I9f4d649df82e6b052d74c890abef08dd08eb985e --- drivers/regulator/fan53555.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index 30fc79325b23..e00dd5ae52b8 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -92,6 +92,10 @@ enum { TCS4525_CHIP_ID_12 = 12, }; +enum { + TCS4526_CHIP_ID_00 = 0, +}; + /* IC mask revision */ enum { FAN53555_CHIP_REV_00 = 0x3, @@ -381,6 +385,7 @@ static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) { switch (di->chip_id) { case TCS4525_CHIP_ID_12: + case TCS4526_CHIP_ID_00: di->slew_reg = TCS4525_TIME; di->slew_mask = TCS_SLEW_MASK; di->slew_shift = TCS_SLEW_SHIFT; @@ -571,6 +576,9 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { }, { .compatible = "tcs,tcs4525", .data = (void *)FAN53526_VENDOR_TCS + }, { + .compatible = "tcs,tcs4526", + .data = (void *)FAN53526_VENDOR_TCS }, { } }; @@ -681,6 +689,9 @@ static const struct i2c_device_id fan53555_id[] = { }, { .name = "tcs4525", .driver_data = FAN53526_VENDOR_TCS + }, { + .name = "tcs4526", + .driver_data = FAN53526_VENDOR_TCS }, { }, }; From 50497409761daa7041f7502ed5f49d3fc56b80af Mon Sep 17 00:00:00 2001 From: shengfei Xu Date: Mon, 11 Jan 2021 10:10:08 +0000 Subject: [PATCH 188/258] regulator: fan53555: support reboot Fixes: 91c0d689ea8a ("Revert "regulator: fan53555: support reboot"") Signed-off-by: shengfei Xu Signed-off-by: Elaine Zhang Change-Id: I143fc44f49c95f01248c72a8f48282bf984b826b --- drivers/regulator/fan53555.c | 42 +++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index e00dd5ae52b8..9ed748d603f6 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -29,6 +29,7 @@ #define TCS4525_VSEL1 0x10 #define TCS4525_TIME 0x13 #define TCS4525_COMMAND 0x14 +#define TCS4525_LIMCONF 0x16 /* Control register */ #define FAN53555_CONTROL 0x02 @@ -109,6 +110,7 @@ enum { struct fan53555_device_info { enum fan53555_vendor vendor; + struct regmap *regmap; struct device *dev; struct regulator_desc desc; struct regulator_init_data *regulator; @@ -635,6 +637,7 @@ static int fan53555_regulator_probe(struct i2c_client *client, dev_err(&client->dev, "Failed to allocate regmap!\n"); return PTR_ERR(regmap); } + di->regmap = regmap; di->dev = &client->dev; i2c_set_clientdata(client, di); /* Get chip ID */ @@ -669,8 +672,44 @@ static int fan53555_regulator_probe(struct i2c_client *client, ret = fan53555_regulator_register(di, &config); if (ret < 0) dev_err(&client->dev, "Failed to register regulator!\n"); - return ret; + return ret; +} + +static void fan53555_regulator_shutdown(struct i2c_client *client) +{ + struct fan53555_device_info *di; + int ret; + + di = i2c_get_clientdata(client); + + dev_info(di->dev, "fan53555..... reset\n"); + + switch (di->vendor) { + case FAN53555_VENDOR_FAIRCHILD: + case FAN53555_VENDOR_SILERGY: + ret = regmap_update_bits(di->regmap, di->slew_reg, + CTL_RESET, CTL_RESET); + break; + case FAN53526_VENDOR_TCS: + ret = regmap_update_bits(di->regmap, TCS4525_LIMCONF, + CTL_RESET, CTL_RESET); + /* + * the device can't return 'ack' during the reset, + * it will return -ENXIO, ignore this error. + */ + if (ret == -ENXIO) + ret = 0; + break; + default: + ret = -EINVAL; + break; + } + + if (ret < 0) + dev_err(di->dev, "reset: force fan53555_reset error! ret=%d\n", ret); + else + dev_info(di->dev, "reset: force fan53555_reset ok!\n"); } static const struct i2c_device_id fan53555_id[] = { @@ -703,6 +742,7 @@ static struct i2c_driver fan53555_regulator_driver = { .of_match_table = of_match_ptr(fan53555_dt_ids), }, .probe = fan53555_regulator_probe, + .shutdown = fan53555_regulator_shutdown, .id_table = fan53555_id, }; From b19cb16194baa058c113d34df5384855d8dd9f51 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Mon, 30 Jan 2023 09:51:50 +0000 Subject: [PATCH 189/258] arm64: dts: rockchip: Update tcs425x to tcs4525 or tcs4526 Signed-off-by: Joseph Chen Change-Id: Ieb3e514877099f1073475cd24b6319ba7db8543d --- arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3368-tablet.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3368a-817-tablet-bnd.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi | 8 ++++---- .../boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts | 8 ++++---- arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts | 8 ++++---- arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts | 8 ++++---- arch/arm64/boot/dts/rockchip/rk3399pro-npu-evb-v10.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts | 2 +- .../arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-v10.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi | 2 +- 17 files changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi index d17dc23898ff..bb57ae176c92 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi @@ -256,7 +256,7 @@ clock-frequency = <400000>; vdd_npu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-tablet.dts b/arch/arm64/boot/dts/rockchip/rk3368-tablet.dts index d7dc6d67e242..1674731ebc13 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-tablet.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-tablet.dts @@ -383,8 +383,8 @@ &i2c0 { status = "okay"; - vdd_cpu: tcs4525@10 { - compatible = "tcs,tcs452x"; + vdd_cpu: tcs4526@10 { + compatible = "tcs,tcs4526"; reg = <0x10>; regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel_gpio>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368a-817-tablet-bnd.dts b/arch/arm64/boot/dts/rockchip/rk3368a-817-tablet-bnd.dts index 0a489bf8fc84..eeaf205e577a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368a-817-tablet-bnd.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368a-817-tablet-bnd.dts @@ -339,8 +339,8 @@ &i2c0 { status = "okay"; - vdd_cpu: tcs4525@10 { - compatible = "tcs,tcs452x"; + vdd_cpu: tcs4526@10 { + compatible = "tcs,tcs4526"; reg = <0x10>; regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel_gpio>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi index 78c2d2f87e5d..5e77d8156dfa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi @@ -444,8 +444,8 @@ i2c-scl-falling-time-ns = <4>; clock-frequency = <400000>; - vdd_cpu_b: tcs452x@1c { - compatible = "tcs,tcs452x"; + vdd_cpu_b: tcs4525@1c { + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; @@ -464,8 +464,8 @@ }; }; - vdd_gpu: tcs452x@10 { - compatible = "tcs,tcs452x"; + vdd_gpu: tcs4526@10 { + compatible = "tcs,tcs4526"; reg = <0x10>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts index e0a75ed92439..4800dbfd298d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts @@ -713,8 +713,8 @@ }; }; - vdd_cpu_b: tcs452x@1c { - compatible = "tcs,tcs452x"; + vdd_cpu_b: tcs4525@1c { + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; @@ -733,8 +733,8 @@ }; }; - vdd_gpu: tcs452x@10 { - compatible = "tcs,tcs452x"; + vdd_gpu: tcs4526@10 { + compatible = "tcs,tcs4526"; reg = <0x10>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts index 84fc2c743c57..1b0f4ffbc2f8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts @@ -634,8 +634,8 @@ }; }; - vdd_cpu_b: tcs452x@1c { - compatible = "tcs,tcs452x"; + vdd_cpu_b: tcs4525@1c { + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; @@ -654,8 +654,8 @@ }; }; - vdd_gpu: tcs452x@10 { - compatible = "tcs,tcs452x"; + vdd_gpu: tcs4526@10 { + compatible = "tcs,tcs4526"; reg = <0x10>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts index 6fea49960e39..2b14880203ea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts @@ -628,8 +628,8 @@ }; }; - vdd_cpu_b: tcs452x@1c { - compatible = "tcs,tcs452x"; + vdd_cpu_b: tcs4525@1c { + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; @@ -648,8 +648,8 @@ }; }; - vdd_gpu: tcs452x@10 { - compatible = "tcs,tcs452x"; + vdd_gpu: tcs4526@10 { + compatible = "tcs,tcs4526"; reg = <0x10>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-npu-evb-v10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-npu-evb-v10.dts index 96a3fb56cfe5..a7ce00ceb177 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-npu-evb-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-npu-evb-v10.dts @@ -72,8 +72,8 @@ &i2c1 { status = "okay"; - vdd_npu: tcs452x@1c { - compatible = "tcs,tcs452x"; + vdd_npu: tcs4525@1c { + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts index 3f559fca27f8..f1eb6ad62908 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts @@ -366,7 +366,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vccsys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts index 2e6d3160aa16..ab8e87e16c2e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts @@ -265,7 +265,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vccsys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts index d491ba8ee87d..39543fd013a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts @@ -229,7 +229,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vccsys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts index 4dcace8cf857..179641a3d322 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts @@ -558,7 +558,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vccsys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts index dc4d251c085c..c414eec30e25 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts @@ -376,7 +376,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vccsys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-v10.dts index 5b24f068019d..9cdae500f0ac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-v10.dts @@ -482,7 +482,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vccsys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts index 4ecb8bfdf8ec..10efbdb40715 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts @@ -487,7 +487,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vccsys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi index 1116dc0064d8..e0762fae0a17 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi @@ -1088,7 +1088,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi index fc66fdbe137f..400dc44e6bbe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi @@ -258,7 +258,7 @@ status = "okay"; vdd_cpu: tcs4525@1c { - compatible = "tcs,tcs452x"; + compatible = "tcs,tcs4525"; reg = <0x1c>; vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; From 78cef6d34315f2b29d3895769bf430b5ac921a41 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 7 Feb 2023 17:05:22 +0800 Subject: [PATCH 190/258] regulator: fan53555: add tcs452x Signed-off-by: Elaine Zhang Change-Id: I7d9f02f637108e941e526e21bd0e24d6f99cd328 --- drivers/regulator/fan53555.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index 9ed748d603f6..eca3e3aa6b08 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -581,6 +581,9 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { }, { .compatible = "tcs,tcs4526", .data = (void *)FAN53526_VENDOR_TCS + }, { + .compatible = "tcs,tcs452x", + .data = (void *)FAN53526_VENDOR_TCS }, { } }; @@ -731,6 +734,9 @@ static const struct i2c_device_id fan53555_id[] = { }, { .name = "tcs4526", .driver_data = FAN53526_VENDOR_TCS + }, { + .name = "tcs452x", + .driver_data = FAN53526_VENDOR_TCS }, { }, }; From c44ab0fa47b0200f24d336c040dd5713de6c6fbd Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 14 Feb 2023 17:24:57 +0800 Subject: [PATCH 191/258] soc: rockchip: opp_select: adjust opp-table by otp Signed-off-by: Liang Chen Change-Id: I8d642bbcb4dafcfa62d85cf108623e92f6fd4572 --- drivers/soc/rockchip/rockchip_opp_select.c | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c index 8a785e6b64c0..3a6cfe60a49e 100644 --- a/drivers/soc/rockchip/rockchip_opp_select.c +++ b/drivers/soc/rockchip/rockchip_opp_select.c @@ -66,6 +66,13 @@ struct lkg_conversion_table { int conv; }; +struct otp_opp_info { + u16 min_freq; + u16 max_freq; + u8 volt; + u8 length; +} __packed; + #define PVTM_CH_MAX 8 #define PVTM_SUB_CH_MAX 8 @@ -1443,6 +1450,44 @@ static void rockchip_adjust_opp_by_mbist_vmin(struct device *dev, mutex_unlock(&opp_table->lock); } +static void rockchip_adjust_opp_by_otp(struct device *dev, + struct device_node *np) +{ + struct dev_pm_opp *opp; + struct opp_table *opp_table; + struct otp_opp_info opp_info = {}; + int ret; + + ret = rockchip_nvmem_cell_read_common(np, "opp-info", &opp_info, + sizeof(opp_info)); + if (ret || !opp_info.volt) + return; + + dev_info(dev, "adjust opp-table by otp: min=%uM, max=%uM, volt=%umV\n", + opp_info.min_freq, opp_info.max_freq, opp_info.volt); + + opp_table = dev_pm_opp_get_opp_table(dev); + if (!opp_table) + return; + + mutex_lock(&opp_table->lock); + list_for_each_entry(opp, &opp_table->opp_list, node) { + if (!opp->available) + continue; + if (opp->rate < opp_info.min_freq * 1000000) + continue; + if (opp->rate > opp_info.max_freq * 1000000) + continue; + + opp->supplies->u_volt += opp_info.volt * 1000; + if (opp->supplies->u_volt > opp->supplies->u_volt_max) + opp->supplies->u_volt = opp->supplies->u_volt_max; + } + mutex_unlock(&opp_table->lock); + + dev_pm_opp_put_opp_table(opp_table); +} + static int rockchip_adjust_opp_table(struct device *dev, unsigned long scale_rate) { @@ -1489,6 +1534,7 @@ int rockchip_adjust_power_scale(struct device *dev, int scale) of_property_read_u32(np, "rockchip,avs-enable", &avs); of_property_read_u32(np, "rockchip,avs", &avs); of_property_read_u32(np, "rockchip,avs-scale", &avs_scale); + rockchip_adjust_opp_by_otp(dev, np); rockchip_adjust_opp_by_mbist_vmin(dev, np); rockchip_adjust_opp_by_irdrop(dev, np, &safe_rate, &max_rate); From 1c4ec7310bebc45494f49fefd5492a3cd8bc8d62 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 14 Feb 2023 17:25:50 +0800 Subject: [PATCH 192/258] arm64: dts: rockchip: rk3528: set otp-opp-info for cpu/gpu/dmc Signed-off-by: Liang Chen Change-Id: Ie0bcaf096c423a942e91a057b98cefda5111a971 --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index b947fe4f2cf4..fa52ff71455e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -144,8 +144,8 @@ compatible = "operating-points-v2"; opp-shared; - nvmem-cells = <&cpu_leakage>; - nvmem-cell-names = "leakage"; + nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>; + nvmem-cell-names = "leakage", "opp-info"; rockchip,video-4k-freq = <1200000>; rockchip,pvtm-voltage-sel = < @@ -882,8 +882,8 @@ gpu_opp_table: gpu-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&gpu_leakage>; - nvmem-cell-names = "leakage"; + nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>; + nvmem-cell-names = "leakage", "opp-info"; rockchip,pvtm-voltage-sel = < 0 820 0 @@ -2039,6 +2039,15 @@ macphy_txlevel: macphy-txlevel@2e { reg = <0x2e 0x2>; }; + cpu_opp_info: cpu-opp-info@32 { + reg = <0x32 0x6>; + }; + gpu_opp_info: gpu-opp-info@38 { + reg = <0x38 0x6>; + }; + dmc_opp_info: dmc-opp-info@3e { + reg = <0x3e 0x6>; + }; }; dmac: dma-controller@ffd60000 { From e5be89a49c2e0e290d0e52b9105bd58752d004a5 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Wed, 15 Feb 2023 18:00:22 +0800 Subject: [PATCH 193/258] pwm: rockchip: release clk if pinctrl check failed Fixes: 718c02ce1848 ("pwm: rockchip: Make pwm pinctrl setting after pwm enabled") Signed-off-by: Damon Ding Change-Id: Ic67407ee416a24ba368c3cff21aefde0ddf63700 --- drivers/pwm/pwm-rockchip.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 460a65452008..67bab5c7f484 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -395,13 +395,15 @@ static int rockchip_pwm_probe(struct platform_device *pdev) pc->pinctrl = devm_pinctrl_get(&pdev->dev); if (IS_ERR(pc->pinctrl)) { dev_err(&pdev->dev, "Get pinctrl failed!\n"); - return PTR_ERR(pc->pinctrl); + ret = PTR_ERR(pc->pinctrl); + goto err_pclk; } pc->active_state = pinctrl_lookup_state(pc->pinctrl, "active"); if (IS_ERR(pc->active_state)) { dev_err(&pdev->dev, "No active pinctrl state\n"); - return PTR_ERR(pc->active_state); + ret = PTR_ERR(pc->active_state); + goto err_pclk; } platform_set_drvdata(pdev, pc); From a607f6bfd4d48e464db54728b27469eb857cf475 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 15 Feb 2023 19:49:52 +0800 Subject: [PATCH 194/258] net: phy: rk630phy: Fix typo drivers/net/phy/rk630phy.c:388:27: error: use of undeclared identifier 'rockchip_phy_tbl'; MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl); Fixes: f5f864ab5186 ("driver: rk630: Add RK630 MAC PHY support") Signed-off-by: Tao Huang Change-Id: I22a5805014cde850e77f493c4f56833a3d96bde5 --- drivers/net/phy/rk630phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/rk630phy.c b/drivers/net/phy/rk630phy.c index 260f79e9bf3e..3579397410b9 100644 --- a/drivers/net/phy/rk630phy.c +++ b/drivers/net/phy/rk630phy.c @@ -385,7 +385,7 @@ static struct mdio_device_id __maybe_unused rk630_phy_tbl[] = { { } }; -MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl); +MODULE_DEVICE_TABLE(mdio, rk630_phy_tbl); module_phy_driver(rk630_phy_driver); From 571548a6569ee806f4e6438c2392e035f6b95c50 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 15 Feb 2023 19:55:03 +0800 Subject: [PATCH 195/258] input: touchscreen: gsl3673_800x1280: Fix build as module drivers/input/touchscreen/gsl3673_800x1280.c:68:11: fatal error: 'gsl3680b_zm97f.h' file not found Signed-off-by: Tao Huang Change-Id: I4754dafc101df625c557a777829e32b42f9d768c --- drivers/input/touchscreen/gsl3673_800x1280.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/touchscreen/gsl3673_800x1280.c b/drivers/input/touchscreen/gsl3673_800x1280.c index a279b26e5f7d..da97d928d3b0 100644 --- a/drivers/input/touchscreen/gsl3673_800x1280.c +++ b/drivers/input/touchscreen/gsl3673_800x1280.c @@ -60,7 +60,7 @@ static char chip_type; #include "gsl3680_tab106.h" #define TP_SIZE_1366X768 #define Y_POL -#elif defined(CONFIG_TOUCHSCREEN_GSL3673_800X1280) +#elif IS_ENABLED(CONFIG_TOUCHSCREEN_GSL3673_800X1280) #define TP_SIZE_800X1280 #include "rochkchip_gslX680_8inch_800x1280_tg806_10.h" // #include "gsl3673_800x1280.h" From 3d20aac6460619de8534b55f207fc2b7a34a171a Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Thu, 9 Feb 2023 09:53:19 +0000 Subject: [PATCH 196/258] arm64: dts: rockchip: rk3562-rk817-tablet-v10: enable display logo Change-Id: I5df32ea65901ded3ebc7ae6ba9082a4be01de0f7 Signed-off-by: Guochun Huang --- arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts index 22cc6295ae55..1ad9c6be3551 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts @@ -962,6 +962,10 @@ status = "okay"; }; +&route_dsi { + status = "okay"; +}; + &saradc0 { status = "okay"; vref-supply = <&vcc_1v8>; From 4a7b2952e88f34b2c1a9a8be862ff061f64d5635 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Thu, 16 Feb 2023 09:15:48 +0800 Subject: [PATCH 197/258] drm/rockchip: vop2: remove duplicate init of nr_pds Fixes: aa3aee14d0ec("drm/rockchip: vop2: Add vop2 internal pd support for rk3588") Signed-off-by: Andy Yan Change-Id: I7899bf5ab4ae3b4465e3f352133daef0e2e47e82 --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 5e7f3bc64e85..ff7659280df4 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -3814,7 +3814,6 @@ static const struct vop2_data rk3588_vop = { .nr_mixers = 7, .nr_layers = 8, .nr_gammas = 4, - .nr_pds = 7, .max_input = { 4096, 4320 }, .max_output = { 4096, 4320 }, .ctrl = &rk3588_vop_ctrl, From 146f0f25ff882af6c868440279a31590ed0340ee Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Fri, 3 Feb 2023 19:30:38 +0800 Subject: [PATCH 198/258] iommu/rockchip: Do not disable vop_mmu runtime PM when shutdown iommu maybe enable failed at the following case: rk_iommu_shutdown() -> disable runtime PM --> rockchip_drm_lastclose() --> vop2_crtc_atomic_flush() --> rockchip_drm_dma_attach_device() --> rk_iommu_attach_device() --> rk_iommu_detach_device() --> pm_runtime_get_if_in_use() check failed but drm is unknown, Do not disable vop_mmu runtime PM as a workaround Signed-off-by: Sandy Huang Signed-off-by: Simon Xue Change-Id: Ic4102371534bbc3ece344401301a437711d69226 --- drivers/iommu/rockchip-iommu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index cf4f03f33421..79def9a85535 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -1968,7 +1968,8 @@ static void rk_iommu_shutdown(struct platform_device *pdev) } skip_free_irq: - pm_runtime_force_suspend(&pdev->dev); + if (!iommu->dlr_disable) + pm_runtime_force_suspend(&pdev->dev); } static int __maybe_unused rk_iommu_suspend(struct device *dev) From 150af0ebb0d9dc900f20b984ca9dffee87410207 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 15 Feb 2023 16:31:23 +0800 Subject: [PATCH 199/258] ASoC: rk312x: Fix wrong component assignment Should use dai->component instead of the fixed rtd->codec[0], because codec may be addressed in multi-codecs situation, Obviously, it's wrong. the dais' one is always RIGHT. Signed-off-by: Sugar Zhang Change-Id: I4d95b82e36a929e46f4992cbb198b6a060c5c939 --- sound/soc/codecs/rk312x_codec.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sound/soc/codecs/rk312x_codec.c b/sound/soc/codecs/rk312x_codec.c index 0e3ac4008962..aba53c198407 100644 --- a/sound/soc/codecs/rk312x_codec.c +++ b/sound/soc/codecs/rk312x_codec.c @@ -1424,8 +1424,7 @@ static int rk312x_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; + struct snd_soc_component *component = dai->component; struct rk312x_codec_priv *rk312x = rk312x_priv; unsigned int rate = params_rate(params); unsigned int div; From 53c5baa3cde9390b7bfd9fff6aa554f4e9c06e1c Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 15 Feb 2023 16:37:21 +0800 Subject: [PATCH 200/258] ASoC: rk817: Fix wrong component assignment Should use dai->component instead of the fixed rtd->codec[0], because codec may be addressed in multi-codecs situation, Obviously, it's wrong. the dais' one is always RIGHT. Signed-off-by: Sugar Zhang Change-Id: I97cd09aa0886e2b89f2c2f257defb228168e93b0 --- sound/soc/codecs/rk817_codec.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c index 358ec3787bf7..bbd561d1dbe6 100644 --- a/sound/soc/codecs/rk817_codec.c +++ b/sound/soc/codecs/rk817_codec.c @@ -892,8 +892,7 @@ static int rk817_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; + struct snd_soc_component *component = dai->component; struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); unsigned int rate = params_rate(params); unsigned char apll_cfg3_val; From b7494b0ea95321995941f9f3d9dba53e7d49eb05 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Sat, 26 Nov 2022 14:13:37 +0800 Subject: [PATCH 201/258] ASoc: rockchip: multicodecs: Set sysclk for all sub codecs Signed-off-by: Sugar Zhang Change-Id: I86c47651bb456a066c80d688afddd078ffe0389e --- sound/soc/rockchip/rockchip_multicodecs.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/sound/soc/rockchip/rockchip_multicodecs.c b/sound/soc/rockchip/rockchip_multicodecs.c index 4529c3cb5b39..d136ff3ffe59 100644 --- a/sound/soc/rockchip/rockchip_multicodecs.c +++ b/sound/soc/rockchip/rockchip_multicodecs.c @@ -338,18 +338,20 @@ static int rk_multicodecs_hw_params(struct snd_pcm_substream *substream, { struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); - struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); + struct snd_soc_dai *codec_dai; struct multicodecs_data *mc_data = snd_soc_card_get_drvdata(rtd->card); unsigned int mclk; - int ret; + int ret, i; mclk = params_rate(params) * mc_data->mclk_fs; - ret = snd_soc_dai_set_sysclk(codec_dai, substream->stream, mclk, - SND_SOC_CLOCK_IN); - if (ret && ret != -ENOTSUPP) { - pr_err("Set codec_dai sysclk failed: %d\n", ret); - goto out; + for_each_rtd_codec_dais(rtd, i, codec_dai) { + ret = snd_soc_dai_set_sysclk(codec_dai, substream->stream, mclk, + SND_SOC_CLOCK_IN); + if (ret && ret != -ENOTSUPP) { + pr_err("Set codec_dai sysclk failed: %d\n", ret); + goto out; + } } ret = snd_soc_dai_set_sysclk(cpu_dai, substream->stream, mclk, From 1b6481bb651bc28784443071b9e3dce47ed0d06b Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 15 Feb 2023 17:33:44 +0800 Subject: [PATCH 202/258] ASoC: rockchip: multicodecs: Fix the jack assignment Set jack for the first successful one to fix the disorder codec assignment. And of course, we suggest user to place the one which use the jack in the first place in Device Tree. Signed-off-by: Sugar Zhang Change-Id: I8dc5d95ba73c053a599d95c0448042fd04765c05 --- sound/soc/rockchip/rockchip_multicodecs.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/sound/soc/rockchip/rockchip_multicodecs.c b/sound/soc/rockchip/rockchip_multicodecs.c index d136ff3ffe59..7961b47913d5 100644 --- a/sound/soc/rockchip/rockchip_multicodecs.c +++ b/sound/soc/rockchip/rockchip_multicodecs.c @@ -432,9 +432,16 @@ static int rk_dailink_init(struct snd_soc_pcm_runtime *rtd) mc_data->jack_headset = jack_headset; if (mc_data->codec_hp_det) { - struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; + struct snd_soc_dai *codec_dai; + int i; - snd_soc_component_set_jack(component, jack_headset, NULL); + /* set jack for the first successful one */ + for_each_rtd_codec_dais(rtd, i, codec_dai) { + ret = snd_soc_component_set_jack(codec_dai->component, + jack_headset, NULL); + if (ret >= 0) + break; + } } else { irq = gpiod_to_irq(mc_data->hp_det_gpio); if (irq >= 0) { From 9a673d9b4888d0dc494425b3519f0a8690683e51 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 15 Feb 2023 17:50:33 +0800 Subject: [PATCH 203/258] ASoC: rockchip: i2s-tdm: Explicit info for Multi-DAI It's helpful for user to observe the DAI path by kmsg. Signed-off-by: Sugar Zhang Change-Id: I60baaf787551362994c2bcb58a1c2d7c21bd23d4 --- sound/soc/rockchip/rockchip_i2s_tdm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/sound/soc/rockchip/rockchip_i2s_tdm.c b/sound/soc/rockchip/rockchip_i2s_tdm.c index ea886a876fe4..83128bcf00f5 100644 --- a/sound/soc/rockchip/rockchip_i2s_tdm.c +++ b/sound/soc/rockchip/rockchip_i2s_tdm.c @@ -2271,8 +2271,10 @@ static int rockchip_i2s_tdm_probe(struct platform_device *pdev) goto err_suspend; } - if (of_property_read_bool(node, "rockchip,no-dmaengine")) - return ret; + if (of_property_read_bool(node, "rockchip,no-dmaengine")) { + dev_info(&pdev->dev, "Used for Multi-DAI\n"); + return 0; + } if (of_property_read_bool(node, "rockchip,digital-loopback")) ret = devm_snd_dmaengine_dlp_register(&pdev->dev, &dconfig); From 0648aa45ac5947ba06e81e504011f49c0df113fb Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 15 Feb 2023 17:55:22 +0800 Subject: [PATCH 204/258] ASoC: rockchip: i2s: Explicit info for Multi-DAI It's helpful for user to observe the DAI path by kmsg. Signed-off-by: Sugar Zhang Change-Id: Iebf69a9ecbca5fe6a98ca1512ea549c67f18cdff --- sound/soc/rockchip/rockchip_i2s.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index d29ab5c33468..0a7304807f30 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -785,8 +785,10 @@ static int rockchip_i2s_probe(struct platform_device *pdev) goto err_suspend; } - if (of_property_read_bool(node, "rockchip,no-dmaengine")) + if (of_property_read_bool(node, "rockchip,no-dmaengine")) { + dev_info(&pdev->dev, "Used for Multi-DAI\n"); return 0; + } ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); if (ret) { From 454734f2dce7986e7b3c06ebf073f26c7fe71119 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 15 Feb 2023 17:55:50 +0800 Subject: [PATCH 205/258] ASoC: rockchip: pdm: Explicit info for Multi-DAI It's helpful for user to observe the DAI path by kmsg. Signed-off-by: Sugar Zhang Change-Id: I4e4e0c784a70d19b2b3c05d7fa424022e79a94ba --- sound/soc/rockchip/rockchip_pdm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c index 5ec3fe8c1f33..5d54317ed685 100644 --- a/sound/soc/rockchip/rockchip_pdm.c +++ b/sound/soc/rockchip/rockchip_pdm.c @@ -969,8 +969,10 @@ static int rockchip_pdm_probe(struct platform_device *pdev) if (ret != 0 && ret != -ENOENT) goto err_suspend; - if (of_property_read_bool(node, "rockchip,no-dmaengine")) + if (of_property_read_bool(node, "rockchip,no-dmaengine")) { + dev_info(&pdev->dev, "Used for Multi-DAI\n"); return 0; + } ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); if (ret) { From ccf3f0670c3694ec1605d97a9fe32a91ca63113e Mon Sep 17 00:00:00 2001 From: Zhen Chen Date: Mon, 13 Feb 2023 10:08:48 +0800 Subject: [PATCH 206/258] MALI: bifrost: from ARM: Remove references to PageMovable() The original patch is attached in the mail of Zhigang.Yao@arm.com at 2023-02-08 09:00. Commit message in the original patch: { From d1245d8578ba6ae4fb1b0f70417a97ea6afa920d Mon Sep 17 00:00:00 2001 From: Raffaele Aquilone Date: Thu, 19 Jan 2023 15:26:12 +0000 Subject: [PATCH] GPUCORE-36657 Remove PageMovable() symbol The PageMovable() function has been removed from the DDK because it cannot be used in Android. The movable status of the page has been duplicated into the status variable of the page metadata, and it's kept up to date every time the movable property is set or cleared, except in those cases where it's not necessary to keep alive the information. The unit test that attempts to migrate a firmware page has been removed because now the driver has no way to detect that a page without metadata is not movable; the driver has to trust that the system doesn't try to isolate pages which are not movable. ... } Its base is not current g15. I applied it manually on DDK g15. Change-Id: I7e8a29f3ce79d991bc8b3a746690e9ef279e572a Signed-off-by: Zhen Chen --- .../gpu/arm/bifrost/mali_kbase_mem_migrate.c | 14 +++++++++++--- .../gpu/arm/bifrost/mali_kbase_mem_migrate.h | 17 +++++++++++++---- 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/arm/bifrost/mali_kbase_mem_migrate.c b/drivers/gpu/arm/bifrost/mali_kbase_mem_migrate.c index dfa70252bcf1..8526688b7b12 100644 --- a/drivers/gpu/arm/bifrost/mali_kbase_mem_migrate.c +++ b/drivers/gpu/arm/bifrost/mali_kbase_mem_migrate.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note /* * - * (C) COPYRIGHT 2022 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2022-2023 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -51,8 +51,10 @@ bool kbase_alloc_page_metadata(struct kbase_device *kbdev, struct page *p, dma_a spin_lock_init(&page_md->migrate_lock); lock_page(p); - if (kbdev->mem_migrate.mapping) + if (kbdev->mem_migrate.mapping) { __SetPageMovable(p, kbdev->mem_migrate.mapping); + page_md->status = PAGE_MOVABLE_SET(page_md->status); + } unlock_page(p); return true; @@ -81,6 +83,7 @@ static void kbase_free_pages_worker(struct work_struct *work) container_of(work, struct kbase_mem_migrate, free_pages_work); struct kbase_device *kbdev = container_of(mem_migrate, struct kbase_device, mem_migrate); struct page *p, *tmp; + struct kbase_page_metadata *page_md; LIST_HEAD(free_list); spin_lock(&mem_migrate->free_pages_lock); @@ -91,8 +94,11 @@ static void kbase_free_pages_worker(struct work_struct *work) list_del_init(&p->lru); lock_page(p); - if (PageMovable(p)) + page_md = kbase_page_private(p); + if (IS_PAGE_MOVABLE(page_md->status)) { __ClearPageMovable(p); + page_md->status = PAGE_MOVABLE_CLEAR(page_md->status); + } unlock_page(p); kbase_free_page_metadata(kbdev, p); @@ -246,6 +252,7 @@ static int kbase_page_migrate(struct address_space *mapping, struct page *new_pa kbase_free_page_metadata(kbdev, old_page); __ClearPageMovable(old_page); + page_md->status = PAGE_MOVABLE_CLEAR(page_md->status); /* Just free new page to avoid lock contention. */ INIT_LIST_HEAD(&new_page->lru); @@ -302,6 +309,7 @@ static void kbase_page_putback(struct page *p) struct kbase_mem_migrate *mem_migrate = &kbdev->mem_migrate; __ClearPageMovable(p); + page_md->status = PAGE_MOVABLE_CLEAR(page_md->status); list_del_init(&p->lru); kbase_free_page_later(kbdev, p); queue_work(mem_migrate->free_pages_workq, &mem_migrate->free_pages_work); diff --git a/drivers/gpu/arm/bifrost/mali_kbase_mem_migrate.h b/drivers/gpu/arm/bifrost/mali_kbase_mem_migrate.h index 6610c0ccc40c..d4796327b8d7 100644 --- a/drivers/gpu/arm/bifrost/mali_kbase_mem_migrate.h +++ b/drivers/gpu/arm/bifrost/mali_kbase_mem_migrate.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * - * (C) COPYRIGHT 2022 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2022-2023 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -23,13 +23,22 @@ * DOC: Base kernel page migration implementation. */ -#define PAGE_STATUS_MASK ((u8)0x7F) +#define PAGE_STATUS_MASK ((u8)0x3F) #define PAGE_STATUS_GET(status) (status & PAGE_STATUS_MASK) #define PAGE_STATUS_SET(status, value) ((status & ~PAGE_STATUS_MASK) | (value & PAGE_STATUS_MASK)) + #define PAGE_ISOLATE_SHIFT (7) +#define PAGE_ISOLATE_MASK ((u8)1 << PAGE_ISOLATE_SHIFT) #define PAGE_ISOLATE_SET(status, value) \ - ((status & PAGE_STATUS_MASK) | (value << PAGE_ISOLATE_SHIFT)) -#define IS_PAGE_ISOLATED(status) ((bool)(status & ~PAGE_STATUS_MASK)) + ((status & ~PAGE_ISOLATE_MASK) | (value << PAGE_ISOLATE_SHIFT)) +#define IS_PAGE_ISOLATED(status) ((bool)(status & PAGE_ISOLATE_MASK)) + +#define PAGE_MOVABLE_SHIFT (6) +#define PAGE_MOVABLE_MASK ((u8)1 << PAGE_MOVABLE_SHIFT) +#define PAGE_MOVABLE_CLEAR(status) ((status) & ~PAGE_MOVABLE_MASK) +#define PAGE_MOVABLE_SET(status) (status | PAGE_MOVABLE_MASK) + +#define IS_PAGE_MOVABLE(status) ((bool)(status & PAGE_MOVABLE_MASK)) /* Global integer used to determine if module parameter value has been * provided and if page migration feature is enabled. From ebb21b99369b46630dbc268061ae30a9dcc842b9 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Thu, 12 Jan 2023 21:45:36 +0800 Subject: [PATCH 207/258] media: rockchip: ispp: fec support in out diff size Change-Id: I469876b24fb96a856703625a0bec23d2e0dbd3e5 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/ispp/fec.c | 33 ++++++++++++---------- include/uapi/linux/rkispp-config.h | 6 ++-- 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/media/platform/rockchip/ispp/fec.c b/drivers/media/platform/rockchip/ispp/fec.c index cdd355f61fa6..b14917d4c0bb 100644 --- a/drivers/media/platform/rockchip/ispp/fec.c +++ b/drivers/media/platform/rockchip/ispp/fec.c @@ -124,7 +124,9 @@ static int fec_running(struct file *file, struct rkispp_fec_in_out *buf) struct rkispp_fec_dev *fec = video_drvdata(file); u32 in_fmt, out_fmt, in_mult = 1, out_mult = 1; u32 in_size, in_offs, out_size, out_offs, val; - u32 w = buf->width, h = buf->height, density, mesh_size; + u32 in_w = buf->in_width, in_h = buf->in_height; + u32 out_w = buf->out_width, out_h = buf->out_height; + u32 density, mesh_size; void __iomem *base = fec->hw->base_addr; void *mem; int ret = -EINVAL; @@ -134,8 +136,8 @@ static int fec_running(struct file *file, struct rkispp_fec_in_out *buf) if (rkispp_debug) t = ktime_get(); v4l2_dbg(3, rkispp_debug, &fec->v4l2_dev, - "%s enter %dx%d format(in:%c%c%c%c out:%c%c%c%c)\n", - __func__, w, h, + "%s enter %dx%d->%dx%d format(in:%c%c%c%c out:%c%c%c%c)\n", + __func__, in_w, in_h, out_w, out_h, buf->in_fourcc, buf->in_fourcc >> 8, buf->in_fourcc >> 16, buf->in_fourcc >> 24, buf->out_fourcc, buf->out_fourcc >> 8, @@ -145,8 +147,8 @@ static int fec_running(struct file *file, struct rkispp_fec_in_out *buf) rkispp_set_clk_rate(fec->hw->clks[0], fec->hw->core_clk_max); init_completion(&fec->cmpl); - density = w > 1920 ? SW_MESH_DENSITY : 0; - mesh_size = cal_fec_mesh(w, h, !!density); + density = out_w > 1920 ? SW_MESH_DENSITY : 0; + mesh_size = cal_fec_mesh(out_w, out_h, !!density); switch (buf->in_fourcc) { case V4L2_PIX_FMT_YUYV: @@ -170,9 +172,9 @@ static int fec_running(struct file *file, struct rkispp_fec_in_out *buf) buf->in_fourcc >> 16, buf->in_fourcc >> 24); return -EINVAL; } - in_offs = w * h; + in_offs = in_w * in_h; in_size = (in_fmt & FMT_YUV422) ? - w * h * 2 : w * h * 3 / 2; + in_w * in_h * 2 : in_w * in_h * 3 / 2; switch (buf->out_fourcc) { case V4L2_PIX_FMT_YUYV: @@ -202,15 +204,15 @@ static int fec_running(struct file *file, struct rkispp_fec_in_out *buf) return -EINVAL; } out_size = 0; - out_offs = w * h; + out_offs = out_w * out_h; if (out_fmt & FMT_FBC) { - w = ALIGN(w, 16); - h = ALIGN(h, 16); - out_offs = w * h >> 4; + out_w = ALIGN(out_w, 16); + out_h = ALIGN(out_h, 16); + out_offs = out_w * out_h >> 4; out_size = out_offs; } out_size += (out_fmt & FMT_YUV422) ? - w * h * 2 : w * h * 3 / 2; + out_w * out_h * 2 : out_w * out_h * 3 / 2; /* input picture buf */ mem = fec_buf_add(file, buf->in_pic_fd, in_size); @@ -260,12 +262,13 @@ static int fec_running(struct file *file, struct rkispp_fec_in_out *buf) val = out_fmt << 4 | in_fmt; writel(val, base + RKISPP_FEC_CTRL); - val = ALIGN(buf->width * in_mult, 16) >> 2; + val = ALIGN(in_w * in_mult, 16) >> 2; writel(val, base + RKISPP_FEC_RD_VIR_STRIDE); - val = ALIGN(buf->width * out_mult, 16) >> 2; + val = ALIGN(out_w * out_mult, 16) >> 2; writel(val, base + RKISPP_FEC_WR_VIR_STRIDE); - val = buf->height << 16 | buf->width; + val = out_h << 16 | out_w; writel(val, base + RKISPP_FEC_DST_SIZE); + val = in_h << 16 | in_w; writel(val, base + RKISPP_FEC_SRC_SIZE); writel(mesh_size, base + RKISPP_FEC_MESH_SIZE); val = SW_FEC_EN | density; diff --git a/include/uapi/linux/rkispp-config.h b/include/uapi/linux/rkispp-config.h index 65867cda0046..1707d1123e94 100644 --- a/include/uapi/linux/rkispp-config.h +++ b/include/uapi/linux/rkispp-config.h @@ -114,8 +114,10 @@ (V4L2_EVENT_PRIVATE_START + 3) struct rkispp_fec_in_out { - int width; - int height; + int in_width; + int in_height; + int out_width; + int out_height; int in_fourcc; int out_fourcc; int in_pic_fd; From 0bd9d79eb9b90cce8c7e847c66c7558da55b666f Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 16 Feb 2023 18:41:34 +0800 Subject: [PATCH 208/258] arm64: dts: rockchip: rk3562: Assign spi0 sclk_in to SCLK_IN_PMU1_SPI0 Change-Id: I574752dc3509df2307322b934da6939d590c4fba Signed-off-by: Jon Lin --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 019358146f82..4b88350da734 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -968,7 +968,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>; + clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru SCLK_IN_PMU1_SPI0>; clock-names = "spiclk", "apb_pclk", "sclk_in"; dmas = <&dmac 13>, <&dmac 12>; dma-names = "tx", "rx"; From 494eee4070e445f3db902687add5ecb29f5f955b Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Wed, 15 Feb 2023 15:51:02 +0800 Subject: [PATCH 209/258] mmc: sdhci-of-dwcmshc: Sync code with kernel 4.19 1. remove execute_tuning api 2. remove RK_RXCLK_NO_INVERTER for RK3528 and RK3562 3. set strbin tap to 3 for RK3528 and RK3562 4. fixed tap value by software 5. Disable output clock while config DLL Signed-off-by: Yifeng Zhao Change-Id: Icad745d09a0fad37ec58d2071ba780b9749d1c16 --- drivers/mmc/host/sdhci-of-dwcmshc.c | 76 +++++++++++------------------ 1 file changed, 29 insertions(+), 47 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 251e9d3cc2d8..9db254ef6484 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -53,6 +53,8 @@ #define DWCMSHC_EMMC_DLL_INC 8 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) +#define DLL_TAP_VALUE_SEL BIT(25) +#define DLL_TAP_VALUE_OFFSET 8 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) @@ -91,7 +93,7 @@ struct dwcmshc_driver_data { #define RK_PLATFROM BIT(0) #define RK_DLL_CMD_OUT BIT(1) #define RK_RXCLK_NO_INVERTER BIT(2) -#define RK_RXCLK_SW_TUNING BIT(3) +#define RK_TAP_VALUE_SEL BIT(3) u8 hs200_tx_tap; u8 hs400_tx_tap; @@ -107,7 +109,6 @@ struct rk35xx_priv { enum dwcmshc_rk_type devtype; u8 txclk_tapnum; u32 cclk_rate; - u8 hs200_rx_tap; unsigned int actual_clk; const struct dwcmshc_driver_data *drv_data; u32 acpi_en; @@ -234,9 +235,8 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); struct rk35xx_priv *priv = dwc_priv->priv; const struct dwcmshc_driver_data *drv_data = priv->drv_data; - u8 rxclk_tapnum; u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; - u32 extra, reg; + u32 extra, reg, dll_lock_value; int err; host->mmc->actual_clock = 0; @@ -274,9 +274,14 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock extra &= ~BIT(0); sdhci_writel(host, extra, reg); + /* Disable output clock while config DLL */ + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + if (clock <= 52000000) { + /* Disable DLL */ + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); /* - * Disable DLL and reset both of sample and drive clock. + * Config DLL BYPASS and Reset both of sample and drive clock. * The bypass bit and start bit need to set if DLL is not locked. */ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); @@ -292,7 +297,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock DLL_STRBIN_DELAY_NUM_SEL | drv_data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); - return; + goto exit; } /* Reset DLL */ @@ -312,26 +317,21 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock 500 * USEC_PER_MSEC); if (err) { dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); - return; + goto exit; } + dll_lock_value = ((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) & 0xFF) * 2) & 0xFF; + extra = 0x1 << 16 | /* tune clock stop en */ 0x3 << 17 | /* pre-change delay */ 0x3 << 19; /* post-change delay */ sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); - rxclk_tapnum = priv->hs200_rx_tap; - if ((drv_data->flags & RK_RXCLK_NO_INVERTER) && - host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { - extra = drv_data->hs200_tx_tap - drv_data->hs400_tx_tap; - if (rxclk_tapnum + extra < DLL_RXCLK_MAX_TAP) - rxclk_tapnum += extra; - } extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE; if (drv_data->flags & RK_RXCLK_NO_INVERTER) extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; - if (drv_data->flags & RK_RXCLK_SW_TUNING && priv->hs200_rx_tap) - extra |= DLL_RXCLK_TAPNUM_FROM_SW | rxclk_tapnum; + if (drv_data->flags & RK_TAP_VALUE_SEL) + extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); txclk_tapnum = drv_data->hs200_tx_tap; @@ -343,18 +343,28 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock DWCMSHC_EMMC_DLL_DLYENA | drv_data->hs400_cmd_tap | DLL_CMDOUT_TAPNUM_FROM_SW; + if (drv_data->flags & RK_TAP_VALUE_SEL) + extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET; sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); } extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_TXCLK_TAPNUM_FROM_SW | DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL | txclk_tapnum; + if (drv_data->flags & RK_TAP_VALUE_SEL) + extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); extra = DWCMSHC_EMMC_DLL_DLYENA | drv_data->hs400_strbin_tap | DLL_STRBIN_TAPNUM_FROM_SW; + if (drv_data->flags & RK_TAP_VALUE_SEL) + extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); + +exit: + /* enable output clock */ + sdhci_enable_clk(host, 0); } static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) @@ -380,31 +390,6 @@ static void sdhci_dwcmshc_request_done(struct sdhci_host *host, struct mmc_reque mmc_request_done(host->mmc, mrq); } -static int dwcmshc_rk_execute_tuning(struct mmc_host *mmc, u32 opcode) -{ - struct sdhci_host *host = mmc_priv(mmc); - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); - struct rk35xx_priv *priv = dwc_priv->priv; - int rx_delay, dll_lock_num, ret; - u32 extra; - - ret = sdhci_execute_tuning(mmc, opcode); - if (!ret) { - rx_delay = (sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS1) >> 8) & 0xFF; - dll_lock_num = sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) & 0xFF; - sdhci_reset_tuning(host); - priv->hs200_rx_tap = rx_delay * 16 / dll_lock_num; - extra = sdhci_readl(host, DWCMSHC_EMMC_DLL_RXCLK); - extra &= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; - extra |= DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE | - DLL_RXCLK_TAPNUM_FROM_SW | priv->hs200_rx_tap; - sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); - } - - return ret; -} - static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -528,7 +513,7 @@ static const struct dwcmshc_driver_data rk3588_drvdata = { static const struct dwcmshc_driver_data rk3528_drvdata = { .pdata = &sdhci_dwcmshc_rk35xx_pdata, - .flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_RXCLK_SW_TUNING | RK_RXCLK_NO_INVERTER, + .flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL, .hs200_tx_tap = 12, .hs400_tx_tap = 6, .hs400_cmd_tap = 6, @@ -538,11 +523,11 @@ static const struct dwcmshc_driver_data rk3528_drvdata = { static const struct dwcmshc_driver_data rk3562_drvdata = { .pdata = &sdhci_dwcmshc_rk35xx_pdata, - .flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_RXCLK_SW_TUNING | RK_RXCLK_NO_INVERTER, + .flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL, .hs200_tx_tap = 12, .hs400_tx_tap = 6, .hs400_cmd_tap = 6, - .hs400_strbin_tap = 1, + .hs400_strbin_tap = 3, .ddr50_strbin_delay_num = 10, }; @@ -663,7 +648,6 @@ static int dwcmshc_probe(struct platform_device *pdev) } rk_priv->drv_data = drv_data; - rk_priv->hs200_rx_tap = 0; rk_priv->acpi_en = has_acpi_companion(&pdev->dev); if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc")) @@ -673,8 +657,6 @@ static int dwcmshc_probe(struct platform_device *pdev) priv->priv = rk_priv; - if (drv_data->flags & RK_RXCLK_SW_TUNING) - host->mmc_host_ops.execute_tuning = dwcmshc_rk_execute_tuning; err = dwcmshc_rk35xx_init(host, priv); if (err) goto err_clk; From 0c941636662989ba6b29268c4f66c669b7aaca02 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Fri, 2 Dec 2022 16:04:25 +0800 Subject: [PATCH 210/258] drm/rockchip: vop3: rk3528: fix filter mode define error Signed-off-by: Sandy Huang Change-Id: I0695947cf5389a473f586e100dc1ed30fb806537 --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index ff7659280df4..74fcfd40fa88 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1993,8 +1993,8 @@ static const struct vop2_scl_regs rk3528_cluster0_win_scl = { .yrgb_ver_scl_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 14), .yrgb_hor_scl_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 22), - .yrgb_hscl_filter_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 12),/* supported from vop3 */ - .yrgb_vscl_filter_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 20),/* supported from vop3 */ + .yrgb_vscl_filter_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 12),/* supported from vop3 */ + .yrgb_hscl_filter_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 20),/* supported from vop3 */ .vsd_yrgb_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 28), .vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 29), @@ -3755,7 +3755,6 @@ static const struct vop2_data rk3528_vop = { .nr_axi_intr = ARRAY_SIZE(rk3528_vop_axi_intr), .vp = rk3528_vop_video_ports, .wb = &rk3568_vop_wb_data, - .layer = rk3568_vop_layers, .win = rk3528_vop_win_data, .win_size = ARRAY_SIZE(rk3528_vop_win_data), .dump_regs = rk3528_dump_regs, From 2ae2025cb0742168e55bbeb0085a624a73d9b6a7 Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Tue, 6 Sep 2022 18:28:55 +0800 Subject: [PATCH 211/258] soc: rockchip: pm-config: simplify parse_on_off_regulator Change-Id: I47f92ed326a4c813a6be83a82761b427e2ca4065 Signed-off-by: XiaoDong Huang --- drivers/soc/rockchip/rockchip_pm_config.c | 94 ++++++++--------------- 1 file changed, 33 insertions(+), 61 deletions(-) diff --git a/drivers/soc/rockchip/rockchip_pm_config.c b/drivers/soc/rockchip/rockchip_pm_config.c index 8e5fafda0824..fba2882bd69a 100644 --- a/drivers/soc/rockchip/rockchip_pm_config.c +++ b/drivers/soc/rockchip/rockchip_pm_config.c @@ -34,6 +34,12 @@ enum rk_pm_state { RK_PM_STATE_MAX }; +static const char * const pm_state_str[RK_PM_STATE_MAX] = { + [RK_PM_MEM] = "mem", + [RK_PM_MEM_LITE] = "mem-lite", + [RK_PM_MEM_ULTRA] = "mem-ultra", +}; + static struct rk_on_off_regulator_list { struct regulator_dev *on_reg_list[MAX_ON_OFF_REG_NUM]; struct regulator_dev *off_reg_list[MAX_ON_OFF_REG_NUM]; @@ -73,84 +79,50 @@ static void rockchip_pm_virt_pwroff_prepare(void) sip_smc_virtual_poweroff(); } -static int parse_on_off_regulator(struct device_node *node, enum rk_pm_state state) +static int parse_regulator_list(struct device_node *node, + char *prop_name, + struct regulator_dev **out_list) { - char on_prop_name[MAX_ON_OFF_REG_PROP_NAME_LEN] = {0}; - char off_prop_name[MAX_ON_OFF_REG_PROP_NAME_LEN] = {0}; - int i, j; struct device_node *dn; struct regulator_dev *reg; - struct regulator_dev **on_list; - struct regulator_dev **off_list; + int i, j; - switch (state) { - case RK_PM_MEM: - strncpy(on_prop_name, "rockchip,regulator-on-in-mem", - MAX_ON_OFF_REG_PROP_NAME_LEN); - strncpy(off_prop_name, "rockchip,regulator-off-in-mem", - MAX_ON_OFF_REG_PROP_NAME_LEN); - break; - - case RK_PM_MEM_LITE: - strncpy(on_prop_name, "rockchip,regulator-on-in-mem-lite", - MAX_ON_OFF_REG_PROP_NAME_LEN); - strncpy(off_prop_name, "rockchip,regulator-off-in-mem-lite", - MAX_ON_OFF_REG_PROP_NAME_LEN); - break; - - case RK_PM_MEM_ULTRA: - strncpy(on_prop_name, "rockchip,regulator-on-in-mem-ultra", - MAX_ON_OFF_REG_PROP_NAME_LEN); - strncpy(off_prop_name, "rockchip,regulator-off-in-mem-ultra", - MAX_ON_OFF_REG_PROP_NAME_LEN); - break; - - default: - return 0; - } - - on_list = on_off_regs_list[state].on_reg_list; - off_list = on_off_regs_list[state].off_reg_list; - - if (of_find_property(node, on_prop_name, NULL)) { + if (of_find_property(node, prop_name, NULL)) { for (i = 0, j = 0; - (dn = of_parse_phandle(node, on_prop_name, i)); + (dn = of_parse_phandle(node, prop_name, i)) && j < MAX_ON_OFF_REG_NUM; i++) { reg = of_find_regulator_by_node(dn); if (reg == NULL) { pr_warn("failed to find regulator %s for %s\n", - dn->name, on_prop_name); + dn->name, prop_name); } else { - pr_debug("%s on regulator=%s\n", __func__, + pr_debug("%s %s regulator=%s\n", __func__, + prop_name, reg->desc->name); - on_list[j++] = reg; + out_list[j++] = reg; } of_node_put(dn); - - if (j >= MAX_ON_OFF_REG_NUM) - return 0; } } - if (of_find_property(node, off_prop_name, NULL)) { - for (i = 0, j = 0; - (dn = of_parse_phandle(node, off_prop_name, i)); - i++) { - reg = of_find_regulator_by_node(dn); - if (reg == NULL) { - pr_warn("failed to find regulator %s for %s\n", - dn->name, off_prop_name); - } else { - pr_debug("%s off regulator=%s\n", __func__, - reg->desc->name); - off_list[j++] = reg; - } - of_node_put(dn); + return 0; +} - if (j >= MAX_ON_OFF_REG_NUM) - return 0; - } - } +static int parse_on_off_regulator(struct device_node *node, enum rk_pm_state state) +{ + char on_prop_name[MAX_ON_OFF_REG_PROP_NAME_LEN]; + char off_prop_name[MAX_ON_OFF_REG_PROP_NAME_LEN]; + + if (state >= RK_PM_STATE_MAX) + return -EINVAL; + + snprintf(on_prop_name, sizeof(on_prop_name), + "rockchip,regulator-on-in-%s", pm_state_str[state]); + snprintf(off_prop_name, sizeof(off_prop_name), + "rockchip,regulator-off-in-%s", pm_state_str[state]); + + parse_regulator_list(node, on_prop_name, on_off_regs_list[state].on_reg_list); + parse_regulator_list(node, off_prop_name, on_off_regs_list[state].off_reg_list); return 0; } From ec0076dc3bdb94c55953210d7e9b83b772c36385 Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Tue, 6 Sep 2022 17:51:37 +0800 Subject: [PATCH 212/258] soc: rockchip: pm-config: support sleep config for mem_lite/mem_ultra sleep-mode-config-mem-lite = <...> is mode_config for mem_lite. wakeup-config-mem-lite = <...> is wakeup_config for mem_lite. sleep-mode-config-mem-ultra = <...> is mode_config for mem_ultra. wakeup-config-mem-ultra = <...> is wakeup_config for mem_ultra. Change-Id: If41ef73d8075c9e74b87a0ebf1634622e5625db3 Signed-off-by: XiaoDong Huang --- drivers/soc/rockchip/rockchip_pm_config.c | 71 ++++++++++++++++++++--- 1 file changed, 63 insertions(+), 8 deletions(-) diff --git a/drivers/soc/rockchip/rockchip_pm_config.c b/drivers/soc/rockchip/rockchip_pm_config.c index fba2882bd69a..c9ed5d576db0 100644 --- a/drivers/soc/rockchip/rockchip_pm_config.c +++ b/drivers/soc/rockchip/rockchip_pm_config.c @@ -25,8 +25,8 @@ #define PM_INVALID_GPIO 0xffff #define MAX_ON_OFF_REG_NUM 30 #define MAX_ON_OFF_REG_PROP_NAME_LEN 60 +#define MAX_CONFIG_PROP_NAME_LEN 60 -#ifndef MODULE enum rk_pm_state { RK_PM_MEM = 0, RK_PM_MEM_LITE, @@ -34,6 +34,7 @@ enum rk_pm_state { RK_PM_STATE_MAX }; +#ifndef MODULE static const char * const pm_state_str[RK_PM_STATE_MAX] = { [RK_PM_MEM] = "mem", [RK_PM_MEM_LITE] = "mem-lite", @@ -46,6 +47,11 @@ static struct rk_on_off_regulator_list { } on_off_regs_list[RK_PM_STATE_MAX]; #endif +static struct rk_sleep_config { + u32 mode_config; + u32 wakeup_config; +} sleep_config[RK_PM_STATE_MAX]; + static const struct of_device_id pm_match_table[] = { { .compatible = "rockchip,pm-px30",}, { .compatible = "rockchip,pm-rk1808",}, @@ -79,6 +85,37 @@ static void rockchip_pm_virt_pwroff_prepare(void) sip_smc_virtual_poweroff(); } +static int parse_sleep_config(struct device_node *node, enum rk_pm_state state) +{ + char mode_prop_name[MAX_CONFIG_PROP_NAME_LEN]; + char wkup_prop_name[MAX_CONFIG_PROP_NAME_LEN]; + struct rk_sleep_config *config; + + if (state == RK_PM_MEM || state >= RK_PM_STATE_MAX) + return -EINVAL; + + snprintf(mode_prop_name, sizeof(mode_prop_name), + "sleep-mode-config-%s", pm_state_str[state]); + snprintf(wkup_prop_name, sizeof(wkup_prop_name), + "wakeup-config-%s", pm_state_str[state]); + + config = &sleep_config[state]; + + if (of_property_read_u32_array(node, + mode_prop_name, + &config->mode_config, 1)) + pr_info("%s not set sleep-mode-config for %s\n", + node->name, pm_state_str[state]); + + if (of_property_read_u32_array(node, + wkup_prop_name, + &config->wakeup_config, 1)) + pr_info("%s not set wakeup-config for %s\n", + node->name, pm_state_str[state]); + + return 0; +} + static int parse_regulator_list(struct device_node *node, char *prop_name, struct regulator_dev **out_list) @@ -132,8 +169,7 @@ static int pm_config_probe(struct platform_device *pdev) { const struct of_device_id *match_id; struct device_node *node; - u32 mode_config = 0; - u32 wakeup_config = 0; + struct rk_sleep_config *config = &sleep_config[RK_PM_MEM]; u32 pwm_regulator_config = 0; int gpio_temp[10]; u32 sleep_debug_en = 0; @@ -160,17 +196,17 @@ static int pm_config_probe(struct platform_device *pdev) if (of_property_read_u32_array(node, "rockchip,sleep-mode-config", - &mode_config, 1)) + &config->mode_config, 1)) dev_warn(&pdev->dev, "not set sleep mode config\n"); else - sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, mode_config, 0); + sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, config->mode_config, 0); if (of_property_read_u32_array(node, "rockchip,wakeup-config", - &wakeup_config, 1)) + &config->wakeup_config, 1)) dev_warn(&pdev->dev, "not set wakeup-config\n"); else - sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, wakeup_config, 0); + sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, config->wakeup_config, 0); if (of_property_read_u32_array(node, "rockchip,pwm-regulator-config", @@ -229,8 +265,10 @@ static int pm_config_probe(struct platform_device *pdev) virtual_poweroff_en) pm_power_off_prepare = rockchip_pm_virt_pwroff_prepare; - for (i = RK_PM_MEM; i < RK_PM_STATE_MAX; i++) + for (i = RK_PM_MEM; i < RK_PM_STATE_MAX; i++) { + parse_sleep_config(node, i); parse_on_off_regulator(node, i); + } #endif return 0; @@ -244,6 +282,7 @@ static int pm_config_prepare(struct device *dev) enum rk_pm_state state = suspend_state - PM_SUSPEND_MEM; struct regulator_dev **on_list; struct regulator_dev **off_list; + struct rk_sleep_config *config, *def_config = &sleep_config[RK_PM_MEM]; sip_smc_set_suspend_mode(LINUX_PM_STATE, suspend_state, @@ -252,6 +291,22 @@ static int pm_config_prepare(struct device *dev) if (state >= RK_PM_STATE_MAX) return 0; + config = &sleep_config[state]; + + if (config->mode_config) + sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, + config->mode_config, 0); + else if (def_config->mode_config) + sip_smc_set_suspend_mode(SUSPEND_MODE_CONFIG, + def_config->mode_config, 0); + + if (config->wakeup_config) + sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, + config->wakeup_config, 0); + else if (def_config->wakeup_config) + sip_smc_set_suspend_mode(WKUP_SOURCE_CONFIG, + def_config->wakeup_config, 0); + on_list = on_off_regs_list[state].on_reg_list; off_list = on_off_regs_list[state].off_reg_list; From 91ef5c438c1292e0d22942686bf268f1506937b7 Mon Sep 17 00:00:00 2001 From: Cai YiWei Date: Fri, 9 Dec 2022 15:57:22 +0800 Subject: [PATCH 213/258] media: rockchip: isp: dvfs for multi dev on/off Change-Id: I5ba04caebbaafd49d86bc615d1d69ea6ab2b9343 Signed-off-by: Cai YiWei --- drivers/media/platform/rockchip/isp/dev.c | 51 ++++++++++------- drivers/media/platform/rockchip/isp/dev.h | 2 +- drivers/media/platform/rockchip/isp/hw.h | 3 + drivers/media/platform/rockchip/isp/rkisp.c | 62 +++++++++++++++++---- 4 files changed, 87 insertions(+), 31 deletions(-) diff --git a/drivers/media/platform/rockchip/isp/dev.c b/drivers/media/platform/rockchip/isp/dev.c index 51efdfd457d2..a9c4d086dbfa 100644 --- a/drivers/media/platform/rockchip/isp/dev.c +++ b/drivers/media/platform/rockchip/isp/dev.c @@ -176,26 +176,34 @@ static int __isp_pipeline_s_isp_clk(struct rkisp_pipeline *p) { struct rkisp_device *dev = container_of(p, struct rkisp_device, pipe); struct rkisp_hw_dev *hw_dev = dev->hw_dev; - u32 w = hw_dev->max_in.w ? hw_dev->max_in.w : dev->isp_sdev.in_frm.width; struct v4l2_subdev *sd; struct v4l2_ctrl *ctrl; - u64 data_rate; - int i; + u64 data_rate = 0; + int i, fps; + + hw_dev->isp_size[dev->dev_id].is_on = true; + if (hw_dev->is_runing) { + if (dev->isp_ver >= ISP_V30 && !rkisp_clk_dbg) + hw_dev->is_dvfs = true; + return 0; + } if (dev->isp_inp & (INP_RAWRD0 | INP_RAWRD1 | INP_RAWRD2)) { - for (i = 0; i < hw_dev->num_clk_rate_tbl; i++) { - if (w <= hw_dev->clk_rate_tbl[i].refer_data) - break; + if (dev->isp_ver < ISP_V30) { + /* isp with mipi no support dvfs, calculate max data rate */ + for (i = 0; i < hw_dev->dev_num; i++) { + fps = hw_dev->isp_size[i].fps; + if (!fps) + fps = 30; + data_rate += (fps * hw_dev->isp_size[i].size); + } + } else { + i = dev->dev_id; + fps = hw_dev->isp_size[i].fps; + if (!fps) + fps = 30; + data_rate = fps * hw_dev->isp_size[i].size; } - if (!hw_dev->is_single) - i++; - - /* use lager clk in 4 vir-isp mode */ - if (hw_dev->dev_num >= 4) - i++; - - if (i > hw_dev->num_clk_rate_tbl - 1) - i = hw_dev->num_clk_rate_tbl - 1; goto end; } @@ -228,6 +236,7 @@ static int __isp_pipeline_s_isp_clk(struct rkisp_pipeline *p) data_rate = v4l2_ctrl_g_ctrl_int64(ctrl) * dev->isp_sdev.in_fmt.bus_width; data_rate >>= 3; +end: do_div(data_rate, 1000 * 1000); /* increase 25% margin */ @@ -239,7 +248,7 @@ static int __isp_pipeline_s_isp_clk(struct rkisp_pipeline *p) break; if (i == hw_dev->num_clk_rate_tbl) i--; -end: + /* set isp clock rate */ rkisp_set_clk_rate(hw_dev->clks[0], hw_dev->clk_rate_tbl[i].clk_rate * 1000000UL); if (hw_dev->is_unite) @@ -284,11 +293,13 @@ static int rkisp_pipeline_close(struct rkisp_pipeline *p) { struct rkisp_device *dev = container_of(p, struct rkisp_device, pipe); - atomic_dec(&p->power_cnt); - - if (!atomic_read(&p->power_cnt) && dev->isp_ver >= ISP_V30) - rkisp_rx_buf_pool_free(dev); + if (atomic_dec_return(&p->power_cnt)) + return 0; + rkisp_rx_buf_pool_free(dev); + dev->hw_dev->isp_size[dev->dev_id].is_on = false; + if (dev->hw_dev->is_runing && (dev->isp_ver >= ISP_V30) && !rkisp_clk_dbg) + dev->hw_dev->is_dvfs = true; return 0; } diff --git a/drivers/media/platform/rockchip/isp/dev.h b/drivers/media/platform/rockchip/isp/dev.h index a5fe217bcff8..37b52d159c49 100644 --- a/drivers/media/platform/rockchip/isp/dev.h +++ b/drivers/media/platform/rockchip/isp/dev.h @@ -227,7 +227,7 @@ struct rkisp_device { struct rkisp_ispp_buf *cur_fbcgain; struct rkisp_buffer *cur_spbuf; - struct tasklet_struct rdbk_tasklet; + struct work_struct rdbk_work; struct kfifo rdbk_kfifo; spinlock_t rdbk_lock; int rdbk_cnt; diff --git a/drivers/media/platform/rockchip/isp/hw.h b/drivers/media/platform/rockchip/isp/hw.h index cd689701e005..04dedc22921c 100644 --- a/drivers/media/platform/rockchip/isp/hw.h +++ b/drivers/media/platform/rockchip/isp/hw.h @@ -44,6 +44,8 @@ struct rkisp_size_info { u32 w; u32 h; u32 size; + u32 fps; + bool is_on; }; struct rkisp_hw_dev { @@ -101,6 +103,7 @@ struct rkisp_hw_dev { bool is_multi_overflow; bool is_runing; bool is_frm_buf; + bool is_dvfs; }; int rkisp_register_irq(struct rkisp_hw_dev *dev); diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c index ed63881799c5..82bb3d09bf1c 100644 --- a/drivers/media/platform/rockchip/isp/rkisp.c +++ b/drivers/media/platform/rockchip/isp/rkisp.c @@ -425,7 +425,10 @@ int rkisp_update_sensor_info(struct rkisp_device *dev) v4l2_subdev_call(sensor->sd, video, g_frame_interval, &sensor->fi); dev->active_sensor = sensor; - + i = dev->dev_id; + if (sensor->fi.interval.numerator) + dev->hw_dev->isp_size[i].fps = + sensor->fi.interval.denominator / sensor->fi.interval.numerator; return ret; } @@ -492,6 +495,45 @@ u32 rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode) return pixelformat; } +static void rkisp_dvfs(struct rkisp_device *dev) +{ + struct rkisp_hw_dev *hw = dev->hw_dev; + u64 data_rate = 0; + int i, fps, num = 0; + + if (!hw->is_dvfs) + return; + hw->is_dvfs = false; + for (i = 0; i < hw->dev_num; i++) { + if (!hw->isp_size[i].is_on) + continue; + fps = hw->isp_size[i].fps; + if (!fps) + fps = 30; + data_rate += (fps * hw->isp_size[i].size); + num++; + } + do_div(data_rate, 1000 * 1000); + /* increase margin: 25% * num */ + data_rate += (data_rate >> 2) * num; + + /* compare with isp clock adjustment table */ + for (i = 0; i < hw->num_clk_rate_tbl; i++) + if (data_rate <= hw->clk_rate_tbl[i].clk_rate) + break; + if (i == hw->num_clk_rate_tbl) + i--; + + /* set isp clock rate */ + rkisp_set_clk_rate(hw->clks[0], hw->clk_rate_tbl[i].clk_rate * 1000000UL); + if (hw->is_unite) + rkisp_set_clk_rate(hw->clks[5], hw->clk_rate_tbl[i].clk_rate * 1000000UL); + /* aclk equal to core clk */ + if (dev->isp_ver == ISP_V32) + rkisp_set_clk_rate(hw->clks[1], hw->clk_rate_tbl[i].clk_rate * 1000000UL); + dev_info(hw->dev, "set isp clk = %luHz\n", clk_get_rate(hw->clks[0])); +} + static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on) { struct rkisp_hw_dev *hw = dev->hw_dev; @@ -779,7 +821,6 @@ static void rkisp_fast_switch_rx_buf(struct rkisp_device *dev, bool is_current) } } - static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd) { struct rkisp_hw_dev *hw = dev->hw_dev; @@ -902,10 +943,11 @@ int rkisp_rdbk_trigger_event(struct rkisp_device *dev, u32 cmd, void *arg) return ret; } -static void rkisp_rdbk_task(unsigned long arg) +static void rkisp_rdbk_work(struct work_struct *work) { - struct rkisp_device *dev = (struct rkisp_device *)arg; + struct rkisp_device *dev = container_of(work, struct rkisp_device, rdbk_work); + rkisp_dvfs(dev); rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL); } @@ -971,7 +1013,10 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq) end: dev->irq_ends = 0; - tasklet_schedule(&dev->rdbk_tasklet); + if (dev->hw_dev->is_dvfs) + schedule_work(&dev->rdbk_work); + else + rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL); } static void rkisp_set_state(u32 *state, u32 val) @@ -2033,6 +2078,7 @@ static int rkisp_isp_stop(struct rkisp_device *dev) rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true); } + hw->is_dvfs = false; hw->is_runing = false; dev->hw_dev->is_idle = true; dev->hw_dev->is_mi_update = false; @@ -2789,12 +2835,10 @@ static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on) atomic_dec(&hw_dev->refcnt); rkisp_params_stream_stop(&isp_dev->params_vdev); atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0); - tasklet_disable(&isp_dev->rdbk_tasklet); return 0; } hw_dev->is_runing = true; - tasklet_enable(&isp_dev->rdbk_tasklet); rkisp_start_3a_run(isp_dev); memset(&isp_dev->isp_sdev.dbg, 0, sizeof(isp_dev->isp_sdev.dbg)); if (atomic_inc_return(&hw_dev->refcnt) > hw_dev->dev_link_num) { @@ -3670,8 +3714,7 @@ int rkisp_register_isp_subdev(struct rkisp_device *isp_dev, isp_dev->isp_state = ISP_STOP; atomic_set(&isp_sdev->frm_sync_seq, 0); rkisp_monitor_init(isp_dev); - tasklet_init(&isp_dev->rdbk_tasklet, rkisp_rdbk_task, (unsigned long)isp_dev); - tasklet_disable(&isp_dev->rdbk_tasklet); + INIT_WORK(&isp_dev->rdbk_work, rkisp_rdbk_work); return 0; err_cleanup_media_entity: media_entity_cleanup(&sd->entity); @@ -3684,7 +3727,6 @@ void rkisp_unregister_isp_subdev(struct rkisp_device *isp_dev) { struct v4l2_subdev *sd = &isp_dev->isp_sdev.sd; - tasklet_kill(&isp_dev->rdbk_tasklet); kfifo_free(&isp_dev->rdbk_kfifo); v4l2_device_unregister_subdev(sd); media_entity_cleanup(&sd->entity); From 9ecef75fd615ac493f490fadf814481720eaf0df Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Thu, 16 Feb 2023 17:00:26 +0800 Subject: [PATCH 214/258] arm64: dts: rockchip: rk3562-amp: protect TIMER4 and UART7M1 Signed-off-by: Steven Liu Change-Id: I220e00435cbd3a771f4286cb97d8bbfa5427cd7f --- arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi index 66ece0360c78..0968d9616850 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi @@ -8,14 +8,11 @@ compatible = "rockchip,mcu-amp"; clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>, <&cru PCLK_MAILBOX>, <&cru PCLK_INTC>, - <&cru SCLK_UART5>, <&cru PCLK_UART5>, - <&cru PCLK_TIMER>, <&cru CLK_TIMER5>; - clock-names = "fclk_bus_cm0_core", "clk_bus_cm0_rtc", - "pclk_maikbox", "pclk_intc", - "baudclk", "apb_pclk", "pclk", "timer"; + <&cru SCLK_UART7>, <&cru PCLK_UART7>, + <&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>; pinctrl-names = "default"; - pinctrl-0 = <&uart5m0_xfer>; + pinctrl-0 = <&uart7m1_xfer>; status = "okay"; }; From bc1ebbaed7fc1851607b45e931e78bb6dea47f68 Mon Sep 17 00:00:00 2001 From: XiaoTan Luo Date: Thu, 16 Feb 2023 15:29:40 +0800 Subject: [PATCH 215/258] arm64: dts: rockchip: set 128 mclk-fs for spdiftx Signed-off-by: XiaoTan Luo Change-Id: I170bb55c9e093693c642a8b750971362c2a7de3f --- arch/arm64/boot/dts/rockchip/rk3308-evb-v10.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3308b-evb-v10.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3328-evb-android.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3399-box.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3399-firefly-android.dts | 1 + arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts | 1 + arch/arm64/boot/dts/rockchip/rk3399-mid-818-android.dts | 1 + arch/arm64/boot/dts/rockchip/rk3399-rock960-ab.dts | 1 + arch/arm64/boot/dts/rockchip/rk3399-videostrong-linux.dts | 1 + arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3566-box.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi | 1 + 22 files changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-evb-v10.dtsi index ad79bcc8d8d3..56ca962a660f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-evb-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-v10.dtsi @@ -139,6 +139,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-tx-sound"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_tx>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi b/arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi index 0e0cbb2932d5..1be3c9d873ca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi @@ -112,6 +112,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-rx-sound"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_rx>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3308b-evb-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3308b-evb-v10.dtsi index a93eb0d95cf2..60da7032773a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308b-evb-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308b-evb-v10.dtsi @@ -125,7 +125,7 @@ compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-tx-sound"; status = "disabled"; - + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_tx>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts index 30c73ef25370..980e5e92cde1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts @@ -55,7 +55,7 @@ spdif-sound { compatible = "simple-audio-card"; simple-audio-card,name = "SPDIF"; - + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi index ad7ef6be49fa..e64cf04972d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtsi @@ -87,6 +87,7 @@ spdif-sound { compatible = "simple-audio-card"; simple-audio-card,name = "rockchip-spdif"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-evb-android.dtsi index e050047420a6..708d580015cc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-evb-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328-evb-android.dtsi @@ -59,6 +59,7 @@ spdif-sound { compatible = "simple-audio-card"; simple-audio-card,name = "rockchip-spdif"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi index 310367d947ed..e8c75eb6c500 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-box.dtsi @@ -89,6 +89,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi index 5e77d8156dfa..31e3ae2cc471 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi @@ -138,6 +138,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi index 48679b72dedd..5ef489c1a1ad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi @@ -173,6 +173,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly-android.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly-android.dts index 46e2fce08e9c..1579231f7b35 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly-android.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly-android.dts @@ -215,6 +215,7 @@ status = "okay"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts index 4c1f3c653135..48bfaf095bb2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts @@ -159,6 +159,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-mid-818-android.dts b/arch/arm64/boot/dts/rockchip/rk3399-mid-818-android.dts index f950a76831ae..3eda89f629ad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-mid-818-android.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-mid-818-android.dts @@ -204,6 +204,7 @@ spdif-sound { compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960-ab.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960-ab.dts index 86e45dc0074d..ea9c3e589d94 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960-ab.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960-ab.dts @@ -122,6 +122,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-videostrong-linux.dts b/arch/arm64/boot/dts/rockchip/rk3399-videostrong-linux.dts index 10ba2048483d..142515e57127 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-videostrong-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-videostrong-linux.dts @@ -89,6 +89,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi index 61efa7c29a77..e2a83bd941a9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi @@ -78,6 +78,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_8ch>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi index 778f22fe87b1..24df0a0e0f79 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi @@ -110,6 +110,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "rk-spdif-sound"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_8ch>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi index 087e97ed8043..8a45da25bbf2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-box.dtsi @@ -75,6 +75,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_8ch>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi index e0762fae0a17..21f4252e1384 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi @@ -208,6 +208,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_8ch>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi index 400dc44e6bbe..d030582d6c55 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi @@ -74,6 +74,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_8ch>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi index a5fb689390c0..ca5c8aee8d81 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi @@ -142,6 +142,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_tx1>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi index 2d24de69805c..3e8a1aaf4585 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi @@ -142,6 +142,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_tx1>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi index 82488ea1330a..ff63cbe613e7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi @@ -119,6 +119,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_tx1>; }; From 5fb123e773d22de863bbfc2038823a9269593555 Mon Sep 17 00:00:00 2001 From: XiaoTan Luo Date: Thu, 16 Feb 2023 15:31:24 +0800 Subject: [PATCH 216/258] ARM: dts: rockchip: set 128 mclk-fs for spdiftx Signed-off-by: XiaoTan Luo Change-Id: I9725660493739f080b0c5b3d7714ba9545fb975e --- arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts | 1 + arch/arm/boot/dts/rk3128h-box.dtsi | 1 + arch/arm/boot/dts/rk3229-evb-android.dtsi | 1 + arch/arm/boot/dts/rk3288-firefly-reload-linux.dts | 1 + arch/arm/boot/dts/rk3288-firefly-reload.dts | 1 + arch/arm/boot/dts/rk3288-firefly-rk808.dts | 1 + arch/arm/boot/dts/rk3288-rock2-square.dts | 1 + arch/arm/boot/dts/rk3308-dot-v10-aarch32.dts | 1 + arch/arm/boot/dts/rk3308-voice-module-v10-aarch32.dtsi | 1 + arch/arm/boot/dts/rk3308-voice-module-v11-aarch32.dtsi | 1 + 10 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts b/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts index 2098a9f795d1..2151849d8fac 100644 --- a/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts +++ b/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts @@ -127,6 +127,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm/boot/dts/rk3128h-box.dtsi b/arch/arm/boot/dts/rk3128h-box.dtsi index 4fda0be65420..11e7edc1cfdd 100644 --- a/arch/arm/boot/dts/rk3128h-box.dtsi +++ b/arch/arm/boot/dts/rk3128h-box.dtsi @@ -160,6 +160,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP-SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm/boot/dts/rk3229-evb-android.dtsi b/arch/arm/boot/dts/rk3229-evb-android.dtsi index 1c1ae22e2a6e..b927af04690b 100644 --- a/arch/arm/boot/dts/rk3229-evb-android.dtsi +++ b/arch/arm/boot/dts/rk3229-evb-android.dtsi @@ -102,6 +102,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-linux.dts b/arch/arm/boot/dts/rk3288-firefly-reload-linux.dts index 0aefa4c0f9fd..b86d5b047309 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-linux.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload-linux.dts @@ -82,6 +82,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 9a4a9749c405..332917a0178c 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -74,6 +74,7 @@ sound { compatible = "simple-audio-card"; simple-audio-card,name = "SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ cpu { sound-dai = <&spdif>; }; codec { sound-dai = <&spdif_out>; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-rk808.dts b/arch/arm/boot/dts/rk3288-firefly-rk808.dts index dc418937de2d..384f400983fa 100644 --- a/arch/arm/boot/dts/rk3288-firefly-rk808.dts +++ b/arch/arm/boot/dts/rk3288-firefly-rk808.dts @@ -130,6 +130,7 @@ status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif>; }; diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index c4d1d142d8c6..bd6177c3879a 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -64,6 +64,7 @@ sound { compatible = "simple-audio-card"; simple-audio-card,name = "SPDIF"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ cpu { sound-dai = <&spdif>; }; codec { sound-dai = <&spdif_out>; }; diff --git a/arch/arm/boot/dts/rk3308-dot-v10-aarch32.dts b/arch/arm/boot/dts/rk3308-dot-v10-aarch32.dts index 315c4495b2be..384dd9ebf6b5 100644 --- a/arch/arm/boot/dts/rk3308-dot-v10-aarch32.dts +++ b/arch/arm/boot/dts/rk3308-dot-v10-aarch32.dts @@ -81,6 +81,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-tx-sound"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_tx>; }; diff --git a/arch/arm/boot/dts/rk3308-voice-module-v10-aarch32.dtsi b/arch/arm/boot/dts/rk3308-voice-module-v10-aarch32.dtsi index efff5f119ed6..46a1bb049194 100644 --- a/arch/arm/boot/dts/rk3308-voice-module-v10-aarch32.dtsi +++ b/arch/arm/boot/dts/rk3308-voice-module-v10-aarch32.dtsi @@ -112,6 +112,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-tx-sound"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_tx>; }; diff --git a/arch/arm/boot/dts/rk3308-voice-module-v11-aarch32.dtsi b/arch/arm/boot/dts/rk3308-voice-module-v11-aarch32.dtsi index 559527cc4e67..a977ea318fe3 100644 --- a/arch/arm/boot/dts/rk3308-voice-module-v11-aarch32.dtsi +++ b/arch/arm/boot/dts/rk3308-voice-module-v11-aarch32.dtsi @@ -108,6 +108,7 @@ status = "disabled"; compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,spdif-tx-sound"; + simple-audio-card,mclk-fs = <128>; simple-audio-card,cpu { sound-dai = <&spdif_tx>; }; From f67f48f03950403ed3e924091612b8b41494a1d5 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 17 Feb 2023 10:45:38 +0800 Subject: [PATCH 217/258] phy: rockchip-naneng-combo: Support phy grf reset 1.Assert phy-reset via PIPEPHY GRF instead of asserting via CRU that would be useless when PD_PHP is off. 2.RK3562 change to use phy grf reset Change-Id: Id30e8bf28c0bb8d30bab27ad069201978ec74785 Signed-off-by: Jon Lin --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 3ace49e41bbd..f12c6e1ec1bd 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -64,6 +64,7 @@ struct rockchip_combphy_grfcfg { struct combphy_reg pipe_xpcs_phy_ready; struct combphy_reg u3otg0_port_en; struct combphy_reg u3otg1_port_en; + struct combphy_reg pipe_phy_grf_reset; }; struct rockchip_combphy_cfg { @@ -252,6 +253,9 @@ static int rockchip_combphy_init(struct phy *phy) if (ret) goto err_clk; + if (cfg->pipe_phy_grf_reset.enable) + param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); + if (priv->mode == PHY_TYPE_USB3) { ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, priv, val, @@ -272,6 +276,10 @@ err_clk: static int rockchip_combphy_exit(struct phy *phy) { struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + + if (cfg->pipe_phy_grf_reset.enable) + param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); clk_bulk_disable_unprepare(priv->num_clks, priv->clks); reset_control_assert(priv->phy_rst); @@ -728,6 +736,7 @@ static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 }, /* peri-grf */ .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 }, }; From 0d285d7f917cf8d272a8f4661a38a21d5192304e Mon Sep 17 00:00:00 2001 From: Wangqiang Guo Date: Mon, 30 Jan 2023 07:39:58 +0000 Subject: [PATCH 218/258] arm64: dts: rockchip: rk3562-evb: support IR remote ctrl. Change-Id: Iea742c38e0e4fd62ff8664cc479475f5939f08ef Signed-off-by: Wangqiang Guo --- .../dts/rockchip/rk3562-evb1-lp4x-v10.dtsi | 107 ++++++++++++++++++ .../dts/rockchip/rk3562-evb2-ddr4-v10.dtsi | 107 ++++++++++++++++++ 2 files changed, 214 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi index bfd17a8d4af1..1f3a4d5fd616 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi @@ -298,6 +298,113 @@ }; }; +&pwm3 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + assigned-clocks = <&cru CLK_PMU1_PWM0>; + assigned-clock-rates = <24000000>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + &pwm6 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi index 8ed465c2b6fe..d8ee68d507c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi @@ -309,6 +309,113 @@ }; }; +&pwm3 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + assigned-clocks = <&cru CLK_PMU1_PWM0>; + assigned-clock-rates = <24000000>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + &pwm6 { status = "okay"; }; From 7cfd42e08cb5ce31e2953545e99a07cbf497532c Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Sat, 18 Feb 2023 03:30:19 +0000 Subject: [PATCH 219/258] drm/rockchip: dsi2: fix mode valid func when work in dual channel dsi Change-Id: Ib26202b9fdd908c9a3dd7d2f50f407a7c8f63c46 Signed-off-by: Guochun Huang --- .../gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index f55a3a5c5c7c..19111b487c0c 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -1000,7 +1000,9 @@ static enum drm_mode_status dw_mipi_dsi2_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { + struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector); struct videomode vm; + u8 min_pixels = dsi2->slave ? 8 : 4; drm_display_mode_to_videomode(mode, &vm); @@ -1008,21 +1010,21 @@ dw_mipi_dsi2_connector_mode_valid(struct drm_connector *connector, * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels * which is the ip known issues and limitations. */ - if (!(vm.hsync_len < 4 || vm.hback_porch < 4 || - vm.hfront_porch < 4 || vm.hactive < 4)) + if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || + vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) return MODE_OK; - if (vm.hsync_len < 4) - vm.hsync_len = 4; + if (vm.hsync_len < min_pixels) + vm.hsync_len = min_pixels; - if (vm.hback_porch < 4) - vm.hback_porch = 4; + if (vm.hback_porch < min_pixels) + vm.hback_porch = min_pixels; - if (vm.hfront_porch < 4) - vm.hfront_porch = 4; + if (vm.hfront_porch < min_pixels) + vm.hfront_porch = min_pixels; - if (vm.hactive < 4) - vm.hactive = 4; + if (vm.hactive < min_pixels) + vm.hactive = min_pixels; drm_display_mode_from_videomode(&vm, mode); From 5394193532235c5d1201f67d299cf2404793f19c Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Fri, 17 Feb 2023 20:29:57 +0800 Subject: [PATCH 220/258] ASoC: rockchip: pdm: fix channel disorder Fix channel disorder caused by "ASoC: rockchip: pdm: Fix pop noise in the beginning". The PDM device need to delete some unused data since the pdm of various manufacturers can not be stable quickly. This is done by commit "ASoC: rockchip: pdm: Fix pop noise in the beginning". But we do not know how many data we delete, this cause channel disorder. For example, we record two channel 24-bit sound, then delete some starting data. Because the deleted starting data is uncertain, the next data may be left or right channel and cause channel disorder. Luckily, we can use the PDM_RX_CLR to fix this. Use the PDM_RX_CLR to clear fifo written data and address, but can not clear the read data and address. In initial state, the read data and address are zero. Signed-off-by: Jason Zhu Change-Id: I248744c7982365adeb23aa516cf5bed346f4beaf --- sound/soc/rockchip/rockchip_pdm.c | 35 +++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c index 5d54317ed685..ae529a69d8cf 100644 --- a/sound/soc/rockchip/rockchip_pdm.c +++ b/sound/soc/rockchip/rockchip_pdm.c @@ -204,22 +204,35 @@ static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai) return snd_soc_dai_get_drvdata(dai); } -static void rockchip_pdm_drop_fifo(struct rk_pdm_dev *pdm) -{ - int cnt, val, i; - - /* drop the dirty data */ - regmap_read(pdm->regmap, PDM_FIFO_CTRL, &cnt); - for (i = 0; i < PDM_FIFO_CNT(cnt); i++) - regmap_read(pdm->regmap, PDM_RXFIFO_DATA, &val); -} - static void rockchip_pdm_rxctrl(struct rk_pdm_dev *pdm, int on) { + unsigned long flags; + if (on) { - rockchip_pdm_drop_fifo(pdm); + /* The PDM device need to delete some unused data + * since the pdm of various manufacturers can not + * be stable quickly. This is done by commit "ASoC: + * rockchip: pdm: Fix pop noise in the beginning". + * + * But we do not know how many data we delete, this + * cause channel disorder. For example, we record + * two channel 24-bit sound, then delete some starting + * data. Because the deleted starting data is uncertain, + * the next data may be left or right channel and cause + * channel disorder. + * + * Luckily, we can use the PDM_RX_CLR to fix this. + * Use the PDM_RX_CLR to clear fifo written data and + * address, but can not clear the read data and address. + * In initial state, the read data and address are zero. + */ + local_irq_save(flags); + regmap_update_bits(pdm->regmap, PDM_SYSCONFIG, + PDM_RX_CLR_MASK, + PDM_RX_CLR_WR); regmap_update_bits(pdm->regmap, PDM_DMA_CTRL, PDM_DMA_RD_MSK, PDM_DMA_RD_EN); + local_irq_restore(flags); } else { regmap_update_bits(pdm->regmap, PDM_DMA_CTRL, PDM_DMA_RD_MSK, PDM_DMA_RD_DIS); From 35b202eb29b2d3985221728d57dc82ca372ce2a0 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 20 Feb 2023 10:09:07 +0800 Subject: [PATCH 221/258] clk: rockchip: rk3562: Fix mclkin_saix clk name Should be explicit direction for mclkin, such as "mclk_sai0_from_io" instead of "mclk_sai0_io". Signed-off-by: Sugar Zhang Change-Id: I6a4a3ecad527c610cc1577faca169588545f0765 --- drivers/clk/rockchip/clk-rk3562.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c index d88791d4d529..582b213fa94a 100644 --- a/drivers/clk/rockchip/clk-rk3562.c +++ b/drivers/clk/rockchip/clk-rk3562.c @@ -169,11 +169,11 @@ PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" }; PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" }; PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" }; PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; -PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_io" }; +PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" }; PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" }; -PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_io" }; +PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_from_io" }; PNAME(mclk_sai1_out2io_p) = { "mclk_sai1", "xin_osc0_half" }; -PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_io" }; +PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_from_io" }; PNAME(mclk_sai2_out2io_p) = { "mclk_sai2", "xin_osc0_half" }; PNAME(clk_spdif_p) = { "clk_spdif_src", "clk_spdif_frac", "xin_osc0_half" }; PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; From b3cfac5e37cdd449aee04257bb18513cd429ad84 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 30 Jan 2023 09:25:18 +0800 Subject: [PATCH 222/258] clk: rockchip: Add support for clk input / output switch This patch add support switch for clk-bidirection which located at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin. and these config maybe located in many pieces of GRF, which hard to addressed in one single clk driver. so, we add this simple helper driver to address this situation. In order to simplify implement and usage, and also for safety clk usage (avoid high freq glitch), we set all clk out as disabled (which means Input default for clk-bidrection) in the pre-stage, such boot-loader or init by HW default. And then set a safety freq before enable clk-out, such as "assign-clock-rates" or clk_set_rate in drivers. e.g. 1. mclk{out,in}_sai0 define: mclkin_sai0: mclkin-sai0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <12288000>; clock-output-names = "mclk_sai0_from_io"; }; mclkout_sai0: mclkout-sai0@ff040070 { compatible = "rockchip,clk-out"; reg = <0 0xff040070 0 0x4>; clocks = <&cru MCLK_SAI0_OUT2IO>; #clock-cells = <0>; clock-output-names = "mclk_sai0_to_io"; rockchip,bit-shift = <4>; //example with PD if reg access needed power-domains = <&power RK3562_PD_VO>; }; Note: clock-output-names of mclkin_sai0 should equal to strings in drivers. such as: drivers/clk/rockchip/clk-rk3562.c: PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" }; 2. mclkout_sai0 usage: &ext_codec { clocks = <&mclkout_sai0>; clock-names = "mclk"; assigned-clocks = <&mclkout_sai0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0m0_mclk>; }; clk_summary on sai0 work: cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0" clk_sai0_src 1 1 0 1188000000 0 0 50000 clk_sai0_frac 1 1 0 12288000 0 0 50000 clk_sai0 1 1 0 12288000 0 0 50000 mclk_sai0 1 1 0 12288000 0 0 50000 mclk_sai0_out2io 1 1 0 12288000 0 0 50000 mclk_sai0_to_io 1 1 0 12288000 0 0 50000 example with PD if reg access needed: * PD status when mclk_sai0_to_io on: cat /sys/kernel/debug/pm_genpd/pm_genpd_summary domain status children /device runtime status ---------------------------------------------------------------------- ... vo on /devices/platform/clocks/ff040070.mclkout-sai0 active ... * PD status when mclk_sai0_to_io off: cat /sys/kernel/debug/pm_genpd/pm_genpd_summary domain status children /device runtime status ---------------------------------------------------------------------- ... vo off-0 /devices/platform/clocks/ff040070.mclkout-sai0 suspended ... 3. mclkin_sai0 usage: please override freq of mclkin as the real external clkin, such as: &mclkin_sai0 { clock-frequency = <24576000>; } &ext_codec { clocks = <&mclkin_sai0>; clock-names = "mclk"; assigned-clocks = <&cru CLK_SAI0>; assigned-clock-parents = <&mclkin_sai0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0m0_mclk>; }; clk_summary on sai0 work: cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0" mclk_sai0_from_io 1 1 0 12288000 0 0 50000 clk_sai0 1 1 0 12288000 0 0 50000 mclk_sai0 1 1 0 12288000 0 0 50000 mclk_sai0_out2io 0 0 0 12288000 0 0 50000 mclk_sai0_to_io 0 0 0 12288000 0 0 50000 Signed-off-by: Sugar Zhang Change-Id: Ibe8286bb98ea1fc3bc6421c30f6e46fc0b1b0d88 --- .../bindings/clock/rockchip,clk-out.yaml | 107 ++++++++++++++++++ drivers/clk/rockchip/Kconfig | 6 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-out.c | 99 ++++++++++++++++ 4 files changed, 213 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml create mode 100644 drivers/clk/rockchip/clk-out.c diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml new file mode 100644 index 000000000000..6582605ab945 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Clock Out Control Module Binding + +maintainers: + - Sugar Zhang + +description: | + This add support switch for clk-bidirection which located + at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin. + and these config maybe located in many pieces of GRF, + which hard to addressed in one single clk driver. so, we add + this simple helper driver to address this situation. + + In order to simplify implement and usage, and also for safety + clk usage (avoid high freq glitch), we set all clk out as disabled + (which means Input default for clk-bidrection) in the pre-stage, + such boot-loader or init by HW default. And then set a safety freq + before enable clk-out, such as "assign-clock-rates" or clk_set_rate + in drivers. + +properties: + compatible: + enum: + - rockchip,clk-out + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + description: parent clocks. + + power-domains: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + rockchip,bit-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Defines the bit shift of clk out enable. + + rockchip,bit-set-to-disable: + type: boolean + description: | + By default this clock sets the bit at bit-shift to enable the clock. + Setting this property does the opposite: setting the bit disable + the clock and clearing it enables the clock. + +required: + - compatible + - reg + - clocks + - "#clock-cells" + - clock-output-names + - rockchip,bit-shift + +additionalProperties: false + +examples: + # Clock Provider node: + - | + mclkin_sai0: mclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "mclk_sai0_from_io"; + }; + + mclkout_sai0: mclkout-sai0@ff040070 { + compatible = "rockchip,clk-out"; + reg = <0 0xff040070 0 0x4>; + clocks = <&cru MCLK_SAI0_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai0_to_io"; + rockchip,bit-shift = <4>; + }; + + # Clock mclkout Consumer node: + - | + ext_codec { + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + }; + + # Clock mclkin Consumer node: + - | + ext_codec { + clocks = <&mclkin_sai0>; + clock-names = "mclk"; + assigned-clocks = <&cru CLK_SAI0>; + assigned-clock-parents = <&mclkin_sai0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + }; diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index e711ba005825..3ba13a494af3 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -158,6 +158,12 @@ config ROCKCHIP_CLK_INV help Say y here to enable clk Inverter. +config ROCKCHIP_CLK_OUT + tristate "Rockchip Clk Out / Input Switch" + default y if !ROCKCHIP_MINI_KERNEL + help + Say y here to enable clk out / input switch. + config ROCKCHIP_CLK_PVTM bool "Rockchip Clk Pvtm" default y if !CPU_RV1126 && !CPU_RV1106 diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 65e7dc9c5bb1..03ddb4baaa5a 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -18,6 +18,7 @@ clk-rockchip-$(CONFIG_ROCKCHIP_CLK_PVTM) += clk-pvtm.o clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_ROCKCHIP_CLK_LINK) += clk-link.o +obj-$(CONFIG_ROCKCHIP_CLK_OUT) += clk-out.o obj-$(CONFIG_CLK_PX30) += clk-px30.o obj-$(CONFIG_CLK_RV1106) += clk-rv1106.o diff --git a/drivers/clk/rockchip/clk-out.c b/drivers/clk/rockchip/clk-out.c new file mode 100644 index 000000000000..22dcd98fbbef --- /dev/null +++ b/drivers/clk/rockchip/clk-out.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(clk_out_lock); + +static int rockchip_clk_out_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct clk_hw *hw; + struct resource *res; + const char *clk_name = node->name; + const char *parent_name; + void __iomem *reg; + u32 shift = 0; + u8 clk_gate_flags = CLK_GATE_HIWORD_MASK; + int ret; + + ret = device_property_read_string(dev, "clock-output-names", &clk_name); + if (ret) + return ret; + + ret = device_property_read_u32(dev, "rockchip,bit-shift", &shift); + if (ret) + return ret; + + if (device_property_read_bool(dev, "rockchip,bit-set-to-disable")) + clk_gate_flags |= CLK_GATE_SET_TO_DISABLE; + + ret = of_clk_parent_fill(node, &parent_name, 1); + if (ret != 1) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + + reg = devm_ioremap(dev, res->start, resource_size(res)); + if (!reg) + return -ENOMEM; + + pm_runtime_enable(dev); + + hw = clk_hw_register_gate(dev, clk_name, parent_name, CLK_SET_RATE_PARENT, + reg, shift, clk_gate_flags, &clk_out_lock); + if (IS_ERR(hw)) { + ret = -EINVAL; + goto err_disable_pm_runtime; + } + + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + return 0; + +err_disable_pm_runtime: + pm_runtime_disable(dev); + + return ret; +} + +static int rockchip_clk_out_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + + of_clk_del_provider(node); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id rockchip_clk_out_match[] = { + { .compatible = "rockchip,clk-out", }, + {}, +}; + +static struct platform_driver rockchip_clk_out_driver = { + .driver = { + .name = "rockchip-clk-out", + .of_match_table = rockchip_clk_out_match, + }, + .probe = rockchip_clk_out_probe, + .remove = rockchip_clk_out_remove, +}; + +module_platform_driver(rockchip_clk_out_driver); + +MODULE_DESCRIPTION("Rockchip Clock Input-Output-Switch"); +MODULE_AUTHOR("Sugar Zhang "); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, rockchip_clk_out_match); From afa07cbc46753d712564287efeb644e94f74a786 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 20 Feb 2023 10:07:17 +0800 Subject: [PATCH 223/258] arm64: dts: rockchip: rk3562: Add mclk{out,in}_saix device nodes Signed-off-by: Sugar Zhang Change-Id: Iff3f55286d1e209929c9667871c0f06842a4d7d1 --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 48 ++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 4b88350da734..f22152bd47af 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -133,6 +133,54 @@ #power-domain-cells = <1>; #clock-cells = <0>; }; + + mclkin_sai0: mclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "mclk_sai0_from_io"; + }; + + mclkin_sai1: mclkin-sai1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "mclk_sai1_from_io"; + }; + + mclkin_sai2: mclkin-sai2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "mclk_sai2_from_io"; + }; + + mclkout_sai0: mclkout-sai0@ff040070 { + compatible = "rockchip,clk-out"; + reg = <0 0xff040070 0 0x4>; + clocks = <&cru MCLK_SAI0_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai0_to_io"; + rockchip,bit-shift = <4>; + }; + + mclkout_sai1: mclkout-sai1@ff040070 { + compatible = "rockchip,clk-out"; + reg = <0 0xff040070 0 0x4>; + clocks = <&cru MCLK_SAI1_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai1_to_io"; + rockchip,bit-shift = <9>; + }; + + mclkout_sai2: mclkout-sai2@ff040070 { + compatible = "rockchip,clk-out"; + reg = <0 0xff040070 0 0x4>; + clocks = <&cru MCLK_SAI2_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai2_to_io"; + rockchip,bit-shift = <11>; + }; }; cpus { From 645df41e1cfa5b2237a8fa61cf38dc7a740facf7 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 20 Feb 2023 10:13:57 +0800 Subject: [PATCH 224/258] arm64: dts: rockchip: rk3562: Use mclk{out,in}_saix for devices e.g. 1. mclkout_sai0: &ext_codec { clocks = <&mclkout_sai0>; clock-names = "mclk"; assigned-clocks = <&mclkout_sai0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0m0_mclk>; }; clk_summary on sai0 work: cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0" clk_sai0_src 1 1 0 1188000000 0 0 50000 clk_sai0_frac 1 1 0 12288000 0 0 50000 clk_sai0 1 1 0 12288000 0 0 50000 mclk_sai0 1 1 0 12288000 0 0 50000 mclk_sai0_out2io 1 1 0 12288000 0 0 50000 mclk_sai0_to_io 1 1 0 12288000 0 0 50000 2. mclkin_sai0: &ext_codec { clocks = <&mclkin_sai0>; clock-names = "mclk"; assigned-clocks = <&cru CLK_SAI0>; assigned-clock-parents = <&mclkin_sai0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0m0_mclk>; }; clk_summary on sai0 work: cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0" mclk_sai0_from_io 1 1 0 12288000 0 0 50000 clk_sai0 1 1 0 12288000 0 0 50000 mclk_sai0 1 1 0 12288000 0 0 50000 mclk_sai0_out2io 0 0 0 12288000 0 0 50000 mclk_sai0_to_io 0 0 0 12288000 0 0 50000 Signed-off-by: Sugar Zhang Change-Id: Ib8441bfd0dbb69353a6492f2d406b29a26d1dba0 --- arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi index 13f19d71171c..02f91919b705 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi @@ -254,9 +254,9 @@ rk809_codec: codec { #sound-dai-cells = <1>; compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; - clocks = <&cru MCLK_SAI0_OUT2IO>; + clocks = <&mclkout_sai0>; clock-names = "mclk"; - assigned-clocks = <&cru MCLK_SAI0_OUT2IO>; + assigned-clocks = <&mclkout_sai0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0m0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts index 1ad9c6be3551..4b176101580b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts @@ -799,9 +799,9 @@ rk817_codec: codec { #sound-dai-cells = <0>; compatible = "rockchip,rk817-codec"; - clocks = <&cru MCLK_SAI0_OUT2IO>; + clocks = <&mclkout_sai0>; clock-names = "mclk"; - assigned-clocks = <&cru MCLK_SAI0_OUT2IO>; + assigned-clocks = <&mclkout_sai0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0m0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi index a89d9ca2d593..2b66e836bf2a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi @@ -242,9 +242,9 @@ rk817_codec: codec { #sound-dai-cells = <0>; compatible = "rockchip,rk817-codec"; - clocks = <&cru MCLK_SAI0_OUT2IO>; + clocks = <&mclkout_sai0>; clock-names = "mclk"; - assigned-clocks = <&cru MCLK_SAI0_OUT2IO>; + assigned-clocks = <&mclkout_sai0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0m0_mclk>; From 5d2e0b332bdbbe88461d0bc740a8e693d938ee56 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 30 Jan 2023 09:40:23 +0800 Subject: [PATCH 225/258] arm64: dts: rockchip: rk3588: Add I2Sx_MCLK{OUT,IN} nodes e.g. mclkin_i2s0: mclkin-i2s0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <12288000>; clock-output-names = "i2s0_mclkin"; }; mclkout_i2s0: mclkout-i2s0@fd58c318 { compatible = "rockchip,clk-out"; reg = <0 0xfd58c318 0 0x4>; clocks = <&cru I2S0_8CH_MCLKOUT>; #clock-cells = <0>; clock-output-names = "i2s0_mclkout_to_io"; rockchip,bit-shift = <0>; rockchip,bit-set-to-disable; }; Note: clock-output-names of mclkin_i2s0 should equal to strings in drivers. such as: drivers/clk/rockchip/clk-rk3588.c: PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; Signed-off-by: Sugar Zhang Change-Id: Iefca0d7f8b90473a1331a15b1b82f389254ca015 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 68 +++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index fd5053c69eaf..a1fc41745f59 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -295,6 +295,74 @@ clock-names = "link"; #clock-cells = <0>; }; + + mclkin_i2s0: mclkin-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s0_mclkin"; + }; + + mclkin_i2s1: mclkin-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s1_mclkin"; + }; + + mclkin_i2s2: mclkin-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s2_mclkin"; + }; + + mclkin_i2s3: mclkin-i2s3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s3_mclkin"; + }; + + mclkout_i2s0: mclkout-i2s0@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s0_mclkout_to_io"; + rockchip,bit-shift = <0>; + rockchip,bit-set-to-disable; + }; + + mclkout_i2s1: mclkout-i2s1@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru I2S1_8CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s1_mclkout_to_io"; + rockchip,bit-shift = <1>; + rockchip,bit-set-to-disable; + }; + + mclkout_i2s2: mclkout-i2s2@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru I2S2_2CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s2_mclkout_to_io"; + rockchip,bit-shift = <2>; + rockchip,bit-set-to-disable; + }; + + mclkout_i2s3: mclkout-i2s3@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru I2S3_2CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s3_mclkout_to_io"; + rockchip,bit-shift = <7>; + rockchip,bit-set-to-disable; + }; }; cpus { From c3d3a14f49c9caaa69a02aac09a4cd51432e47d7 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 21 Feb 2023 00:01:23 +0800 Subject: [PATCH 226/258] arm64: dts: rockchip: rk3588: Use mclkout_i2sx for devices replace.sh #!/bin/sh grep -lr "$1" | xargs sed -i "s/$1/$2/g" e.g. ./replace.sh "cru I2S1_8CH_MCLKOUT" "mclkout_i2s1" Signed-off-by: Sugar Zhang Change-Id: I742c35e23a54facb90cde8f9d0d2b935be69152b --- arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi | 8 ++++---- arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi | 4 ++-- .../boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi | 4 ++-- 16 files changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi index 813a8e2f1fd1..431a5bbdb641 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi @@ -501,9 +501,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi index 37d7bdfe5706..1d0ef3c5178c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi @@ -336,9 +336,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi index 3b08bb998fe9..4213e54ab0b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi @@ -994,9 +994,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi index 4faf8ada7a43..69a328b2c8d7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi @@ -571,9 +571,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi index bf8fd852d028..ecbc0b5718bc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi @@ -648,9 +648,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi index 02c4202b3d52..5c345b2cde2d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi @@ -355,9 +355,9 @@ adc-volume = <0xbf>; /* 0dB */ dac-volume = <0xbf>; /* 0dB */ aec-mode = "adc left, adc right"; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi index 9f8768cec79e..1dbb39cd381e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi @@ -527,9 +527,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi index ea8cab776e77..812f7b113cf5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi @@ -521,9 +521,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb.dtsi index 7c5bc3ea7e05..166bcd049890 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb.dtsi @@ -375,9 +375,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi index 2396a91d06a1..68f17eec6956 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi @@ -309,9 +309,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; @@ -322,9 +322,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8326"; reg = <0x18>; - clocks = <&cru I2S1_8CH_MCLKOUT>; + clocks = <&mclkout_i2s1>; clock-names = "mclk"; - assigned-clocks = <&cru I2S1_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s1>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s1m0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi index 263bdfe3bd70..d2a17c411b8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi @@ -823,9 +823,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi index d61d365c80dc..ee707d4820fc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi @@ -465,7 +465,7 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi index a9e68fe49ee8..4e0cc72ff2ac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi @@ -353,9 +353,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi index 4357661eac4c..5799b980d15e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi @@ -1205,7 +1205,7 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi index 71d24d238f81..b9a9ef526170 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi @@ -528,9 +528,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi index 21c5e721d4cc..e8652e4f0639 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi @@ -460,9 +460,9 @@ #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; + clocks = <&mclkout_i2s0>; clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&mclkout_i2s0>; assigned-clock-rates = <12288000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_mclk>; From a0538ddf89d36d62a40b033afef2fa680969032c Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 17 Feb 2023 20:00:17 +0800 Subject: [PATCH 227/258] mtd: spinand: dosilicon: Support new devices DS35Q12B, DS35M12B Change-Id: I8e4bf56f1cb1873c9b11858cfb567b276d980e14 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/dosilicon.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/mtd/nand/spi/dosilicon.c b/drivers/mtd/nand/spi/dosilicon.c index ab9f4e258781..d6e38ae71f08 100644 --- a/drivers/mtd/nand/spi/dosilicon.c +++ b/drivers/mtd/nand/spi/dosilicon.c @@ -193,6 +193,26 @@ static const struct spinand_info dosilicon_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q12B", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF5), + NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, + ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35M12B", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5), + NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, + ds35xxgb_ecc_get_status)), }; static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = { From 66b04a5c5f07c61cff13c5004bd305b0f4c446c4 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Mon, 12 Dec 2022 19:57:55 +0800 Subject: [PATCH 228/258] drm: bridge: dw-hdmi: Set rk3528 hpd status when resume Signed-off-by: Algea Cao Change-Id: I105e9a8c44dfd4ea78af406c011b3b7eb1c8f742 --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index ce4a17dcb780..c26e60617827 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -3737,8 +3737,10 @@ static int dw_hdmi_rockchip_resume(struct device *dev) enable_irq(hdmi->hpd_irq); drm_helper_hpd_irq_event(hdmi->drm_dev); } else { - if (hdmi->hpd_gpiod) + if (hdmi->hpd_gpiod) { + dw_hdmi_rk3528_gpio_hpd_init(hdmi); enable_irq(hdmi->hpd_irq); + } dw_hdmi_resume(hdmi->hdmi); } pm_runtime_get_sync(dev); From 5d81881b45c0a46a60c62ee5adb357a333793835 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Wed, 8 Feb 2023 17:47:56 +0800 Subject: [PATCH 229/258] drm/rockchip: Support parse edid colorimetry Signed-off-by: Algea Cao Change-Id: I051adb0d5fa5ecfa95cebb13539c440646512a77 --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 2 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 ++ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 +++++ drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 44 ++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 + include/drm/bridge/dw_hdmi.h | 2 + 6 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index 262b9e1d45da..cb18cf2fd388 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -2109,6 +2109,8 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) if (hdmi->plat_data->get_edid_dsc_info) hdmi->plat_data->get_edid_dsc_info(data, edid); ret = drm_add_edid_modes(connector, edid); + if (hdmi->plat_data->get_colorimetry) + hdmi->plat_data->get_colorimetry(data, edid); dw_hdmi_update_hdr_property(connector); if (ret > 0 && hdmi->plat_data->split_mode) { struct dw_hdmi_qp *secondary = NULL; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 3918df0ffb58..09e66d8818c4 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2945,6 +2945,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) struct edid *edid; struct drm_display_mode *mode; struct drm_display_info *info = &connector->display_info; + void *data = hdmi->plat_data->phy_data; int i, ret = 0; memset(metedata, 0, sizeof(*metedata)); @@ -2959,6 +2960,8 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) ret = drm_add_edid_modes(connector, edid); if (hdmi->plat_data->get_color_changed) hdmi->plat_data->get_yuv422_format(connector, edid); + if (hdmi->plat_data->get_colorimetry) + hdmi->plat_data->get_colorimetry(data, edid); list_for_each_entry(mode, &connector->probed_modes, head) { vic = drm_match_cea_mode(mode); diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index c26e60617827..ca11c4b53987 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -231,6 +231,7 @@ struct rockchip_hdmi { u8 max_frl_rate_per_lane; u8 max_lanes; u8 add_func; + u8 edid_colorimetry; struct rockchip_drm_dsc_cap dsc_cap; struct next_hdr_sink_data next_hdr_data; struct dw_hdmi_link_config link_cfg; @@ -2332,6 +2333,13 @@ dw_hdmi_rockchip_get_next_hdr_data(void *data, struct edid *edid, return ret; }; +static int dw_hdmi_rockchip_get_colorimetry(void *data, struct edid *edid) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return rockchip_drm_parse_colorimetry_data_block(&hdmi->edid_colorimetry, edid); +} + static struct dw_hdmi_link_config *dw_hdmi_rockchip_get_link_cfg(void *data) { @@ -3321,6 +3329,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, dw_hdmi_rockchip_get_edid_dsc_info; plat_data->get_next_hdr_data = dw_hdmi_rockchip_get_next_hdr_data; + plat_data->get_colorimetry = + dw_hdmi_rockchip_get_colorimetry; plat_data->get_link_cfg = dw_hdmi_rockchip_get_link_cfg; plat_data->set_grf_cfg = rk3588_set_grf_cfg; plat_data->get_grf_color_fmt = rk3588_get_grf_color_fmt; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 212191aa8cd2..5dfa4583008b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -987,6 +987,50 @@ int rockchip_drm_parse_next_hdr(struct next_hdr_sink_data *sink_data, } EXPORT_SYMBOL(rockchip_drm_parse_next_hdr); +#define COLORIMETRY_DATA_BLOCK 0x5 +#define USE_EXTENDED_TAG 0x07 + +static bool cea_db_is_hdmi_colorimetry_data_block(const u8 *db) +{ + if (cea_db_tag(db) != USE_EXTENDED_TAG) + return false; + + if (db[1] != COLORIMETRY_DATA_BLOCK) + return false; + + return true; +} + +int +rockchip_drm_parse_colorimetry_data_block(u8 *colorimetry, const struct edid *edid) +{ + const u8 *edid_ext; + int i, start, end; + + if (!colorimetry || !edid) + return -EINVAL; + + *colorimetry = 0; + + edid_ext = find_cea_extension(edid); + if (!edid_ext) + return -EINVAL; + + if (cea_db_offsets(edid_ext, &start, &end)) + return -EINVAL; + + for_each_cea_db(edid_ext, i, start, end) { + const u8 *db = &edid_ext[i]; + + if (cea_db_is_hdmi_colorimetry_data_block(db)) + /* As per CEA 861-G spec */ + *colorimetry = ((db[3] & (0x1 << 7)) << 1) | db[2]; + } + + return 0; +} +EXPORT_SYMBOL(rockchip_drm_parse_colorimetry_data_block); + /* * Attach a (component) device to the shared drm dma mapping from master drm * device. This is used by the VOPs to map GEM buffers to a common DMA diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index 224c0f346c65..2b7293505a9a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -525,6 +525,8 @@ int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap, const struct edid *edid); int rockchip_drm_parse_next_hdr(struct next_hdr_sink_data *sink_data, const struct edid *edid); +int rockchip_drm_parse_colorimetry_data_block(u8 *colorimetry, const struct edid *edid); + __printf(3, 4) void rockchip_drm_dbg(const struct device *dev, enum rockchip_drm_debug_category category, const char *format, ...); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index 5a2352981d24..e7365e9e4df6 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -254,6 +254,8 @@ struct dw_hdmi_plat_data { int (*get_vp_id)(struct drm_crtc_state *crtc_state); void (*update_color_format)(struct drm_connector_state *conn_state, void *data); bool (*check_hdr_color_change)(struct drm_connector_state *conn_state, void *data); + int (*get_colorimetry)(void *data, struct edid *edid); + void (*set_prev_bus_format)(void *data, unsigned long bus_format); /* Vendor Property support */ const struct dw_hdmi_property_ops *property_ops; From 053a921a195ec0d433e99c006a27643d4c633a6d Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Wed, 8 Feb 2023 17:29:50 +0800 Subject: [PATCH 230/258] drm: bridge: dw-hdmi: Support BT709 hdr and 8-bit hdr output Signed-off-by: Algea Cao Change-Id: If9a90c05f98f39aa2481aec9a4b2fa5378313f45 --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 42 +++++++++++++++++-- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 45 +++++++++++++++------ include/drm/bridge/dw_hdmi.h | 2 +- 3 files changed, 72 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 09e66d8818c4..2a4ed62e06e0 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2279,6 +2279,11 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); + /* + * avi and hdr infoframe cannot be sent at the same time + * for compatibility with Huawei TV + */ + mdelay(50); hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); @@ -2639,6 +2644,9 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; + if (hdmi->plat_data->set_prev_bus_format) + hdmi->plat_data->set_prev_bus_format(data, hdmi->hdmi_data.enc_out_bus_format); + /* TOFIX: Get input encoding from plat data or fallback to none */ if (hdmi->plat_data->get_enc_in_encoding) hdmi->hdmi_data.enc_in_encoding = @@ -3032,9 +3040,31 @@ static bool hdr_metadata_equal(const struct drm_connector_state *old_state, { struct drm_property_blob *old_blob = old_state->hdr_output_metadata; struct drm_property_blob *new_blob = new_state->hdr_output_metadata; + int i; + u8 *data; - if (!old_blob || !new_blob) - return old_blob == new_blob; + if (!old_blob && !new_blob) + return true; + + if (!old_blob) { + data = (u8 *)new_blob->data; + + for (i = 0; i < new_blob->length; i++) + if (data[i]) + return false; + + return true; + } + + if (!new_blob) { + data = (u8 *)old_blob->data; + + for (i = 0; i < old_blob->length; i++) + if (data[i]) + return false; + + return true; + } if (old_blob->length != new_blob->length) return false; @@ -3048,8 +3078,10 @@ static bool check_hdr_color_change(struct drm_connector_state *old_state, { void *data = hdmi->plat_data->phy_data; - if (!hdr_metadata_equal(old_state, new_state)) - return hdmi->plat_data->check_hdr_color_change(new_state, data); + if (!hdr_metadata_equal(old_state, new_state)) { + hdmi->plat_data->check_hdr_color_change(new_state, data); + return true; + } return false; } @@ -3083,6 +3115,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, * drm_display_mode and set phy status to enabled. */ if (!vmode->mpixelclock) { + hdmi->curr_conn = connector; + if (hdmi->plat_data->get_enc_in_encoding) hdmi->hdmi_data.enc_in_encoding = hdmi->plat_data->get_enc_in_encoding(data); diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index ca11c4b53987..9d53a137c57d 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -201,6 +201,7 @@ struct rockchip_hdmi { unsigned long bus_format; unsigned long output_bus_format; unsigned long enc_out_encoding; + unsigned long prev_bus_format; int color_changed; int hpd_irq; @@ -1870,6 +1871,7 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state, unsigned int color_depth; bool support_dc = false; bool sink_is_hdmi = true; + bool yuv422_out = false; u32 max_tmds_clock = info->max_tmds_clock; int output_eotf; @@ -1962,21 +1964,29 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state, hdmi->colorimetry = conn_state->colorspace; - if ((*eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR && - conn_state->connector->hdr_sink_metadata.hdmi_type1.eotf & - BIT(*eotf)) || ((hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_CYCC) && - (hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_YCC))) + /* bt2020 sdr/hdr output */ + if ((hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_CYCC) && + (hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_YCC) && + hdmi->edid_colorimetry & (BIT(6) | BIT(7))) { *enc_out_encoding = V4L2_YCBCR_ENC_BT2020; - else if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || - (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) - *enc_out_encoding = V4L2_YCBCR_ENC_601; - else + yuv422_out = true; + /* bt709 hdr output */ + } else if ((hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_CYCC) && + (hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_YCC) && + (conn_state->connector->hdr_sink_metadata.hdmi_type1.eotf & BIT(*eotf) && + *eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR)) { *enc_out_encoding = V4L2_YCBCR_ENC_709; + yuv422_out = true; + } else if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || + (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) { + *enc_out_encoding = V4L2_YCBCR_ENC_601; + } else { + *enc_out_encoding = V4L2_YCBCR_ENC_709; + } - if (*enc_out_encoding == V4L2_YCBCR_ENC_BT2020 && color_depth == 8) { - /* BT2020 require color depth at lest 10bit */ - color_depth = 10; - /* We prefer use YCbCr422 to send 10bit */ + if ((yuv422_out || hdmi->hdmi_output == RK_IF_FORMAT_YCBCR_HQ) && + color_depth == 10 && hdmi_bus_fmt_color_depth(hdmi->prev_bus_format) == 8) { + /* We prefer use YCbCr422 to send hdr 10bit */ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) *color_format = RK_IF_FORMAT_YCBCR422; if (hdmi->is_hdmi_qp) { @@ -2433,6 +2443,13 @@ dw_hdmi_rockchip_check_hdr_color_change(struct drm_connector_state *conn_state, return false; } +static void dw_hdmi_rockchip_set_prev_bus_format(void *data, unsigned long bus_format) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + hdmi->prev_bus_format = bus_format; +} + static const struct drm_prop_enum_list color_depth_enum_list[] = { { 0, "Automatic" }, /* Prefer highest color depth */ { 8, "24bit" }, @@ -2515,6 +2532,7 @@ dw_hdmi_rockchip_attach_properties(struct drm_connector *connector, } hdmi->bus_format = color; + hdmi->prev_bus_format = color; if (hdmi->hdmi_output == RK_IF_FORMAT_YCBCR422) { if (hdmi->colordepth == 12) @@ -3211,6 +3229,7 @@ static const struct dw_hdmi_plat_data rk3528_hdmi_drv_data = { .phy_ops = &rk3528_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", .phy_force_vendor = true, + .use_drm_infoframe = true, .ycbcr_420_allowed = true, }; @@ -3343,6 +3362,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, dw_hdmi_rockchip_update_color_format; plat_data->check_hdr_color_change = dw_hdmi_rockchip_check_hdr_color_change; + plat_data->set_prev_bus_format = + dw_hdmi_rockchip_set_prev_bus_format; plat_data->property_ops = &dw_hdmi_rockchip_property_ops; secondary = rockchip_hdmi_find_by_id(dev->driver, !hdmi->id); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index e7365e9e4df6..306d504a531e 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -254,8 +254,8 @@ struct dw_hdmi_plat_data { int (*get_vp_id)(struct drm_crtc_state *crtc_state); void (*update_color_format)(struct drm_connector_state *conn_state, void *data); bool (*check_hdr_color_change)(struct drm_connector_state *conn_state, void *data); - int (*get_colorimetry)(void *data, struct edid *edid); void (*set_prev_bus_format)(void *data, unsigned long bus_format); + int (*get_colorimetry)(void *data, struct edid *edid); /* Vendor Property support */ const struct dw_hdmi_property_ops *property_ops; From 9828e0f315e0bdefae455676502d374be54e9161 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Tue, 3 Jan 2023 10:49:48 +0800 Subject: [PATCH 231/258] drm: bridge: dw-hdmi: Don't go to seamless switching process when hdmi plug in Signed-off-by: Algea Cao Change-Id: Ib2884ba796baa051972c032fad3e8117cb6dcc30 --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 2a4ed62e06e0..ffc59800e3f3 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -3166,7 +3166,7 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, if (hdmi->hdmi_data.video_mode.mpixelclock == (mode->clock * 1000) && hdmi->hdmi_data.video_mode.mtmdsclock == (mtmdsclk * 1000) && - !hdmi->logo_plug_out) { + !hdmi->logo_plug_out && !hdmi->disabled) { hdmi->update = true; hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP); mdelay(50); From b2e231e53f259215e5096f68d936944388f89621 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Wed, 4 Jan 2023 14:29:10 +0800 Subject: [PATCH 232/258] drm: bridge: dw-hdmi: Send audio uevent when play hdr video Signed-off-by: Algea Cao Change-Id: I349b862d2a918f5938b149b0d52ed9fc840b5a4b --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index ffc59800e3f3..30dfb029c45b 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -3170,6 +3170,7 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, hdmi->update = true; hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP); mdelay(50); + handle_plugged_change(hdmi, false); } else { hdmi->update = false; crtc_state->mode_changed = true; @@ -3233,6 +3234,7 @@ static void dw_hdmi_connector_atomic_commit(struct drm_connector *connector, if (hdmi->update) { dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); mdelay(50); + handle_plugged_change(hdmi, true); hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP); hdmi->update = false; } @@ -3831,6 +3833,7 @@ static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, mutex_lock(&hdmi->mutex); hdmi->disabled = true; + handle_plugged_change(hdmi, false); hdmi->curr_conn = NULL; dw_hdmi_update_power(hdmi); dw_hdmi_update_phy_mask(hdmi); @@ -3852,6 +3855,7 @@ static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, hdmi->curr_conn = connector; dw_hdmi_update_power(hdmi); dw_hdmi_update_phy_mask(hdmi); + handle_plugged_change(hdmi, true); mutex_unlock(&hdmi->mutex); } From b74c9ae9347ea2838abdafc09b8e409e275048d3 Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Thu, 5 Jan 2023 15:39:24 +0800 Subject: [PATCH 233/258] drm: bridge: dw-hdmi: Update hdr panel metadata when can't get edid Signed-off-by: Algea Cao Change-Id: Ide73e5f10a591a9f85061461fa34a66bc3ac5d95 --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 30dfb029c45b..86a62c61a476 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2982,7 +2982,6 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) } } - dw_hdmi_update_hdr_property(connector); kfree(edid); } else { hdmi->support_hdmi = true; @@ -3008,6 +3007,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) dev_info(hdmi->dev, "failed to get edid\n"); } + dw_hdmi_update_hdr_property(connector); dw_hdmi_check_output_type_changed(hdmi); return ret; From e965510afec9995cbad94182e3f622457bd745fb Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Tue, 31 Jan 2023 18:26:17 +0800 Subject: [PATCH 234/258] drm: bridge: dw-hdmi: clear overflow when switch color format Signed-off-by: Algea Cao Change-Id: I98682e8cc085829fd9fde16d7e14efa08ab8128a --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 86a62c61a476..721b5857331c 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2539,8 +2539,6 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) unsigned int i; u8 val; - if (hdmi->update) - return; /* * Under some circumstances the Frame Composer arithmetic unit can miss * an FC register write due to being busy processing the previous one. @@ -2584,8 +2582,6 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) { - if (hdmi->update) - return; hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, HDMI_IH_MUTE_FC_STAT2); } From a93d8eea5982089177ce56bc5eab30a884d7ad9e Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Wed, 1 Feb 2023 11:25:45 +0800 Subject: [PATCH 235/258] drm: bridge: dw-hdmi: Fix 1080p RGB/YUV444 10BIT display blur If set default phase to 1, 1080p RGB/YUV444 10BIT display blur when switch from 4K YUV420 8BIT. Signed-off-by: Algea Cao Change-Id: I8ccd1cef40f3e47ce481a176a41c569ab2932b83 --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 721b5857331c..30346c8ddd3d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1486,14 +1486,7 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi) HDMI_VP_CONF_PR_EN_MASK | HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); - if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) || - (color_depth == 6 && hdmi->previous_mode.htotal % 2)) - hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, - HDMI_VP_STUFF); - else - hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, - HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); - + hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { From 5ba3ec652a63983ee351d1bf5b39216903d4ff6c Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Thu, 16 Feb 2023 15:30:31 +0800 Subject: [PATCH 236/258] ASoC: rockchip: mdais: Skip DAIs which have no channel mapping There is no need to start DAIs which have no channel mapping. Signed-off-by: Sugar Zhang Change-Id: Ia6be32d474845b9ecb443c38b6801e9836e8a77a --- sound/soc/rockchip/rockchip_multi_dais.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sound/soc/rockchip/rockchip_multi_dais.c b/sound/soc/rockchip/rockchip_multi_dais.c index 7ef37d470831..e52be215dab1 100644 --- a/sound/soc/rockchip/rockchip_multi_dais.c +++ b/sound/soc/rockchip/rockchip_multi_dais.c @@ -80,9 +80,19 @@ static int rockchip_mdais_trigger(struct snd_pcm_substream *substream, { struct rk_mdais_dev *mdais = to_info(dai); struct snd_soc_dai *child; + unsigned int *channel_maps; int ret = 0, i = 0; + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + channel_maps = mdais->playback_channel_maps; + else + channel_maps = mdais->capture_channel_maps; + for (i = 0; i < mdais->num_dais; i++) { + /* skip DAIs which have no channel mapping */ + if (!channel_maps[i]) + continue; + child = mdais->dais[i].dai; if (child->driver->ops && child->driver->ops->trigger) { ret = child->driver->ops->trigger(substream, From f0dbc8bbb00b03bcdfb87f30cfc66a6d43283adc Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 14 Feb 2023 10:07:50 +0800 Subject: [PATCH 237/258] drivers: rkflash: Support sfc ver6 and sfc ver8 Change-Id: I21b11e414ab48c7b3ae7dd8e6ab9dc1e8bcadee6 Signed-off-by: Jon Lin --- drivers/rkflash/sfc.c | 10 +++++++--- drivers/rkflash/sfc.h | 2 ++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/rkflash/sfc.c b/drivers/rkflash/sfc.c index 8237e765cdf8..44a14792a90d 100644 --- a/drivers/rkflash/sfc.c +++ b/drivers/rkflash/sfc.c @@ -42,12 +42,16 @@ u32 sfc_get_max_iosize(void) u32 sfc_get_max_dll_cells(void) { - if (sfc_get_version() == SFC_VER_5) + switch (sfc_get_version()) { + case SFC_VER_8: + case SFC_VER_6: + case SFC_VER_5: return SCLK_SMP_SEL_MAX_V5; - else if (sfc_get_version() == SFC_VER_4) + case SFC_VER_4: return SCLK_SMP_SEL_MAX_V4; - else + default: return 0; + } } void sfc_set_delay_lines(u16 cells) diff --git a/drivers/rkflash/sfc.h b/drivers/rkflash/sfc.h index 8e91c376acf0..918811a5cb3f 100644 --- a/drivers/rkflash/sfc.h +++ b/drivers/rkflash/sfc.h @@ -8,6 +8,8 @@ #define SFC_VER_3 0x3 #define SFC_VER_4 0x4 #define SFC_VER_5 0x5 +#define SFC_VER_6 0x6 +#define SFC_VER_8 0x8 #define SFC_EN_INT (0) /* enable interrupt */ #define SFC_EN_DMA (1) /* enable dma */ From 9cd6a5c06d786e5ce26da88fea7c9307c27793a6 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 14 Feb 2023 10:08:06 +0800 Subject: [PATCH 238/258] drivers: rkflash: Support new devices Change-Id: Ieb7a1217a92d47581faf0ac3dfcd4db78b84f098 Signed-off-by: Jon Lin --- drivers/rkflash/sfc_nand.c | 91 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 88 insertions(+), 3 deletions(-) diff --git a/drivers/rkflash/sfc_nand.c b/drivers/rkflash/sfc_nand.c index ddb7861880f2..f0eeec956fd8 100644 --- a/drivers/rkflash/sfc_nand.c +++ b/drivers/rkflash/sfc_nand.c @@ -22,6 +22,7 @@ static u32 sfc_nand_get_ecc_status5(void); static u32 sfc_nand_get_ecc_status6(void); static u32 sfc_nand_get_ecc_status7(void); static u32 sfc_nand_get_ecc_status8(void); +static u32 sfc_nand_get_ecc_status9(void); static struct nand_info spi_nand_tbl[] = { /* TC58CVG0S0HxAIx */ @@ -47,6 +48,12 @@ static struct nand_info spi_nand_tbl[] = { { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, /* MX35UF2GE4AC */ { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, + /* MX35UF1GE4AD */ + { 0xC2, 0x96, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, + /* MX35UF2GE4AD */ + { 0xC2, 0xA6, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, + /* MX35UF4GE4AD */ + { 0xC2, 0xB7, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, /* GD5F1GQ4UAYIG */ { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, @@ -61,11 +68,23 @@ static struct nand_info spi_nand_tbl[] = { /* GD5F1GQ4R */ { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, /* GD5F4GQ6RExxG 1*4096 */ - { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, + { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 }, /* GD5F4GQ6UExxG 1*4096 */ - { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, + { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 }, /* GD5F1GQ4UExxH */ { 0xC8, 0xD9, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, + /* GD5F1GQ5REYIG */ + { 0xC8, 0x41, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, + /* GD5F2GQ5REYIG */ + { 0xC8, 0x42, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, + /* GD5F2GM7RxG */ + { 0xC8, 0x82, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, + /* GD5F2GM7UxG */ + { 0xC8, 0x92, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, + /* GD5F1GM7UxG */ + { 0xC8, 0x91, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, + /* GD5F4GQ4UAYIG 1*4096 */ + { 0xC8, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, /* W25N01GV */ { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, @@ -74,9 +93,13 @@ static struct nand_info spi_nand_tbl[] = { /* W25N04KVZEIR */ { 0xEF, 0xAA, 0x23, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 0, { 0x04, 0x14, 0x24, 0x34 }, &sfc_nand_get_ecc_status0 }, /* W25N01GW */ - { 0xEF, 0xBA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, + { 0xEF, 0xBA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* W25N02KW */ + { 0xEF, 0xBA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, /* W25N512GVEIG */ { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* W25N01KV */ + { 0xEF, 0xAE, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, /* HYF2GQ4UAACAE */ { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, @@ -103,6 +126,12 @@ static struct nand_info spi_nand_tbl[] = { { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* F35SQA001G */ { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* F35SQA002G */ + { 0xCD, 0x72, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* F35SQA512M */ + { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* F35UQA512M */ + { 0xCD, 0x60, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* DS35Q1GA-IB */ { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, @@ -110,8 +139,16 @@ static struct nand_info spi_nand_tbl[] = { { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* DS35M1GA-1B */ { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* DS35M2GA-IB */ + { 0xE5, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* DS35Q1GB-IB */ + { 0xE5, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, /* DS35Q2GB-IB */ { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, + /* DS35Q4GM */ + { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, + /* DS35M1GB-IB */ + { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, /* EM73C044VCC-H */ { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, @@ -152,6 +189,8 @@ static struct nand_info spi_nand_tbl[] = { { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* FM25S02A */ { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* FM25LS01 */ + { 0xA1, 0xA5, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* IS37SML01G1 */ { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, @@ -165,6 +204,12 @@ static struct nand_info spi_nand_tbl[] = { { 0xBF, 0x21, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, /* SGM7000I-S24W1GH */ { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + /* TX25G01 */ + { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, + /* S35ML02G3 */ + { 0x01, 0x25, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, + /* S35ML04G3 */ + { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, }; static struct nand_info *p_nand_info; @@ -689,6 +734,46 @@ static u32 sfc_nand_get_ecc_status8(void) return ret; } +/* + * ecc spectial type9: + * ecc bits: 0xC0[4,5] + * 0b00, No bit errors were detected + * 0b01, 1-2Bit errors were detected and corrected. + * 0b10, 3-4Bit errors were detected and corrected. + * 0b11, 11 can be used as uncorrectable + */ +static u32 sfc_nand_get_ecc_status9(void) +{ + u32 ret; + u32 i; + u8 ecc; + u8 status; + u32 timeout = 1000 * 1000; + + for (i = 0; i < timeout; i++) { + ret = sfc_nand_read_feature(0xC0, &status); + + if (ret != SFC_OK) + return SFC_NAND_ECC_ERROR; + + if (!(status & (1 << 0))) + break; + + sfc_delay(1); + } + + ecc = (status >> 4) & 0x03; + + if (ecc <= 1) + ret = SFC_NAND_ECC_OK; + else if (ecc == 2) + ret = SFC_NAND_ECC_REFRESH; + else + ret = (u32)SFC_NAND_ECC_ERROR; + + return ret; +} + u32 sfc_nand_erase_block(u8 cs, u32 addr) { int ret; From 3fb2e28edd06d378e59b84a544e0e7483953a8a5 Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Thu, 16 Feb 2023 10:17:41 +0800 Subject: [PATCH 239/258] video: rockchip: mpp: change the way to refresh the dma cache Signed-off-by: Yandong Lin Change-Id: I0a929cb896069d7bc4a782f19e2fde4de5dc58db --- drivers/video/rockchip/mpp/mpp_iommu.c | 46 +++++++++++++++++++++++- drivers/video/rockchip/mpp/mpp_iommu.h | 3 ++ drivers/video/rockchip/mpp/mpp_rkvenc2.c | 46 ++++++++++-------------- drivers/video/rockchip/mpp/mpp_vepu2.c | 33 +++++++---------- 4 files changed, 79 insertions(+), 49 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_iommu.c b/drivers/video/rockchip/mpp/mpp_iommu.c index 5ba44f54f5fe..612813bf615d 100644 --- a/drivers/video/rockchip/mpp/mpp_iommu.c +++ b/drivers/video/rockchip/mpp/mpp_iommu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,7 @@ #include "mpp_iommu.h" #include "mpp_common.h" -static struct mpp_dma_buffer * +struct mpp_dma_buffer * mpp_dma_find_buffer_fd(struct mpp_dma_session *dma, int fd) { struct dma_buf *dmabuf; @@ -374,6 +375,49 @@ mpp_dma_session_create(struct device *dev, u32 max_buffers) return dma; } +/* + * begin cpu access => for_cpu = true + * end cpu access => for_cpu = false + */ +void mpp_dma_buf_sync(struct mpp_dma_buffer *buffer, u32 offset, u32 length, + enum dma_data_direction dir, bool for_cpu) +{ + struct scatterlist *sg; + unsigned int len = 0; + dma_addr_t sg_dma_addr; + int i; + struct sg_table *sgt = buffer->sgt; + struct device *dev = buffer->dma->dev; + + for_each_sgtable_sg(sgt, sg, i) { + unsigned int sg_offset, sg_left, size = 0; + + sg_dma_addr = sg_dma_address(sg); + + len += sg->length; + if (len <= offset) + continue; + + sg_left = len - offset; + sg_offset = sg->length - sg_left; + + size = (length < sg_left) ? length : sg_left; + + if (for_cpu) + dma_sync_single_range_for_cpu(dev, sg_dma_addr, + sg_offset, size, dir); + else + dma_sync_single_range_for_device(dev, sg_dma_addr, + sg_offset, size, dir); + + offset += size; + length -= size; + + if (length == 0) + break; + } +} + int mpp_iommu_detach(struct mpp_iommu_info *info) { if (!info) diff --git a/drivers/video/rockchip/mpp/mpp_iommu.h b/drivers/video/rockchip/mpp/mpp_iommu.h index 4419741e5fb0..12c2044d6318 100644 --- a/drivers/video/rockchip/mpp/mpp_iommu.h +++ b/drivers/video/rockchip/mpp/mpp_iommu.h @@ -103,6 +103,9 @@ int mpp_dma_unmap_kernel(struct mpp_dma_session *dma, struct mpp_dma_buffer *buffer); int mpp_dma_map_kernel(struct mpp_dma_session *dma, struct mpp_dma_buffer *buffer); +struct mpp_dma_buffer *mpp_dma_find_buffer_fd(struct mpp_dma_session *dma, int fd); +void mpp_dma_buf_sync(struct mpp_dma_buffer *buffer, u32 offset, u32 length, + enum dma_data_direction dir, bool for_cpu); struct mpp_iommu_info * mpp_iommu_probe(struct device *dev); diff --git a/drivers/video/rockchip/mpp/mpp_rkvenc2.c b/drivers/video/rockchip/mpp/mpp_rkvenc2.c index 4d911088f215..4a808f32074e 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvenc2.c +++ b/drivers/video/rockchip/mpp/mpp_rkvenc2.c @@ -228,7 +228,7 @@ struct rkvenc_task { DECLARE_KFIFO(slice_info, union rkvenc2_slice_len_info, RKVENC_MAX_SLICE_FIFO_LEN); /* jpege bitstream */ - struct dma_buf *dmabuf_bs; + struct mpp_dma_buffer *bs_buf; u32 offset_bs; }; @@ -915,6 +915,7 @@ static void *rkvenc_alloc_task(struct mpp_session *session, u32 off; const u16 *tbl; struct rkvenc_hw_info *hw = task->hw_info; + int fd_bs = -1; for (i = 0; i < hw->fd_class; i++) { u32 class = hw->fd_reg[i].class; @@ -925,22 +926,13 @@ static void *rkvenc_alloc_task(struct mpp_session *session, if (!reg) continue; - if (fmt == RKVENC_FMT_JPEGE && class == RKVENC_CLASS_PIC && - !task->dmabuf_bs) { - int bs_fd, bs_index; - struct dma_buf *dmabuf_bs; + if (fmt == RKVENC_FMT_JPEGE && class == RKVENC_CLASS_PIC && fd_bs == -1) { + int bs_index; bs_index = mpp->var->trans_info[fmt].table[2]; - bs_fd = reg[bs_index]; + fd_bs = reg[bs_index]; task->offset_bs = mpp_query_reg_offset_info(&task->off_inf, bs_index + ss); - dmabuf_bs = dma_buf_get(bs_fd); - if (!IS_ERR(dmabuf_bs)) { - dma_buf_end_cpu_access_partial(dmabuf_bs, - DMA_TO_DEVICE, - 0, task->offset_bs); - task->dmabuf_bs = dmabuf_bs; - } } ret = mpp_translate_reg_address(session, mpp_task, fmt, reg, NULL); @@ -955,6 +947,17 @@ static void *rkvenc_alloc_task(struct mpp_session *session, reg[tbl[j]] += off; } } + + if (fd_bs >= 0) { + struct mpp_dma_buffer *bs_buf = + mpp_dma_find_buffer_fd(session->dma, fd_bs); + + if (bs_buf && task->offset_bs > 0) { + mpp_dma_buf_sync(bs_buf, 0, task->offset_bs, + DMA_TO_DEVICE, false); + task->bs_buf = bs_buf; + } + } } rkvenc2_setup_task_id(session->index, task); task->clk_mode = CLK_MODE_NORMAL; @@ -965,11 +968,6 @@ static void *rkvenc_alloc_task(struct mpp_session *session, return mpp_task; fail: - if (task->dmabuf_bs) { - dma_buf_put(task->dmabuf_bs); - task->dmabuf_bs = NULL; - task->offset_bs = 0; - } mpp_task_dump_mem_region(mpp, mpp_task); mpp_task_dump_reg(mpp, mpp_task); mpp_task_finalize(session, mpp_task); @@ -1408,11 +1406,11 @@ static int rkvenc_finish(struct mpp_dev *mpp, struct mpp_task *mpp_task) } - if (task->dmabuf_bs) { + if (task->bs_buf) { u32 bs_size = mpp_read(mpp, 0x4064); - dma_buf_begin_cpu_access_partial(task->dmabuf_bs, DMA_FROM_DEVICE, 0, - bs_size / 8 + task->offset_bs); + mpp_dma_buf_sync(task->bs_buf, 0, bs_size / 8 + task->offset_bs, + DMA_FROM_DEVICE, true); } /* revert hack for irq status */ @@ -1456,12 +1454,6 @@ static int rkvenc_free_task(struct mpp_session *session, { struct rkvenc_task *task = to_rkvenc_task(mpp_task); - if (task->dmabuf_bs) { - dma_buf_put(task->dmabuf_bs); - task->dmabuf_bs = NULL; - task->offset_bs = 0; - } - mpp_task_finalize(session, mpp_task); rkvenc_free_class_msg(task); kfree(task); diff --git a/drivers/video/rockchip/mpp/mpp_vepu2.c b/drivers/video/rockchip/mpp/mpp_vepu2.c index d87f7788dbc0..acb1dc0dbfe3 100644 --- a/drivers/video/rockchip/mpp/mpp_vepu2.c +++ b/drivers/video/rockchip/mpp/mpp_vepu2.c @@ -99,7 +99,7 @@ struct vepu_task { u32 width; u32 height; u32 pixels; - struct dma_buf *dmabuf_bs; + struct mpp_dma_buffer *bs_buf; u32 offset_bs; }; @@ -200,17 +200,14 @@ static int vepu_process_reg_fd(struct mpp_session *session, &task->off_inf, task->reg); if (fmt == VEPU2_FMT_JPEGE) { + struct mpp_dma_buffer *bs_buf = mpp_dma_find_buffer_fd(session->dma, fd_bs); + task->offset_bs = mpp_query_reg_offset_info(&task->off_inf, VEPU2_REG_OUT_INDEX); - - task->dmabuf_bs = dma_buf_get(fd_bs); - - if (IS_ERR_OR_NULL(task->dmabuf_bs)) { - task->dmabuf_bs = NULL; - return 0; + if (bs_buf && task->offset_bs > 0) { + mpp_dma_buf_sync(bs_buf, 0, task->offset_bs, DMA_TO_DEVICE, false); + task->bs_buf = bs_buf; } - if (task->offset_bs > 0) - dma_buf_end_cpu_access_partial(task->dmabuf_bs, DMA_TO_DEVICE, 0, - task->offset_bs); + } return 0; @@ -484,6 +481,11 @@ static int vepu_finish(struct mpp_dev *mpp, /* revert hack for irq status */ task->reg[VEPU2_REG_INT_INDEX] = task->irq_status; + if (task->bs_buf) + mpp_dma_buf_sync(task->bs_buf, 0, + task->reg[VEPU2_REG_STRM_INDEX] / 8 + + task->offset_bs, + DMA_FROM_DEVICE, true); mpp_debug_leave(); return 0; @@ -509,11 +511,6 @@ static int vepu_result(struct mpp_dev *mpp, } } - if (task->dmabuf_bs) - dma_buf_begin_cpu_access_partial(task->dmabuf_bs, DMA_FROM_DEVICE, 0, - task->reg[VEPU2_REG_STRM_INDEX] / 8 + - task->offset_bs); - return 0; } @@ -522,12 +519,6 @@ static int vepu_free_task(struct mpp_session *session, { struct vepu_task *task = to_vepu_task(mpp_task); - if (task->dmabuf_bs) { - dma_buf_put(task->dmabuf_bs); - task->dmabuf_bs = NULL; - task->offset_bs = 0; - } - mpp_task_finalize(session, mpp_task); kfree(task); From 0df0ba8a9820682ac4a11b93f01d1b3e85e4fa8a Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 21 Feb 2023 09:28:48 +0800 Subject: [PATCH 240/258] arm64: dts: rockchip: rk3528: Add SAIx_MCLK{OUT,IN} nodes e.g. mclkin_sai0: mclkin-sai0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <12288000>; clock-output-names = "i2s0_mclkin"; }; mclkout_sai0: mclkout-sai0@ff340014 { compatible = "rockchip,clk-out"; reg = <0 0xff340014 0 0x4>; clocks = <&cru MCLK_SAI_I2S0>; #clock-cells = <0>; clock-output-names = "mclk_sai0_to_io"; rockchip,bit-shift = <1>; rockchip,bit-set-to-disable; }; Note: clock-output-names of mclkin_sai0 should equal to strings in drivers. such as: drivers/clk/rockchip/clk-rk3528.c: PNAME(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src", "i2s0_mclkin" }; PNAME(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src", "i2s1_mclkin" }; Signed-off-by: Sugar Zhang Change-Id: Id7eef076aaa55d59beadfd340a513152727112f9 --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 55 +++++++++++++++++++++--- 1 file changed, 48 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index fa52ff71455e..451625761900 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -52,6 +52,54 @@ spi2 = &sfc; }; + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + mclkin_sai0: mclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s0_mclkin"; + }; + + mclkin_sai1: mclkin-sai1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s1_mclkin"; + }; + + mclkout_sai0: mclkout-sai0@ff340014 { + compatible = "rockchip,clk-out"; + reg = <0 0xff340014 0 0x4>; + clocks = <&cru MCLK_SAI_I2S0>; + #clock-cells = <0>; + clock-output-names = "mclk_sai0_to_io"; + rockchip,bit-shift = <1>; + rockchip,bit-set-to-disable; + }; + + mclkout_sai1: mclkout-sai1@ff320004 { + compatible = "rockchip,clk-out"; + reg = <0 0xff320004 0 0x4>; + clocks = <&cru MCLK_SAI_I2S1>; + #clock-cells = <0>; + clock-output-names = "mclk_sai1_to_io"; + rockchip,bit-shift = <14>; + rockchip,bit-set-to-disable; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -375,13 +423,6 @@ ; }; - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - scmi_shmem: scmi-shmem@10f000 { compatible = "arm,scmi-shmem"; reg = <0x0 0x0010f000 0x0 0x100>; From e42f67144763bbbd99e1a56f29d5ce6b167624c6 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Tue, 21 Feb 2023 15:26:53 +0800 Subject: [PATCH 241/258] arm64: dts: rockchip: rk3562: vicap add csirx data clk control Signed-off-by: Zefa Chen Change-Id: I15baadf44db6c1325812b925e7ac84c636f6303c --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index f22152bd47af..339567802cb4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -1422,8 +1422,12 @@ reg-names = "cif_regs"; interrupts = ; interrupt-names = "cif-intr"; - clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>; - clock-names = "aclk_cif", "hclk_cif", "dclk_cif"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, + <&cru CSIRX0_CLK_DATA>, <&cru CSIRX1_CLK_DATA>, + <&cru CSIRX2_CLK_DATA>, <&cru CSIRX3_CLK_DATA>; + clock-names = "aclk_cif", "hclk_cif", "dclk_cif", + "csirx0_data", "csirx1_data", "csirx2_data", + "csirx3_data"; resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>, <&cru SRST_I3_VICAP>; From 2b6fcece05db3ff89103a8b7fa4c70e2adb446ad Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Tue, 21 Feb 2023 15:27:58 +0800 Subject: [PATCH 242/258] media: rockchip: vicap: rk3562 add csirx data clk if not control csirx data clk, may cause vicap do cru reset fail Signed-off-by: Zefa Chen Change-Id: I38bd186e8add2d3e7df1df527f3d02bf4e7d5d76 --- drivers/media/platform/rockchip/cif/hw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/platform/rockchip/cif/hw.c b/drivers/media/platform/rockchip/cif/hw.c index f9e621852e99..5724ffa81eb9 100644 --- a/drivers/media/platform/rockchip/cif/hw.c +++ b/drivers/media/platform/rockchip/cif/hw.c @@ -869,6 +869,10 @@ static const char * const rk3562_cif_clks[] = { "aclk_cif", "hclk_cif", "dclk_cif", + "csirx0_data", + "csirx1_data", + "csirx2_data", + "csirx3_data", }; static const char * const rk3562_cif_rsts[] = { From 0669486cd50dcb854c8a02bef775c740dfc4e98a Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Mon, 20 Feb 2023 22:24:58 +0800 Subject: [PATCH 243/258] media: rockchip: vicap fixes tasklet error for vb_done Fixes: 824a24f4 ("media: rockchip: vicap use tasklet to done buf") Signed-off-by: Zefa Chen Change-Id: I231edb728285c049e96cfd48b4dfb19b6d31bfe8 --- drivers/media/platform/rockchip/cif/capture.c | 6 +++--- drivers/media/platform/rockchip/cif/cif-tools.c | 2 +- drivers/media/platform/rockchip/cif/dev.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/capture.c b/drivers/media/platform/rockchip/cif/capture.c index bd977c7dbe5c..0ac8786e02cf 100644 --- a/drivers/media/platform/rockchip/cif/capture.c +++ b/drivers/media/platform/rockchip/cif/capture.c @@ -4220,11 +4220,11 @@ void rkcif_do_stop_stream(struct rkcif_stream *stream, dev->wait_line = 0; stream->is_line_wake_up = false; } + tasklet_disable(&stream->vb_done_tasklet); } if (can_reset && hw_dev->dummy_buf.vaddr) rkcif_destroy_dummy_buf(stream); stream->cur_stream_mode &= ~mode; - tasklet_disable(&stream->vb_done_tasklet); INIT_LIST_HEAD(&stream->vb_done_list); v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished, dma_en 0x%x\n", stream->id, stream->dma_en); mutex_unlock(&dev->stream_lock); @@ -5213,6 +5213,7 @@ int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode) mutex_unlock(&hw_dev->dev_lock); if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) { + tasklet_enable(&stream->vb_done_tasklet); ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true); if (ret < 0) { v4l2_err(v4l2_dev, "open cif pipeline failed %d\n", @@ -5286,7 +5287,6 @@ int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode) dev->reset_work_cancel = false; stream->cur_stream_mode |= mode; rkcif_monitor_reset_event(dev); - tasklet_enable(&stream->vb_done_tasklet); goto out; stop_stream: @@ -6232,7 +6232,7 @@ static void rkcif_tasklet_handle(unsigned long data) } } -static void rkcif_vb_done_tasklet(struct rkcif_stream *stream, struct rkcif_buffer *buf) +void rkcif_vb_done_tasklet(struct rkcif_stream *stream, struct rkcif_buffer *buf) { unsigned long flags = 0; diff --git a/drivers/media/platform/rockchip/cif/cif-tools.c b/drivers/media/platform/rockchip/cif/cif-tools.c index caf528c9323b..a2fb0847999f 100644 --- a/drivers/media/platform/rockchip/cif/cif-tools.c +++ b/drivers/media/platform/rockchip/cif/cif-tools.c @@ -618,7 +618,7 @@ static void rkcif_tools_work(struct work_struct *work) list_add_tail(&tools_buf->list, &tools_vdev->src_buf_head); } tools_buf->use_cnt = 2; - rkcif_vb_done_oneframe(stream, &tools_work->active_buf->vb); + rkcif_vb_done_tasklet(stream, tools_work->active_buf); if (tools_vdev->stopping) { rkcif_buf_queue(&tools_work->active_buf->vb.vb2_buf); diff --git a/drivers/media/platform/rockchip/cif/dev.h b/drivers/media/platform/rockchip/cif/dev.h index 8f7d18135b0f..b3e7d1cab3c9 100644 --- a/drivers/media/platform/rockchip/cif/dev.h +++ b/drivers/media/platform/rockchip/cif/dev.h @@ -833,8 +833,8 @@ void rkcif_do_stop_stream(struct rkcif_stream *stream, void rkcif_irq_handle_scale(struct rkcif_device *cif_dev, unsigned int intstat_glb); void rkcif_buf_queue(struct vb2_buffer *vb); -void rkcif_vb_done_oneframe(struct rkcif_stream *stream, - struct vb2_v4l2_buffer *vb_done); + +void rkcif_vb_done_tasklet(struct rkcif_stream *stream, struct rkcif_buffer *buf); int rkcif_scale_start(struct rkcif_scale_vdev *scale_vdev); From 5dabd04f93c172a90138d41f4cdc30399954e6c4 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Sat, 18 Feb 2023 09:54:55 +0800 Subject: [PATCH 244/258] drm/rockchip: vop2: adjust writeback commit time adjust commit time from 1/8 to 7/8 scan timing when enable writeback; Signed-off-by: Sandy Huang Change-Id: Iea0dd9e29b83399c1a0966e0c3ff68b861acd020 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 81 ++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 574172068dae..92f35c24ed4a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -9556,6 +9556,72 @@ static void vop2_cfg_update(struct drm_crtc *crtc, spin_unlock(&vop2->reg_lock); } +static void vop2_sleep_scan_line_time(struct vop2_video_port *vp, int scan_line) +{ + struct vop2 *vop2 = vp->vop2; + struct drm_display_mode *mode = &vp->rockchip_crtc.crtc.state->adjusted_mode; + + if (scan_line <= 0) + return; + + if (IS_ENABLED(CONFIG_HIGH_RES_TIMERS) && + (!IS_ENABLED(CONFIG_NO_GKI) || (hrtimer_resolution != LOW_RES_NSEC))) { + u16 htotal = VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16; + u32 linedur_ns = div_u64((u64) htotal * 1000000, mode->crtc_clock); + u64 sleep_time = linedur_ns * scan_line; + + sleep_time = div_u64((sleep_time + 1000), 1000); + if (sleep_time > 200) + usleep_range(sleep_time, sleep_time); + } +} + +/* + * return scan timing from FS to the assigned wait line + */ +static void vop2_wait_for_scan_timing_max_to_assigned_line(struct vop2_video_port *vp, + u32 current_line, + u32 wait_line) + +{ + struct vop2 *vop2 = vp->vop2; + u32 vcnt; + int ret; + u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal); + int delta_line = vtotal - current_line; + + vop2_sleep_scan_line_time(vp, delta_line); + if (vop2_read_vcnt(vp) < wait_line) + return; + + ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt < wait_line, 0, 50 * 1000); + if (ret) + DRM_DEV_ERROR(vop2->dev, "wait scan timing from FS to the assigned wait line: %d, vcnt:%d, ret:%d\n", + wait_line, vcnt, ret); +} + +/* + * return scan timing from the assigned wait line + */ +static void vop2_wait_for_scan_timing_from_the_assigned_line(struct vop2_video_port *vp, + u32 current_line, + u32 wait_line) +{ + struct vop2 *vop2 = vp->vop2; + u32 vcnt; + int ret; + int delta_line = wait_line - current_line; + + vop2_sleep_scan_line_time(vp, delta_line); + if (vop2_read_vcnt(vp) > wait_line) + return; + + ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt > wait_line, 0, 50 * 1000); + if (ret) + DRM_DEV_ERROR(vop2->dev, "wait scan timing from the assigned wait line: %d, vcnt:%d, ret:%d\n", + wait_line, vcnt, ret); +} + static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_cstate) { struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); @@ -9566,6 +9632,21 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state struct drm_plane *plane; unsigned long flags; int i, ret; + struct vop2_wb *wb = &vop2->wb; + struct drm_writeback_connector *wb_conn = &wb->conn; + struct drm_connector_state *conn_state = wb_conn->base.state; + + if (conn_state && conn_state->writeback_job && conn_state->writeback_job->fb) { + u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal); + u32 current_line = vop2_read_vcnt(vp); + + if (current_line > vtotal * 7 >> 3) + vop2_wait_for_scan_timing_max_to_assigned_line(vp, current_line, vtotal * 7 >> 3); + + current_line = vop2_read_vcnt(vp); + if (current_line < vtotal >> 3) + vop2_wait_for_scan_timing_from_the_assigned_line(vp, current_line, vtotal >> 3); + } vop2_cfg_update(crtc, old_cstate); From d6593774374493e9df39d7ca35e44fafb11afe20 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 22 Feb 2023 09:27:39 +0800 Subject: [PATCH 245/258] clk: rockchip: rk3128: fix up the sdmmc drv and sample set phase failed Signed-off-by: Elaine Zhang Change-Id: I9e8b25c8f85594ee9c3e7d5d3e2d47ac05fdda94 --- drivers/clk/rockchip/clk-rk3128.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index 90f32d465550..1b1111e88089 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -311,7 +311,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", 0, RK2928_CLKGATE_CON(2), 15, GFLAGS), - COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), From aec5968aadf3ba8722f47332410ef8b0b6bc62c6 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Tue, 21 Feb 2023 07:19:32 +0000 Subject: [PATCH 246/258] clk: rockchip: rk3528: Allow disable clk_400m_src There is not any child under clk_400m_src. Signed-off-by: Joseph Chen Change-Id: I23c96869f69e62ee3ada30d66ffc7b2482bcdd7f --- drivers/clk/rockchip/clk-rk3528.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3528.c b/drivers/clk/rockchip/clk-rk3528.c index 58becedac436..1b14cd57be0a 100644 --- a/drivers/clk/rockchip/clk-rk3528.c +++ b/drivers/clk/rockchip/clk-rk3528.c @@ -280,7 +280,7 @@ static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL, RK3528_CLKSEL_CON(2), 5, 5, DFLAGS, RK3528_CLKGATE_CON(0), 7, GFLAGS), - COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IS_CRITICAL, + COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IGNORE_UNUSED, RK3528_CLKSEL_CON(2), 10, 5, DFLAGS, RK3528_CLKGATE_CON(0), 8, GFLAGS), COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", CLK_IS_CRITICAL, From a4309e65bb637fe1fc2d8614f043a4b0346cb20d Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Mon, 12 Dec 2022 09:48:30 +0800 Subject: [PATCH 247/258] drm/rockchip: vop3: add cluster frame reset Signed-off-by: Sandy Huang Change-Id: I1d7d590ea91c0864cebe11066780789078960120 --- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 1 + drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 0d268f079edb..7b1612937ddb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -724,6 +724,7 @@ struct vop2_cluster_regs { struct vop_reg afbc_enable; struct vop_reg lb_mode; struct vop_reg scl_lb_mode; + struct vop_reg frm_reset_en; struct vop_reg src_color_ctrl; struct vop_reg dst_color_ctrl; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 92f35c24ed4a..c05793605bfd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -5153,6 +5153,7 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode); VOP_CLUSTER_SET(vop2, win, scl_lb_mode, lb_mode == 1 ? 3 : 0); VOP_CLUSTER_SET(vop2, win, enable, 1); + VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1); } spin_unlock(&vop2->reg_lock); } diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 74fcfd40fa88..8079a32dca31 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1921,6 +1921,7 @@ static const struct vop2_cluster_regs rk3528_vop_cluster0 = { .enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0), .lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4), .scl_lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0x3, 9), + .frm_reset_en = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 31), .src_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0), .dst_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0), .src_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0), From 272ce0169e092f043b685df4b9791400871d05cf Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 22 Feb 2023 11:15:09 +0800 Subject: [PATCH 248/258] arm64: dts: rockchip: rk3562: Set mclkin freq as 0 Hz default Use freq 0 Hz to represent the case which not used yet, and, should assign the match freq as external mclk in if used. Signed-off-by: Sugar Zhang Change-Id: Id8d39117ba477285a562e7fa7bf7b28edd5e9212 --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index 339567802cb4..dafa90c2444f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -137,21 +137,21 @@ mclkin_sai0: mclkin-sai0 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "mclk_sai0_from_io"; }; mclkin_sai1: mclkin-sai1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "mclk_sai1_from_io"; }; mclkin_sai2: mclkin-sai2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "mclk_sai2_from_io"; }; From cc54f721740f708e7839bbf3b57cefcbd73a7e2a Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 22 Feb 2023 11:24:10 +0800 Subject: [PATCH 249/258] arm64: dts: rockchip: rk3588: Set mclkin freq as 0 Hz default Use freq 0 Hz to represent the case which not used yet, and, should assign the match freq as external mclk in if used. Signed-off-by: Sugar Zhang Change-Id: I0a731367a81a740df36af7552c7b6a353f9bd2f0 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index a1fc41745f59..1cd8f2f120f0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -299,28 +299,28 @@ mclkin_i2s0: mclkin-i2s0 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "i2s0_mclkin"; }; mclkin_i2s1: mclkin-i2s1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "i2s1_mclkin"; }; mclkin_i2s2: mclkin-i2s2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "i2s2_mclkin"; }; mclkin_i2s3: mclkin-i2s3 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "i2s3_mclkin"; }; From 8b300934b1b6577f992bfb3506364c27b161a1ba Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 22 Feb 2023 11:24:39 +0800 Subject: [PATCH 250/258] arm64: dts: rockchip: rk3528: Set mclkin freq as 0 Hz default Use freq 0 Hz to represent the case which not used yet, and, should assign the match freq as external mclk in if used. Signed-off-by: Sugar Zhang Change-Id: Ida01fcf9fb7c57db2de3d55c19a9bc80ac8fde97 --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 451625761900..ede21515cada 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -68,14 +68,14 @@ mclkin_sai0: mclkin-sai0 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "i2s0_mclkin"; }; mclkin_sai1: mclkin-sai1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <12288000>; + clock-frequency = <0>; clock-output-names = "i2s1_mclkin"; }; From 4bfb57719dc431bc093066f39a3e46e4edecb45e Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 21 Feb 2023 20:39:23 +0800 Subject: [PATCH 251/258] soc: rockchip: opp_select: Fix restricting voltage error Signed-off-by: Finley Xiao Change-Id: Ia4eb980c9b071b5b6bdb2fbb2229de6b17f65d8a --- drivers/soc/rockchip/rockchip_opp_select.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c index 3a6cfe60a49e..79c0b47d6196 100644 --- a/drivers/soc/rockchip/rockchip_opp_select.c +++ b/drivers/soc/rockchip/rockchip_opp_select.c @@ -436,7 +436,7 @@ static int rockchip_get_pvtm_specific_value(struct device *dev, cur_temp, *target_value, avg_value, diff_value); resetore_volt: - regulator_set_voltage(reg, old_volt, old_volt); + regulator_set_voltage(reg, old_volt, INT_MAX); restore_clk: clk_set_rate(clk, old_freq); pvtm_value_out: @@ -1076,7 +1076,7 @@ static int rockchip_get_pvtm_pvtpll(struct device *dev, struct device_node *np, dev_err(dev, "Failed to set pvtm freq\n"); goto put_reg; } - ret = regulator_set_voltage(reg, pvtm->volt, pvtm->volt); + ret = regulator_set_voltage(reg, pvtm->volt, INT_MAX); if (ret) { dev_err(dev, "Failed to set pvtm_volt\n"); goto restore_clk; @@ -1100,7 +1100,7 @@ static int rockchip_get_pvtm_pvtpll(struct device *dev, struct device_node *np, dev_info(dev, "pvtm=%d\n", pvtm_value); resetore_volt: - regulator_set_voltage(reg, old_volt, old_volt); + regulator_set_voltage(reg, old_volt, INT_MAX); restore_clk: clk_set_rate(clk, old_freq); put_reg: From 9b9ba0dcc7496fb40e47c5fe703b32faa41ddbd5 Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Tue, 27 Dec 2022 20:48:12 +0800 Subject: [PATCH 252/258] video: rockchip: mpp: fix rkvdec2 link info err Signed-off-by: Yandong Lin Change-Id: I1f224fa7a8c050f5a782baef7d0bdd6920fad753 --- drivers/video/rockchip/mpp/mpp_rkvdec2_link.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c index 8041b7ae7524..2d37714c59d3 100644 --- a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c +++ b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c @@ -141,7 +141,7 @@ struct rkvdec_link_info rkvdec_link_rk356x_hw_info = { /* vdpu382 link hw info */ struct rkvdec_link_info rkvdec_link_vdpu382_hw_info = { - .tb_reg_num = 218, + .tb_reg_num = 222, .tb_reg_next = 0, .tb_reg_r = 1, .tb_reg_second_en = 8, @@ -181,12 +181,12 @@ struct rkvdec_link_info rkvdec_link_vdpu382_hw_info = { .part_r[0] = { .tb_reg_off = 180, .reg_start = 224, - .reg_num = 10, + .reg_num = 12, }, .part_r[1] = { - .tb_reg_off = 190, + .tb_reg_off = 192, .reg_start = 258, - .reg_num = 28, + .reg_num = 30, }, .tb_reg_int = 180, .hack_setup = 0, From 47c8b6bf3806aebc48d16f48e096dea13508c9d3 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 22 Feb 2023 14:30:31 +0800 Subject: [PATCH 253/258] ARM: dts: rockchip: rk312x: Update sdmmc node Some properties have been removed or modified as kernel upgraded. And add sdmmc_det for rk3128 since rk3128 can use functional det. Signed-off-by: Shawn Lin Change-Id: I256bedb66a1fbf61fdcf40ff9034f69755642b05 --- arch/arm/boot/dts/rk312x.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi index fa548c7d19f9..d3f61b1cccc8 100644 --- a/arch/arm/boot/dts/rk312x.dtsi +++ b/arch/arm/boot/dts/rk312x.dtsi @@ -832,12 +832,11 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - clock-freq-min-max = <400000 50000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; + max-frequency = <50000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; dmas = <&pdma 10>; dma-names = "rx-tx"; - num-slots = <1>; fifo-depth = <0x100>; bus-width = <4>; status = "disabled"; @@ -1466,6 +1465,10 @@ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; }; + sdmmc_det: sdmmc-det { + rockchip,pins = <1 RK_PC1 1 &pcfg_pull_none>; + }; + sdmmc_cmd: sdmmc-cmd { rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; }; From 9014f0d9cb341418ade33aac120fbd6c05009922 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Wed, 20 Apr 2022 08:15:56 +0000 Subject: [PATCH 254/258] drm/rockchip: dw-dp: Add support for drm_panel usage Signed-off-by: Wyon Bi Change-Id: I84545b8465541baf67f62f1deee5a9238a0f89be --- drivers/gpu/drm/rockchip/dw-dp.c | 45 +++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 57a7c66a888f..6627a3f9abde 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -371,6 +372,7 @@ struct dw_dp { struct drm_encoder encoder; struct drm_dp_aux aux; struct drm_bridge *next_bridge; + struct drm_panel *panel; struct dw_dp_link link; struct dw_dp_video video; @@ -1198,6 +1200,9 @@ static int dw_dp_connector_get_modes(struct drm_connector *connector) if (dp->next_bridge) num_modes = drm_bridge_get_modes(dp->next_bridge, connector); + if (dp->panel) + num_modes = drm_panel_get_modes(dp->panel, connector); + if (!num_modes) { edid = drm_bridge_get_edid(&dp->bridge, connector); if (edid) { @@ -2773,7 +2778,7 @@ static int dw_dp_bridge_attach(struct drm_bridge *bridge, return -ENODEV; } - ret = drm_of_find_panel_or_bridge(bridge->of_node, 1, 0, NULL, + ret = drm_of_find_panel_or_bridge(bridge->of_node, 1, -1, &dp->panel, &dp->next_bridge); if (ret < 0 && ret != -ENODEV) return ret; @@ -2840,6 +2845,19 @@ static void dw_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge, if (dp->split_mode) drm_mode_convert_to_origin_mode(m); + + if (dp->panel) + drm_panel_prepare(dp->panel); +} + +static void +dw_dp_bridge_atomic_post_disable(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state) +{ + struct dw_dp *dp = bridge_to_dp(bridge); + + if (dp->panel) + drm_panel_unprepare(dp->panel); } static bool dw_dp_needs_link_retrain(struct dw_dp *dp) @@ -2921,6 +2939,9 @@ static void dw_dp_bridge_atomic_enable(struct drm_bridge *bridge, dev_err(dp->dev, "failed to enable video: %d\n", ret); return; } + + if (dp->panel) + drm_panel_enable(dp->panel); } static void dw_dp_reset(struct dw_dp *dp) @@ -2948,6 +2969,9 @@ static void dw_dp_bridge_atomic_disable(struct drm_bridge *bridge, { struct dw_dp *dp = bridge_to_dp(bridge); + if (dp->panel) + drm_panel_disable(dp->panel); + dw_dp_hdcp_disable(dp); dw_dp_video_disable(dp); dw_dp_link_disable(dp); @@ -2980,6 +3004,9 @@ static enum drm_connector_status dw_dp_bridge_detect(struct drm_bridge *bridge) struct dw_dp *dp = bridge_to_dp(bridge); enum drm_connector_status status = connector_status_connected; + if (dp->panel) + drm_panel_prepare(dp->panel); + if (!dw_dp_detect(dp)) { status = connector_status_disconnected; goto out; @@ -3044,6 +3071,21 @@ static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, if (dp->split_mode) drm_mode_convert_to_origin_mode(&mode); + if (dp->panel) { + *num_output_fmts = 1; + + output_fmts = kzalloc(sizeof(*output_fmts), GFP_KERNEL); + if (!output_fmts) + return NULL; + + if (di->num_bus_formats && di->bus_formats) + output_fmts[0] = di->bus_formats[0]; + else + output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + + return output_fmts; + } + *num_output_fmts = 0; output_fmts = kcalloc(ARRAY_SIZE(possible_output_fmts), @@ -3118,6 +3160,7 @@ static const struct drm_bridge_funcs dw_dp_bridge_funcs = { .mode_valid = dw_dp_bridge_mode_valid, .atomic_check = dw_dp_bridge_atomic_check, .atomic_pre_enable = dw_dp_bridge_atomic_pre_enable, + .atomic_post_disable = dw_dp_bridge_atomic_post_disable, .atomic_enable = dw_dp_bridge_atomic_enable, .atomic_disable = dw_dp_bridge_atomic_disable, .detect = dw_dp_bridge_detect, From 8c62deaf6025ed2e255bd4e500dd03a34b47ea7c Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 22 Feb 2023 14:33:55 +0800 Subject: [PATCH 255/258] ARM: dts: rockchip: rk3128: redefine sdmmc_pwren as GPIO function For rk3128 reference design, sdmmc_pwren is used as a GPIO. Signed-off-by: Shawn Lin Change-Id: If954337fe87da85eb7a088714ac6b0a5777c3cb7 --- arch/arm/boot/dts/rk3128.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3128.dtsi b/arch/arm/boot/dts/rk3128.dtsi index 93d421a80f6b..6a608b9721fa 100644 --- a/arch/arm/boot/dts/rk3128.dtsi +++ b/arch/arm/boot/dts/rk3128.dtsi @@ -169,6 +169,10 @@ <&qos_vip0>; }; +&sdmmc_pwren { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; +}; + &video_phy { status = "okay"; }; From 4cf8e604eb6a220fc03ed88bd45cd6f57620985a Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 22 Feb 2023 14:36:06 +0800 Subject: [PATCH 256/258] ARM: dts: rockchip: rk3128-evb-ddr3-v10-linux: Fix sdmmc sdmmc card wasn't functional at all as some properties copied from old kernel can't work any more. Signed-off-by: Shawn Lin Change-Id: Ib1deb1d5387bbca0e3be22c3175f301005bcee1d --- arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts b/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts index 2151849d8fac..d660c08190d8 100644 --- a/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts +++ b/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts @@ -926,13 +926,13 @@ &sdmmc { cap-mmc-highspeed; cap-sd-highspeed; - supports-sd; + no-sdio; + no-mmc; vmmc-supply = <&vcc_sdmmc>; - broken-cd; card-detect-delay = <800>; - ignore-pm-notify; - keep-power-in-suspend; - cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; /* CD GPIO */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_det>; + rockchip,default-sample-phase=<90>; status = "disabled"; }; From 271f493d1b87d83052248fca5b4e35e0c710f38a Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Fri, 10 Feb 2023 16:51:19 +0800 Subject: [PATCH 257/258] drm/rockchip: vop3: update ygt2/4 triger condition for rk3528 Signed-off-by: Sandy Huang Change-Id: I21768d3aa506a116964084dc0ee09ff68e838fa4 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 45 +++++++++++++++----- 1 file changed, 35 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index c05793605bfd..1686546cdb8f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2573,12 +2573,30 @@ static void vop2_setup_scale(struct vop2 *vop2, struct vop2_win *win, } } - if (src_h >= (4 * dst_h)) { - ygt4 = 1; - src_h >>= 2; - } else if (src_h >= (2 * dst_h)) { - ygt2 = 1; - src_h >>= 1; + /** + * The rk3528 is processed as 2 pixel/cycle, + * so ygt2/ygt4 needs to be triggered in advance to improve performance + * when src_w is bigger than 1920. + * dst_h / src_h is at [1, 0.65) ygt2=0; ygt4=0; + * dst_h / src_h is at [0.65, 0.35) ygt2=1; ygt4=0; + * dst_h / src_h is at [0.35, 0) ygt2=0; ygt4=1; + */ + if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) { + if (src_h >= (100 * dst_h / 35)) { + ygt4 = 1; + src_h >>= 2; + } else if ((src_h >= 100 * dst_h / 65) && (src_h < 100 * dst_h / 35)) { + ygt2 = 1; + src_h >>= 1; + } + } else { + if (src_h >= (4 * dst_h)) { + ygt4 = 1; + src_h >>= 2; + } else if (src_h >= (2 * dst_h)) { + ygt2 = 1; + src_h >>= 1; + } } yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); @@ -2655,10 +2673,17 @@ static void vop2_setup_scale(struct vop2 *vop2, struct vop2_win *win, if (!is_vop3(vop2) || (!vpstate->afbc_en && !vpstate->tiled_en) || win_data->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) { - if (cbcr_src_h >= (4 * dst_h)) - ygt4 = 1; - else if (cbcr_src_h >= (2 * dst_h)) - ygt2 = 1; + if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) { + if (cbcr_src_h >= (100 * dst_h / 35)) + ygt4 = 1; + else if ((cbcr_src_h >= 100 * dst_h / 65) && (cbcr_src_h < 100 * dst_h / 35)) + ygt2 = 1; + } else { + if (cbcr_src_h >= (4 * dst_h)) + ygt4 = 1; + else if (cbcr_src_h >= (2 * dst_h)) + ygt2 = 1; + } if (ygt4) cbcr_src_h >>= 2; From 5071891c1714b30b39bf79e4e0aa8ac953f4940c Mon Sep 17 00:00:00 2001 From: Binyuan Lan Date: Wed, 22 Feb 2023 03:30:39 +0000 Subject: [PATCH 258/258] arm64: dts: rockchip: rk3562-evb: fix uart_rts_gpios Change-Id: Ib90f1ab7cc62a6cf88ec79bec4ac2a68d26b17b6 Signed-off-by: Binyuan Lan --- arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi index 1f3a4d5fd616..5d4cb267f7ee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi @@ -167,7 +167,7 @@ clocks = <&rk817 1>; clock-names = "ext_clock"; //wifi-bt-power-toggle; - uart_rts_gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "rts_gpio"; pinctrl-0 = <&uart1m0_rtsn>; pinctrl-1 = <&uart1_gpios>; @@ -475,7 +475,7 @@ wireless-bluetooth { uart1_gpios: uart1-gpios { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi index d8ee68d507c5..60a5f452b196 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi @@ -170,7 +170,7 @@ clocks = <&rk809 1>; clock-names = "ext_clock"; //wifi-bt-power-toggle; - uart_rts_gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "rts_gpio"; pinctrl-0 = <&uart1m0_rtsn>; pinctrl-1 = <&uart1_gpios>; @@ -304,7 +304,7 @@ wireless-bluetooth { uart1_gpios: uart1-gpios { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts index 4b176101580b..30a98540d187 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts @@ -194,7 +194,7 @@ clocks = <&rk817 1>; clock-names = "ext_clock"; //wifi-bt-power-toggle; - uart_rts_gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "rts_gpio"; pinctrl-0 = <&uart1m0_rtsn>; pinctrl-1 = <&uart1_gpios>; @@ -908,7 +908,7 @@ wireless-bluetooth { uart1_gpios: uart1-gpios { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; };