From 0c5b62a2da96313656efcf527fe5d94b77dc2081 Mon Sep 17 00:00:00 2001
From: Tony Xu <tony.xu@rock-chips.com>
Date: Tue, 3 Nov 2020 09:43:54 +0800
Subject: [PATCH] ARM: dts: rv1126-rmsl-ddr3-v1: support psensor

Signed-off-by: Tony Xu <tony.xu@rock-chips.com>
Change-Id: I7ed60597fef8ae8ca960c7d85581d742ebe588b9
---
 arch/arm/boot/dts/rv1126-rmsl-ddr3-v1.dts | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/rv1126-rmsl-ddr3-v1.dts b/arch/arm/boot/dts/rv1126-rmsl-ddr3-v1.dts
index 5349d7bc1780..f96cdfc3a81f 100644
--- a/arch/arm/boot/dts/rv1126-rmsl-ddr3-v1.dts
+++ b/arch/arm/boot/dts/rv1126-rmsl-ddr3-v1.dts
@@ -200,6 +200,26 @@
 	};
 };
 
+&i2c2 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <275>;
+	i2c-scl-falling-time-ns = <16>;
+	clock-frequency = <400000>;
+
+	ltr507als: ltr507@3a {
+		status = "okay";
+		compatible = "ltr507als";
+		reg = <0x3a>;
+		rockchip,pwr-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ltr507_irq_gpios>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
 &spi0 {
 	status = "okay";
 	//assigned-clocks = <&cru SCLK_SPI0>;
@@ -277,4 +297,11 @@
 				<0 RK_PA0 1 &pcfg_pull_none>;
 		};
 	};
+	ltr507als_gpio {
+		ltr507_irq_gpios: ltr507-irq-gpios {
+			rockchip,pins =
+				<0 RK_PC0 0 &pcfg_pull_up>;
+		};
+	};
 };
+