diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h
index 295974d9bc89..43c595b70e52 100644
--- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h
+++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-common.h
@@ -128,6 +128,7 @@ struct csi2_dphy_hw {
 	int dphy_dev_num;
 	enum csi2_dphy_lane_mode lane_mode;
 	struct resource *res;
+	int hw_idx;
 
 	int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
 	int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
index 2816abd07a00..47ac3ce72124 100644
--- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
+++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
@@ -712,7 +712,7 @@ static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy,
 
 	if (hw->lane_mode == LANE_MODE_FULL) {
 		val = !GRF_CSI2PHY_LANE_SEL_SPLIT;
-		if (dphy->phy_index < 3) {
+		if (hw->hw_idx == 0) {
 			write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
 				      GENMASK(sensor->lanes - 1, 0));
 			write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
diff --git a/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c b/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c
index 9bbf7f5d1a3b..418405ed4bc0 100644
--- a/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c
@@ -1161,6 +1161,7 @@ static int rockchip_csi2_dphy_get_inno_phy_hw(struct csi2_dphy *dphy)
 				dphy->phy_index);
 			return -EINVAL;
 		}
+		dphy_hw->hw_idx = i;
 		dphy->dphy_hw_group[i] = dphy_hw;
 	}
 	return 0;