From 0df0ba8a9820682ac4a11b93f01d1b3e85e4fa8a Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Tue, 21 Feb 2023 09:28:48 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3528: Add SAIx_MCLK{OUT,IN} nodes

e.g.

  mclkin_sai0: mclkin-sai0 {
      compatible = "fixed-clock";
      #clock-cells = <0>;
      clock-frequency = <12288000>;
      clock-output-names = "i2s0_mclkin";
  };

  mclkout_sai0: mclkout-sai0@ff340014 {
      compatible = "rockchip,clk-out";
      reg = <0 0xff340014 0 0x4>;
      clocks = <&cru MCLK_SAI_I2S0>;
      #clock-cells = <0>;
      clock-output-names = "mclk_sai0_to_io";
      rockchip,bit-shift = <1>;
      rockchip,bit-set-to-disable;
  };

Note:

clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:

drivers/clk/rockchip/clk-rk3528.c:

PNAME(mclk_sai_i2s0_p)                  = { "mclk_i2s0_2ch_sai_src", "i2s0_mclkin" };
PNAME(mclk_sai_i2s1_p)                  = { "mclk_i2s1_8ch_sai_src", "i2s1_mclkin" };

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id7eef076aaa55d59beadfd340a513152727112f9
---
 arch/arm64/boot/dts/rockchip/rk3528.dtsi | 55 +++++++++++++++++++++---
 1 file changed, 48 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index fa52ff71455e..451625761900 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -52,6 +52,54 @@
 		spi2 = &sfc;
 	};
 
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		xin24m: xin24m {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+			clock-output-names = "xin24m";
+		};
+
+		mclkin_sai0: mclkin-sai0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12288000>;
+			clock-output-names = "i2s0_mclkin";
+		};
+
+		mclkin_sai1: mclkin-sai1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12288000>;
+			clock-output-names = "i2s1_mclkin";
+		};
+
+		mclkout_sai0: mclkout-sai0@ff340014 {
+			compatible = "rockchip,clk-out";
+			reg = <0 0xff340014 0 0x4>;
+			clocks = <&cru MCLK_SAI_I2S0>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai0_to_io";
+			rockchip,bit-shift = <1>;
+			rockchip,bit-set-to-disable;
+		};
+
+		mclkout_sai1: mclkout-sai1@ff320004 {
+			compatible = "rockchip,clk-out";
+			reg = <0 0xff320004 0 0x4>;
+			clocks = <&cru MCLK_SAI_I2S1>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai1_to_io";
+			rockchip,bit-shift = <14>;
+			rockchip,bit-set-to-disable;
+		};
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -375,13 +423,6 @@
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	xin24m: xin24m {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-		clock-output-names = "xin24m";
-	};
-
 	scmi_shmem: scmi-shmem@10f000 {
 		compatible = "arm,scmi-shmem";
 		reg = <0x0 0x0010f000 0x0 0x100>;