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clk: rockchip: rk3399: Don't allow VPLL as aclk_cci clock source

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vpll is just for dclk_vop.
Don't allow are other child under the VPLL.

Change-Id: I755348b4104b532c693c6874127a25721187a4ad
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-03-31 11:18:39 +08:00
committed by Huang, Tao
parent f19cbe449b
commit 0f1294525b
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3399.c
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@@ -151,7 +151,7 @@ PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = { "dummy_vpll", "cpll", "gpll" };
PNAME(mux_aclk_cci_p) = { "dummy_cpll",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
"vpll_aclk_cci_src" };
"dummy_vpll" };
PNAME(mux_cci_trace_p) = { "dummy_cpll",
"gpll_cci_trace" };
PNAME(mux_cs_p) = { "dummy_cpll", "gpll_cs",
@@ -205,7 +205,7 @@ PNAME(mux_aclk_gmac_p) = { "dummy_cpll",
PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
"vpll_aclk_cci_src" };
"dummy_vpll" };
PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
"gpll_cci_trace" };
PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",