From 53ee20ccf2c29c799849b332d29e3bae066facd0 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 11 Oct 2024 16:22:23 +0800 Subject: [PATCH 1/7] scsi: ufs: rockchip: Fix compile error if not define CONFIG_PM Change-Id: Ic2c6dc5fed2aa8daca375eb8884ec809c0e89193 Signed-off-by: Shawn Lin --- drivers/ufs/host/ufs-rockchip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ufs/host/ufs-rockchip.c b/drivers/ufs/host/ufs-rockchip.c index 6c73679669b0..53104cceb299 100644 --- a/drivers/ufs/host/ufs-rockchip.c +++ b/drivers/ufs/host/ufs-rockchip.c @@ -626,8 +626,8 @@ static void ufs_rockchip_shutdown(struct platform_device *pdev) } static const struct dev_pm_ops ufs_rockchip_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(ufs_rockchip_suspend, ufs_rockchip_resume) - SET_RUNTIME_PM_OPS(ufs_rockchip_runtime_suspend, ufs_rockchip_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(ufs_rockchip_suspend, ufs_rockchip_resume) + RUNTIME_PM_OPS(ufs_rockchip_runtime_suspend, ufs_rockchip_runtime_resume, NULL) .prepare = ufshcd_suspend_prepare, .complete = ufshcd_resume_complete, }; @@ -638,7 +638,7 @@ static struct platform_driver ufs_rockchip_pltform = { .shutdown = ufs_rockchip_shutdown, .driver = { .name = "ufshcd-rockchip", - .pm = &ufs_rockchip_pm_ops, + .pm = pm_ptr(&ufs_rockchip_pm_ops), .of_match_table = of_match_ptr(ufs_rockchip_of_match), }, }; From 838172a6b278446005eac6b5ce52251364b56bbc Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Wed, 9 Oct 2024 18:59:48 +0800 Subject: [PATCH 2/7] ARM: keep .vectors on CONFIG_LD_DEAD_CODE_DATA_ELIMINATION When CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y and CONFIG_VMAP_STACK=n, .vectors sections will disappear. Use KEEP to keep. Fixes: cf50c9c2e448 ("BACKPORT: ARM: 9404/1: arm32: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION") Link: https://lore.kernel.org/all/20240307151231.654025-1-liuyuntao12@huawei.com/ Change-Id: I6c7e90a3e035980e6cdbd7b830fbd30abea5b157 Signed-off-by: Tao Huang --- arch/arm/include/asm/vmlinux.lds.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/include/asm/vmlinux.lds.h b/arch/arm/include/asm/vmlinux.lds.h index fa031135710f..861f7f43a31e 100644 --- a/arch/arm/include/asm/vmlinux.lds.h +++ b/arch/arm/include/asm/vmlinux.lds.h @@ -135,6 +135,11 @@ *(.vectors.bhb.bpiall) \ } \ } \ + .vectors.text : { \ + KEEP(*(.vectors)) \ + KEEP(*(.vectors.bhb.loop8)) \ + KEEP(*(.vectors.bhb.bpiall)) \ + } \ ARM_LMA(__vectors, .vectors); \ ARM_LMA(__vectors_bhb_loop8, .vectors.bhb.loop8); \ ARM_LMA(__vectors_bhb_bpiall, .vectors.bhb.bpiall); \ From e20881778049ecf6d3b15c599dc61342332f3a5e Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Thu, 10 Oct 2024 15:17:45 +0800 Subject: [PATCH 3/7] ARM: dts: rockchip: add dtsi for rk3502 Change-Id: Icf8d08d7154ec21d4a0852aed7fe99826fd3091f Signed-off-by: Huibin Hong --- arch/arm/boot/dts/rk3502.dtsi | 1407 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3506.dtsi | 1426 +-------------------------------- 2 files changed, 1424 insertions(+), 1409 deletions(-) create mode 100644 arch/arm/boot/dts/rk3502.dtsi diff --git a/arch/arm/boot/dts/rk3502.dtsi b/arch/arm/boot/dts/rk3502.dtsi new file mode 100644 index 000000000000..d1eeaf85a57e --- /dev/null +++ b/arch/arm/boot/dts/rk3502.dtsi @@ -0,0 +1,1407 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rk3502"; + + interrupt-parent = <&gic>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &fspi; + spi3 = &flexbus_fspi; + spi4 = &flexbus_spi; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_rc: clk-rc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000>; + clock-output-names = "clk_rc"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + clk_spdifrx_to_asrc: clk-spdifrx-to-asrc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_spdifrx_to_asrc"; + }; + + mclkin_sai0: mclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai0_mclk_in"; + }; + + mclkin_sai1: mclkin-sai1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai1_mclk_in"; + }; + + mclkin_sai2: mclkin-sai2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai2_mclk_in"; + }; + + mclkin_sai3: mclkin-sai3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai3_mclk_in"; + }; + + mclkout_sai0: mclkout-sai0@ff910004 { + compatible = "rockchip,clk-out"; + reg = <0xff910004 0x4>; + clocks = <&cru MCLK_OUT_SAI0>; + #clock-cells = <0>; + clock-output-names = "mclk_sai0_to_io"; + rockchip,bit-shift = <8>; + }; + + mclkout_sai1: mclkout-sai1@ff910004 { + compatible = "rockchip,clk-out"; + reg = <0xff910004 0x4>; + clocks = <&cru MCLK_OUT_SAI1>; + #clock-cells = <0>; + clock-output-names = "mclk_sai1_to_io"; + rockchip,bit-shift = <9>; + }; + + mclkout_sai2: mclkout-sai2@ff288004 { + compatible = "rockchip,clk-out"; + reg = <0xff288004 0x4>; + clocks = <&cru MCLK_OUT_SAI2>; + #clock-cells = <0>; + clock-output-names = "mclk_sai2_to_io"; + rockchip,bit-shift = <2>; + }; + + mclkout_sai3: mclkout-sai3@ff288004 { + compatible = "rockchip,clk-out"; + reg = <0xff288004 0x4>; + clocks = <&cru MCLK_OUT_SAI3>; + #clock-cells = <0>; + clock-output-names = "mclk_sai3_to_io"; + rockchip,bit-shift = <3>; + }; + + pvtpll_core: pvtpll-core@ff840000 { + compatible = "rockchip,rk3506-core-pvtpll", "syscon"; + reg = <0xff840000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_core_pvtpll"; + assigned-clocks = <&pvtpll_core>; + assigned-clock-rates = <1200000000>; + }; + + sai0_fs: sai0-fs { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai0_fs"; + }; + + sai1_fs: sai1-fs { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai1_fs"; + }; + + sai2_fs: sai2-fs { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai2_fs"; + }; + + sai3_fs: sai3-fs { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai3_fs"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + + rockchip,pvtm-voltage-sel = < + 0 1584 0 + 1585 1619 1 + 1620 1654 2 + 1655 1689 3 + 1690 1724 4 + 1725 1759 5 + 1760 1794 6 + 1795 9999 7 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <500>; + rockchip,pvtm-freq = <1608000>; + rockchip,pvtm-volt = <1000000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <0 0>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <&pvtpll_core>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000 850000 1000000>; + opp-microvolt-L0 = <875000 875000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000 850000 1000000>; + opp-microvolt-L0 = <875000 875000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L0 = <900000 900000 1000000>; + opp-microvolt-L1 = <887500 887500 1000000>; + opp-microvolt-L2 = <875000 875000 1000000>; + opp-microvolt-L3 = <862500 862500 1000000>; + opp-microvolt-L4 = <850000 850000 1000000>; + opp-microvolt-L5 = <850000 850000 1000000>; + opp-microvolt-L6 = <850000 850000 1000000>; + opp-microvolt-L7 = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <937500 937500 1000000>; + opp-microvolt-L0 = <937500 937500 1000000>; + opp-microvolt-L1 = <925000 925000 1000000>; + opp-microvolt-L2 = <912500 912500 1000000>; + opp-microvolt-L3 = <900000 900000 1000000>; + opp-microvolt-L4 = <887500 887500 1000000>; + opp-microvolt-L5 = <875000 875000 1000000>; + opp-microvolt-L6 = <862500 862500 1000000>; + opp-microvolt-L7 = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <975000 975000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <962500 962500 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <937500 937500 1000000>; + opp-microvolt-L4 = <925000 925000 1000000>; + opp-microvolt-L5 = <912500 912000 1000000>; + opp-microvolt-L6 = <900000 900000 1000000>; + opp-microvolt-L7 = <887500 887500 1000000>; + clock-latency-ns = <40000>; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + trust@0 { + reg = <0x0 0x62000>; + }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + linux,cma-default; + }; + + drm_logo: drm-logo@0 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0>; + }; + + ramoops: ramoops@83000 { + compatible = "ramoops"; + reg = <0x83000 0x2d000>; + boot-log-size = <0xd000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x20000>; + pmsg-size = <0x0>; + ftrace-size = <0x0>; + record-size = <0x0>; + }; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-config"; + status = "okay"; + + rockchip,sleep-mode-config = < + (0 + | RKPM_ARMOFF_DDRPD + | RKPM_24M_OSC_DIS + | RKPM_32K_CLK + | RKPM_32K_SRC_RC + ) + >; + + rockchip,wakeup-config = < + (0 + | RKPM_GPIO0_WAKEUP_EN + ) + >; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 0>; + trips { + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + dmac0: dma-controller@ff000000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff000000 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <5>; + arm,pl330-periph-burst; + }; + + dmac1: dma-controller@ff008000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff008000 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <5>; + arm,pl330-periph-burst; + }; + + i2c0: i2c@ff040000 { + compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; + reg = <0xff040000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + status = "disabled"; + }; + + i2c1: i2c@ff050000 { + compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; + reg = <0xff050000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + status = "disabled"; + }; + + i2c2: i2c@ff060000 { + compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; + reg = <0xff060000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + status = "disabled"; + }; + + uart0: serial@ff0a0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0a0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 4 0xff2880a8 0x03000100 0x0 0x0>, + <&dmac0 5 0xff2880a8 0x0c000400 0x0 0x0>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer_pins>; + status = "disabled"; + }; + + uart1: serial@ff0b0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0b0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 6 0xff2880a8 0x30001000 0x0 0x0>, + <&dmac0 7 0xff2880a8 0xc0004000 0x0 0x0>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@ff0c0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0c0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 8 0xff2880ac 0x00030001 0x0 0x0>, + <&dmac0 9 0xff2880ac 0x000c0004 0x0 0x0>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@ff0d0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0d0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 10 0xff2880ac 0x00300010 0x0 0x0>, + <&dmac0 11 0xff2880ac 0x00c00040 0x0 0x0>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart4: serial@ff0e0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0e0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 12 0x0 0x0 0x0 0x0>, <&dmac1 13 0x0 0x0 0x0 0x0>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + spi0: spi@ff120000 { + compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi"; + reg = <0xff120000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 0 0xff2880a8 0x00030001 0x0 0x0>, + <&dmac0 1 0xff2880a8 0x000c0004 0x0 0x0>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_csn0_pins &spi0_csn1_pins &spi0_clk_pins>; + status = "disabled"; + }; + + spi1: spi@ff130000 { + compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi"; + reg = <0xff130000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 2 0xff2880a8 0x00300010 0x0 0x0>, + <&dmac0 3 0xff2880a8 0x00c00040 0x0 0x0>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_csn0_pins &spi1_csn1_pins &spi1_clk_pins>; + status = "disabled"; + }; + + pwm1_8ch_0: pwm@ff170000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff170000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_1: pwm@ff171000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff171000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_2: pwm@ff172000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff172000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_3: pwm@ff173000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff173000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_4: pwm@ff174000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff174000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_5: pwm@ff175000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff175000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_6: pwm@ff176000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff176000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_7: pwm@ff177000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff177000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + hwlock0: hwspinlock@ff240000 { + compatible = "rockchip,hwspinlock"; + reg = <0xff240000 0x20>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <8>; + status = "disabled"; + }; + + hwlock1: hwspinlock@ff241000 { + compatible = "rockchip,hwspinlock"; + reg = <0xff241000 0x20>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <8>; + status = "disabled"; + }; + + hwlock2: hwspinlock@ff242000 { + compatible = "rockchip,hwspinlock"; + reg = <0xff242000 0x20>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <8>; + status = "disabled"; + }; + + hwlock3: hwspinlock@ff243000 { + compatible = "rockchip,hwspinlock"; + reg = <0xff243000 0x20>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <8>; + status = "disabled"; + }; + + wdt0: watchdog@ff260000 { + compatible = "snps,dw-wdt"; + reg = <0xff260000 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + wdt1: watchdog@ff268000 { + compatible = "snps,dw-wdt"; + reg = <0xff268000 0x100>; + clocks = <&cru TCLK_WDT1>, <&cru PCLK_WDT1>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + grf: syscon@ff288000 { + compatible = "rockchip,rk3506-grf", "syscon", "simple-mfd"; + reg = <0xff288000 0x4000>; + }; + + mailbox0: mailbox@ff290000 { + compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; + reg = <0xff290000 0x20>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox1: mailbox@ff291000 { + compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; + reg = <0xff291000 0x20>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox2: mailbox@ff292000 { + compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; + reg = <0xff292000 0x20>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox3: mailbox@ff293000 { + compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; + reg = <0xff293000 0x20>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + usb2phy: usb2-phy@ff2b0000 { + compatible = "rockchip,rk3506-usb2phy"; + reg = <0xff2b0000 0x8000>; + clocks = <&cru CLK_REF_USBPHY_TOP>, <&cru PCLK_USBPHY>; + clock-names = "phyclk", "apb_pclk"; + #clock-cells = <0>; + rockchip,usbgrf = <&grf>; + status = "disabled"; + + u2phy_otg0: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", + "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy_otg1: host-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", + "otg-id", + "linestate"; + status = "disabled"; + }; + }; + + sai0: sai@ff300000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff300000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 1 0xff2880a4 0x01000000 0x0 0x0>, + <&dmac1 0 0xff2880a4 0x00800000 0x0 0x0>; + // dmas = <&dmac0 9 0xff2880a4 0x01000100 0xff2880ac 0x000c0000>, + // <&dmac0 8 0xff2880a4 0x00800080 0xff2880ac 0x00030002>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI0>, <&cru SRST_H_SAI0>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI0"; + pinctrl-names = "default"; + pinctrl-0 = <&sai0_lrck_pins + &sai0_sclk_pins + &sai0_sdi0_pins + &sai0_sdi1_pins + &sai0_sdi2_pins + &sai0_sdi3_pins + &sai0_sdo_pins>; + status = "disabled"; + }; + + sai1: sai@ff310000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff310000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 3 0xff2880a4 0x04000000 0x0 0x0>, + <&dmac1 2 0xff2880a4 0x02000000 0x0 0x0>; + // dmas = <&dmac0 11 0xff2880a4 0x04000400 0xff2880ac 0x00c00000>, + // <&dmac0 10 0xff2880a4 0x02000200 0xff2880ac 0x00300020>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI1>, <&cru SRST_H_SAI1>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI1"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1_lrck_pins + &sai1_sclk_pins + &sai1_sdi_pins + &sai1_sdo0_pins + &sai1_sdo1_pins + &sai1_sdo2_pins + &sai1_sdo3_pins>; + status = "disabled"; + }; + + pdm: pdm@ff380000 { + compatible = "rockchip,rk3506-pdm", "rockchip,rk3576-pdm"; + reg = <0xff380000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>, <&cru CLKOUT_PDM>; + clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; + dmas = <&dmac1 9 0xff2880a4 0x00100000 0x0 0x0>; + // dmas = <&dmac0 5 0xff2880a4 0x00100010 0xff2880a8 0x0c000800>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io0_pdm_clk0 + &rm_io0_pdm_clk1 + &rm_io0_pdm_sdi0 + &rm_io0_pdm_sdi1 + &rm_io0_pdm_sdi2 + &rm_io0_pdm_sdi3>; + #sound-dai-cells = <0>; + sound-name-prefix = "PDM0"; + status = "disabled"; + }; + + spdif_tx: spdif-tx@ff3a0000 { + compatible = "rockchip,rk3506-spdif", "rockchip,rk3066-spdif"; + reg = <0xff3a0000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFTX>, <&cru HCLK_SPDIFTX>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 10 0xff2880a4 0x00200000 0xff2880ac 0x03000100>; + // dmas = <&dmac0 6 0xff2880a4 0x00200020 0xff2880a8 0x30000000>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io0_spdif_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx: spdif-rx@ff3b0000 { + compatible = "rockchip,rk3506-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0xff3b0000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFRX>, <&cru HCLK_SPDIFRX>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 11 0xff2880a4 0x00400000 0xff2880ac 0x0c000400>; + // dmas = <&dmac0 7 0xff2880a4 0x00400040 0xff2880a8 0xc0000000>; + dma-names = "rx"; + resets = <&cru SRST_SPDIFRX>; + reset-names = "spdifrx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io0_spdif_rx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + asrc0: asrc@ff3c0000 { + compatible = "rockchip,rk3506-asrc"; + reg = <0xff3c0000 0x1000>; + interrupts = ; + clocks = <&cru CLK_ASRC0>, <&cru HCLK_ASRC0>, + <&cru LRCK_ASRC0_SRC>, <&cru LRCK_ASRC0_DST>; + clock-names = "mclk", "hclk", + "src_lrck", "dst_lrck"; + // dmas = <&dmac0 0 0xff2880a4 0x00010001 0xff2880a8 0x00030002>, + // <&dmac0 1 0xff2880a4 0x00020002 0xff2880a8 0x000c0008>; + dmas = <&dmac1 16 0xff2880a4 0x00010000 0x0 0x0>, + <&dmac1 17 0xff2880a4 0x00020000 0x0 0x0>; + dma-names = "rx", "tx"; + resets = <&cru SRST_ASRC0>, <&cru SRST_H_ASRC0>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "ASRC0"; + status = "disabled"; + }; + + asrc1: asrc@ff3d0000 { + compatible = "rockchip,rk3506-asrc"; + reg = <0xff3d0000 0x1000>; + interrupts = ; + clocks = <&cru CLK_ASRC1>, <&cru HCLK_ASRC1>, + <&cru LRCK_ASRC1_SRC>, <&cru LRCK_ASRC1_DST>; + clock-names = "mclk", "hclk", + "src_lrck", "dst_lrck"; + // dmas = <&dmac0 2 0xff2880a4 0x00040004 0xff2880a8 0x00300020>, + // <&dmac0 3 0xff2880a4 0x00080008 0xff2880a8 0x00c00080>; + dmas = <&dmac1 18 0xff2880a4 0x00040000 0x0 0x0>, + <&dmac1 19 0xff2880a4 0x00080000 0x0 0x0>; + dma-names = "rx", "tx"; + resets = <&cru SRST_ASRC1>, <&cru SRST_H_ASRC1>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "ASRC1"; + status = "disabled"; + }; + + mmc: mmc@ff480000 { + compatible = "rockchip,rk3506-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xff480000 0x4000>; + interrupts = ; + max-frequency = <150000000>; + bus-width = <4>; + clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + resets = <&cru SRST_H_SDMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + fspi: spi@ff488000 { + compatible = "rockchip,fspi"; + reg = <0xff488000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_FSPI>, <&cru HCLK_FSPI>; + clock-names = "clk_sfc", "hclk_sfc"; + rockchip,max-dll = <0x17F>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sai2: sai@ff498000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff498000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 5 0x0 0x0 0x0 0x0>, <&dmac1 4 0x0 0x0 0x0 0x0>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI2>, <&cru SRST_H_SAI2>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI2"; + pinctrl-names = "default"; + pinctrl-0 = <&sai2m0_lrck_pins + &sai2m0_sclk_pins + &sai2m0_sdi_pins + &sai2m0_sdo_pins>; + status = "disabled"; + }; + + sai3: sai@ff4a0000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff4a0000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI3>, <&cru HCLK_SAI3>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 6 0x0 0x0 0x0 0x0>, <&dmac1 7 0x0 0x0 0x0 0x0>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI3>, <&cru SRST_H_SAI3>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI3"; + pinctrl-names = "default"; + pinctrl-0 = <&sai3_lrck_pins + &sai3_sclk_pins + &sai3_sdi_pins + &sai3_sdo_pins>; + status = "disabled"; + }; + + sai4: sai@ff4a8000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff4a8000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI4>, <&cru HCLK_SAI4>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 8 0x0 0x0 0x0 0x0>; + dma-names = "rx"; + resets = <&cru SRST_M_SAI4>, <&cru SRST_H_SAI4>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI4"; + status = "disabled"; + }; + + acdcdig_dsm: acdcdig-dsm@ff4b0000 { + compatible = "rockchip,rk3506-dsm"; + reg = <0xff4b0000 0x1000>; + clocks = <&cru MCLK_DSM>, <&cru HCLK_DSM>; + clock-names = "dac", "pclk"; + resets = <&cru SRST_M_DSM>; + reset-names = "reset" ; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&dsm_audm0_ln_pins + &dsm_audm0_lp_pins + &dsm_audm0_rn_pins + &dsm_audm0_rp_pins>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ioc_grf: syscon@ff4d8000 { + compatible = "rockchip,rk3506-ioc-grf", "syscon"; + reg = <0xff4d8000 0x8000>; + }; + + uart5: serial@ff4e0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff4e0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 14 0x0 0x0 0x0 0x0>, <&dmac1 15 0x0 0x0 0x0 0x0>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins &uart5m0_rtsn_pins>; + status = "disabled"; + }; + + saradc: adc@ff4e8000 { + compatible = "rockchip,rk3506-saradc", "rockchip,rk3562-saradc"; + reg = <0xff4e8000 0x8000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + otp: otp@ff4f0000 { + compatible = "rockchip,rk3506-otp"; + reg = <0xff4f0000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, + <&cru PCLK_OTPC_NS>; + clock-names = "usr", "sbpi", "apb"; + resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, + <&cru SRST_P_OTPC_NS>; + reset-names = "usr", "sbpi", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@5 { + reg = <0x05 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpu_leakage: cpu-leakage@1e { + reg = <0x1e 0x1>; + }; + log_leakage: log-leakage@1f { + reg = <0x1f 0x1>; + }; + cpu_tsadc_trim_l: cpu-tsadc-trim-l@20 { + reg = <0x20 0x1>; + }; + cpu_tsadc_trim_h: cpu-tsadc-trim-h@21 { + reg = <0x21 0x1>; + bits = <0 2>; + }; + }; + + audio_codec: audio-codec@ff4f8000 { + compatible = "rockchip,rk3506-codec"; + reg = <0xff4f8000 0x1000>; + #sound-dai-cells = <0>; + clocks = <&cru PCLK_AUDIO_ADC>, <&cru MCLK_AUDIO_ADC>; + clock-names = "pclk", "mclk"; + resets = <&cru SRST_M_AUDIO_ADC>; + reset-names = "rst"; + status = "disabled"; + }; + + gic: interrupt-controller@ff581000 { + compatible = "arm,gic-400"; + reg = <0xff581000 0x1000>, + <0xff582000 0x2000>, + <0xff584000 0x2000>, + <0xff586000 0x2000>; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <0>; + }; + + rga2: rga@ff610000 { + compatible = "rockchip,rga2"; + reg = <0xff610000 0x1000>; + interrupts = ; + interrupt-names = "rga2_irq"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + status = "disabled"; + }; + + tsadc: tsadc@ff650000 { + compatible = "rockchip,rk3506-tsadc"; + reg = <0xff650000 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>; + clock-names = "tsadc", "apb_pclk", "tsen"; + assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; + assigned-clock-rates = <1000000>, <12000000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; + reset-names = "tsadc", "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + status = "disabled"; + }; + + ioc1: syscon@ff660000 { + compatible = "rockchip,rk3506-ioc1", "syscon"; + reg = <0xff660000 0x10000>; + }; + + crypto: crypto@ff700000 { + compatible = "rockchip,crypto-v4"; + reg = <0xff700000 0x2000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, + <&cru CLK_CORE_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>; + clock-names = "aclk", "hclk", "core", "pka"; + resets = <&cru SRST_H_CRYPTO>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@ff710000 { + compatible = "rockchip,rkrng"; + reg = <0xff710000 0x200>; + interrupts = ; + clocks = <&cru HCLK_RNG>; + clock-names = "hclk_trng"; + resets = <&cru SRST_H_RNG>; + reset-names = "reset"; + status = "disabled"; + }; + + usb20_otg0: usb@ff740000 { + compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff740000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBOTG0>, <&cru HCLK_USBOTG0_PMU>, + <&cru CLK_USBOTG0_ADP>; + clock-names = "otg", "pmu", "adp"; + dr_mode = "otg"; + phys = <&u2phy_otg0>; + phy-names = "usb2-phy"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + status = "disabled"; + }; + + usb20_otg1: usb@ff780000 { + compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff780000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBOTG1>, <&cru HCLK_USBOTG1_PMU>, + <&cru CLK_USBOTG1_ADP>; + clock-names = "otg", "pmu", "adp"; + dr_mode = "otg"; + phys = <&u2phy_otg1>; + phy-names = "usb2-phy"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + status = "disabled"; + }; + + arm-debug@ff810000 { + compatible = "rockchip,debug"; + reg = <0xff810000 0x1000>, + <0xff812000 0x1000>, + <0xff814000 0x1000>; + }; + + flexbus: flexbus@ff880000 { + compatible = "rockchip,rk3506-flexbus"; + reg = <0xff880000 0x200>; + interrupts = ; + clocks = <&cru CLK_FLEXBUS_TX>, <&cru CLK_FLEXBUS_RX>, + <&cru ACLK_FLEXBUS>, <&cru HCLK_FLEXBUS>; + clock-names = "tx_clk_flexbus", "rx_clk_flexbus", + "aclk_flexbus", "hclk_flexbus"; + rockchip,grf = <&grf>; + status = "disabled"; + + flexbus_adc: adc { + compatible = "rockchip,flexbus-adc"; + #io-channel-cells = <0>; + clocks = <&cru CLK_REF_OUT1>; + clock-names = "ref_clk"; /* ref_clk is only used for slave-mode */ + rockchip,slave-mode; + rockchip,free-sclk; + rockchip,auto-pad; + rockchip,dfs = <16>; + status = "disabled"; + }; + + flexbus_cif: cif { + compatible = "rockchip,flexbus-cif-rk3506"; + status = "disabled"; + }; + + flexbus_dac: dac { + compatible = "rockchip,flexbus-dac"; + #io-channel-cells = <0>; + rockchip,free-sclk; + rockchip,dfs = <16>; + status = "disabled"; + }; + + flexbus_fspi: fspi { + compatible = "rockchip,flexbus-fspi"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + flexbus_spi: spi { + compatible = "rockchip,flexbus-spi"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + grf_pmu: syscon@ff910000 { + compatible = "rockchip,rk3506-grf-pmu", "syscon", "simple-mfd"; + reg = <0xff910000 0x4000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + }; + }; + + pwm0_4ch_0: pwm@ff930000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff930000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; + clock-names = "pwm", "pclk", "osc"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_4ch_1: pwm@ff931000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff931000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; + clock-names = "pwm", "pclk", "osc"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_4ch_2: pwm@ff932000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff932000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; + clock-names = "pwm", "pclk", "osc"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_4ch_3: pwm@ff933000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff933000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; + clock-names = "pwm", "pclk", "osc"; + #pwm-cells = <3>; + status = "disabled"; + }; + + ioc_pmu: syscon@ff950000 { + compatible = "rockchip,rk3506-ioc-pmu", "syscon"; + reg = <0xff950000 0x10000>; + }; + + cru: clock-controller@ff9a0000 { + compatible = "rockchip,rk3506-cru"; + reg = <0xff9a0000 0x20000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3506-pinctrl"; + rockchip,grf = <&ioc_grf>; + rockchip,ioc1 = <&ioc1>; + rockchip,pmu = <&ioc_pmu>; + rockchip,rmio = <&grf_pmu>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@ff940000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff940000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff870000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff870000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff1c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff1c0000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff1d0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff1d0000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ff1e0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff1e0000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3506-pinctrl.dtsi" +#include "rk3506-pinctrl-rmio.dtsi" diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 492108fd608c..1d172643c8b8 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -3,320 +3,14 @@ * Copyright (c) 2023 Rockchip Electronics Co., Ltd. */ -#include -#include -#include -#include -#include -#include -#include +#include "rk3502.dtsi" / { - #address-cells = <1>; - #size-cells = <1>; - compatible = "rockchip,rk3506"; - interrupt-parent = <&gic>; - aliases { ethernet0 = &gmac0; ethernet1 = &gmac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &fspi; - spi3 = &flexbus_fspi; - spi4 = &flexbus_spi; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_rc: clk-rc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000>; - clock-output-names = "clk_rc"; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; - - clk_spdifrx_to_asrc: clk-spdifrx-to-asrc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "clk_spdifrx_to_asrc"; - }; - - mclkin_sai0: mclkin-sai0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "sai0_mclk_in"; - }; - - mclkin_sai1: mclkin-sai1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "sai1_mclk_in"; - }; - - mclkin_sai2: mclkin-sai2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "sai2_mclk_in"; - }; - - mclkin_sai3: mclkin-sai3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "sai3_mclk_in"; - }; - - mclkout_sai0: mclkout-sai0@ff910004 { - compatible = "rockchip,clk-out"; - reg = <0xff910004 0x4>; - clocks = <&cru MCLK_OUT_SAI0>; - #clock-cells = <0>; - clock-output-names = "mclk_sai0_to_io"; - rockchip,bit-shift = <8>; - }; - - mclkout_sai1: mclkout-sai1@ff910004 { - compatible = "rockchip,clk-out"; - reg = <0xff910004 0x4>; - clocks = <&cru MCLK_OUT_SAI1>; - #clock-cells = <0>; - clock-output-names = "mclk_sai1_to_io"; - rockchip,bit-shift = <9>; - }; - - mclkout_sai2: mclkout-sai2@ff288004 { - compatible = "rockchip,clk-out"; - reg = <0xff288004 0x4>; - clocks = <&cru MCLK_OUT_SAI2>; - #clock-cells = <0>; - clock-output-names = "mclk_sai2_to_io"; - rockchip,bit-shift = <2>; - }; - - mclkout_sai3: mclkout-sai3@ff288004 { - compatible = "rockchip,clk-out"; - reg = <0xff288004 0x4>; - clocks = <&cru MCLK_OUT_SAI3>; - #clock-cells = <0>; - clock-output-names = "mclk_sai3_to_io"; - rockchip,bit-shift = <3>; - }; - - pvtpll_core: pvtpll-core@ff840000 { - compatible = "rockchip,rk3506-core-pvtpll", "syscon"; - reg = <0xff840000 0x100>; - #clock-cells = <0>; - clock-output-names = "clk_core_pvtpll"; - assigned-clocks = <&pvtpll_core>; - assigned-clock-rates = <1200000000>; - }; - - sai0_fs: sai0-fs { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "sai0_fs"; - }; - - sai1_fs: sai1-fs { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "sai1_fs"; - }; - - sai2_fs: sai2-fs { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "sai2_fs"; - }; - - sai3_fs: sai3-fs { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "sai3_fs"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - nvmem-cells = <&cpu_leakage>; - nvmem-cell-names = "leakage"; - - rockchip,pvtm-voltage-sel = < - 0 1584 0 - 1585 1619 1 - 1620 1654 2 - 1655 1689 3 - 1690 1724 4 - 1725 1759 5 - 1760 1794 6 - 1795 9999 7 - >; - rockchip,pvtm-pvtpll; - rockchip,pvtm-offset = <0x18>; - rockchip,pvtm-sample-time = <500>; - rockchip,pvtm-freq = <1608000>; - rockchip,pvtm-volt = <1000000>; - rockchip,pvtm-ref-temp = <40>; - rockchip,pvtm-temp-prop = <0 0>; - rockchip,pvtm-thermal-zone = "soc-thermal"; - rockchip,grf = <&pvtpll_core>; - rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <10000>; - rockchip,low-temp-min-volt = <900000>; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <850000 850000 1000000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <850000 850000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <850000 850000 1000000>; - opp-microvolt-L0 = <875000 875000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <850000 850000 1000000>; - opp-microvolt-L0 = <875000 875000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <900000 900000 1000000>; - opp-microvolt-L0 = <900000 900000 1000000>; - opp-microvolt-L1 = <887500 887500 1000000>; - opp-microvolt-L2 = <875000 875000 1000000>; - opp-microvolt-L3 = <862500 862500 1000000>; - opp-microvolt-L4 = <850000 850000 1000000>; - opp-microvolt-L5 = <850000 850000 1000000>; - opp-microvolt-L6 = <850000 850000 1000000>; - opp-microvolt-L7 = <850000 850000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <937500 937500 1000000>; - opp-microvolt-L0 = <937500 937500 1000000>; - opp-microvolt-L1 = <925000 925000 1000000>; - opp-microvolt-L2 = <912500 912500 1000000>; - opp-microvolt-L3 = <900000 900000 1000000>; - opp-microvolt-L4 = <887500 887500 1000000>; - opp-microvolt-L5 = <875000 875000 1000000>; - opp-microvolt-L6 = <862500 862500 1000000>; - opp-microvolt-L7 = <850000 850000 1000000>; - clock-latency-ns = <40000>; - }; - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <975000 975000 1000000>; - opp-microvolt-L0 = <975000 975000 1000000>; - opp-microvolt-L1 = <962500 962500 1000000>; - opp-microvolt-L2 = <950000 950000 1000000>; - opp-microvolt-L3 = <937500 937500 1000000>; - opp-microvolt-L4 = <925000 925000 1000000>; - opp-microvolt-L5 = <912500 912000 1000000>; - opp-microvolt-L6 = <900000 900000 1000000>; - opp-microvolt-L7 = <887500 887500 1000000>; - clock-latency-ns = <40000>; - }; - }; - - arm_pmu: arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; - }; - - cpuinfo { - compatible = "rockchip,cpuinfo"; - nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; - nvmem-cell-names = "id", "cpu-version", "cpu-code"; }; display_subsystem: display-subsystem { @@ -345,531 +39,6 @@ }; }; - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved_memory: reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - trust@0 { - reg = <0x0 0x62000>; - }; - - cma: linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0>; - linux,cma-default; - }; - - drm_logo: drm-logo@0 { - compatible = "rockchip,drm-logo"; - reg = <0x0 0x0>; - }; - - ramoops: ramoops@83000 { - compatible = "ramoops"; - reg = <0x83000 0x2d000>; - boot-log-size = <0xd000>; /* do not change */ - boot-log-count = <0x1>; /* do not change */ - console-size = <0x20000>; - pmsg-size = <0x0>; - ftrace-size = <0x0>; - record-size = <0x0>; - }; - }; - - rockchip_suspend: rockchip-suspend { - compatible = "rockchip,pm-config"; - status = "okay"; - - rockchip,sleep-mode-config = < - (0 - | RKPM_ARMOFF_DDRPD - | RKPM_24M_OSC_DIS - | RKPM_32K_CLK - | RKPM_32K_SRC_RC - ) - >; - - rockchip,wakeup-config = < - (0 - | RKPM_GPIO0_WAKEUP_EN - ) - >; - }; - - rockchip_system_monitor: rockchip-system-monitor { - compatible = "rockchip,system-monitor"; - - rockchip,thermal-zone = "soc-thermal"; - }; - - thermal_zones: thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&tsadc 0>; - trips { - soc_crit: soc-crit { - /* millicelsius */ - temperature = <115000>; - /* millicelsius */ - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - dmac0: dma-controller@ff000000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xff000000 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <5>; - arm,pl330-periph-burst; - }; - - dmac1: dma-controller@ff008000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xff008000 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <5>; - arm,pl330-periph-burst; - }; - - i2c0: i2c@ff040000 { - compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; - reg = <0xff040000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - status = "disabled"; - }; - - i2c1: i2c@ff050000 { - compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; - reg = <0xff050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - status = "disabled"; - }; - - i2c2: i2c@ff060000 { - compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; - reg = <0xff060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - status = "disabled"; - }; - - uart0: serial@ff0a0000 { - compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; - reg = <0xff0a0000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 4 0xff2880a8 0x03000100 0x0 0x0>, - <&dmac0 5 0xff2880a8 0x0c000400 0x0 0x0>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer_pins>; - status = "disabled"; - }; - - uart1: serial@ff0b0000 { - compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; - reg = <0xff0b0000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 6 0xff2880a8 0x30001000 0x0 0x0>, - <&dmac0 7 0xff2880a8 0xc0004000 0x0 0x0>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart2: serial@ff0c0000 { - compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; - reg = <0xff0c0000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 8 0xff2880ac 0x00030001 0x0 0x0>, - <&dmac0 9 0xff2880ac 0x000c0004 0x0 0x0>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart3: serial@ff0d0000 { - compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; - reg = <0xff0d0000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 10 0xff2880ac 0x00300010 0x0 0x0>, - <&dmac0 11 0xff2880ac 0x00c00040 0x0 0x0>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - uart4: serial@ff0e0000 { - compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; - reg = <0xff0e0000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac1 12 0x0 0x0 0x0 0x0>, <&dmac1 13 0x0 0x0 0x0 0x0>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - status = "disabled"; - }; - - spi0: spi@ff120000 { - compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi"; - reg = <0xff120000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 0 0xff2880a8 0x00030001 0x0 0x0>, - <&dmac0 1 0xff2880a8 0x000c0004 0x0 0x0>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_csn0_pins &spi0_csn1_pins &spi0_clk_pins>; - status = "disabled"; - }; - - spi1: spi@ff130000 { - compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi"; - reg = <0xff130000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 2 0xff2880a8 0x00300010 0x0 0x0>, - <&dmac0 3 0xff2880a8 0x00c00040 0x0 0x0>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_csn0_pins &spi1_csn1_pins &spi1_clk_pins>; - status = "disabled"; - }; - - pwm1_8ch_0: pwm@ff170000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff170000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1_8ch_1: pwm@ff171000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff171000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1_8ch_2: pwm@ff172000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff172000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1_8ch_3: pwm@ff173000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff173000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1_8ch_4: pwm@ff174000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff174000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1_8ch_5: pwm@ff175000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff175000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1_8ch_6: pwm@ff176000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff176000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1_8ch_7: pwm@ff177000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff177000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - hwlock0: hwspinlock@ff240000 { - compatible = "rockchip,hwspinlock"; - reg = <0xff240000 0x20>; - #hwlock-cells = <1>; - rockchip,hwlock-num-locks = <8>; - status = "disabled"; - }; - - hwlock1: hwspinlock@ff241000 { - compatible = "rockchip,hwspinlock"; - reg = <0xff241000 0x20>; - #hwlock-cells = <1>; - rockchip,hwlock-num-locks = <8>; - status = "disabled"; - }; - - hwlock2: hwspinlock@ff242000 { - compatible = "rockchip,hwspinlock"; - reg = <0xff242000 0x20>; - #hwlock-cells = <1>; - rockchip,hwlock-num-locks = <8>; - status = "disabled"; - }; - - hwlock3: hwspinlock@ff243000 { - compatible = "rockchip,hwspinlock"; - reg = <0xff243000 0x20>; - #hwlock-cells = <1>; - rockchip,hwlock-num-locks = <8>; - status = "disabled"; - }; - - wdt0: watchdog@ff260000 { - compatible = "snps,dw-wdt"; - reg = <0xff260000 0x100>; - clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; - clock-names = "tclk", "pclk"; - interrupts = ; - status = "disabled"; - }; - - wdt1: watchdog@ff268000 { - compatible = "snps,dw-wdt"; - reg = <0xff268000 0x100>; - clocks = <&cru TCLK_WDT1>, <&cru PCLK_WDT1>; - clock-names = "tclk", "pclk"; - interrupts = ; - status = "disabled"; - }; - - grf: syscon@ff288000 { - compatible = "rockchip,rk3506-grf", "syscon", "simple-mfd"; - reg = <0xff288000 0x4000>; - - rgb: rgb { - compatible = "rockchip,rk3506-rgb"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - rgb_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_rgb>; - }; - }; - }; - }; - }; - - mailbox0: mailbox@ff290000 { - compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; - reg = <0xff290000 0x20>; - interrupts = ; - clocks = <&cru PCLK_MAILBOX>; - clock-names = "pclk_mailbox"; - #mbox-cells = <1>; - status = "disabled"; - }; - - mailbox1: mailbox@ff291000 { - compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; - reg = <0xff291000 0x20>; - interrupts = ; - clocks = <&cru PCLK_MAILBOX>; - clock-names = "pclk_mailbox"; - #mbox-cells = <1>; - status = "disabled"; - }; - - mailbox2: mailbox@ff292000 { - compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; - reg = <0xff292000 0x20>; - interrupts = ; - clocks = <&cru PCLK_MAILBOX>; - clock-names = "pclk_mailbox"; - #mbox-cells = <1>; - status = "disabled"; - }; - - mailbox3: mailbox@ff293000 { - compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; - reg = <0xff293000 0x20>; - interrupts = ; - clocks = <&cru PCLK_MAILBOX>; - clock-names = "pclk_mailbox"; - #mbox-cells = <1>; - status = "disabled"; - }; - - usb2phy: usb2-phy@ff2b0000 { - compatible = "rockchip,rk3506-usb2phy"; - reg = <0xff2b0000 0x8000>; - clocks = <&cru CLK_REF_USBPHY_TOP>, <&cru PCLK_USBPHY>; - clock-names = "phyclk", "apb_pclk"; - #clock-cells = <0>; - rockchip,usbgrf = <&grf>; - status = "disabled"; - - u2phy_otg0: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", - "otg-id", - "linestate"; - status = "disabled"; - }; - - u2phy_otg1: host-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", - "otg-id", - "linestate"; - status = "disabled"; - }; - }; - - sai0: sai@ff300000 { - compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; - reg = <0xff300000 0x1000>; - interrupts = ; - clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 1 0xff2880a4 0x01000000 0x0 0x0>, - <&dmac1 0 0xff2880a4 0x00800000 0x0 0x0>; - // dmas = <&dmac0 9 0xff2880a4 0x01000100 0xff2880ac 0x000c0000>, - // <&dmac0 8 0xff2880a4 0x00800080 0xff2880ac 0x00030002>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_SAI0>, <&cru SRST_H_SAI0>; - reset-names = "m", "h"; - #sound-dai-cells = <0>; - sound-name-prefix = "SAI0"; - pinctrl-names = "default"; - pinctrl-0 = <&sai0_lrck_pins - &sai0_sclk_pins - &sai0_sdi0_pins - &sai0_sdi1_pins - &sai0_sdi2_pins - &sai0_sdi3_pins - &sai0_sdo_pins>; - status = "disabled"; - }; - - sai1: sai@ff310000 { - compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; - reg = <0xff310000 0x1000>; - interrupts = ; - clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 3 0xff2880a4 0x04000000 0x0 0x0>, - <&dmac1 2 0xff2880a4 0x02000000 0x0 0x0>; - // dmas = <&dmac0 11 0xff2880a4 0x04000400 0xff2880ac 0x00c00000>, - // <&dmac0 10 0xff2880a4 0x02000200 0xff2880ac 0x00300020>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_SAI1>, <&cru SRST_H_SAI1>; - reset-names = "m", "h"; - #sound-dai-cells = <0>; - sound-name-prefix = "SAI1"; - pinctrl-names = "default"; - pinctrl-0 = <&sai1_lrck_pins - &sai1_sclk_pins - &sai1_sdi_pins - &sai1_sdo0_pins - &sai1_sdo1_pins - &sai1_sdo2_pins - &sai1_sdo3_pins>; - status = "disabled"; - }; - can0: can@ff320000 { compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd"; reg = <0xff320000 0x1000>; @@ -892,197 +61,6 @@ status = "disabled"; }; - pdm: pdm@ff380000 { - compatible = "rockchip,rk3506-pdm", "rockchip,rk3576-pdm"; - reg = <0xff380000 0x1000>; - interrupts = ; - clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>, <&cru CLKOUT_PDM>; - clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; - dmas = <&dmac1 9 0xff2880a4 0x00100000 0x0 0x0>; - // dmas = <&dmac0 5 0xff2880a4 0x00100010 0xff2880a8 0x0c000800>; - dma-names = "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&rm_io0_pdm_clk0 - &rm_io0_pdm_clk1 - &rm_io0_pdm_sdi0 - &rm_io0_pdm_sdi1 - &rm_io0_pdm_sdi2 - &rm_io0_pdm_sdi3>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM0"; - status = "disabled"; - }; - - spdif_tx: spdif-tx@ff3a0000 { - compatible = "rockchip,rk3506-spdif", "rockchip,rk3066-spdif"; - reg = <0xff3a0000 0x1000>; - interrupts = ; - clocks = <&cru MCLK_SPDIFTX>, <&cru HCLK_SPDIFTX>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 10 0xff2880a4 0x00200000 0xff2880ac 0x03000100>; - // dmas = <&dmac0 6 0xff2880a4 0x00200020 0xff2880a8 0x30000000>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&rm_io0_spdif_tx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif_rx: spdif-rx@ff3b0000 { - compatible = "rockchip,rk3506-spdifrx", "rockchip,rk3308-spdifrx"; - reg = <0xff3b0000 0x1000>; - interrupts = ; - clocks = <&cru MCLK_SPDIFRX>, <&cru HCLK_SPDIFRX>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 11 0xff2880a4 0x00400000 0xff2880ac 0x0c000400>; - // dmas = <&dmac0 7 0xff2880a4 0x00400040 0xff2880a8 0xc0000000>; - dma-names = "rx"; - resets = <&cru SRST_SPDIFRX>; - reset-names = "spdifrx-m"; - pinctrl-names = "default"; - pinctrl-0 = <&rm_io0_spdif_rx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - asrc0: asrc@ff3c0000 { - compatible = "rockchip,rk3506-asrc"; - reg = <0xff3c0000 0x1000>; - interrupts = ; - clocks = <&cru CLK_ASRC0>, <&cru HCLK_ASRC0>, - <&cru LRCK_ASRC0_SRC>, <&cru LRCK_ASRC0_DST>; - clock-names = "mclk", "hclk", - "src_lrck", "dst_lrck"; - // dmas = <&dmac0 0 0xff2880a4 0x00010001 0xff2880a8 0x00030002>, - // <&dmac0 1 0xff2880a4 0x00020002 0xff2880a8 0x000c0008>; - dmas = <&dmac1 16 0xff2880a4 0x00010000 0x0 0x0>, - <&dmac1 17 0xff2880a4 0x00020000 0x0 0x0>; - dma-names = "rx", "tx"; - resets = <&cru SRST_ASRC0>, <&cru SRST_H_ASRC0>; - reset-names = "m", "h"; - #sound-dai-cells = <0>; - sound-name-prefix = "ASRC0"; - status = "disabled"; - }; - - asrc1: asrc@ff3d0000 { - compatible = "rockchip,rk3506-asrc"; - reg = <0xff3d0000 0x1000>; - interrupts = ; - clocks = <&cru CLK_ASRC1>, <&cru HCLK_ASRC1>, - <&cru LRCK_ASRC1_SRC>, <&cru LRCK_ASRC1_DST>; - clock-names = "mclk", "hclk", - "src_lrck", "dst_lrck"; - // dmas = <&dmac0 2 0xff2880a4 0x00040004 0xff2880a8 0x00300020>, - // <&dmac0 3 0xff2880a4 0x00080008 0xff2880a8 0x00c00080>; - dmas = <&dmac1 18 0xff2880a4 0x00040000 0x0 0x0>, - <&dmac1 19 0xff2880a4 0x00080000 0x0 0x0>; - dma-names = "rx", "tx"; - resets = <&cru SRST_ASRC1>, <&cru SRST_H_ASRC1>; - reset-names = "m", "h"; - #sound-dai-cells = <0>; - sound-name-prefix = "ASRC1"; - status = "disabled"; - }; - - mmc: mmc@ff480000 { - compatible = "rockchip,rk3506-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0xff480000 0x4000>; - interrupts = ; - max-frequency = <150000000>; - bus-width = <4>; - clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - resets = <&cru SRST_H_SDMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - fspi: spi@ff488000 { - compatible = "rockchip,fspi"; - reg = <0xff488000 0x4000>; - interrupts = ; - clocks = <&cru SCLK_FSPI>, <&cru HCLK_FSPI>; - clock-names = "clk_sfc", "hclk_sfc"; - rockchip,max-dll = <0x17F>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sai2: sai@ff498000 { - compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; - reg = <0xff498000 0x1000>; - interrupts = ; - clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 5 0x0 0x0 0x0 0x0>, <&dmac1 4 0x0 0x0 0x0 0x0>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_SAI2>, <&cru SRST_H_SAI2>; - reset-names = "m", "h"; - #sound-dai-cells = <0>; - sound-name-prefix = "SAI2"; - pinctrl-names = "default"; - pinctrl-0 = <&sai2m0_lrck_pins - &sai2m0_sclk_pins - &sai2m0_sdi_pins - &sai2m0_sdo_pins>; - status = "disabled"; - }; - - sai3: sai@ff4a0000 { - compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; - reg = <0xff4a0000 0x1000>; - interrupts = ; - clocks = <&cru MCLK_SAI3>, <&cru HCLK_SAI3>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 6 0x0 0x0 0x0 0x0>, <&dmac1 7 0x0 0x0 0x0 0x0>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_SAI3>, <&cru SRST_H_SAI3>; - reset-names = "m", "h"; - #sound-dai-cells = <0>; - sound-name-prefix = "SAI3"; - pinctrl-names = "default"; - pinctrl-0 = <&sai3_lrck_pins - &sai3_sclk_pins - &sai3_sdi_pins - &sai3_sdo_pins>; - status = "disabled"; - }; - - sai4: sai@ff4a8000 { - compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; - reg = <0xff4a8000 0x1000>; - interrupts = ; - clocks = <&cru MCLK_SAI4>, <&cru HCLK_SAI4>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 8 0x0 0x0 0x0 0x0>; - dma-names = "rx"; - resets = <&cru SRST_M_SAI4>, <&cru SRST_H_SAI4>; - reset-names = "m", "h"; - #sound-dai-cells = <0>; - sound-name-prefix = "SAI4"; - status = "disabled"; - }; - - acdcdig_dsm: acdcdig-dsm@ff4b0000 { - compatible = "rockchip,rk3506-dsm"; - reg = <0xff4b0000 0x1000>; - clocks = <&cru MCLK_DSM>, <&cru HCLK_DSM>; - clock-names = "dac", "pclk"; - resets = <&cru SRST_M_DSM>; - reset-names = "reset" ; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&dsm_audm0_ln_pins - &dsm_audm0_lp_pins - &dsm_audm0_rn_pins - &dsm_audm0_rp_pins>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - gmac0: ethernet@ff4c8000 { compatible = "rockchip,rk3506-gmac", "snps,dwmac-4.20a"; reg = <0xff4c8000 0x2000>; @@ -1185,98 +163,6 @@ }; }; - ioc_grf: syscon@ff4d8000 { - compatible = "rockchip,rk3506-ioc-grf", "syscon"; - reg = <0xff4d8000 0x8000>; - }; - - uart5: serial@ff4e0000 { - compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; - reg = <0xff4e0000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac1 14 0x0 0x0 0x0 0x0>, <&dmac1 15 0x0 0x0 0x0 0x0>; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins &uart5m0_rtsn_pins>; - status = "disabled"; - }; - - saradc: adc@ff4e8000 { - compatible = "rockchip,rk3506-saradc", "rockchip,rk3562-saradc"; - reg = <0xff4e8000 0x8000>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - otp: otp@ff4f0000 { - compatible = "rockchip,rk3506-otp"; - reg = <0xff4f0000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, - <&cru PCLK_OTPC_NS>; - clock-names = "usr", "sbpi", "apb"; - resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, - <&cru SRST_P_OTPC_NS>; - reset-names = "usr", "sbpi", "apb"; - - /* Data cells */ - cpu_code: cpu-code@2 { - reg = <0x02 0x2>; - }; - otp_cpu_version: cpu-version@5 { - reg = <0x05 0x1>; - bits = <3 3>; - }; - otp_id: id@a { - reg = <0x0a 0x10>; - }; - cpu_leakage: cpu-leakage@1e { - reg = <0x1e 0x1>; - }; - log_leakage: log-leakage@1f { - reg = <0x1f 0x1>; - }; - cpu_tsadc_trim_l: cpu-tsadc-trim-l@20 { - reg = <0x20 0x1>; - }; - cpu_tsadc_trim_h: cpu-tsadc-trim-h@21 { - reg = <0x21 0x1>; - bits = <0 2>; - }; - }; - - audio_codec: audio-codec@ff4f8000 { - compatible = "rockchip,rk3506-codec"; - reg = <0xff4f8000 0x1000>; - #sound-dai-cells = <0>; - clocks = <&cru PCLK_AUDIO_ADC>, <&cru MCLK_AUDIO_ADC>; - clock-names = "pclk", "mclk"; - resets = <&cru SRST_M_AUDIO_ADC>; - reset-names = "rst"; - status = "disabled"; - }; - - gic: interrupt-controller@ff581000 { - compatible = "arm,gic-400"; - reg = <0xff581000 0x1000>, - <0xff582000 0x2000>, - <0xff584000 0x2000>, - <0xff586000 0x2000>; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - #address-cells = <0>; - }; - vop: vop@ff600000 { compatible = "rockchip,rk3506-vop"; reg = <0xff600000 0x200>, <0xff600a00 0x400>; @@ -1303,16 +189,6 @@ }; }; - rga2: rga@ff610000 { - compatible = "rockchip,rga2"; - reg = <0xff610000 0x1000>; - interrupts = ; - interrupt-names = "rga2_irq"; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>; - clock-names = "aclk_rga", "hclk_rga", "clk_rga"; - status = "disabled"; - }; - dsi: dsi@ff640000 { compatible = "rockchip,rk3506-mipi-dsi"; reg = <0xff640000 0x10000>; @@ -1345,31 +221,6 @@ }; }; - tsadc: tsadc@ff650000 { - compatible = "rockchip,rk3506-tsadc"; - reg = <0xff650000 0x400>; - interrupts = ; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>; - clock-names = "tsadc", "apb_pclk", "tsen"; - assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; - assigned-clock-rates = <1000000>, <12000000>; - resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; - reset-names = "tsadc", "tsadc-apb"; - #thermal-sensor-cells = <1>; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <120000>; - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>; - nvmem-cell-names = "trim_l", "trim_h"; - status = "disabled"; - }; - - ioc1: syscon@ff660000 { - compatible = "rockchip,rk3506-ioc1", "syscon"; - reg = <0xff660000 0x10000>; - }; - dsi_dphy: phy@ff670000 { compatible = "rockchip,rk3506-dsi-dphy"; reg = <0xff670000 0x10000>, @@ -1385,121 +236,6 @@ status = "disabled"; }; - crypto: crypto@ff700000 { - compatible = "rockchip,crypto-v4"; - reg = <0xff700000 0x2000>; - interrupts = ; - clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, - <&cru CLK_CORE_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>; - clock-names = "aclk", "hclk", "core", "pka"; - resets = <&cru SRST_H_CRYPTO>; - reset-names = "crypto-rst"; - status = "disabled"; - }; - - rng: rng@ff710000 { - compatible = "rockchip,rkrng"; - reg = <0xff710000 0x200>; - interrupts = ; - clocks = <&cru HCLK_RNG>; - clock-names = "hclk_trng"; - resets = <&cru SRST_H_RNG>; - reset-names = "reset"; - status = "disabled"; - }; - - usb20_otg0: usb@ff740000 { - compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0xff740000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USBOTG0>, <&cru HCLK_USBOTG0_PMU>, - <&cru CLK_USBOTG0_ADP>; - clock-names = "otg", "pmu", "adp"; - dr_mode = "otg"; - phys = <&u2phy_otg0>; - phy-names = "usb2-phy"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - status = "disabled"; - }; - - usb20_otg1: usb@ff780000 { - compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0xff780000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USBOTG1>, <&cru HCLK_USBOTG1_PMU>, - <&cru CLK_USBOTG1_ADP>; - clock-names = "otg", "pmu", "adp"; - dr_mode = "otg"; - phys = <&u2phy_otg1>; - phy-names = "usb2-phy"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - status = "disabled"; - }; - - arm-debug@ff810000 { - compatible = "rockchip,debug"; - reg = <0xff810000 0x1000>, - <0xff812000 0x1000>, - <0xff814000 0x1000>; - }; - - flexbus: flexbus@ff880000 { - compatible = "rockchip,rk3506-flexbus"; - reg = <0xff880000 0x200>; - interrupts = ; - clocks = <&cru CLK_FLEXBUS_TX>, <&cru CLK_FLEXBUS_RX>, - <&cru ACLK_FLEXBUS>, <&cru HCLK_FLEXBUS>; - clock-names = "tx_clk_flexbus", "rx_clk_flexbus", - "aclk_flexbus", "hclk_flexbus"; - rockchip,grf = <&grf>; - status = "disabled"; - - flexbus_adc: adc { - compatible = "rockchip,flexbus-adc"; - #io-channel-cells = <0>; - clocks = <&cru CLK_REF_OUT1>; - clock-names = "ref_clk"; /* ref_clk is only used for slave-mode */ - rockchip,slave-mode; - rockchip,free-sclk; - rockchip,auto-pad; - rockchip,dfs = <16>; - status = "disabled"; - }; - - flexbus_cif: cif { - compatible = "rockchip,flexbus-cif-rk3506"; - status = "disabled"; - }; - - flexbus_dac: dac { - compatible = "rockchip,flexbus-dac"; - #io-channel-cells = <0>; - rockchip,free-sclk; - rockchip,dfs = <16>; - status = "disabled"; - }; - - flexbus_fspi: fspi { - compatible = "rockchip,flexbus-fspi"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - flexbus_spi: spi { - compatible = "rockchip,flexbus-spi"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - dsmc_lb_slave: dsmc-lb-slave@ff880000 { compatible = "rockchip,rk3506-dsmc-lb-slave"; reg = <0xff880000 0x10000>; @@ -1735,155 +471,27 @@ }; }; }; +}; - grf_pmu: syscon@ff910000 { - compatible = "rockchip,rk3506-grf-pmu", "syscon", "simple-mfd"; - reg = <0xff910000 0x4000>; - - reboot_mode: reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x200>; - mode-bootloader = ; - mode-charge = ; - mode-fastboot = ; - mode-loader = ; - mode-normal = ; - mode-recovery = ; - mode-ums = ; - mode-panic = ; - mode-watchdog = ; - }; - }; - - pwm0_4ch_0: pwm@ff930000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff930000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; - clock-names = "pwm", "pclk", "osc"; - #pwm-cells = <3>; +&grf { + rgb: rgb { + compatible = "rockchip,rk3506-rgb"; status = "disabled"; - }; - pwm0_4ch_1: pwm@ff931000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff931000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; - clock-names = "pwm", "pclk", "osc"; - #pwm-cells = <3>; - status = "disabled"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - pwm0_4ch_2: pwm@ff932000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff932000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; - clock-names = "pwm", "pclk", "osc"; - #pwm-cells = <3>; - status = "disabled"; - }; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; - pwm0_4ch_3: pwm@ff933000 { - compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; - reg = <0xff933000 0x200>; - interrupts = ; - clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>; - clock-names = "pwm", "pclk", "osc"; - #pwm-cells = <3>; - status = "disabled"; - }; - - ioc_pmu: syscon@ff950000 { - compatible = "rockchip,rk3506-ioc-pmu", "syscon"; - reg = <0xff950000 0x10000>; - }; - - cru: clock-controller@ff9a0000 { - compatible = "rockchip,rk3506-cru"; - reg = <0xff9a0000 0x20000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3506-pinctrl"; - rockchip,grf = <&ioc_grf>; - rockchip,ioc1 = <&ioc1>; - rockchip,pmu = <&ioc_pmu>; - rockchip,rmio = <&grf_pmu>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@ff940000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff940000 0x200>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff870000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff870000 0x200>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 32 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff1c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff1c0000 0x200>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 64 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff1d0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff1d0000 0x200>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 96 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ff1e0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff1e0000 0x200>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 128 32>; - interrupt-controller; - #interrupt-cells = <2>; + rgb_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_rgb>; + }; + }; }; }; }; - -#include "rk3506-pinctrl.dtsi" -#include "rk3506-pinctrl-rmio.dtsi" From 5aca25fd6fc92ff931e358a1702d2705f9534933 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Thu, 10 Oct 2024 16:42:10 +0800 Subject: [PATCH 4/7] ARM: dts: rockchip: add evb1 dts for rk3502 Change-Id: Ib1b2d3be3914960c5e17d0195cf67be696074755 Signed-off-by: Chris Zhong --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3502-evb1-v10.dtsi | 460 +++++++++++++++++++++++++ arch/arm/boot/dts/rk3502g-evb1-v10.dts | 96 ++++++ arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 403 +--------------------- 4 files changed, 558 insertions(+), 402 deletions(-) create mode 100644 arch/arm/boot/dts/rk3502-evb1-v10.dtsi create mode 100644 arch/arm/boot/dts/rk3502g-evb1-v10.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1c6a631085df..b7d9a15341b8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1221,6 +1221,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3308bs-evb-dmic-pdm-v11-aarch32.dtb \ rk3308bs-evb-mipi-display-v11-aarch32.dtb \ rk3308hs-voice-module-board-v10-aarch32.dtb \ + rk3502g-evb1-v10.dtb \ rk3503g-evb1-v10.dtb \ rk3506b-evb1-v10.dtb \ rk3506g-demo-display-control.dtb \ diff --git a/arch/arm/boot/dts/rk3502-evb1-v10.dtsi b/arch/arm/boot/dts/rk3502-evb1-v10.dtsi new file mode 100644 index 000000000000..8f4e57790602 --- /dev/null +++ b/arch/arm/boot/dts/rk3502-evb1-v10.dtsi @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include + +/ { + model = "Rockchip RK3502 EVB1 V10 Board"; + compatible = "rockchip,rk3502-evb1-v10", "rockchip,rk3502"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 ubi.mtd=5 ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + }; + + acodec_sound: acodec-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,acodec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <1024>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + simple-audio-card,cpu { + sound-dai = <&sai4>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + }; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <16000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <420000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <800000>; + }; + + esc-key { + label = "esc"; + linux,code = ; + press-threshold-microvolt = <1200000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0_4ch_2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + status = "okay"; + }; + + dsm_sound: dsm-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,dsm-sound"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + sndcodec: simple-audio-card,codec { + sound-dai = <&acdcdig_dsm>; + }; + }; + + es8388_sound: es8388-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + spk-con-gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,pre-power-on-delay-ms = <30>; + rockchip,post-power-down-delay-ms = <40>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai1>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Speaker", "LOUT1", + "Speaker", "ROUT1", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Main Mic", + "RINPUT2", "Main Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctrl>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_wake_up>; + + wake_up: wake-up { + label = "Wake-up"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + vcc12v_dc: vcc12v-dc { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dc>; + }; + + vcc3v3_stb: vcc3v3-stb { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_stb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_stb>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0_4ch_0 0 5000 1>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <710000>; + regulator-max-microvolt = <1207000>; + regulator-init-microvolt = <1011000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart5m0_rtsn_pins>; + pinctrl-1 = <&uart5_gpios>; + BT,power_gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>; + wifi_chip_type = "cyw43455"; + WIFI,host_wake_irq = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&audio_codec { + status = "okay"; +}; + +&cma { + size = <0x800000>; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&flexbus_fspi { + pinctrl-names = "default"; + pinctrl-0 = <&flexbus0m1_pins &flexbus0_clk_pins + &flexbus0_d0_pins &flexbus0_d1_pins + &flexbus0_d2_pins &flexbus0_d3_pins>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io13_i2c0_scl + &rm_io14_i2c0_sda>; + + es8388: es8388@11 { + status = "disabled"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io8_sai1_mclk>; + }; +}; + +&mmc { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk_pins &sdmmc_cmd_pins &sdmmc_bus4_pins>; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&pinctrl { + gpio-keys { + key_wake_up: key-wake-up { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + speaker { + spk_ctrl: spk-ctrl { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart5_gpios: uart5-gpios { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0_4ch_0 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io21_pwm0_ch0>; + status = "okay"; +}; + +&pwm0_4ch_1 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io20_pwm0_ch1>; + status = "okay"; +}; + +&pwm0_4ch_2 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io3_pwm0_ch2>; + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_ARMOFF_DDRPD + | RKPM_24M_OSC_DIS + | RKPM_32K_CLK + | RKPM_32K_SRC_RC + | RKPM_PWM0_CH0_REGULATOR + ) + >; + + rockchip,apios-suspend = < + (0 + | RKPM_PWREN_CORE_GPIO0A2 | RKPM_PWREN_CORE_ACT_LOW + | RKPM_PWREN_SLEEP_GPIO0A0 | RKPM_PWREN_SLEEP_ACT_LOW + ) + >; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&rm_io9_sai1_sclk + &rm_io10_sai1_lrck + &rm_io11_sai1_sdi + &rm_io12_sai1_sdo0>; +}; + +&sai4 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins>; + status = "okay"; +}; + +&u2phy_otg0 { + status = "okay"; +}; + +&u2phy_otg1 { + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb20_otg0 { + status = "okay"; +}; + +&usb20_otg1 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3502g-evb1-v10.dts b/arch/arm/boot/dts/rk3502g-evb1-v10.dts new file mode 100644 index 000000000000..531a9fc86e84 --- /dev/null +++ b/arch/arm/boot/dts/rk3502g-evb1-v10.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3502.dtsi" +#include "rk3502-evb1-v10.dtsi" + +/ { + model = "Rockchip RK3502G(QFN128) EVB1 V10 Board"; + compatible = "rockchip,rk3502g-evb1-v10", "rockchip,rk3502"; + + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_extcon_vbus>; + status = "okay"; + }; + + vcc5v0_otg0: vcc5v0-otg0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg0_en>; + }; + + vcc5v0_otg1: vcc5v0-otg1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg1"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg1_en>; + }; +}; + +&cma { + size = <0x1600000>; +}; + +&es8388 { + status = "okay"; +}; + +&es8388_sound { + status = "okay"; +}; + +&pinctrl { + usb { + usb_extcon_vbus: usb-extcon-vbus { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg0_en: vcc5v0-otg0-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg1_en: vcc5v0-otg1-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai1 { + status = "okay"; +}; + +&u2phy_otg0 { + vbus-supply = <&vcc5v0_otg0>; + rockchip,gpio-vbus-det; + status = "okay"; +}; + +&u2phy_otg1 { + phy-supply = <&vcc5v0_otg1>; + status = "okay"; +}; + +&usb2phy { + extcon = <&extcon_usb>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index e3cd2869b58c..b1b182de74eb 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include "rk3502-evb1-v10.dtsi" / { model = "Rockchip RK3506 EVB1 V10 Board"; @@ -15,53 +16,6 @@ bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 ubi.mtd=5 ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; }; - acodec_sound: acodec-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,acodec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <1024>; - simple-audio-card,bitclock-master = <&codec_master>; - simple-audio-card,frame-master = <&codec_master>; - simple-audio-card,cpu { - sound-dai = <&sai4>; - }; - codec_master: simple-audio-card,codec { - sound-dai = <&audio_codec>; - }; - }; - - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <16000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <420000>; - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <800000>; - }; - - esc-key { - label = "esc"; - linux,code = ; - press-threshold-microvolt = <1200000>; - }; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm0_4ch_2 0 25000 0>; @@ -102,166 +56,6 @@ default-brightness-level = <200>; status = "okay"; }; - - dsm_sound: dsm-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,dsm-sound"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - sndcpu: simple-audio-card,cpu { - sound-dai = <&sai3>; - }; - sndcodec: simple-audio-card,codec { - sound-dai = <&acdcdig_dsm>; - }; - }; - - es8388_sound: es8388-sound { - status = "disabled"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - spk-con-gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - rockchip,pre-power-on-delay-ms = <30>; - rockchip,post-power-down-delay-ms = <40>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&sai1>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Speaker", "LOUT1", - "Speaker", "ROUT1", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Main Mic", - "RINPUT2", "Main Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&spk_ctrl>; - }; - - fiq_debugger: fiq-debugger { - compatible = "rockchip,fiq-debugger"; - rockchip,serial-id = <0>; - rockchip,wake-irq = <0>; - rockchip,irq-mode-enable = <1>; - rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ - interrupts = ; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_wake_up>; - - wake_up: wake-up { - label = "Wake-up"; - gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - vcc12v_dc: vcc12v-dc { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dc>; - }; - - vcc3v3_stb: vcc3v3-stb { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_stb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - vcc_1v8: vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_stb>; - }; - - vcc_ddr: vcc-ddr { - compatible = "regulator-fixed"; - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm { - compatible = "pwm-regulator"; - pwms = <&pwm0_4ch_0 0 5000 1>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <710000>; - regulator-max-microvolt = <1207000>; - regulator-init-microvolt = <1011000>; - regulator-always-on; - regulator-boot-on; - regulator-settling-time-up-us = <250>; - pwm-supply = <&vcc_sys>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - }; - - wireless-bluetooth { - compatible = "bluetooth-platdata"; - uart_rts_gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart5m0_rtsn_pins>; - pinctrl-1 = <&uart5_gpios>; - BT,power_gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless-wlan { - compatible = "wlan-platdata"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_wake_host>; - wifi_chip_type = "cyw43455"; - WIFI,host_wake_irq = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&audio_codec { - status = "okay"; }; &can0 { @@ -272,14 +66,6 @@ status = "disabled"; }; -&cma { - size = <0x800000>; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - &display_subsystem { logo-memory-region = <&drm_logo>; status = "okay"; @@ -556,34 +342,6 @@ status = "disabled"; }; -&flexbus_fspi { - pinctrl-names = "default"; - pinctrl-0 = <&flexbus0m1_pins &flexbus0_clk_pins - &flexbus0_d0_pins &flexbus0_d1_pins - &flexbus0_d2_pins &flexbus0_d3_pins>; - status = "disabled"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&fspi { - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - &gmac0 { phy-mode = "rmii"; clock_in_out = "output"; @@ -602,26 +360,6 @@ status = "okay"; }; -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rm_io13_i2c0_scl - &rm_io14_i2c0_sda>; - - es8388: es8388@11 { - status = "disabled"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_sai1>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_sai1>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&rm_io8_sai1_mclk>; - }; -}; - &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -645,145 +383,6 @@ }; }; -&mmc { - bus-width = <4>; - cap-sd-highspeed; - no-sd; - no-mmc; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk_pins &sdmmc_cmd_pins &sdmmc_bus4_pins>; - ignore-pm-notify; - keep-power-in-suspend; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - sd-uhs-sdr104; - status = "okay"; -}; - -&pinctrl { - gpio-keys { - key_wake_up: key-wake-up { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - speaker { - spk_ctrl: spk-ctrl { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart5_gpios: uart5-gpios { - rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_wake_host: wifi-wake-host { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0_4ch_0 { - pinctrl-names = "active"; - pinctrl-0 = <&rm_io21_pwm0_ch0>; - status = "okay"; -}; - -&pwm0_4ch_1 { - pinctrl-names = "active"; - pinctrl-0 = <&rm_io20_pwm0_ch1>; - status = "okay"; -}; - -&pwm0_4ch_2 { - pinctrl-names = "active"; - pinctrl-0 = <&rm_io3_pwm0_ch2>; - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rng { - status = "okay"; -}; - -&rockchip_suspend { - rockchip,sleep-mode-config = < - (0 - | RKPM_ARMOFF_DDRPD - | RKPM_24M_OSC_DIS - | RKPM_32K_CLK - | RKPM_32K_SRC_RC - | RKPM_PWM0_CH0_REGULATOR - ) - >; - - rockchip,apios-suspend = < - (0 - | RKPM_PWREN_CORE_GPIO0A2 | RKPM_PWREN_CORE_ACT_LOW - | RKPM_PWREN_SLEEP_GPIO0A0 | RKPM_PWREN_SLEEP_ACT_LOW - ) - >; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&rm_io9_sai1_sclk - &rm_io10_sai1_lrck - &rm_io11_sai1_sdi - &rm_io12_sai1_sdo0>; -}; - -&sai4 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart5 { - pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins>; - status = "okay"; -}; - -&u2phy_otg0 { - status = "okay"; -}; - -&u2phy_otg1 { - status = "okay"; -}; - -&usb2phy { - status = "okay"; -}; - -&usb20_otg0 { - status = "okay"; -}; - -&usb20_otg1 { - dr_mode = "host"; - status = "okay"; -}; - &vop { status = "okay"; }; From 0308f07933f7a1ef6c53ecc6556c3e5115b13e74 Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Mon, 14 Oct 2024 17:34:19 +0800 Subject: [PATCH 5/7] video: rockchip: mpp: iep2: fix err log false print Change-Id: I032a7a038839b6b5ff83d79f5880955608f90a62 Signed-off-by: Yandong Lin --- drivers/video/rockchip/mpp/mpp_iep2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_iep2.c b/drivers/video/rockchip/mpp/mpp_iep2.c index 4a9e733c5133..3d53664b129e 100644 --- a/drivers/video/rockchip/mpp/mpp_iep2.c +++ b/drivers/video/rockchip/mpp/mpp_iep2.c @@ -893,9 +893,9 @@ static int iep2_init(struct mpp_dev *mpp) iep->roi.vaddr = dma_alloc_coherent(mpp->dev, iep->roi.size, &iep->roi.iova, GFP_KERNEL); - if (iep->roi.vaddr) { + if (!iep->roi.vaddr) { dev_err(mpp->dev, "allocate roi buffer failed\n"); - //return -ENOMEM; + return -ENOMEM; } return 0; From 04db30fe2176f0a456dbff2452f39b2dab3d2784 Mon Sep 17 00:00:00 2001 From: Zhibin Huang Date: Sat, 12 Oct 2024 09:57:38 +0800 Subject: [PATCH 6/7] misc: rk628: rgb/bt1120: modify decoder dclk delay The original configuration will lead to some screen display screen offset, adjust the dclk delay again to make the compatibility higher Type: Fix Redmine ID: N/A Associated modifications: N/A Test: N/A Signed-off-by: Zhibin Huang Change-Id: I732556b429b49418123fd889b67e26885e9b25f8 --- drivers/misc/rk628/rk628_rgb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/misc/rk628/rk628_rgb.c b/drivers/misc/rk628/rk628_rgb.c index f99d9cf9b41b..05a410025960 100644 --- a/drivers/misc/rk628/rk628_rgb.c +++ b/drivers/misc/rk628/rk628_rgb.c @@ -110,7 +110,7 @@ static void rk628_rgb_decoder_enable(struct rk628 *rk628) RGB_RX_MODET_EN | RGB_RX_DCLK_EN); rk628_i2c_update_bits(rk628, GRF_RGB_RX_DBG_MEAS3, RGB_RX_CNT_EN_MASK, RGB_RX_CNT_EN(1)); - rk628_i2c_write(rk628, GRF_BT1120_DCLK_DELAY_CON0, 0x10000); + rk628_i2c_write(rk628, GRF_BT1120_DCLK_DELAY_CON0, 0x10000000); rk628_i2c_write(rk628, GRF_BT1120_DCLK_DELAY_CON1, 0); } @@ -294,7 +294,7 @@ static void rk628_bt1120_decoder_enable(struct rk628 *rk628) } else { if (rk628->version == RK628F_VERSION) { rk628_i2c_write(rk628, GRF_BT1120_DCLK_DELAY_CON0, - 0x10000); + 0x08000000); rk628_i2c_write(rk628, GRF_BT1120_DCLK_DELAY_CON1, 0); } } From 5ef6efa7e56bdd34cd5d0a2288710bdc5288e13a Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 11 Oct 2024 10:05:10 +0800 Subject: [PATCH 7/7] mmc: sdhci-of-dwcmshc: Fix unblanced runtime calls echo 2a330000.mmc > /sys/bus/platform/drivers/sdhci-dwcmshc/unbind echo 2a330000.mmc > /sys/bus/platform/drivers/sdhci-dwcmshc/bind [ 386.150651] mmc2: CQHCI version 5.10 [ 386.183313] mmc2: SDHCI controller on 2a330000.mmc [2a330000.mmc] using ADMA 64-bit [ 386.183385] sdhci-dwcmshc 2a330000.mmc: Unbalanced pm_runtime_enable! Change-Id: I8926029274656f5f9820658325edec0449c8ac5f Signed-off-by: Shawn Lin --- drivers/mmc/host/sdhci-of-dwcmshc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 674c291d28fa..5e55b6439c71 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -983,6 +983,13 @@ static int dwcmshc_remove(struct platform_device *pdev) struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); struct rk35xx_priv *rk_priv = priv->priv; + if (rk_priv && !rk_priv->acpi_en) { + pm_runtime_get_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); + } + sdhci_remove_host(host, 0); clk_disable_unprepare(pltfm_host->clk);