From 0f39cdefa8bd9ca7911318b747c09adb125ab5cd Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Tue, 22 Aug 2023 10:16:30 +0800 Subject: [PATCH] ARM: rockchip: rv1106: sleep: decrease pmu-fsm time Change-Id: I57e88bb222ce26c7bf4736244e958e13b91ae184 Signed-off-by: XiaoDong Huang --- arch/arm/mach-rockchip/rv1106_pm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-rockchip/rv1106_pm.c b/arch/arm/mach-rockchip/rv1106_pm.c index 60315940d27c..5b04bfda7983 100644 --- a/arch/arm/mach-rockchip/rv1106_pm.c +++ b/arch/arm/mach-rockchip/rv1106_pm.c @@ -785,16 +785,16 @@ static void pmu_sleep_config(void) writel_relaxed(BITS_WITH_WMASK(0x1, 0xf, 4), ioc_base[1] + 0); /* pmu count */ - writel_relaxed(clk_freq_khz * 32, pmu_base + RV1106_PMU_OSC_STABLE_CNT); - writel_relaxed(clk_freq_khz * 32, pmu_base + RV1106_PMU_PMIC_STABLE_CNT); + writel_relaxed(clk_freq_khz * 10, pmu_base + RV1106_PMU_OSC_STABLE_CNT); + writel_relaxed(clk_freq_khz * 5, pmu_base + RV1106_PMU_PMIC_STABLE_CNT); /* Pmu's clk has switched to 24M back When pmu FSM counts * the follow counters, so we should use 24M to calculate * these counters. */ - writel_relaxed(24000 * 2, pmu_base + RV1106_PMU_WAKEUP_RSTCLR_CNT); - writel_relaxed(24000 * 5, pmu_base + RV1106_PMU_PLL_LOCK_CNT); - writel_relaxed(24000 * 5, pmu_base + RV1106_PMU_PWM_SWITCH_CNT); + writel_relaxed(12000, pmu_base + RV1106_PMU_WAKEUP_RSTCLR_CNT); + writel_relaxed(12000, pmu_base + RV1106_PMU_PLL_LOCK_CNT); + writel_relaxed(24000 * 2, pmu_base + RV1106_PMU_PWM_SWITCH_CNT); /* pmu reset hold */ writel_relaxed(0xffffffff, pmugrf_base + RV1106_PMUGRF_SOC_CON(4));